Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
bdc4abec YL |
30 | struct pci_dev_resource { |
31 | struct list_head list; | |
2934a0de YL |
32 | struct resource *res; |
33 | struct pci_dev *dev; | |
568ddef8 YL |
34 | resource_size_t start; |
35 | resource_size_t end; | |
c8adf9a3 | 36 | resource_size_t add_size; |
2bbc6942 | 37 | resource_size_t min_align; |
568ddef8 YL |
38 | unsigned long flags; |
39 | }; | |
40 | ||
bdc4abec YL |
41 | #define free_list(type, head) do { \ |
42 | struct type *dev_res, *tmp; \ | |
43 | list_for_each_entry_safe(dev_res, tmp, head, list) { \ | |
44 | list_del(&dev_res->list); \ | |
45 | kfree(dev_res); \ | |
46 | } \ | |
094732a5 RP |
47 | } while (0) |
48 | ||
f483d392 RP |
49 | int pci_realloc_enable = 0; |
50 | #define pci_realloc_enabled() pci_realloc_enable | |
51 | void pci_realloc(void) | |
52 | { | |
53 | pci_realloc_enable = 1; | |
54 | } | |
55 | ||
c8adf9a3 RP |
56 | /** |
57 | * add_to_list() - add a new resource tracker to the list | |
58 | * @head: Head of the list | |
59 | * @dev: device corresponding to which the resource | |
60 | * belongs | |
61 | * @res: The resource to be tracked | |
62 | * @add_size: additional size to be optionally added | |
63 | * to the resource | |
64 | */ | |
bdc4abec | 65 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 66 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 67 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 68 | { |
764242a0 | 69 | struct pci_dev_resource *tmp; |
568ddef8 | 70 | |
bdc4abec | 71 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 72 | if (!tmp) { |
c8adf9a3 | 73 | pr_warning("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 74 | return -ENOMEM; |
568ddef8 YL |
75 | } |
76 | ||
568ddef8 YL |
77 | tmp->res = res; |
78 | tmp->dev = dev; | |
79 | tmp->start = res->start; | |
80 | tmp->end = res->end; | |
81 | tmp->flags = res->flags; | |
c8adf9a3 | 82 | tmp->add_size = add_size; |
2bbc6942 | 83 | tmp->min_align = min_align; |
bdc4abec YL |
84 | |
85 | list_add(&tmp->list, head); | |
ef62dfef YL |
86 | |
87 | return 0; | |
568ddef8 YL |
88 | } |
89 | ||
bdc4abec | 90 | static void add_to_failed_list(struct list_head *head, |
c8adf9a3 RP |
91 | struct pci_dev *dev, struct resource *res) |
92 | { | |
2bbc6942 RP |
93 | add_to_list(head, dev, res, |
94 | 0 /* dont care */, | |
95 | 0 /* dont care */); | |
c8adf9a3 RP |
96 | } |
97 | ||
b9b0bba9 | 98 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
99 | struct resource *res) |
100 | { | |
b9b0bba9 | 101 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 102 | |
b9b0bba9 YL |
103 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
104 | if (dev_res->res == res) { | |
105 | list_del(&dev_res->list); | |
106 | kfree(dev_res); | |
bdc4abec | 107 | break; |
3e6e0d80 | 108 | } |
3e6e0d80 YL |
109 | } |
110 | } | |
111 | ||
b9b0bba9 | 112 | static resource_size_t get_res_add_size(struct list_head *head, |
1c372353 YL |
113 | struct resource *res) |
114 | { | |
b9b0bba9 | 115 | struct pci_dev_resource *dev_res; |
bdc4abec | 116 | |
b9b0bba9 YL |
117 | list_for_each_entry(dev_res, head, list) { |
118 | if (dev_res->res == res) { | |
119 | dev_printk(KERN_DEBUG, &dev_res->dev->dev, | |
bdc4abec | 120 | "%pR get_res_add_size add_size %llx\n", |
b9b0bba9 YL |
121 | dev_res->res, |
122 | (unsigned long long)dev_res->add_size); | |
123 | return dev_res->add_size; | |
bdc4abec | 124 | } |
3e6e0d80 | 125 | } |
1c372353 YL |
126 | |
127 | return 0; | |
128 | } | |
129 | ||
78c3b329 | 130 | /* Sort resources by alignment */ |
bdc4abec | 131 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
132 | { |
133 | int i; | |
134 | ||
135 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
136 | struct resource *r; | |
bdc4abec | 137 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 138 | resource_size_t r_align; |
bdc4abec | 139 | struct list_head *n; |
78c3b329 YL |
140 | |
141 | r = &dev->resource[i]; | |
142 | ||
143 | if (r->flags & IORESOURCE_PCI_FIXED) | |
144 | continue; | |
145 | ||
146 | if (!(r->flags) || r->parent) | |
147 | continue; | |
148 | ||
149 | r_align = pci_resource_alignment(dev, r); | |
150 | if (!r_align) { | |
151 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
152 | i, r); | |
153 | continue; | |
154 | } | |
78c3b329 | 155 | |
bdc4abec YL |
156 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
157 | if (!tmp) | |
158 | panic("pdev_sort_resources(): " | |
159 | "kmalloc() failed!\n"); | |
160 | tmp->res = r; | |
161 | tmp->dev = dev; | |
162 | ||
163 | /* fallback is smallest one or list is empty*/ | |
164 | n = head; | |
165 | list_for_each_entry(dev_res, head, list) { | |
166 | resource_size_t align; | |
167 | ||
168 | align = pci_resource_alignment(dev_res->dev, | |
169 | dev_res->res); | |
78c3b329 YL |
170 | |
171 | if (r_align > align) { | |
bdc4abec | 172 | n = &dev_res->list; |
78c3b329 YL |
173 | break; |
174 | } | |
175 | } | |
bdc4abec YL |
176 | /* Insert it just before n*/ |
177 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
178 | } |
179 | } | |
180 | ||
6841ec68 | 181 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 182 | struct list_head *head) |
1da177e4 | 183 | { |
6841ec68 | 184 | u16 class = dev->class >> 8; |
1da177e4 | 185 | |
6841ec68 YL |
186 | /* Don't touch classless devices or host bridges or ioapics. */ |
187 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
188 | return; | |
1da177e4 | 189 | |
6841ec68 YL |
190 | /* Don't touch ioapic devices already enabled by firmware */ |
191 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
192 | u16 command; | |
193 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
194 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
195 | return; | |
196 | } | |
1da177e4 | 197 | |
6841ec68 YL |
198 | pdev_sort_resources(dev, head); |
199 | } | |
23186279 | 200 | |
fc075e1d RP |
201 | static inline void reset_resource(struct resource *res) |
202 | { | |
203 | res->start = 0; | |
204 | res->end = 0; | |
205 | res->flags = 0; | |
206 | } | |
207 | ||
c8adf9a3 | 208 | /** |
9e8bf93a | 209 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 210 | * |
9e8bf93a | 211 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
212 | * resources |
213 | * @head : head of the list tracking requests with allocated | |
214 | * resources | |
215 | * | |
9e8bf93a | 216 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
217 | * additional resources for the element, provided the element |
218 | * is in the head list. | |
219 | */ | |
bdc4abec YL |
220 | static void reassign_resources_sorted(struct list_head *realloc_head, |
221 | struct list_head *head) | |
6841ec68 YL |
222 | { |
223 | struct resource *res; | |
b9b0bba9 | 224 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 225 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 226 | resource_size_t add_size; |
6841ec68 | 227 | int idx; |
1da177e4 | 228 | |
b9b0bba9 | 229 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
230 | bool found_match = false; |
231 | ||
b9b0bba9 | 232 | res = add_res->res; |
c8adf9a3 RP |
233 | /* skip resource that has been reset */ |
234 | if (!res->flags) | |
235 | goto out; | |
236 | ||
237 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
238 | list_for_each_entry(dev_res, head, list) { |
239 | if (dev_res->res == res) { | |
240 | found_match = true; | |
241 | break; | |
242 | } | |
c8adf9a3 | 243 | } |
bdc4abec YL |
244 | if (!found_match)/* just skip */ |
245 | continue; | |
c8adf9a3 | 246 | |
b9b0bba9 YL |
247 | idx = res - &add_res->dev->resource[0]; |
248 | add_size = add_res->add_size; | |
2bbc6942 | 249 | if (!resource_size(res)) { |
b9b0bba9 | 250 | res->start = add_res->start; |
2bbc6942 | 251 | res->end = res->start + add_size - 1; |
b9b0bba9 | 252 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 253 | reset_resource(res); |
2bbc6942 | 254 | } else { |
b9b0bba9 YL |
255 | resource_size_t align = add_res->min_align; |
256 | res->flags |= add_res->flags & | |
bdc4abec | 257 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 258 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 259 | add_size, align)) |
b9b0bba9 | 260 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
bdc4abec | 261 | "failed to add optional resources res=%pR\n", |
2bbc6942 | 262 | res); |
c8adf9a3 RP |
263 | } |
264 | out: | |
b9b0bba9 YL |
265 | list_del(&add_res->list); |
266 | kfree(add_res); | |
c8adf9a3 RP |
267 | } |
268 | } | |
269 | ||
270 | /** | |
271 | * assign_requested_resources_sorted() - satisfy resource requests | |
272 | * | |
273 | * @head : head of the list tracking requests for resources | |
274 | * @failed_list : head of the list tracking requests that could | |
275 | * not be allocated | |
276 | * | |
277 | * Satisfy resource requests of each element in the list. Add | |
278 | * requests that could not satisfied to the failed_list. | |
279 | */ | |
bdc4abec YL |
280 | static void assign_requested_resources_sorted(struct list_head *head, |
281 | struct list_head *fail_head) | |
c8adf9a3 RP |
282 | { |
283 | struct resource *res; | |
bdc4abec | 284 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 285 | int idx; |
9a928660 | 286 | |
bdc4abec YL |
287 | list_for_each_entry(dev_res, head, list) { |
288 | res = dev_res->res; | |
289 | idx = res - &dev_res->dev->resource[0]; | |
290 | if (resource_size(res) && | |
291 | pci_assign_resource(dev_res->dev, idx)) { | |
292 | if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) { | |
9a928660 YL |
293 | /* |
294 | * if the failed res is for ROM BAR, and it will | |
295 | * be enabled later, don't add it to the list | |
296 | */ | |
297 | if (!((idx == PCI_ROM_RESOURCE) && | |
298 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
bdc4abec YL |
299 | add_to_failed_list(fail_head, |
300 | dev_res->dev, res); | |
9a928660 | 301 | } |
fc075e1d | 302 | reset_resource(res); |
542df5de | 303 | } |
1da177e4 LT |
304 | } |
305 | } | |
306 | ||
bdc4abec YL |
307 | static void __assign_resources_sorted(struct list_head *head, |
308 | struct list_head *realloc_head, | |
309 | struct list_head *fail_head) | |
c8adf9a3 | 310 | { |
3e6e0d80 YL |
311 | /* |
312 | * Should not assign requested resources at first. | |
313 | * they could be adjacent, so later reassign can not reallocate | |
314 | * them one by one in parent resource window. | |
315 | * Try to assign requested + add_size at begining | |
316 | * if could do that, could get out early. | |
317 | * if could not do that, we still try to assign requested at first, | |
318 | * then try to reassign add_size for some resources. | |
319 | */ | |
bdc4abec YL |
320 | LIST_HEAD(save_head); |
321 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 322 | struct pci_dev_resource *save_res; |
bdc4abec | 323 | struct pci_dev_resource *dev_res; |
3e6e0d80 YL |
324 | |
325 | /* Check if optional add_size is there */ | |
bdc4abec | 326 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
327 | goto requested_and_reassign; |
328 | ||
329 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
330 | list_for_each_entry(dev_res, head, list) { |
331 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
764242a0 | 332 | free_list(pci_dev_resource, &save_head); |
3e6e0d80 YL |
333 | goto requested_and_reassign; |
334 | } | |
bdc4abec | 335 | } |
3e6e0d80 YL |
336 | |
337 | /* Update res in head list with add_size in realloc_head list */ | |
bdc4abec YL |
338 | list_for_each_entry(dev_res, head, list) |
339 | dev_res->res->end += get_res_add_size(realloc_head, | |
340 | dev_res->res); | |
3e6e0d80 YL |
341 | |
342 | /* Try updated head list with add_size added */ | |
3e6e0d80 YL |
343 | assign_requested_resources_sorted(head, &local_fail_head); |
344 | ||
345 | /* all assigned with add_size ? */ | |
bdc4abec | 346 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 347 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
348 | list_for_each_entry(dev_res, head, list) |
349 | remove_from_list(realloc_head, dev_res->res); | |
764242a0 | 350 | free_list(pci_dev_resource, &save_head); |
bdc4abec | 351 | free_list(pci_dev_resource, head); |
3e6e0d80 YL |
352 | return; |
353 | } | |
354 | ||
764242a0 | 355 | free_list(pci_dev_resource, &local_fail_head); |
3e6e0d80 | 356 | /* Release assigned resource */ |
bdc4abec YL |
357 | list_for_each_entry(dev_res, head, list) |
358 | if (dev_res->res->parent) | |
359 | release_resource(dev_res->res); | |
3e6e0d80 | 360 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
361 | list_for_each_entry(save_res, &save_head, list) { |
362 | struct resource *res = save_res->res; | |
3e6e0d80 | 363 | |
b9b0bba9 YL |
364 | res->start = save_res->start; |
365 | res->end = save_res->end; | |
366 | res->flags = save_res->flags; | |
3e6e0d80 | 367 | } |
764242a0 | 368 | free_list(pci_dev_resource, &save_head); |
3e6e0d80 YL |
369 | |
370 | requested_and_reassign: | |
c8adf9a3 RP |
371 | /* Satisfy the must-have resource requests */ |
372 | assign_requested_resources_sorted(head, fail_head); | |
373 | ||
0a2daa1c | 374 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 375 | requests */ |
9e8bf93a RP |
376 | if (realloc_head) |
377 | reassign_resources_sorted(realloc_head, head); | |
bdc4abec | 378 | free_list(pci_dev_resource, head); |
c8adf9a3 RP |
379 | } |
380 | ||
6841ec68 | 381 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
382 | struct list_head *add_head, |
383 | struct list_head *fail_head) | |
6841ec68 | 384 | { |
bdc4abec | 385 | LIST_HEAD(head); |
6841ec68 | 386 | |
6841ec68 | 387 | __dev_sort_resources(dev, &head); |
8424d759 | 388 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
389 | |
390 | } | |
391 | ||
392 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
393 | struct list_head *realloc_head, |
394 | struct list_head *fail_head) | |
6841ec68 YL |
395 | { |
396 | struct pci_dev *dev; | |
bdc4abec | 397 | LIST_HEAD(head); |
6841ec68 | 398 | |
6841ec68 YL |
399 | list_for_each_entry(dev, &bus->devices, bus_list) |
400 | __dev_sort_resources(dev, &head); | |
401 | ||
9e8bf93a | 402 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
403 | } |
404 | ||
b3743fa4 | 405 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
406 | { |
407 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 408 | struct resource *res; |
1da177e4 LT |
409 | struct pci_bus_region region; |
410 | ||
865df576 BH |
411 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
412 | bus->secondary, bus->subordinate); | |
1da177e4 | 413 | |
c7dabef8 BH |
414 | res = bus->resource[0]; |
415 | pcibios_resource_to_bus(bridge, ®ion, res); | |
416 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
417 | /* |
418 | * The IO resource is allocated a range twice as large as it | |
419 | * would normally need. This allows us to set both IO regs. | |
420 | */ | |
c7dabef8 | 421 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
422 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
423 | region.start); | |
424 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
425 | region.end); | |
426 | } | |
427 | ||
c7dabef8 BH |
428 | res = bus->resource[1]; |
429 | pcibios_resource_to_bus(bridge, ®ion, res); | |
430 | if (res->flags & IORESOURCE_IO) { | |
431 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
432 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
433 | region.start); | |
434 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
435 | region.end); | |
436 | } | |
437 | ||
c7dabef8 BH |
438 | res = bus->resource[2]; |
439 | pcibios_resource_to_bus(bridge, ®ion, res); | |
440 | if (res->flags & IORESOURCE_MEM) { | |
441 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
442 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
443 | region.start); | |
444 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
445 | region.end); | |
446 | } | |
447 | ||
c7dabef8 BH |
448 | res = bus->resource[3]; |
449 | pcibios_resource_to_bus(bridge, ®ion, res); | |
450 | if (res->flags & IORESOURCE_MEM) { | |
451 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
452 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
453 | region.start); | |
454 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
455 | region.end); | |
456 | } | |
457 | } | |
b3743fa4 | 458 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
459 | |
460 | /* Initialize bridges with base/limit values we have collected. | |
461 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
462 | requires that if there is no I/O ports or memory behind the | |
463 | bridge, corresponding range must be turned off by writing base | |
464 | value greater than limit to the bridge's base/limit registers. | |
465 | ||
466 | Note: care must be taken when updating I/O base/limit registers | |
467 | of bridges which support 32-bit I/O. This update requires two | |
468 | config space writes, so it's quite possible that an I/O window of | |
469 | the bridge will have some undesirable address (e.g. 0) after the | |
470 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 471 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
472 | { |
473 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 474 | struct resource *res; |
1da177e4 | 475 | struct pci_bus_region region; |
7cc5997d | 476 | u32 l, io_upper16; |
1da177e4 LT |
477 | |
478 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
479 | res = bus->resource[0]; |
480 | pcibios_resource_to_bus(bridge, ®ion, res); | |
481 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
482 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
483 | l &= 0xffff0000; | |
484 | l |= (region.start >> 8) & 0x00f0; | |
485 | l |= region.end & 0xf000; | |
486 | /* Set up upper 16 bits of I/O base/limit. */ | |
487 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 488 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 489 | } else { |
1da177e4 LT |
490 | /* Clear upper 16 bits of I/O base/limit. */ |
491 | io_upper16 = 0; | |
492 | l = 0x00f0; | |
1da177e4 LT |
493 | } |
494 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
495 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
496 | /* Update lower 16 bits of I/O base/limit. */ | |
497 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
498 | /* Update upper 16 bits of I/O base/limit. */ | |
499 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
500 | } |
501 | ||
502 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
503 | { | |
504 | struct pci_dev *bridge = bus->self; | |
505 | struct resource *res; | |
506 | struct pci_bus_region region; | |
507 | u32 l; | |
1da177e4 | 508 | |
7cc5997d | 509 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
510 | res = bus->resource[1]; |
511 | pcibios_resource_to_bus(bridge, ®ion, res); | |
512 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
513 | l = (region.start >> 16) & 0xfff0; |
514 | l |= region.end & 0xfff00000; | |
c7dabef8 | 515 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 516 | } else { |
1da177e4 | 517 | l = 0x0000fff0; |
1da177e4 LT |
518 | } |
519 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
520 | } |
521 | ||
522 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
523 | { | |
524 | struct pci_dev *bridge = bus->self; | |
525 | struct resource *res; | |
526 | struct pci_bus_region region; | |
527 | u32 l, bu, lu; | |
1da177e4 LT |
528 | |
529 | /* Clear out the upper 32 bits of PREF limit. | |
530 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
531 | disables PREF range, which is ok. */ | |
532 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
533 | ||
534 | /* Set up PREF base/limit. */ | |
c40a22e0 | 535 | bu = lu = 0; |
c7dabef8 BH |
536 | res = bus->resource[2]; |
537 | pcibios_resource_to_bus(bridge, ®ion, res); | |
538 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
539 | l = (region.start >> 16) & 0xfff0; |
540 | l |= region.end & 0xfff00000; | |
c7dabef8 | 541 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
542 | bu = upper_32_bits(region.start); |
543 | lu = upper_32_bits(region.end); | |
1f82de10 | 544 | } |
c7dabef8 | 545 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 546 | } else { |
1da177e4 | 547 | l = 0x0000fff0; |
1da177e4 LT |
548 | } |
549 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
550 | ||
59353ea3 AW |
551 | /* Set the upper 32 bits of PREF base & limit. */ |
552 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
553 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
554 | } |
555 | ||
556 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
557 | { | |
558 | struct pci_dev *bridge = bus->self; | |
559 | ||
7cc5997d YL |
560 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
561 | bus->secondary, bus->subordinate); | |
562 | ||
563 | if (type & IORESOURCE_IO) | |
564 | pci_setup_bridge_io(bus); | |
565 | ||
566 | if (type & IORESOURCE_MEM) | |
567 | pci_setup_bridge_mmio(bus); | |
568 | ||
569 | if (type & IORESOURCE_PREFETCH) | |
570 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
571 | |
572 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
573 | } | |
574 | ||
e2444273 | 575 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
576 | { |
577 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
578 | IORESOURCE_PREFETCH; | |
579 | ||
580 | __pci_setup_bridge(bus, type); | |
581 | } | |
582 | ||
1da177e4 LT |
583 | /* Check whether the bridge supports optional I/O and |
584 | prefetchable memory ranges. If not, the respective | |
585 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 586 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
587 | { |
588 | u16 io; | |
589 | u32 pmem; | |
590 | struct pci_dev *bridge = bus->self; | |
591 | struct resource *b_res; | |
592 | ||
593 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
594 | b_res[1].flags |= IORESOURCE_MEM; | |
595 | ||
596 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
597 | if (!io) { | |
598 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
599 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
600 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
601 | } | |
602 | if (io) | |
603 | b_res[0].flags |= IORESOURCE_IO; | |
604 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
605 | disconnect boundary by one PCI data phase. | |
606 | Workaround: do not use prefetching on this device. */ | |
607 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
608 | return; | |
609 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
610 | if (!pmem) { | |
611 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
612 | 0xfff0fff0); | |
613 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
614 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
615 | } | |
1f82de10 | 616 | if (pmem) { |
1da177e4 | 617 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
618 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
619 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 620 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
621 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
622 | } | |
1f82de10 YL |
623 | } |
624 | ||
625 | /* double check if bridge does support 64 bit pref */ | |
626 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
627 | u32 mem_base_hi, tmp; | |
628 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
629 | &mem_base_hi); | |
630 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
631 | 0xffffffff); | |
632 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
633 | if (!tmp) | |
634 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
635 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
636 | mem_base_hi); | |
637 | } | |
1da177e4 LT |
638 | } |
639 | ||
640 | /* Helper function for sizing routines: find first available | |
641 | bus resource of a given type. Note: we intentionally skip | |
642 | the bus resources which have already been assigned (that is, | |
643 | have non-NULL parent resource). */ | |
96bde06a | 644 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
645 | { |
646 | int i; | |
647 | struct resource *r; | |
648 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
649 | IORESOURCE_PREFETCH; | |
650 | ||
89a74ecc | 651 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
652 | if (r == &ioport_resource || r == &iomem_resource) |
653 | continue; | |
55a10984 JB |
654 | if (r && (r->flags & type_mask) == type && !r->parent) |
655 | return r; | |
1da177e4 LT |
656 | } |
657 | return NULL; | |
658 | } | |
659 | ||
13583b16 RP |
660 | static resource_size_t calculate_iosize(resource_size_t size, |
661 | resource_size_t min_size, | |
662 | resource_size_t size1, | |
663 | resource_size_t old_size, | |
664 | resource_size_t align) | |
665 | { | |
666 | if (size < min_size) | |
667 | size = min_size; | |
668 | if (old_size == 1 ) | |
669 | old_size = 0; | |
670 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
671 | flag in the struct pci_bus. */ | |
672 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
673 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
674 | #endif | |
675 | size = ALIGN(size + size1, align); | |
676 | if (size < old_size) | |
677 | size = old_size; | |
678 | return size; | |
679 | } | |
680 | ||
681 | static resource_size_t calculate_memsize(resource_size_t size, | |
682 | resource_size_t min_size, | |
683 | resource_size_t size1, | |
684 | resource_size_t old_size, | |
685 | resource_size_t align) | |
686 | { | |
687 | if (size < min_size) | |
688 | size = min_size; | |
689 | if (old_size == 1 ) | |
690 | old_size = 0; | |
691 | if (size < old_size) | |
692 | size = old_size; | |
693 | size = ALIGN(size + size1, align); | |
694 | return size; | |
695 | } | |
696 | ||
c8adf9a3 RP |
697 | /** |
698 | * pbus_size_io() - size the io window of a given bus | |
699 | * | |
700 | * @bus : the bus | |
701 | * @min_size : the minimum io window that must to be allocated | |
702 | * @add_size : additional optional io window | |
9e8bf93a | 703 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
704 | * |
705 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
706 | * since these windows have 4K granularity and the IO ranges | |
707 | * of non-bridge PCI devices are limited to 256 bytes. | |
708 | * We must be careful with the ISA aliasing though. | |
709 | */ | |
710 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 711 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
712 | { |
713 | struct pci_dev *dev; | |
714 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
c8adf9a3 | 715 | unsigned long size = 0, size0 = 0, size1 = 0; |
be768912 | 716 | resource_size_t children_add_size = 0; |
1da177e4 LT |
717 | |
718 | if (!b_res) | |
719 | return; | |
720 | ||
721 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
722 | int i; | |
723 | ||
724 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
725 | struct resource *r = &dev->resource[i]; | |
726 | unsigned long r_size; | |
727 | ||
728 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
729 | continue; | |
022edd86 | 730 | r_size = resource_size(r); |
1da177e4 LT |
731 | |
732 | if (r_size < 0x400) | |
733 | /* Might be re-aligned for ISA */ | |
734 | size += r_size; | |
735 | else | |
736 | size1 += r_size; | |
be768912 | 737 | |
9e8bf93a RP |
738 | if (realloc_head) |
739 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
740 | } |
741 | } | |
c8adf9a3 RP |
742 | size0 = calculate_iosize(size, min_size, size1, |
743 | resource_size(b_res), 4096); | |
be768912 YL |
744 | if (children_add_size > add_size) |
745 | add_size = children_add_size; | |
9e8bf93a | 746 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 747 | calculate_iosize(size, min_size, add_size + size1, |
13583b16 | 748 | resource_size(b_res), 4096); |
c8adf9a3 | 749 | if (!size0 && !size1) { |
865df576 BH |
750 | if (b_res->start || b_res->end) |
751 | dev_info(&bus->self->dev, "disabling bridge window " | |
752 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
753 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
754 | b_res->flags = 0; |
755 | return; | |
756 | } | |
757 | /* Alignment of the IO window is always 4K */ | |
758 | b_res->start = 4096; | |
c8adf9a3 | 759 | b_res->end = b_res->start + size0 - 1; |
88452565 | 760 | b_res->flags |= IORESOURCE_STARTALIGN; |
9e8bf93a RP |
761 | if (size1 > size0 && realloc_head) |
762 | add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096); | |
1da177e4 LT |
763 | } |
764 | ||
c8adf9a3 RP |
765 | /** |
766 | * pbus_size_mem() - size the memory window of a given bus | |
767 | * | |
768 | * @bus : the bus | |
769 | * @min_size : the minimum memory window that must to be allocated | |
770 | * @add_size : additional optional memory window | |
9e8bf93a | 771 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
772 | * |
773 | * Calculate the size of the bus and minimal alignment which | |
774 | * guarantees that all child resources fit in this size. | |
775 | */ | |
28760489 | 776 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
c8adf9a3 RP |
777 | unsigned long type, resource_size_t min_size, |
778 | resource_size_t add_size, | |
bdc4abec | 779 | struct list_head *realloc_head) |
1da177e4 LT |
780 | { |
781 | struct pci_dev *dev; | |
c8adf9a3 | 782 | resource_size_t min_align, align, size, size0, size1; |
c40a22e0 | 783 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
784 | int order, max_order; |
785 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 786 | unsigned int mem64_mask = 0; |
be768912 | 787 | resource_size_t children_add_size = 0; |
1da177e4 LT |
788 | |
789 | if (!b_res) | |
790 | return 0; | |
791 | ||
792 | memset(aligns, 0, sizeof(aligns)); | |
793 | max_order = 0; | |
794 | size = 0; | |
795 | ||
1f82de10 YL |
796 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
797 | b_res->flags &= ~IORESOURCE_MEM_64; | |
798 | ||
1da177e4 LT |
799 | list_for_each_entry(dev, &bus->devices, bus_list) { |
800 | int i; | |
1f82de10 | 801 | |
1da177e4 LT |
802 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
803 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 804 | resource_size_t r_size; |
1da177e4 LT |
805 | |
806 | if (r->parent || (r->flags & mask) != type) | |
807 | continue; | |
022edd86 | 808 | r_size = resource_size(r); |
2aceefcb YL |
809 | #ifdef CONFIG_PCI_IOV |
810 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 811 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb YL |
812 | i <= PCI_IOV_RESOURCE_END) { |
813 | r->end = r->start - 1; | |
9e8bf93a | 814 | add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); |
2aceefcb YL |
815 | children_add_size += r_size; |
816 | continue; | |
817 | } | |
818 | #endif | |
1da177e4 | 819 | /* For bridges size != alignment */ |
6faf17f6 | 820 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
821 | order = __ffs(align) - 20; |
822 | if (order > 11) { | |
865df576 BH |
823 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
824 | "(bad alignment %#llx)\n", i, r, | |
825 | (unsigned long long) align); | |
1da177e4 LT |
826 | r->flags = 0; |
827 | continue; | |
828 | } | |
829 | size += r_size; | |
830 | if (order < 0) | |
831 | order = 0; | |
832 | /* Exclude ranges with size > align from | |
833 | calculation of the alignment. */ | |
834 | if (r_size == align) | |
835 | aligns[order] += align; | |
836 | if (order > max_order) | |
837 | max_order = order; | |
1f82de10 | 838 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
be768912 | 839 | |
9e8bf93a RP |
840 | if (realloc_head) |
841 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
842 | } |
843 | } | |
1da177e4 LT |
844 | align = 0; |
845 | min_align = 0; | |
846 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
847 | resource_size_t align1 = 1; |
848 | ||
849 | align1 <<= (order + 20); | |
850 | ||
1da177e4 LT |
851 | if (!align) |
852 | min_align = align1; | |
6f6f8c2f | 853 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
854 | min_align = align1 >> 1; |
855 | align += aligns[order]; | |
856 | } | |
b42282e5 | 857 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
be768912 YL |
858 | if (children_add_size > add_size) |
859 | add_size = children_add_size; | |
9e8bf93a | 860 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 861 | calculate_memsize(size, min_size, add_size, |
b42282e5 | 862 | resource_size(b_res), min_align); |
c8adf9a3 | 863 | if (!size0 && !size1) { |
865df576 BH |
864 | if (b_res->start || b_res->end) |
865 | dev_info(&bus->self->dev, "disabling bridge window " | |
866 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
867 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
868 | b_res->flags = 0; |
869 | return 1; | |
870 | } | |
871 | b_res->start = min_align; | |
c8adf9a3 RP |
872 | b_res->end = size0 + min_align - 1; |
873 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; | |
9e8bf93a RP |
874 | if (size1 > size0 && realloc_head) |
875 | add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); | |
1da177e4 LT |
876 | return 1; |
877 | } | |
878 | ||
0a2daa1c RP |
879 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
880 | { | |
881 | if (res->flags & IORESOURCE_IO) | |
882 | return pci_cardbus_io_size; | |
883 | if (res->flags & IORESOURCE_MEM) | |
884 | return pci_cardbus_mem_size; | |
885 | return 0; | |
886 | } | |
887 | ||
888 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 889 | struct list_head *realloc_head) |
1da177e4 LT |
890 | { |
891 | struct pci_dev *bridge = bus->self; | |
892 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
893 | u16 ctrl; | |
894 | ||
895 | /* | |
896 | * Reserve some resources for CardBus. We reserve | |
897 | * a fixed amount of bus space for CardBus bridges. | |
898 | */ | |
934b7024 | 899 | b_res[0].start = 0; |
934b7024 | 900 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
901 | if (realloc_head) |
902 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 0 /* dont care */); | |
1da177e4 | 903 | |
934b7024 | 904 | b_res[1].start = 0; |
934b7024 | 905 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
906 | if (realloc_head) |
907 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */); | |
1da177e4 LT |
908 | |
909 | /* | |
910 | * Check whether prefetchable memory is supported | |
911 | * by this bridge. | |
912 | */ | |
913 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
914 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
915 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
916 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
917 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
918 | } | |
919 | ||
920 | /* | |
921 | * If we have prefetchable memory support, allocate | |
922 | * two regions. Otherwise, allocate one region of | |
923 | * twice the size. | |
924 | */ | |
925 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
934b7024 | 926 | b_res[2].start = 0; |
934b7024 | 927 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
928 | if (realloc_head) |
929 | add_to_list(realloc_head, bridge, b_res+2, pci_cardbus_mem_size, 0 /* dont care */); | |
1da177e4 | 930 | |
934b7024 | 931 | b_res[3].start = 0; |
934b7024 | 932 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
933 | if (realloc_head) |
934 | add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size, 0 /* dont care */); | |
1da177e4 | 935 | } else { |
934b7024 | 936 | b_res[3].start = 0; |
934b7024 | 937 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
938 | if (realloc_head) |
939 | add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size * 2, 0 /* dont care */); | |
1da177e4 | 940 | } |
0a2daa1c RP |
941 | |
942 | /* set the size of the resource to zero, so that the resource does not | |
943 | * get assigned during required-resource allocation cycle but gets assigned | |
944 | * during the optional-resource allocation cycle. | |
945 | */ | |
946 | b_res[0].start = b_res[1].start = b_res[2].start = b_res[3].start = 1; | |
947 | b_res[0].end = b_res[1].end = b_res[2].end = b_res[3].end = 0; | |
1da177e4 LT |
948 | } |
949 | ||
c8adf9a3 | 950 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
bdc4abec | 951 | struct list_head *realloc_head) |
1da177e4 LT |
952 | { |
953 | struct pci_dev *dev; | |
954 | unsigned long mask, prefmask; | |
c8adf9a3 | 955 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1da177e4 LT |
956 | |
957 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
958 | struct pci_bus *b = dev->subordinate; | |
959 | if (!b) | |
960 | continue; | |
961 | ||
962 | switch (dev->class >> 8) { | |
963 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 964 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
965 | break; |
966 | ||
967 | case PCI_CLASS_BRIDGE_PCI: | |
968 | default: | |
9e8bf93a | 969 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
970 | break; |
971 | } | |
972 | } | |
973 | ||
974 | /* The root bus? */ | |
975 | if (!bus->self) | |
976 | return; | |
977 | ||
978 | switch (bus->self->class >> 8) { | |
979 | case PCI_CLASS_BRIDGE_CARDBUS: | |
980 | /* don't size cardbuses yet. */ | |
981 | break; | |
982 | ||
983 | case PCI_CLASS_BRIDGE_PCI: | |
984 | pci_bridge_check_ranges(bus); | |
28760489 | 985 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
986 | additional_io_size = pci_hotplug_io_size; |
987 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 988 | } |
c8adf9a3 RP |
989 | /* |
990 | * Follow thru | |
991 | */ | |
1da177e4 | 992 | default: |
19aa7ee4 YL |
993 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
994 | additional_io_size, realloc_head); | |
1da177e4 LT |
995 | /* If the bridge supports prefetchable range, size it |
996 | separately. If it doesn't, or its prefetchable window | |
997 | has already been allocated by arch code, try | |
998 | non-prefetchable range for both types of PCI memory | |
999 | resources. */ | |
1000 | mask = IORESOURCE_MEM; | |
1001 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
19aa7ee4 YL |
1002 | if (pbus_size_mem(bus, prefmask, prefmask, |
1003 | realloc_head ? 0 : additional_mem_size, | |
1004 | additional_mem_size, realloc_head)) | |
1da177e4 | 1005 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 | 1006 | else |
c8adf9a3 | 1007 | additional_mem_size += additional_mem_size; |
19aa7ee4 YL |
1008 | pbus_size_mem(bus, mask, IORESOURCE_MEM, |
1009 | realloc_head ? 0 : additional_mem_size, | |
1010 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1011 | break; |
1012 | } | |
1013 | } | |
c8adf9a3 RP |
1014 | |
1015 | void __ref pci_bus_size_bridges(struct pci_bus *bus) | |
1016 | { | |
1017 | __pci_bus_size_bridges(bus, NULL); | |
1018 | } | |
1da177e4 LT |
1019 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1020 | ||
568ddef8 | 1021 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
bdc4abec YL |
1022 | struct list_head *realloc_head, |
1023 | struct list_head *fail_head) | |
1da177e4 LT |
1024 | { |
1025 | struct pci_bus *b; | |
1026 | struct pci_dev *dev; | |
1027 | ||
9e8bf93a | 1028 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1029 | |
1da177e4 LT |
1030 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1031 | b = dev->subordinate; | |
1032 | if (!b) | |
1033 | continue; | |
1034 | ||
9e8bf93a | 1035 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1036 | |
1037 | switch (dev->class >> 8) { | |
1038 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1039 | if (!pci_is_enabled(dev)) |
1040 | pci_setup_bridge(b); | |
1da177e4 LT |
1041 | break; |
1042 | ||
1043 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1044 | pci_setup_cardbus(b); | |
1045 | break; | |
1046 | ||
1047 | default: | |
80ccba11 BH |
1048 | dev_info(&dev->dev, "not setting up bridge for bus " |
1049 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
1050 | break; |
1051 | } | |
1052 | } | |
1053 | } | |
568ddef8 YL |
1054 | |
1055 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
1056 | { | |
c8adf9a3 | 1057 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1058 | } |
1da177e4 LT |
1059 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1060 | ||
6841ec68 | 1061 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
bdc4abec YL |
1062 | struct list_head *add_head, |
1063 | struct list_head *fail_head) | |
6841ec68 YL |
1064 | { |
1065 | struct pci_bus *b; | |
1066 | ||
8424d759 YL |
1067 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1068 | add_head, fail_head); | |
6841ec68 YL |
1069 | |
1070 | b = bridge->subordinate; | |
1071 | if (!b) | |
1072 | return; | |
1073 | ||
8424d759 | 1074 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1075 | |
1076 | switch (bridge->class >> 8) { | |
1077 | case PCI_CLASS_BRIDGE_PCI: | |
1078 | pci_setup_bridge(b); | |
1079 | break; | |
1080 | ||
1081 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1082 | pci_setup_cardbus(b); | |
1083 | break; | |
1084 | ||
1085 | default: | |
1086 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
1087 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1088 | break; | |
1089 | } | |
1090 | } | |
5009b460 YL |
1091 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1092 | unsigned long type) | |
1093 | { | |
1094 | int idx; | |
1095 | bool changed = false; | |
1096 | struct pci_dev *dev; | |
1097 | struct resource *r; | |
1098 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1099 | IORESOURCE_PREFETCH; | |
1100 | ||
1101 | dev = bus->self; | |
1102 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
1103 | idx++) { | |
1104 | r = &dev->resource[idx]; | |
1105 | if ((r->flags & type_mask) != type) | |
1106 | continue; | |
1107 | if (!r->parent) | |
1108 | continue; | |
1109 | /* | |
1110 | * if there are children under that, we should release them | |
1111 | * all | |
1112 | */ | |
1113 | release_child_resources(r); | |
1114 | if (!release_resource(r)) { | |
1115 | dev_printk(KERN_DEBUG, &dev->dev, | |
1116 | "resource %d %pR released\n", idx, r); | |
1117 | /* keep the old size */ | |
1118 | r->end = resource_size(r) - 1; | |
1119 | r->start = 0; | |
1120 | r->flags = 0; | |
1121 | changed = true; | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | if (changed) { | |
1126 | /* avoiding touch the one without PREF */ | |
1127 | if (type & IORESOURCE_PREFETCH) | |
1128 | type = IORESOURCE_PREFETCH; | |
1129 | __pci_setup_bridge(bus, type); | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | enum release_type { | |
1134 | leaf_only, | |
1135 | whole_subtree, | |
1136 | }; | |
1137 | /* | |
1138 | * try to release pci bridge resources that is from leaf bridge, | |
1139 | * so we can allocate big new one later | |
1140 | */ | |
1141 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
1142 | unsigned long type, | |
1143 | enum release_type rel_type) | |
1144 | { | |
1145 | struct pci_dev *dev; | |
1146 | bool is_leaf_bridge = true; | |
1147 | ||
1148 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1149 | struct pci_bus *b = dev->subordinate; | |
1150 | if (!b) | |
1151 | continue; | |
1152 | ||
1153 | is_leaf_bridge = false; | |
1154 | ||
1155 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1156 | continue; | |
1157 | ||
1158 | if (rel_type == whole_subtree) | |
1159 | pci_bus_release_bridge_resources(b, type, | |
1160 | whole_subtree); | |
1161 | } | |
1162 | ||
1163 | if (pci_is_root_bus(bus)) | |
1164 | return; | |
1165 | ||
1166 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1167 | return; | |
1168 | ||
1169 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1170 | pci_bridge_release_resources(bus, type); | |
1171 | } | |
1172 | ||
76fbc263 YL |
1173 | static void pci_bus_dump_res(struct pci_bus *bus) |
1174 | { | |
89a74ecc BH |
1175 | struct resource *res; |
1176 | int i; | |
7c9342b8 | 1177 | |
89a74ecc | 1178 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1179 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
1180 | continue; |
1181 | ||
c7dabef8 | 1182 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
1183 | } |
1184 | } | |
1185 | ||
1186 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1187 | { | |
1188 | struct pci_bus *b; | |
1189 | struct pci_dev *dev; | |
1190 | ||
1191 | ||
1192 | pci_bus_dump_res(bus); | |
1193 | ||
1194 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1195 | b = dev->subordinate; | |
1196 | if (!b) | |
1197 | continue; | |
1198 | ||
1199 | pci_bus_dump_resources(b); | |
1200 | } | |
1201 | } | |
1202 | ||
da7822e5 YL |
1203 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
1204 | { | |
1205 | int depth = 0; | |
1206 | struct pci_dev *dev; | |
1207 | ||
1208 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1209 | int ret; | |
1210 | struct pci_bus *b = dev->subordinate; | |
1211 | if (!b) | |
1212 | continue; | |
1213 | ||
1214 | ret = pci_bus_get_depth(b); | |
1215 | if (ret + 1 > depth) | |
1216 | depth = ret + 1; | |
1217 | } | |
1218 | ||
1219 | return depth; | |
1220 | } | |
1221 | static int __init pci_get_max_depth(void) | |
1222 | { | |
1223 | int depth = 0; | |
1224 | struct pci_bus *bus; | |
1225 | ||
1226 | list_for_each_entry(bus, &pci_root_buses, node) { | |
1227 | int ret; | |
1228 | ||
1229 | ret = pci_bus_get_depth(bus); | |
1230 | if (ret > depth) | |
1231 | depth = ret; | |
1232 | } | |
1233 | ||
1234 | return depth; | |
1235 | } | |
1236 | ||
f483d392 | 1237 | |
da7822e5 YL |
1238 | /* |
1239 | * first try will not touch pci bridge res | |
1240 | * second and later try will clear small leaf bridge res | |
1241 | * will stop till to the max deepth if can not find good one | |
1242 | */ | |
1da177e4 LT |
1243 | void __init |
1244 | pci_assign_unassigned_resources(void) | |
1245 | { | |
1246 | struct pci_bus *bus; | |
bdc4abec | 1247 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1248 | want additional resources */ |
bdc4abec | 1249 | struct list_head *add_list = NULL; |
da7822e5 YL |
1250 | int tried_times = 0; |
1251 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1252 | LIST_HEAD(fail_head); |
b9b0bba9 | 1253 | struct pci_dev_resource *fail_res; |
da7822e5 YL |
1254 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1255 | IORESOURCE_PREFETCH; | |
1256 | unsigned long failed_type; | |
19aa7ee4 | 1257 | int pci_try_num = 1; |
da7822e5 | 1258 | |
19aa7ee4 YL |
1259 | /* don't realloc if asked to do so */ |
1260 | if (pci_realloc_enabled()) { | |
1261 | int max_depth = pci_get_max_depth(); | |
1262 | ||
1263 | pci_try_num = max_depth + 1; | |
1264 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", | |
1265 | max_depth, pci_try_num); | |
1266 | } | |
da7822e5 YL |
1267 | |
1268 | again: | |
19aa7ee4 YL |
1269 | /* |
1270 | * last try will use add_list, otherwise will try good to have as | |
1271 | * must have, so can realloc parent bridge resource | |
1272 | */ | |
1273 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1274 | add_list = &realloc_head; |
1da177e4 LT |
1275 | /* Depth first, calculate sizes and alignments of all |
1276 | subordinate buses. */ | |
da7822e5 | 1277 | list_for_each_entry(bus, &pci_root_buses, node) |
19aa7ee4 | 1278 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1279 | |
1da177e4 | 1280 | /* Depth last, allocate resources and update the hardware. */ |
da7822e5 | 1281 | list_for_each_entry(bus, &pci_root_buses, node) |
bdc4abec | 1282 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1283 | if (add_list) |
bdc4abec | 1284 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1285 | tried_times++; |
1286 | ||
1287 | /* any device complain? */ | |
bdc4abec | 1288 | if (list_empty(&fail_head)) |
da7822e5 | 1289 | goto enable_and_dump; |
f483d392 | 1290 | |
da7822e5 | 1291 | failed_type = 0; |
b9b0bba9 YL |
1292 | list_for_each_entry(fail_res, &fail_head, list) |
1293 | failed_type |= fail_res->flags; | |
bdc4abec | 1294 | |
da7822e5 YL |
1295 | /* |
1296 | * io port are tight, don't try extra | |
1297 | * or if reach the limit, don't want to try more | |
1298 | */ | |
1299 | failed_type &= type_mask; | |
1300 | if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) { | |
764242a0 | 1301 | free_list(pci_dev_resource, &fail_head); |
da7822e5 YL |
1302 | goto enable_and_dump; |
1303 | } | |
1304 | ||
1305 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1306 | tried_times + 1); | |
1307 | ||
1308 | /* third times and later will not check if it is leaf */ | |
1309 | if ((tried_times + 1) > 2) | |
1310 | rel_type = whole_subtree; | |
1311 | ||
1312 | /* | |
1313 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1314 | * child device under that bridge | |
1315 | */ | |
b9b0bba9 YL |
1316 | list_for_each_entry(fail_res, &fail_head, list) { |
1317 | bus = fail_res->dev->bus; | |
bdc4abec | 1318 | pci_bus_release_bridge_resources(bus, |
b9b0bba9 | 1319 | fail_res->flags & type_mask, |
bdc4abec | 1320 | rel_type); |
da7822e5 YL |
1321 | } |
1322 | /* restore size and flags */ | |
b9b0bba9 YL |
1323 | list_for_each_entry(fail_res, &fail_head, list) { |
1324 | struct resource *res = fail_res->res; | |
da7822e5 | 1325 | |
b9b0bba9 YL |
1326 | res->start = fail_res->start; |
1327 | res->end = fail_res->end; | |
1328 | res->flags = fail_res->flags; | |
1329 | if (fail_res->dev->subordinate) | |
da7822e5 | 1330 | res->flags = 0; |
da7822e5 | 1331 | } |
764242a0 | 1332 | free_list(pci_dev_resource, &fail_head); |
da7822e5 YL |
1333 | |
1334 | goto again; | |
1335 | ||
1336 | enable_and_dump: | |
1337 | /* Depth last, update the hardware. */ | |
1338 | list_for_each_entry(bus, &pci_root_buses, node) | |
1339 | pci_enable_bridges(bus); | |
76fbc263 YL |
1340 | |
1341 | /* dump the resource on buses */ | |
da7822e5 | 1342 | list_for_each_entry(bus, &pci_root_buses, node) |
76fbc263 | 1343 | pci_bus_dump_resources(bus); |
1da177e4 | 1344 | } |
6841ec68 YL |
1345 | |
1346 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1347 | { | |
1348 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1349 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1350 | want additional resources */ |
32180e40 | 1351 | int tried_times = 0; |
bdc4abec | 1352 | LIST_HEAD(fail_head); |
b9b0bba9 | 1353 | struct pci_dev_resource *fail_res; |
6841ec68 | 1354 | int retval; |
32180e40 YL |
1355 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1356 | IORESOURCE_PREFETCH; | |
1357 | ||
32180e40 | 1358 | again: |
8424d759 | 1359 | __pci_bus_size_bridges(parent, &add_list); |
bdc4abec YL |
1360 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1361 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
1362 | tried_times++; |
1363 | ||
bdc4abec | 1364 | if (list_empty(&fail_head)) |
3f579c34 | 1365 | goto enable_all; |
32180e40 YL |
1366 | |
1367 | if (tried_times >= 2) { | |
1368 | /* still fail, don't need to try more */ | |
764242a0 | 1369 | free_list(pci_dev_resource, &fail_head); |
3f579c34 | 1370 | goto enable_all; |
32180e40 YL |
1371 | } |
1372 | ||
1373 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1374 | tried_times + 1); | |
1375 | ||
1376 | /* | |
1377 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1378 | * child device under that bridge | |
1379 | */ | |
b9b0bba9 YL |
1380 | list_for_each_entry(fail_res, &fail_head, list) { |
1381 | struct pci_bus *bus = fail_res->dev->bus; | |
1382 | unsigned long flags = fail_res->flags; | |
32180e40 YL |
1383 | |
1384 | pci_bus_release_bridge_resources(bus, flags & type_mask, | |
1385 | whole_subtree); | |
32180e40 YL |
1386 | } |
1387 | /* restore size and flags */ | |
b9b0bba9 YL |
1388 | list_for_each_entry(fail_res, &fail_head, list) { |
1389 | struct resource *res = fail_res->res; | |
32180e40 | 1390 | |
b9b0bba9 YL |
1391 | res->start = fail_res->start; |
1392 | res->end = fail_res->end; | |
1393 | res->flags = fail_res->flags; | |
1394 | if (fail_res->dev->subordinate) | |
32180e40 | 1395 | res->flags = 0; |
32180e40 | 1396 | } |
764242a0 | 1397 | free_list(pci_dev_resource, &fail_head); |
32180e40 YL |
1398 | |
1399 | goto again; | |
3f579c34 YL |
1400 | |
1401 | enable_all: | |
1402 | retval = pci_reenable_device(bridge); | |
1403 | pci_set_master(bridge); | |
1404 | pci_enable_bridges(parent); | |
6841ec68 YL |
1405 | } |
1406 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f YL |
1407 | |
1408 | #ifdef CONFIG_HOTPLUG | |
1409 | /** | |
1410 | * pci_rescan_bus - scan a PCI bus for devices. | |
1411 | * @bus: PCI bus to scan | |
1412 | * | |
1413 | * Scan a PCI bus and child buses for new devices, adds them, | |
1414 | * and enables them. | |
1415 | * | |
1416 | * Returns the max number of subordinate bus discovered. | |
1417 | */ | |
1418 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) | |
1419 | { | |
1420 | unsigned int max; | |
1421 | struct pci_dev *dev; | |
bdc4abec | 1422 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
1423 | want additional resources */ |
1424 | ||
1425 | max = pci_scan_child_bus(bus); | |
1426 | ||
9b03088f YL |
1427 | down_read(&pci_bus_sem); |
1428 | list_for_each_entry(dev, &bus->devices, bus_list) | |
1429 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1430 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1431 | if (dev->subordinate) | |
1432 | __pci_bus_size_bridges(dev->subordinate, | |
1433 | &add_list); | |
1434 | up_read(&pci_bus_sem); | |
1435 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 1436 | BUG_ON(!list_empty(&add_list)); |
9b03088f YL |
1437 | |
1438 | pci_enable_bridges(bus); | |
1439 | pci_bus_add_devices(bus); | |
1440 | ||
1441 | return max; | |
1442 | } | |
1443 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1444 | #endif |