Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
47087700 | 28 | #include <asm-generic/pci-bridge.h> |
6faf17f6 | 29 | #include "pci.h" |
1da177e4 | 30 | |
844393f4 | 31 | unsigned int pci_flags; |
47087700 | 32 | |
bdc4abec YL |
33 | struct pci_dev_resource { |
34 | struct list_head list; | |
2934a0de YL |
35 | struct resource *res; |
36 | struct pci_dev *dev; | |
568ddef8 YL |
37 | resource_size_t start; |
38 | resource_size_t end; | |
c8adf9a3 | 39 | resource_size_t add_size; |
2bbc6942 | 40 | resource_size_t min_align; |
568ddef8 YL |
41 | unsigned long flags; |
42 | }; | |
43 | ||
bffc56d4 YL |
44 | static void free_list(struct list_head *head) |
45 | { | |
46 | struct pci_dev_resource *dev_res, *tmp; | |
47 | ||
48 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
49 | list_del(&dev_res->list); | |
50 | kfree(dev_res); | |
51 | } | |
52 | } | |
094732a5 | 53 | |
c8adf9a3 RP |
54 | /** |
55 | * add_to_list() - add a new resource tracker to the list | |
56 | * @head: Head of the list | |
57 | * @dev: device corresponding to which the resource | |
58 | * belongs | |
59 | * @res: The resource to be tracked | |
60 | * @add_size: additional size to be optionally added | |
61 | * to the resource | |
62 | */ | |
bdc4abec | 63 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 64 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 65 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 66 | { |
764242a0 | 67 | struct pci_dev_resource *tmp; |
568ddef8 | 68 | |
bdc4abec | 69 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 70 | if (!tmp) { |
c8adf9a3 | 71 | pr_warning("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 72 | return -ENOMEM; |
568ddef8 YL |
73 | } |
74 | ||
568ddef8 YL |
75 | tmp->res = res; |
76 | tmp->dev = dev; | |
77 | tmp->start = res->start; | |
78 | tmp->end = res->end; | |
79 | tmp->flags = res->flags; | |
c8adf9a3 | 80 | tmp->add_size = add_size; |
2bbc6942 | 81 | tmp->min_align = min_align; |
bdc4abec YL |
82 | |
83 | list_add(&tmp->list, head); | |
ef62dfef YL |
84 | |
85 | return 0; | |
568ddef8 YL |
86 | } |
87 | ||
b9b0bba9 | 88 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
89 | struct resource *res) |
90 | { | |
b9b0bba9 | 91 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 92 | |
b9b0bba9 YL |
93 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
94 | if (dev_res->res == res) { | |
95 | list_del(&dev_res->list); | |
96 | kfree(dev_res); | |
bdc4abec | 97 | break; |
3e6e0d80 | 98 | } |
3e6e0d80 YL |
99 | } |
100 | } | |
101 | ||
b9b0bba9 | 102 | static resource_size_t get_res_add_size(struct list_head *head, |
1c372353 YL |
103 | struct resource *res) |
104 | { | |
b9b0bba9 | 105 | struct pci_dev_resource *dev_res; |
bdc4abec | 106 | |
b9b0bba9 YL |
107 | list_for_each_entry(dev_res, head, list) { |
108 | if (dev_res->res == res) { | |
b592443d YL |
109 | int idx = res - &dev_res->dev->resource[0]; |
110 | ||
b9b0bba9 | 111 | dev_printk(KERN_DEBUG, &dev_res->dev->dev, |
b592443d YL |
112 | "res[%d]=%pR get_res_add_size add_size %llx\n", |
113 | idx, dev_res->res, | |
b9b0bba9 | 114 | (unsigned long long)dev_res->add_size); |
b592443d | 115 | |
b9b0bba9 | 116 | return dev_res->add_size; |
bdc4abec | 117 | } |
3e6e0d80 | 118 | } |
1c372353 YL |
119 | |
120 | return 0; | |
121 | } | |
122 | ||
78c3b329 | 123 | /* Sort resources by alignment */ |
bdc4abec | 124 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
125 | { |
126 | int i; | |
127 | ||
128 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
129 | struct resource *r; | |
bdc4abec | 130 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 131 | resource_size_t r_align; |
bdc4abec | 132 | struct list_head *n; |
78c3b329 YL |
133 | |
134 | r = &dev->resource[i]; | |
135 | ||
136 | if (r->flags & IORESOURCE_PCI_FIXED) | |
137 | continue; | |
138 | ||
139 | if (!(r->flags) || r->parent) | |
140 | continue; | |
141 | ||
142 | r_align = pci_resource_alignment(dev, r); | |
143 | if (!r_align) { | |
144 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
145 | i, r); | |
146 | continue; | |
147 | } | |
78c3b329 | 148 | |
bdc4abec YL |
149 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
150 | if (!tmp) | |
151 | panic("pdev_sort_resources(): " | |
152 | "kmalloc() failed!\n"); | |
153 | tmp->res = r; | |
154 | tmp->dev = dev; | |
155 | ||
156 | /* fallback is smallest one or list is empty*/ | |
157 | n = head; | |
158 | list_for_each_entry(dev_res, head, list) { | |
159 | resource_size_t align; | |
160 | ||
161 | align = pci_resource_alignment(dev_res->dev, | |
162 | dev_res->res); | |
78c3b329 YL |
163 | |
164 | if (r_align > align) { | |
bdc4abec | 165 | n = &dev_res->list; |
78c3b329 YL |
166 | break; |
167 | } | |
168 | } | |
bdc4abec YL |
169 | /* Insert it just before n*/ |
170 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
171 | } |
172 | } | |
173 | ||
6841ec68 | 174 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 175 | struct list_head *head) |
1da177e4 | 176 | { |
6841ec68 | 177 | u16 class = dev->class >> 8; |
1da177e4 | 178 | |
6841ec68 YL |
179 | /* Don't touch classless devices or host bridges or ioapics. */ |
180 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
181 | return; | |
1da177e4 | 182 | |
6841ec68 YL |
183 | /* Don't touch ioapic devices already enabled by firmware */ |
184 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
185 | u16 command; | |
186 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
187 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
188 | return; | |
189 | } | |
1da177e4 | 190 | |
6841ec68 YL |
191 | pdev_sort_resources(dev, head); |
192 | } | |
23186279 | 193 | |
fc075e1d RP |
194 | static inline void reset_resource(struct resource *res) |
195 | { | |
196 | res->start = 0; | |
197 | res->end = 0; | |
198 | res->flags = 0; | |
199 | } | |
200 | ||
c8adf9a3 | 201 | /** |
9e8bf93a | 202 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 203 | * |
9e8bf93a | 204 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
205 | * resources |
206 | * @head : head of the list tracking requests with allocated | |
207 | * resources | |
208 | * | |
9e8bf93a | 209 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
210 | * additional resources for the element, provided the element |
211 | * is in the head list. | |
212 | */ | |
bdc4abec YL |
213 | static void reassign_resources_sorted(struct list_head *realloc_head, |
214 | struct list_head *head) | |
6841ec68 YL |
215 | { |
216 | struct resource *res; | |
b9b0bba9 | 217 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 218 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 219 | resource_size_t add_size; |
6841ec68 | 220 | int idx; |
1da177e4 | 221 | |
b9b0bba9 | 222 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
223 | bool found_match = false; |
224 | ||
b9b0bba9 | 225 | res = add_res->res; |
c8adf9a3 RP |
226 | /* skip resource that has been reset */ |
227 | if (!res->flags) | |
228 | goto out; | |
229 | ||
230 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
231 | list_for_each_entry(dev_res, head, list) { |
232 | if (dev_res->res == res) { | |
233 | found_match = true; | |
234 | break; | |
235 | } | |
c8adf9a3 | 236 | } |
bdc4abec YL |
237 | if (!found_match)/* just skip */ |
238 | continue; | |
c8adf9a3 | 239 | |
b9b0bba9 YL |
240 | idx = res - &add_res->dev->resource[0]; |
241 | add_size = add_res->add_size; | |
2bbc6942 | 242 | if (!resource_size(res)) { |
b9b0bba9 | 243 | res->start = add_res->start; |
2bbc6942 | 244 | res->end = res->start + add_size - 1; |
b9b0bba9 | 245 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 246 | reset_resource(res); |
2bbc6942 | 247 | } else { |
b9b0bba9 YL |
248 | resource_size_t align = add_res->min_align; |
249 | res->flags |= add_res->flags & | |
bdc4abec | 250 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 251 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 252 | add_size, align)) |
b9b0bba9 | 253 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
b592443d YL |
254 | "failed to add %llx res[%d]=%pR\n", |
255 | (unsigned long long)add_size, | |
256 | idx, res); | |
c8adf9a3 RP |
257 | } |
258 | out: | |
b9b0bba9 YL |
259 | list_del(&add_res->list); |
260 | kfree(add_res); | |
c8adf9a3 RP |
261 | } |
262 | } | |
263 | ||
264 | /** | |
265 | * assign_requested_resources_sorted() - satisfy resource requests | |
266 | * | |
267 | * @head : head of the list tracking requests for resources | |
268 | * @failed_list : head of the list tracking requests that could | |
269 | * not be allocated | |
270 | * | |
271 | * Satisfy resource requests of each element in the list. Add | |
272 | * requests that could not satisfied to the failed_list. | |
273 | */ | |
bdc4abec YL |
274 | static void assign_requested_resources_sorted(struct list_head *head, |
275 | struct list_head *fail_head) | |
c8adf9a3 RP |
276 | { |
277 | struct resource *res; | |
bdc4abec | 278 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 279 | int idx; |
9a928660 | 280 | |
bdc4abec YL |
281 | list_for_each_entry(dev_res, head, list) { |
282 | res = dev_res->res; | |
283 | idx = res - &dev_res->dev->resource[0]; | |
284 | if (resource_size(res) && | |
285 | pci_assign_resource(dev_res->dev, idx)) { | |
286 | if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) { | |
9a928660 YL |
287 | /* |
288 | * if the failed res is for ROM BAR, and it will | |
289 | * be enabled later, don't add it to the list | |
290 | */ | |
291 | if (!((idx == PCI_ROM_RESOURCE) && | |
292 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
67cc7e26 YL |
293 | add_to_list(fail_head, |
294 | dev_res->dev, res, | |
295 | 0 /* dont care */, | |
296 | 0 /* dont care */); | |
9a928660 | 297 | } |
fc075e1d | 298 | reset_resource(res); |
542df5de | 299 | } |
1da177e4 LT |
300 | } |
301 | } | |
302 | ||
bdc4abec YL |
303 | static void __assign_resources_sorted(struct list_head *head, |
304 | struct list_head *realloc_head, | |
305 | struct list_head *fail_head) | |
c8adf9a3 | 306 | { |
3e6e0d80 YL |
307 | /* |
308 | * Should not assign requested resources at first. | |
309 | * they could be adjacent, so later reassign can not reallocate | |
310 | * them one by one in parent resource window. | |
311 | * Try to assign requested + add_size at begining | |
312 | * if could do that, could get out early. | |
313 | * if could not do that, we still try to assign requested at first, | |
314 | * then try to reassign add_size for some resources. | |
315 | */ | |
bdc4abec YL |
316 | LIST_HEAD(save_head); |
317 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 318 | struct pci_dev_resource *save_res; |
bdc4abec | 319 | struct pci_dev_resource *dev_res; |
3e6e0d80 YL |
320 | |
321 | /* Check if optional add_size is there */ | |
bdc4abec | 322 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
323 | goto requested_and_reassign; |
324 | ||
325 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
326 | list_for_each_entry(dev_res, head, list) { |
327 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 328 | free_list(&save_head); |
3e6e0d80 YL |
329 | goto requested_and_reassign; |
330 | } | |
bdc4abec | 331 | } |
3e6e0d80 YL |
332 | |
333 | /* Update res in head list with add_size in realloc_head list */ | |
bdc4abec YL |
334 | list_for_each_entry(dev_res, head, list) |
335 | dev_res->res->end += get_res_add_size(realloc_head, | |
336 | dev_res->res); | |
3e6e0d80 YL |
337 | |
338 | /* Try updated head list with add_size added */ | |
3e6e0d80 YL |
339 | assign_requested_resources_sorted(head, &local_fail_head); |
340 | ||
341 | /* all assigned with add_size ? */ | |
bdc4abec | 342 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 343 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
344 | list_for_each_entry(dev_res, head, list) |
345 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
346 | free_list(&save_head); |
347 | free_list(head); | |
3e6e0d80 YL |
348 | return; |
349 | } | |
350 | ||
bffc56d4 | 351 | free_list(&local_fail_head); |
3e6e0d80 | 352 | /* Release assigned resource */ |
bdc4abec YL |
353 | list_for_each_entry(dev_res, head, list) |
354 | if (dev_res->res->parent) | |
355 | release_resource(dev_res->res); | |
3e6e0d80 | 356 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
357 | list_for_each_entry(save_res, &save_head, list) { |
358 | struct resource *res = save_res->res; | |
3e6e0d80 | 359 | |
b9b0bba9 YL |
360 | res->start = save_res->start; |
361 | res->end = save_res->end; | |
362 | res->flags = save_res->flags; | |
3e6e0d80 | 363 | } |
bffc56d4 | 364 | free_list(&save_head); |
3e6e0d80 YL |
365 | |
366 | requested_and_reassign: | |
c8adf9a3 RP |
367 | /* Satisfy the must-have resource requests */ |
368 | assign_requested_resources_sorted(head, fail_head); | |
369 | ||
0a2daa1c | 370 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 371 | requests */ |
9e8bf93a RP |
372 | if (realloc_head) |
373 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 374 | free_list(head); |
c8adf9a3 RP |
375 | } |
376 | ||
6841ec68 | 377 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
378 | struct list_head *add_head, |
379 | struct list_head *fail_head) | |
6841ec68 | 380 | { |
bdc4abec | 381 | LIST_HEAD(head); |
6841ec68 | 382 | |
6841ec68 | 383 | __dev_sort_resources(dev, &head); |
8424d759 | 384 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
385 | |
386 | } | |
387 | ||
388 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
389 | struct list_head *realloc_head, |
390 | struct list_head *fail_head) | |
6841ec68 YL |
391 | { |
392 | struct pci_dev *dev; | |
bdc4abec | 393 | LIST_HEAD(head); |
6841ec68 | 394 | |
6841ec68 YL |
395 | list_for_each_entry(dev, &bus->devices, bus_list) |
396 | __dev_sort_resources(dev, &head); | |
397 | ||
9e8bf93a | 398 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
399 | } |
400 | ||
b3743fa4 | 401 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
402 | { |
403 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 404 | struct resource *res; |
1da177e4 LT |
405 | struct pci_bus_region region; |
406 | ||
865df576 BH |
407 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
408 | bus->secondary, bus->subordinate); | |
1da177e4 | 409 | |
c7dabef8 BH |
410 | res = bus->resource[0]; |
411 | pcibios_resource_to_bus(bridge, ®ion, res); | |
412 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
413 | /* |
414 | * The IO resource is allocated a range twice as large as it | |
415 | * would normally need. This allows us to set both IO regs. | |
416 | */ | |
c7dabef8 | 417 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
418 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
419 | region.start); | |
420 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
421 | region.end); | |
422 | } | |
423 | ||
c7dabef8 BH |
424 | res = bus->resource[1]; |
425 | pcibios_resource_to_bus(bridge, ®ion, res); | |
426 | if (res->flags & IORESOURCE_IO) { | |
427 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
428 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
429 | region.start); | |
430 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
431 | region.end); | |
432 | } | |
433 | ||
c7dabef8 BH |
434 | res = bus->resource[2]; |
435 | pcibios_resource_to_bus(bridge, ®ion, res); | |
436 | if (res->flags & IORESOURCE_MEM) { | |
437 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
438 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
439 | region.start); | |
440 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
441 | region.end); | |
442 | } | |
443 | ||
c7dabef8 BH |
444 | res = bus->resource[3]; |
445 | pcibios_resource_to_bus(bridge, ®ion, res); | |
446 | if (res->flags & IORESOURCE_MEM) { | |
447 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
448 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
449 | region.start); | |
450 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
451 | region.end); | |
452 | } | |
453 | } | |
b3743fa4 | 454 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
455 | |
456 | /* Initialize bridges with base/limit values we have collected. | |
457 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
458 | requires that if there is no I/O ports or memory behind the | |
459 | bridge, corresponding range must be turned off by writing base | |
460 | value greater than limit to the bridge's base/limit registers. | |
461 | ||
462 | Note: care must be taken when updating I/O base/limit registers | |
463 | of bridges which support 32-bit I/O. This update requires two | |
464 | config space writes, so it's quite possible that an I/O window of | |
465 | the bridge will have some undesirable address (e.g. 0) after the | |
466 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 467 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
468 | { |
469 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 470 | struct resource *res; |
1da177e4 | 471 | struct pci_bus_region region; |
7cc5997d | 472 | u32 l, io_upper16; |
1da177e4 LT |
473 | |
474 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
475 | res = bus->resource[0]; |
476 | pcibios_resource_to_bus(bridge, ®ion, res); | |
477 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
478 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
479 | l &= 0xffff0000; | |
480 | l |= (region.start >> 8) & 0x00f0; | |
481 | l |= region.end & 0xf000; | |
482 | /* Set up upper 16 bits of I/O base/limit. */ | |
483 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 484 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 485 | } else { |
1da177e4 LT |
486 | /* Clear upper 16 bits of I/O base/limit. */ |
487 | io_upper16 = 0; | |
488 | l = 0x00f0; | |
1da177e4 LT |
489 | } |
490 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
491 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
492 | /* Update lower 16 bits of I/O base/limit. */ | |
493 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
494 | /* Update upper 16 bits of I/O base/limit. */ | |
495 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
496 | } |
497 | ||
498 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
499 | { | |
500 | struct pci_dev *bridge = bus->self; | |
501 | struct resource *res; | |
502 | struct pci_bus_region region; | |
503 | u32 l; | |
1da177e4 | 504 | |
7cc5997d | 505 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
506 | res = bus->resource[1]; |
507 | pcibios_resource_to_bus(bridge, ®ion, res); | |
508 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
509 | l = (region.start >> 16) & 0xfff0; |
510 | l |= region.end & 0xfff00000; | |
c7dabef8 | 511 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 512 | } else { |
1da177e4 | 513 | l = 0x0000fff0; |
1da177e4 LT |
514 | } |
515 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
516 | } |
517 | ||
518 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
519 | { | |
520 | struct pci_dev *bridge = bus->self; | |
521 | struct resource *res; | |
522 | struct pci_bus_region region; | |
523 | u32 l, bu, lu; | |
1da177e4 LT |
524 | |
525 | /* Clear out the upper 32 bits of PREF limit. | |
526 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
527 | disables PREF range, which is ok. */ | |
528 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
529 | ||
530 | /* Set up PREF base/limit. */ | |
c40a22e0 | 531 | bu = lu = 0; |
c7dabef8 BH |
532 | res = bus->resource[2]; |
533 | pcibios_resource_to_bus(bridge, ®ion, res); | |
534 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
535 | l = (region.start >> 16) & 0xfff0; |
536 | l |= region.end & 0xfff00000; | |
c7dabef8 | 537 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
538 | bu = upper_32_bits(region.start); |
539 | lu = upper_32_bits(region.end); | |
1f82de10 | 540 | } |
c7dabef8 | 541 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 542 | } else { |
1da177e4 | 543 | l = 0x0000fff0; |
1da177e4 LT |
544 | } |
545 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
546 | ||
59353ea3 AW |
547 | /* Set the upper 32 bits of PREF base & limit. */ |
548 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
549 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
550 | } |
551 | ||
552 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
553 | { | |
554 | struct pci_dev *bridge = bus->self; | |
555 | ||
7cc5997d YL |
556 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
557 | bus->secondary, bus->subordinate); | |
558 | ||
559 | if (type & IORESOURCE_IO) | |
560 | pci_setup_bridge_io(bus); | |
561 | ||
562 | if (type & IORESOURCE_MEM) | |
563 | pci_setup_bridge_mmio(bus); | |
564 | ||
565 | if (type & IORESOURCE_PREFETCH) | |
566 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
567 | |
568 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
569 | } | |
570 | ||
e2444273 | 571 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
572 | { |
573 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
574 | IORESOURCE_PREFETCH; | |
575 | ||
576 | __pci_setup_bridge(bus, type); | |
577 | } | |
578 | ||
1da177e4 LT |
579 | /* Check whether the bridge supports optional I/O and |
580 | prefetchable memory ranges. If not, the respective | |
581 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 582 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
583 | { |
584 | u16 io; | |
585 | u32 pmem; | |
586 | struct pci_dev *bridge = bus->self; | |
587 | struct resource *b_res; | |
588 | ||
589 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
590 | b_res[1].flags |= IORESOURCE_MEM; | |
591 | ||
592 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
593 | if (!io) { | |
594 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
595 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
596 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
597 | } | |
598 | if (io) | |
599 | b_res[0].flags |= IORESOURCE_IO; | |
600 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
601 | disconnect boundary by one PCI data phase. | |
602 | Workaround: do not use prefetching on this device. */ | |
603 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
604 | return; | |
605 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
606 | if (!pmem) { | |
607 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
608 | 0xfff0fff0); | |
609 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
610 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
611 | } | |
1f82de10 | 612 | if (pmem) { |
1da177e4 | 613 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
614 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
615 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 616 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
617 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
618 | } | |
1f82de10 YL |
619 | } |
620 | ||
621 | /* double check if bridge does support 64 bit pref */ | |
622 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
623 | u32 mem_base_hi, tmp; | |
624 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
625 | &mem_base_hi); | |
626 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
627 | 0xffffffff); | |
628 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
629 | if (!tmp) | |
630 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
631 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
632 | mem_base_hi); | |
633 | } | |
1da177e4 LT |
634 | } |
635 | ||
636 | /* Helper function for sizing routines: find first available | |
637 | bus resource of a given type. Note: we intentionally skip | |
638 | the bus resources which have already been assigned (that is, | |
639 | have non-NULL parent resource). */ | |
96bde06a | 640 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
641 | { |
642 | int i; | |
643 | struct resource *r; | |
644 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
645 | IORESOURCE_PREFETCH; | |
646 | ||
89a74ecc | 647 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
648 | if (r == &ioport_resource || r == &iomem_resource) |
649 | continue; | |
55a10984 JB |
650 | if (r && (r->flags & type_mask) == type && !r->parent) |
651 | return r; | |
1da177e4 LT |
652 | } |
653 | return NULL; | |
654 | } | |
655 | ||
13583b16 RP |
656 | static resource_size_t calculate_iosize(resource_size_t size, |
657 | resource_size_t min_size, | |
658 | resource_size_t size1, | |
659 | resource_size_t old_size, | |
660 | resource_size_t align) | |
661 | { | |
662 | if (size < min_size) | |
663 | size = min_size; | |
664 | if (old_size == 1 ) | |
665 | old_size = 0; | |
666 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
667 | flag in the struct pci_bus. */ | |
668 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
669 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
670 | #endif | |
671 | size = ALIGN(size + size1, align); | |
672 | if (size < old_size) | |
673 | size = old_size; | |
674 | return size; | |
675 | } | |
676 | ||
677 | static resource_size_t calculate_memsize(resource_size_t size, | |
678 | resource_size_t min_size, | |
679 | resource_size_t size1, | |
680 | resource_size_t old_size, | |
681 | resource_size_t align) | |
682 | { | |
683 | if (size < min_size) | |
684 | size = min_size; | |
685 | if (old_size == 1 ) | |
686 | old_size = 0; | |
687 | if (size < old_size) | |
688 | size = old_size; | |
689 | size = ALIGN(size + size1, align); | |
690 | return size; | |
691 | } | |
692 | ||
c8adf9a3 RP |
693 | /** |
694 | * pbus_size_io() - size the io window of a given bus | |
695 | * | |
696 | * @bus : the bus | |
697 | * @min_size : the minimum io window that must to be allocated | |
698 | * @add_size : additional optional io window | |
9e8bf93a | 699 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
700 | * |
701 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
702 | * since these windows have 4K granularity and the IO ranges | |
703 | * of non-bridge PCI devices are limited to 256 bytes. | |
704 | * We must be careful with the ISA aliasing though. | |
705 | */ | |
706 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 707 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
708 | { |
709 | struct pci_dev *dev; | |
710 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
c8adf9a3 | 711 | unsigned long size = 0, size0 = 0, size1 = 0; |
be768912 | 712 | resource_size_t children_add_size = 0; |
1da177e4 LT |
713 | |
714 | if (!b_res) | |
715 | return; | |
716 | ||
717 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
718 | int i; | |
719 | ||
720 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
721 | struct resource *r = &dev->resource[i]; | |
722 | unsigned long r_size; | |
723 | ||
724 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
725 | continue; | |
022edd86 | 726 | r_size = resource_size(r); |
1da177e4 LT |
727 | |
728 | if (r_size < 0x400) | |
729 | /* Might be re-aligned for ISA */ | |
730 | size += r_size; | |
731 | else | |
732 | size1 += r_size; | |
be768912 | 733 | |
9e8bf93a RP |
734 | if (realloc_head) |
735 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
736 | } |
737 | } | |
c8adf9a3 RP |
738 | size0 = calculate_iosize(size, min_size, size1, |
739 | resource_size(b_res), 4096); | |
be768912 YL |
740 | if (children_add_size > add_size) |
741 | add_size = children_add_size; | |
9e8bf93a | 742 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 743 | calculate_iosize(size, min_size, add_size + size1, |
13583b16 | 744 | resource_size(b_res), 4096); |
c8adf9a3 | 745 | if (!size0 && !size1) { |
865df576 BH |
746 | if (b_res->start || b_res->end) |
747 | dev_info(&bus->self->dev, "disabling bridge window " | |
748 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
749 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
750 | b_res->flags = 0; |
751 | return; | |
752 | } | |
753 | /* Alignment of the IO window is always 4K */ | |
754 | b_res->start = 4096; | |
c8adf9a3 | 755 | b_res->end = b_res->start + size0 - 1; |
88452565 | 756 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 757 | if (size1 > size0 && realloc_head) { |
9e8bf93a | 758 | add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096); |
b592443d YL |
759 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " |
760 | "%pR to [bus %02x-%02x] add_size %lx\n", b_res, | |
761 | bus->secondary, bus->subordinate, size1-size0); | |
762 | } | |
1da177e4 LT |
763 | } |
764 | ||
c8adf9a3 RP |
765 | /** |
766 | * pbus_size_mem() - size the memory window of a given bus | |
767 | * | |
768 | * @bus : the bus | |
769 | * @min_size : the minimum memory window that must to be allocated | |
770 | * @add_size : additional optional memory window | |
9e8bf93a | 771 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
772 | * |
773 | * Calculate the size of the bus and minimal alignment which | |
774 | * guarantees that all child resources fit in this size. | |
775 | */ | |
28760489 | 776 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
c8adf9a3 RP |
777 | unsigned long type, resource_size_t min_size, |
778 | resource_size_t add_size, | |
bdc4abec | 779 | struct list_head *realloc_head) |
1da177e4 LT |
780 | { |
781 | struct pci_dev *dev; | |
c8adf9a3 | 782 | resource_size_t min_align, align, size, size0, size1; |
c40a22e0 | 783 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
784 | int order, max_order; |
785 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 786 | unsigned int mem64_mask = 0; |
be768912 | 787 | resource_size_t children_add_size = 0; |
1da177e4 LT |
788 | |
789 | if (!b_res) | |
790 | return 0; | |
791 | ||
792 | memset(aligns, 0, sizeof(aligns)); | |
793 | max_order = 0; | |
794 | size = 0; | |
795 | ||
1f82de10 YL |
796 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
797 | b_res->flags &= ~IORESOURCE_MEM_64; | |
798 | ||
1da177e4 LT |
799 | list_for_each_entry(dev, &bus->devices, bus_list) { |
800 | int i; | |
1f82de10 | 801 | |
1da177e4 LT |
802 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
803 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 804 | resource_size_t r_size; |
1da177e4 LT |
805 | |
806 | if (r->parent || (r->flags & mask) != type) | |
807 | continue; | |
022edd86 | 808 | r_size = resource_size(r); |
2aceefcb YL |
809 | #ifdef CONFIG_PCI_IOV |
810 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 811 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb YL |
812 | i <= PCI_IOV_RESOURCE_END) { |
813 | r->end = r->start - 1; | |
9e8bf93a | 814 | add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); |
2aceefcb YL |
815 | children_add_size += r_size; |
816 | continue; | |
817 | } | |
818 | #endif | |
1da177e4 | 819 | /* For bridges size != alignment */ |
6faf17f6 | 820 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
821 | order = __ffs(align) - 20; |
822 | if (order > 11) { | |
865df576 BH |
823 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
824 | "(bad alignment %#llx)\n", i, r, | |
825 | (unsigned long long) align); | |
1da177e4 LT |
826 | r->flags = 0; |
827 | continue; | |
828 | } | |
829 | size += r_size; | |
830 | if (order < 0) | |
831 | order = 0; | |
832 | /* Exclude ranges with size > align from | |
833 | calculation of the alignment. */ | |
834 | if (r_size == align) | |
835 | aligns[order] += align; | |
836 | if (order > max_order) | |
837 | max_order = order; | |
1f82de10 | 838 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
be768912 | 839 | |
9e8bf93a RP |
840 | if (realloc_head) |
841 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
842 | } |
843 | } | |
1da177e4 LT |
844 | align = 0; |
845 | min_align = 0; | |
846 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
847 | resource_size_t align1 = 1; |
848 | ||
849 | align1 <<= (order + 20); | |
850 | ||
1da177e4 LT |
851 | if (!align) |
852 | min_align = align1; | |
6f6f8c2f | 853 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
854 | min_align = align1 >> 1; |
855 | align += aligns[order]; | |
856 | } | |
b42282e5 | 857 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
be768912 YL |
858 | if (children_add_size > add_size) |
859 | add_size = children_add_size; | |
9e8bf93a | 860 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 861 | calculate_memsize(size, min_size, add_size, |
b42282e5 | 862 | resource_size(b_res), min_align); |
c8adf9a3 | 863 | if (!size0 && !size1) { |
865df576 BH |
864 | if (b_res->start || b_res->end) |
865 | dev_info(&bus->self->dev, "disabling bridge window " | |
866 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
867 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
868 | b_res->flags = 0; |
869 | return 1; | |
870 | } | |
871 | b_res->start = min_align; | |
c8adf9a3 RP |
872 | b_res->end = size0 + min_align - 1; |
873 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; | |
b592443d | 874 | if (size1 > size0 && realloc_head) { |
9e8bf93a | 875 | add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); |
b592443d YL |
876 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " |
877 | "%pR to [bus %02x-%02x] add_size %llx\n", b_res, | |
878 | bus->secondary, bus->subordinate, (unsigned long long)size1-size0); | |
879 | } | |
1da177e4 LT |
880 | return 1; |
881 | } | |
882 | ||
0a2daa1c RP |
883 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
884 | { | |
885 | if (res->flags & IORESOURCE_IO) | |
886 | return pci_cardbus_io_size; | |
887 | if (res->flags & IORESOURCE_MEM) | |
888 | return pci_cardbus_mem_size; | |
889 | return 0; | |
890 | } | |
891 | ||
892 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 893 | struct list_head *realloc_head) |
1da177e4 LT |
894 | { |
895 | struct pci_dev *bridge = bus->self; | |
896 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
11848934 | 897 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
1da177e4 LT |
898 | u16 ctrl; |
899 | ||
3796f1e2 YL |
900 | if (b_res[0].parent) |
901 | goto handle_b_res_1; | |
1da177e4 LT |
902 | /* |
903 | * Reserve some resources for CardBus. We reserve | |
904 | * a fixed amount of bus space for CardBus bridges. | |
905 | */ | |
11848934 YL |
906 | b_res[0].start = pci_cardbus_io_size; |
907 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; | |
908 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
909 | if (realloc_head) { | |
910 | b_res[0].end -= pci_cardbus_io_size; | |
911 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, | |
912 | pci_cardbus_io_size); | |
913 | } | |
1da177e4 | 914 | |
3796f1e2 YL |
915 | handle_b_res_1: |
916 | if (b_res[1].parent) | |
917 | goto handle_b_res_2; | |
11848934 YL |
918 | b_res[1].start = pci_cardbus_io_size; |
919 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; | |
920 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
921 | if (realloc_head) { | |
922 | b_res[1].end -= pci_cardbus_io_size; | |
923 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, | |
924 | pci_cardbus_io_size); | |
925 | } | |
1da177e4 | 926 | |
3796f1e2 | 927 | handle_b_res_2: |
dcef0d06 YL |
928 | /* MEM1 must not be pref mmio */ |
929 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
930 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { | |
931 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; | |
932 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
933 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
934 | } | |
935 | ||
1da177e4 LT |
936 | /* |
937 | * Check whether prefetchable memory is supported | |
938 | * by this bridge. | |
939 | */ | |
940 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
941 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
942 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
943 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
944 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
945 | } | |
946 | ||
3796f1e2 YL |
947 | if (b_res[2].parent) |
948 | goto handle_b_res_3; | |
1da177e4 LT |
949 | /* |
950 | * If we have prefetchable memory support, allocate | |
951 | * two regions. Otherwise, allocate one region of | |
952 | * twice the size. | |
953 | */ | |
954 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
11848934 YL |
955 | b_res[2].start = pci_cardbus_mem_size; |
956 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; | |
957 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | | |
958 | IORESOURCE_STARTALIGN; | |
959 | if (realloc_head) { | |
960 | b_res[2].end -= pci_cardbus_mem_size; | |
961 | add_to_list(realloc_head, bridge, b_res+2, | |
962 | pci_cardbus_mem_size, pci_cardbus_mem_size); | |
963 | } | |
964 | ||
965 | /* reduce that to half */ | |
966 | b_res_3_size = pci_cardbus_mem_size; | |
967 | } | |
968 | ||
3796f1e2 YL |
969 | handle_b_res_3: |
970 | if (b_res[3].parent) | |
971 | goto handle_done; | |
11848934 YL |
972 | b_res[3].start = pci_cardbus_mem_size; |
973 | b_res[3].end = b_res[3].start + b_res_3_size - 1; | |
974 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; | |
975 | if (realloc_head) { | |
976 | b_res[3].end -= b_res_3_size; | |
977 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, | |
978 | pci_cardbus_mem_size); | |
979 | } | |
3796f1e2 YL |
980 | |
981 | handle_done: | |
982 | ; | |
1da177e4 LT |
983 | } |
984 | ||
c8adf9a3 | 985 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
bdc4abec | 986 | struct list_head *realloc_head) |
1da177e4 LT |
987 | { |
988 | struct pci_dev *dev; | |
989 | unsigned long mask, prefmask; | |
c8adf9a3 | 990 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1da177e4 LT |
991 | |
992 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
993 | struct pci_bus *b = dev->subordinate; | |
994 | if (!b) | |
995 | continue; | |
996 | ||
997 | switch (dev->class >> 8) { | |
998 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 999 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
1000 | break; |
1001 | ||
1002 | case PCI_CLASS_BRIDGE_PCI: | |
1003 | default: | |
9e8bf93a | 1004 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
1005 | break; |
1006 | } | |
1007 | } | |
1008 | ||
1009 | /* The root bus? */ | |
1010 | if (!bus->self) | |
1011 | return; | |
1012 | ||
1013 | switch (bus->self->class >> 8) { | |
1014 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1015 | /* don't size cardbuses yet. */ | |
1016 | break; | |
1017 | ||
1018 | case PCI_CLASS_BRIDGE_PCI: | |
1019 | pci_bridge_check_ranges(bus); | |
28760489 | 1020 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
1021 | additional_io_size = pci_hotplug_io_size; |
1022 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 1023 | } |
c8adf9a3 RP |
1024 | /* |
1025 | * Follow thru | |
1026 | */ | |
1da177e4 | 1027 | default: |
19aa7ee4 YL |
1028 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1029 | additional_io_size, realloc_head); | |
1da177e4 LT |
1030 | /* If the bridge supports prefetchable range, size it |
1031 | separately. If it doesn't, or its prefetchable window | |
1032 | has already been allocated by arch code, try | |
1033 | non-prefetchable range for both types of PCI memory | |
1034 | resources. */ | |
1035 | mask = IORESOURCE_MEM; | |
1036 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
19aa7ee4 YL |
1037 | if (pbus_size_mem(bus, prefmask, prefmask, |
1038 | realloc_head ? 0 : additional_mem_size, | |
1039 | additional_mem_size, realloc_head)) | |
1da177e4 | 1040 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 | 1041 | else |
c8adf9a3 | 1042 | additional_mem_size += additional_mem_size; |
19aa7ee4 YL |
1043 | pbus_size_mem(bus, mask, IORESOURCE_MEM, |
1044 | realloc_head ? 0 : additional_mem_size, | |
1045 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1046 | break; |
1047 | } | |
1048 | } | |
c8adf9a3 RP |
1049 | |
1050 | void __ref pci_bus_size_bridges(struct pci_bus *bus) | |
1051 | { | |
1052 | __pci_bus_size_bridges(bus, NULL); | |
1053 | } | |
1da177e4 LT |
1054 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1055 | ||
568ddef8 | 1056 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
bdc4abec YL |
1057 | struct list_head *realloc_head, |
1058 | struct list_head *fail_head) | |
1da177e4 LT |
1059 | { |
1060 | struct pci_bus *b; | |
1061 | struct pci_dev *dev; | |
1062 | ||
9e8bf93a | 1063 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1064 | |
1da177e4 LT |
1065 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1066 | b = dev->subordinate; | |
1067 | if (!b) | |
1068 | continue; | |
1069 | ||
9e8bf93a | 1070 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1071 | |
1072 | switch (dev->class >> 8) { | |
1073 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1074 | if (!pci_is_enabled(dev)) |
1075 | pci_setup_bridge(b); | |
1da177e4 LT |
1076 | break; |
1077 | ||
1078 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1079 | pci_setup_cardbus(b); | |
1080 | break; | |
1081 | ||
1082 | default: | |
80ccba11 BH |
1083 | dev_info(&dev->dev, "not setting up bridge for bus " |
1084 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
1085 | break; |
1086 | } | |
1087 | } | |
1088 | } | |
568ddef8 YL |
1089 | |
1090 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
1091 | { | |
c8adf9a3 | 1092 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1093 | } |
1da177e4 LT |
1094 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1095 | ||
6841ec68 | 1096 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
bdc4abec YL |
1097 | struct list_head *add_head, |
1098 | struct list_head *fail_head) | |
6841ec68 YL |
1099 | { |
1100 | struct pci_bus *b; | |
1101 | ||
8424d759 YL |
1102 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1103 | add_head, fail_head); | |
6841ec68 YL |
1104 | |
1105 | b = bridge->subordinate; | |
1106 | if (!b) | |
1107 | return; | |
1108 | ||
8424d759 | 1109 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1110 | |
1111 | switch (bridge->class >> 8) { | |
1112 | case PCI_CLASS_BRIDGE_PCI: | |
1113 | pci_setup_bridge(b); | |
1114 | break; | |
1115 | ||
1116 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1117 | pci_setup_cardbus(b); | |
1118 | break; | |
1119 | ||
1120 | default: | |
1121 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
1122 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1123 | break; | |
1124 | } | |
1125 | } | |
5009b460 YL |
1126 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1127 | unsigned long type) | |
1128 | { | |
1129 | int idx; | |
1130 | bool changed = false; | |
1131 | struct pci_dev *dev; | |
1132 | struct resource *r; | |
1133 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1134 | IORESOURCE_PREFETCH; | |
1135 | ||
1136 | dev = bus->self; | |
1137 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
1138 | idx++) { | |
1139 | r = &dev->resource[idx]; | |
1140 | if ((r->flags & type_mask) != type) | |
1141 | continue; | |
1142 | if (!r->parent) | |
1143 | continue; | |
1144 | /* | |
1145 | * if there are children under that, we should release them | |
1146 | * all | |
1147 | */ | |
1148 | release_child_resources(r); | |
1149 | if (!release_resource(r)) { | |
1150 | dev_printk(KERN_DEBUG, &dev->dev, | |
1151 | "resource %d %pR released\n", idx, r); | |
1152 | /* keep the old size */ | |
1153 | r->end = resource_size(r) - 1; | |
1154 | r->start = 0; | |
1155 | r->flags = 0; | |
1156 | changed = true; | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | if (changed) { | |
1161 | /* avoiding touch the one without PREF */ | |
1162 | if (type & IORESOURCE_PREFETCH) | |
1163 | type = IORESOURCE_PREFETCH; | |
1164 | __pci_setup_bridge(bus, type); | |
1165 | } | |
1166 | } | |
1167 | ||
1168 | enum release_type { | |
1169 | leaf_only, | |
1170 | whole_subtree, | |
1171 | }; | |
1172 | /* | |
1173 | * try to release pci bridge resources that is from leaf bridge, | |
1174 | * so we can allocate big new one later | |
1175 | */ | |
1176 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
1177 | unsigned long type, | |
1178 | enum release_type rel_type) | |
1179 | { | |
1180 | struct pci_dev *dev; | |
1181 | bool is_leaf_bridge = true; | |
1182 | ||
1183 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1184 | struct pci_bus *b = dev->subordinate; | |
1185 | if (!b) | |
1186 | continue; | |
1187 | ||
1188 | is_leaf_bridge = false; | |
1189 | ||
1190 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1191 | continue; | |
1192 | ||
1193 | if (rel_type == whole_subtree) | |
1194 | pci_bus_release_bridge_resources(b, type, | |
1195 | whole_subtree); | |
1196 | } | |
1197 | ||
1198 | if (pci_is_root_bus(bus)) | |
1199 | return; | |
1200 | ||
1201 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1202 | return; | |
1203 | ||
1204 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1205 | pci_bridge_release_resources(bus, type); | |
1206 | } | |
1207 | ||
76fbc263 YL |
1208 | static void pci_bus_dump_res(struct pci_bus *bus) |
1209 | { | |
89a74ecc BH |
1210 | struct resource *res; |
1211 | int i; | |
7c9342b8 | 1212 | |
89a74ecc | 1213 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1214 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
1215 | continue; |
1216 | ||
c7dabef8 | 1217 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
1218 | } |
1219 | } | |
1220 | ||
1221 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1222 | { | |
1223 | struct pci_bus *b; | |
1224 | struct pci_dev *dev; | |
1225 | ||
1226 | ||
1227 | pci_bus_dump_res(bus); | |
1228 | ||
1229 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1230 | b = dev->subordinate; | |
1231 | if (!b) | |
1232 | continue; | |
1233 | ||
1234 | pci_bus_dump_resources(b); | |
1235 | } | |
1236 | } | |
1237 | ||
da7822e5 YL |
1238 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
1239 | { | |
1240 | int depth = 0; | |
1241 | struct pci_dev *dev; | |
1242 | ||
1243 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1244 | int ret; | |
1245 | struct pci_bus *b = dev->subordinate; | |
1246 | if (!b) | |
1247 | continue; | |
1248 | ||
1249 | ret = pci_bus_get_depth(b); | |
1250 | if (ret + 1 > depth) | |
1251 | depth = ret + 1; | |
1252 | } | |
1253 | ||
1254 | return depth; | |
1255 | } | |
1256 | static int __init pci_get_max_depth(void) | |
1257 | { | |
1258 | int depth = 0; | |
1259 | struct pci_bus *bus; | |
1260 | ||
1261 | list_for_each_entry(bus, &pci_root_buses, node) { | |
1262 | int ret; | |
1263 | ||
1264 | ret = pci_bus_get_depth(bus); | |
1265 | if (ret > depth) | |
1266 | depth = ret; | |
1267 | } | |
1268 | ||
1269 | return depth; | |
1270 | } | |
1271 | ||
b55438fd YL |
1272 | /* |
1273 | * -1: undefined, will auto detect later | |
1274 | * 0: disabled by user | |
1275 | * 1: disabled by auto detect | |
1276 | * 2: enabled by user | |
1277 | * 3: enabled by auto detect | |
1278 | */ | |
1279 | enum enable_type { | |
1280 | undefined = -1, | |
1281 | user_disabled, | |
1282 | auto_disabled, | |
1283 | user_enabled, | |
1284 | auto_enabled, | |
1285 | }; | |
1286 | ||
1287 | static enum enable_type pci_realloc_enable __initdata = undefined; | |
1288 | void __init pci_realloc_get_opt(char *str) | |
1289 | { | |
1290 | if (!strncmp(str, "off", 3)) | |
1291 | pci_realloc_enable = user_disabled; | |
1292 | else if (!strncmp(str, "on", 2)) | |
1293 | pci_realloc_enable = user_enabled; | |
1294 | } | |
1295 | static bool __init pci_realloc_enabled(void) | |
1296 | { | |
1297 | return pci_realloc_enable >= user_enabled; | |
1298 | } | |
f483d392 | 1299 | |
b07f2ebc YL |
1300 | static void __init pci_realloc_detect(void) |
1301 | { | |
1302 | #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) | |
1303 | struct pci_dev *dev = NULL; | |
1304 | ||
1305 | if (pci_realloc_enable != undefined) | |
1306 | return; | |
1307 | ||
1308 | for_each_pci_dev(dev) { | |
1309 | int i; | |
1310 | ||
1311 | for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { | |
1312 | struct resource *r = &dev->resource[i]; | |
1313 | ||
1314 | /* Not assigned, or rejected by kernel ? */ | |
1315 | if (r->flags && !r->start) { | |
1316 | pci_realloc_enable = auto_enabled; | |
1317 | ||
1318 | return; | |
1319 | } | |
1320 | } | |
1321 | } | |
1322 | #endif | |
1323 | } | |
1324 | ||
da7822e5 YL |
1325 | /* |
1326 | * first try will not touch pci bridge res | |
1327 | * second and later try will clear small leaf bridge res | |
1328 | * will stop till to the max deepth if can not find good one | |
1329 | */ | |
1da177e4 LT |
1330 | void __init |
1331 | pci_assign_unassigned_resources(void) | |
1332 | { | |
1333 | struct pci_bus *bus; | |
bdc4abec | 1334 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1335 | want additional resources */ |
bdc4abec | 1336 | struct list_head *add_list = NULL; |
da7822e5 YL |
1337 | int tried_times = 0; |
1338 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1339 | LIST_HEAD(fail_head); |
b9b0bba9 | 1340 | struct pci_dev_resource *fail_res; |
da7822e5 YL |
1341 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1342 | IORESOURCE_PREFETCH; | |
19aa7ee4 | 1343 | int pci_try_num = 1; |
da7822e5 | 1344 | |
19aa7ee4 | 1345 | /* don't realloc if asked to do so */ |
b07f2ebc | 1346 | pci_realloc_detect(); |
19aa7ee4 YL |
1347 | if (pci_realloc_enabled()) { |
1348 | int max_depth = pci_get_max_depth(); | |
1349 | ||
1350 | pci_try_num = max_depth + 1; | |
1351 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", | |
1352 | max_depth, pci_try_num); | |
1353 | } | |
da7822e5 YL |
1354 | |
1355 | again: | |
19aa7ee4 YL |
1356 | /* |
1357 | * last try will use add_list, otherwise will try good to have as | |
1358 | * must have, so can realloc parent bridge resource | |
1359 | */ | |
1360 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1361 | add_list = &realloc_head; |
1da177e4 LT |
1362 | /* Depth first, calculate sizes and alignments of all |
1363 | subordinate buses. */ | |
da7822e5 | 1364 | list_for_each_entry(bus, &pci_root_buses, node) |
19aa7ee4 | 1365 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1366 | |
1da177e4 | 1367 | /* Depth last, allocate resources and update the hardware. */ |
da7822e5 | 1368 | list_for_each_entry(bus, &pci_root_buses, node) |
bdc4abec | 1369 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1370 | if (add_list) |
bdc4abec | 1371 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1372 | tried_times++; |
1373 | ||
1374 | /* any device complain? */ | |
bdc4abec | 1375 | if (list_empty(&fail_head)) |
da7822e5 | 1376 | goto enable_and_dump; |
f483d392 | 1377 | |
0c5be0cb | 1378 | if (tried_times >= pci_try_num) { |
eb572e7c YL |
1379 | if (pci_realloc_enable == undefined) |
1380 | printk(KERN_INFO "Some PCI device resources are unassigned, try booting with pci=realloc\n"); | |
b07f2ebc YL |
1381 | else if (pci_realloc_enable == auto_enabled) |
1382 | printk(KERN_INFO "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); | |
eb572e7c | 1383 | |
bffc56d4 | 1384 | free_list(&fail_head); |
da7822e5 YL |
1385 | goto enable_and_dump; |
1386 | } | |
1387 | ||
1388 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1389 | tried_times + 1); | |
1390 | ||
1391 | /* third times and later will not check if it is leaf */ | |
1392 | if ((tried_times + 1) > 2) | |
1393 | rel_type = whole_subtree; | |
1394 | ||
1395 | /* | |
1396 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1397 | * child device under that bridge | |
1398 | */ | |
b9b0bba9 YL |
1399 | list_for_each_entry(fail_res, &fail_head, list) { |
1400 | bus = fail_res->dev->bus; | |
bdc4abec | 1401 | pci_bus_release_bridge_resources(bus, |
b9b0bba9 | 1402 | fail_res->flags & type_mask, |
bdc4abec | 1403 | rel_type); |
da7822e5 YL |
1404 | } |
1405 | /* restore size and flags */ | |
b9b0bba9 YL |
1406 | list_for_each_entry(fail_res, &fail_head, list) { |
1407 | struct resource *res = fail_res->res; | |
da7822e5 | 1408 | |
b9b0bba9 YL |
1409 | res->start = fail_res->start; |
1410 | res->end = fail_res->end; | |
1411 | res->flags = fail_res->flags; | |
1412 | if (fail_res->dev->subordinate) | |
da7822e5 | 1413 | res->flags = 0; |
da7822e5 | 1414 | } |
bffc56d4 | 1415 | free_list(&fail_head); |
da7822e5 YL |
1416 | |
1417 | goto again; | |
1418 | ||
1419 | enable_and_dump: | |
1420 | /* Depth last, update the hardware. */ | |
1421 | list_for_each_entry(bus, &pci_root_buses, node) | |
1422 | pci_enable_bridges(bus); | |
76fbc263 YL |
1423 | |
1424 | /* dump the resource on buses */ | |
da7822e5 | 1425 | list_for_each_entry(bus, &pci_root_buses, node) |
76fbc263 | 1426 | pci_bus_dump_resources(bus); |
1da177e4 | 1427 | } |
6841ec68 YL |
1428 | |
1429 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1430 | { | |
1431 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1432 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1433 | want additional resources */ |
32180e40 | 1434 | int tried_times = 0; |
bdc4abec | 1435 | LIST_HEAD(fail_head); |
b9b0bba9 | 1436 | struct pci_dev_resource *fail_res; |
6841ec68 | 1437 | int retval; |
32180e40 YL |
1438 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1439 | IORESOURCE_PREFETCH; | |
1440 | ||
32180e40 | 1441 | again: |
8424d759 | 1442 | __pci_bus_size_bridges(parent, &add_list); |
bdc4abec YL |
1443 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1444 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
1445 | tried_times++; |
1446 | ||
bdc4abec | 1447 | if (list_empty(&fail_head)) |
3f579c34 | 1448 | goto enable_all; |
32180e40 YL |
1449 | |
1450 | if (tried_times >= 2) { | |
1451 | /* still fail, don't need to try more */ | |
bffc56d4 | 1452 | free_list(&fail_head); |
3f579c34 | 1453 | goto enable_all; |
32180e40 YL |
1454 | } |
1455 | ||
1456 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1457 | tried_times + 1); | |
1458 | ||
1459 | /* | |
1460 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1461 | * child device under that bridge | |
1462 | */ | |
b9b0bba9 YL |
1463 | list_for_each_entry(fail_res, &fail_head, list) { |
1464 | struct pci_bus *bus = fail_res->dev->bus; | |
1465 | unsigned long flags = fail_res->flags; | |
32180e40 YL |
1466 | |
1467 | pci_bus_release_bridge_resources(bus, flags & type_mask, | |
1468 | whole_subtree); | |
32180e40 YL |
1469 | } |
1470 | /* restore size and flags */ | |
b9b0bba9 YL |
1471 | list_for_each_entry(fail_res, &fail_head, list) { |
1472 | struct resource *res = fail_res->res; | |
32180e40 | 1473 | |
b9b0bba9 YL |
1474 | res->start = fail_res->start; |
1475 | res->end = fail_res->end; | |
1476 | res->flags = fail_res->flags; | |
1477 | if (fail_res->dev->subordinate) | |
32180e40 | 1478 | res->flags = 0; |
32180e40 | 1479 | } |
bffc56d4 | 1480 | free_list(&fail_head); |
32180e40 YL |
1481 | |
1482 | goto again; | |
3f579c34 YL |
1483 | |
1484 | enable_all: | |
1485 | retval = pci_reenable_device(bridge); | |
1486 | pci_set_master(bridge); | |
1487 | pci_enable_bridges(parent); | |
6841ec68 YL |
1488 | } |
1489 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f YL |
1490 | |
1491 | #ifdef CONFIG_HOTPLUG | |
1492 | /** | |
1493 | * pci_rescan_bus - scan a PCI bus for devices. | |
1494 | * @bus: PCI bus to scan | |
1495 | * | |
1496 | * Scan a PCI bus and child buses for new devices, adds them, | |
1497 | * and enables them. | |
1498 | * | |
1499 | * Returns the max number of subordinate bus discovered. | |
1500 | */ | |
1501 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) | |
1502 | { | |
1503 | unsigned int max; | |
1504 | struct pci_dev *dev; | |
bdc4abec | 1505 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
1506 | want additional resources */ |
1507 | ||
1508 | max = pci_scan_child_bus(bus); | |
1509 | ||
9b03088f YL |
1510 | down_read(&pci_bus_sem); |
1511 | list_for_each_entry(dev, &bus->devices, bus_list) | |
1512 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1513 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1514 | if (dev->subordinate) | |
1515 | __pci_bus_size_bridges(dev->subordinate, | |
1516 | &add_list); | |
1517 | up_read(&pci_bus_sem); | |
1518 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 1519 | BUG_ON(!list_empty(&add_list)); |
9b03088f YL |
1520 | |
1521 | pci_enable_bridges(bus); | |
1522 | pci_bus_add_devices(bus); | |
1523 | ||
1524 | return max; | |
1525 | } | |
1526 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1527 | #endif |