Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
47087700 | 28 | #include <asm-generic/pci-bridge.h> |
6faf17f6 | 29 | #include "pci.h" |
1da177e4 | 30 | |
844393f4 | 31 | unsigned int pci_flags; |
47087700 | 32 | |
bdc4abec YL |
33 | struct pci_dev_resource { |
34 | struct list_head list; | |
2934a0de YL |
35 | struct resource *res; |
36 | struct pci_dev *dev; | |
568ddef8 YL |
37 | resource_size_t start; |
38 | resource_size_t end; | |
c8adf9a3 | 39 | resource_size_t add_size; |
2bbc6942 | 40 | resource_size_t min_align; |
568ddef8 YL |
41 | unsigned long flags; |
42 | }; | |
43 | ||
bffc56d4 YL |
44 | static void free_list(struct list_head *head) |
45 | { | |
46 | struct pci_dev_resource *dev_res, *tmp; | |
47 | ||
48 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
49 | list_del(&dev_res->list); | |
50 | kfree(dev_res); | |
51 | } | |
52 | } | |
094732a5 | 53 | |
c8adf9a3 RP |
54 | /** |
55 | * add_to_list() - add a new resource tracker to the list | |
56 | * @head: Head of the list | |
57 | * @dev: device corresponding to which the resource | |
58 | * belongs | |
59 | * @res: The resource to be tracked | |
60 | * @add_size: additional size to be optionally added | |
61 | * to the resource | |
62 | */ | |
bdc4abec | 63 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 64 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 65 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 66 | { |
764242a0 | 67 | struct pci_dev_resource *tmp; |
568ddef8 | 68 | |
bdc4abec | 69 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 70 | if (!tmp) { |
3c78bc61 | 71 | pr_warn("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 72 | return -ENOMEM; |
568ddef8 YL |
73 | } |
74 | ||
568ddef8 YL |
75 | tmp->res = res; |
76 | tmp->dev = dev; | |
77 | tmp->start = res->start; | |
78 | tmp->end = res->end; | |
79 | tmp->flags = res->flags; | |
c8adf9a3 | 80 | tmp->add_size = add_size; |
2bbc6942 | 81 | tmp->min_align = min_align; |
bdc4abec YL |
82 | |
83 | list_add(&tmp->list, head); | |
ef62dfef YL |
84 | |
85 | return 0; | |
568ddef8 YL |
86 | } |
87 | ||
b9b0bba9 | 88 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
89 | struct resource *res) |
90 | { | |
b9b0bba9 | 91 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 92 | |
b9b0bba9 YL |
93 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
94 | if (dev_res->res == res) { | |
95 | list_del(&dev_res->list); | |
96 | kfree(dev_res); | |
bdc4abec | 97 | break; |
3e6e0d80 | 98 | } |
3e6e0d80 YL |
99 | } |
100 | } | |
101 | ||
d74b9027 WY |
102 | static struct pci_dev_resource *res_to_dev_res(struct list_head *head, |
103 | struct resource *res) | |
1c372353 | 104 | { |
b9b0bba9 | 105 | struct pci_dev_resource *dev_res; |
bdc4abec | 106 | |
b9b0bba9 YL |
107 | list_for_each_entry(dev_res, head, list) { |
108 | if (dev_res->res == res) { | |
b592443d YL |
109 | int idx = res - &dev_res->dev->resource[0]; |
110 | ||
b9b0bba9 | 111 | dev_printk(KERN_DEBUG, &dev_res->dev->dev, |
d74b9027 | 112 | "res[%d]=%pR res_to_dev_res add_size %llx min_align %llx\n", |
b592443d | 113 | idx, dev_res->res, |
d74b9027 WY |
114 | (unsigned long long)dev_res->add_size, |
115 | (unsigned long long)dev_res->min_align); | |
b592443d | 116 | |
d74b9027 | 117 | return dev_res; |
bdc4abec | 118 | } |
3e6e0d80 | 119 | } |
1c372353 | 120 | |
d74b9027 | 121 | return NULL; |
1c372353 YL |
122 | } |
123 | ||
d74b9027 WY |
124 | static resource_size_t get_res_add_size(struct list_head *head, |
125 | struct resource *res) | |
126 | { | |
127 | struct pci_dev_resource *dev_res; | |
128 | ||
129 | dev_res = res_to_dev_res(head, res); | |
130 | return dev_res ? dev_res->add_size : 0; | |
131 | } | |
132 | ||
133 | static resource_size_t get_res_add_align(struct list_head *head, | |
134 | struct resource *res) | |
135 | { | |
136 | struct pci_dev_resource *dev_res; | |
137 | ||
138 | dev_res = res_to_dev_res(head, res); | |
139 | return dev_res ? dev_res->min_align : 0; | |
140 | } | |
141 | ||
142 | ||
78c3b329 | 143 | /* Sort resources by alignment */ |
bdc4abec | 144 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
145 | { |
146 | int i; | |
147 | ||
148 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
149 | struct resource *r; | |
bdc4abec | 150 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 151 | resource_size_t r_align; |
bdc4abec | 152 | struct list_head *n; |
78c3b329 YL |
153 | |
154 | r = &dev->resource[i]; | |
155 | ||
156 | if (r->flags & IORESOURCE_PCI_FIXED) | |
157 | continue; | |
158 | ||
159 | if (!(r->flags) || r->parent) | |
160 | continue; | |
161 | ||
162 | r_align = pci_resource_alignment(dev, r); | |
163 | if (!r_align) { | |
164 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
165 | i, r); | |
166 | continue; | |
167 | } | |
78c3b329 | 168 | |
bdc4abec YL |
169 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
170 | if (!tmp) | |
227f0647 | 171 | panic("pdev_sort_resources(): kmalloc() failed!\n"); |
bdc4abec YL |
172 | tmp->res = r; |
173 | tmp->dev = dev; | |
174 | ||
175 | /* fallback is smallest one or list is empty*/ | |
176 | n = head; | |
177 | list_for_each_entry(dev_res, head, list) { | |
178 | resource_size_t align; | |
179 | ||
180 | align = pci_resource_alignment(dev_res->dev, | |
181 | dev_res->res); | |
78c3b329 YL |
182 | |
183 | if (r_align > align) { | |
bdc4abec | 184 | n = &dev_res->list; |
78c3b329 YL |
185 | break; |
186 | } | |
187 | } | |
bdc4abec YL |
188 | /* Insert it just before n*/ |
189 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
190 | } |
191 | } | |
192 | ||
6841ec68 | 193 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 194 | struct list_head *head) |
1da177e4 | 195 | { |
6841ec68 | 196 | u16 class = dev->class >> 8; |
1da177e4 | 197 | |
6841ec68 YL |
198 | /* Don't touch classless devices or host bridges or ioapics. */ |
199 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
200 | return; | |
1da177e4 | 201 | |
6841ec68 YL |
202 | /* Don't touch ioapic devices already enabled by firmware */ |
203 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
204 | u16 command; | |
205 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
206 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
207 | return; | |
208 | } | |
1da177e4 | 209 | |
6841ec68 YL |
210 | pdev_sort_resources(dev, head); |
211 | } | |
23186279 | 212 | |
fc075e1d RP |
213 | static inline void reset_resource(struct resource *res) |
214 | { | |
215 | res->start = 0; | |
216 | res->end = 0; | |
217 | res->flags = 0; | |
218 | } | |
219 | ||
c8adf9a3 | 220 | /** |
9e8bf93a | 221 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 222 | * |
9e8bf93a | 223 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
224 | * resources |
225 | * @head : head of the list tracking requests with allocated | |
226 | * resources | |
227 | * | |
9e8bf93a | 228 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
229 | * additional resources for the element, provided the element |
230 | * is in the head list. | |
231 | */ | |
bdc4abec YL |
232 | static void reassign_resources_sorted(struct list_head *realloc_head, |
233 | struct list_head *head) | |
6841ec68 YL |
234 | { |
235 | struct resource *res; | |
b9b0bba9 | 236 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 237 | struct pci_dev_resource *dev_res; |
d74b9027 | 238 | resource_size_t add_size, align; |
6841ec68 | 239 | int idx; |
1da177e4 | 240 | |
b9b0bba9 | 241 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
242 | bool found_match = false; |
243 | ||
b9b0bba9 | 244 | res = add_res->res; |
c8adf9a3 RP |
245 | /* skip resource that has been reset */ |
246 | if (!res->flags) | |
247 | goto out; | |
248 | ||
249 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
250 | list_for_each_entry(dev_res, head, list) { |
251 | if (dev_res->res == res) { | |
252 | found_match = true; | |
253 | break; | |
254 | } | |
c8adf9a3 | 255 | } |
bdc4abec YL |
256 | if (!found_match)/* just skip */ |
257 | continue; | |
c8adf9a3 | 258 | |
b9b0bba9 YL |
259 | idx = res - &add_res->dev->resource[0]; |
260 | add_size = add_res->add_size; | |
d74b9027 | 261 | align = add_res->min_align; |
2bbc6942 | 262 | if (!resource_size(res)) { |
d74b9027 | 263 | res->start = align; |
2bbc6942 | 264 | res->end = res->start + add_size - 1; |
b9b0bba9 | 265 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 266 | reset_resource(res); |
2bbc6942 | 267 | } else { |
b9b0bba9 | 268 | res->flags |= add_res->flags & |
bdc4abec | 269 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 270 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 271 | add_size, align)) |
b9b0bba9 | 272 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
b592443d YL |
273 | "failed to add %llx res[%d]=%pR\n", |
274 | (unsigned long long)add_size, | |
275 | idx, res); | |
c8adf9a3 RP |
276 | } |
277 | out: | |
b9b0bba9 YL |
278 | list_del(&add_res->list); |
279 | kfree(add_res); | |
c8adf9a3 RP |
280 | } |
281 | } | |
282 | ||
283 | /** | |
284 | * assign_requested_resources_sorted() - satisfy resource requests | |
285 | * | |
286 | * @head : head of the list tracking requests for resources | |
8356aad4 | 287 | * @fail_head : head of the list tracking requests that could |
c8adf9a3 RP |
288 | * not be allocated |
289 | * | |
290 | * Satisfy resource requests of each element in the list. Add | |
291 | * requests that could not satisfied to the failed_list. | |
292 | */ | |
bdc4abec YL |
293 | static void assign_requested_resources_sorted(struct list_head *head, |
294 | struct list_head *fail_head) | |
c8adf9a3 RP |
295 | { |
296 | struct resource *res; | |
bdc4abec | 297 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 298 | int idx; |
9a928660 | 299 | |
bdc4abec YL |
300 | list_for_each_entry(dev_res, head, list) { |
301 | res = dev_res->res; | |
302 | idx = res - &dev_res->dev->resource[0]; | |
303 | if (resource_size(res) && | |
304 | pci_assign_resource(dev_res->dev, idx)) { | |
a3cb999d | 305 | if (fail_head) { |
9a928660 YL |
306 | /* |
307 | * if the failed res is for ROM BAR, and it will | |
308 | * be enabled later, don't add it to the list | |
309 | */ | |
310 | if (!((idx == PCI_ROM_RESOURCE) && | |
311 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
67cc7e26 YL |
312 | add_to_list(fail_head, |
313 | dev_res->dev, res, | |
f7625980 BH |
314 | 0 /* don't care */, |
315 | 0 /* don't care */); | |
9a928660 | 316 | } |
fc075e1d | 317 | reset_resource(res); |
542df5de | 318 | } |
1da177e4 LT |
319 | } |
320 | } | |
321 | ||
aa914f5e YL |
322 | static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) |
323 | { | |
324 | struct pci_dev_resource *fail_res; | |
325 | unsigned long mask = 0; | |
326 | ||
327 | /* check failed type */ | |
328 | list_for_each_entry(fail_res, fail_head, list) | |
329 | mask |= fail_res->flags; | |
330 | ||
331 | /* | |
332 | * one pref failed resource will set IORESOURCE_MEM, | |
333 | * as we can allocate pref in non-pref range. | |
334 | * Will release all assigned non-pref sibling resources | |
335 | * according to that bit. | |
336 | */ | |
337 | return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
338 | } | |
339 | ||
340 | static bool pci_need_to_release(unsigned long mask, struct resource *res) | |
341 | { | |
342 | if (res->flags & IORESOURCE_IO) | |
343 | return !!(mask & IORESOURCE_IO); | |
344 | ||
345 | /* check pref at first */ | |
346 | if (res->flags & IORESOURCE_PREFETCH) { | |
347 | if (mask & IORESOURCE_PREFETCH) | |
348 | return true; | |
349 | /* count pref if its parent is non-pref */ | |
350 | else if ((mask & IORESOURCE_MEM) && | |
351 | !(res->parent->flags & IORESOURCE_PREFETCH)) | |
352 | return true; | |
353 | else | |
354 | return false; | |
355 | } | |
356 | ||
357 | if (res->flags & IORESOURCE_MEM) | |
358 | return !!(mask & IORESOURCE_MEM); | |
359 | ||
360 | return false; /* should not get here */ | |
361 | } | |
362 | ||
bdc4abec YL |
363 | static void __assign_resources_sorted(struct list_head *head, |
364 | struct list_head *realloc_head, | |
365 | struct list_head *fail_head) | |
c8adf9a3 | 366 | { |
3e6e0d80 YL |
367 | /* |
368 | * Should not assign requested resources at first. | |
369 | * they could be adjacent, so later reassign can not reallocate | |
370 | * them one by one in parent resource window. | |
367fa982 | 371 | * Try to assign requested + add_size at beginning |
3e6e0d80 YL |
372 | * if could do that, could get out early. |
373 | * if could not do that, we still try to assign requested at first, | |
374 | * then try to reassign add_size for some resources. | |
aa914f5e YL |
375 | * |
376 | * Separate three resource type checking if we need to release | |
377 | * assigned resource after requested + add_size try. | |
378 | * 1. if there is io port assign fail, will release assigned | |
379 | * io port. | |
380 | * 2. if there is pref mmio assign fail, release assigned | |
381 | * pref mmio. | |
382 | * if assigned pref mmio's parent is non-pref mmio and there | |
383 | * is non-pref mmio assign fail, will release that assigned | |
384 | * pref mmio. | |
385 | * 3. if there is non-pref mmio assign fail or pref mmio | |
386 | * assigned fail, will release assigned non-pref mmio. | |
3e6e0d80 | 387 | */ |
bdc4abec YL |
388 | LIST_HEAD(save_head); |
389 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 390 | struct pci_dev_resource *save_res; |
d74b9027 | 391 | struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; |
aa914f5e | 392 | unsigned long fail_type; |
d74b9027 | 393 | resource_size_t add_align, align; |
3e6e0d80 YL |
394 | |
395 | /* Check if optional add_size is there */ | |
bdc4abec | 396 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
397 | goto requested_and_reassign; |
398 | ||
399 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
400 | list_for_each_entry(dev_res, head, list) { |
401 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 402 | free_list(&save_head); |
3e6e0d80 YL |
403 | goto requested_and_reassign; |
404 | } | |
bdc4abec | 405 | } |
3e6e0d80 YL |
406 | |
407 | /* Update res in head list with add_size in realloc_head list */ | |
d74b9027 | 408 | list_for_each_entry_safe(dev_res, tmp_res, head, list) { |
bdc4abec YL |
409 | dev_res->res->end += get_res_add_size(realloc_head, |
410 | dev_res->res); | |
3e6e0d80 | 411 | |
d74b9027 WY |
412 | /* |
413 | * There are two kinds of additional resources in the list: | |
414 | * 1. bridge resource -- IORESOURCE_STARTALIGN | |
415 | * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN | |
416 | * Here just fix the additional alignment for bridge | |
417 | */ | |
418 | if (!(dev_res->res->flags & IORESOURCE_STARTALIGN)) | |
419 | continue; | |
420 | ||
421 | add_align = get_res_add_align(realloc_head, dev_res->res); | |
422 | ||
423 | /* | |
424 | * The "head" list is sorted by the alignment to make sure | |
425 | * resources with bigger alignment will be assigned first. | |
426 | * After we change the alignment of a dev_res in "head" list, | |
427 | * we need to reorder the list by alignment to make it | |
428 | * consistent. | |
429 | */ | |
430 | if (add_align > dev_res->res->start) { | |
431 | dev_res->res->start = add_align; | |
432 | dev_res->res->end = add_align + | |
433 | resource_size(dev_res->res); | |
434 | ||
435 | list_for_each_entry(dev_res2, head, list) { | |
436 | align = pci_resource_alignment(dev_res2->dev, | |
437 | dev_res2->res); | |
438 | if (add_align > align) | |
439 | list_move_tail(&dev_res->list, | |
440 | &dev_res2->list); | |
441 | } | |
442 | } | |
443 | ||
444 | } | |
445 | ||
3e6e0d80 | 446 | /* Try updated head list with add_size added */ |
3e6e0d80 YL |
447 | assign_requested_resources_sorted(head, &local_fail_head); |
448 | ||
449 | /* all assigned with add_size ? */ | |
bdc4abec | 450 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 451 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
452 | list_for_each_entry(dev_res, head, list) |
453 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
454 | free_list(&save_head); |
455 | free_list(head); | |
3e6e0d80 YL |
456 | return; |
457 | } | |
458 | ||
aa914f5e YL |
459 | /* check failed type */ |
460 | fail_type = pci_fail_res_type_mask(&local_fail_head); | |
461 | /* remove not need to be released assigned res from head list etc */ | |
462 | list_for_each_entry_safe(dev_res, tmp_res, head, list) | |
463 | if (dev_res->res->parent && | |
464 | !pci_need_to_release(fail_type, dev_res->res)) { | |
465 | /* remove it from realloc_head list */ | |
466 | remove_from_list(realloc_head, dev_res->res); | |
467 | remove_from_list(&save_head, dev_res->res); | |
468 | list_del(&dev_res->list); | |
469 | kfree(dev_res); | |
470 | } | |
471 | ||
bffc56d4 | 472 | free_list(&local_fail_head); |
3e6e0d80 | 473 | /* Release assigned resource */ |
bdc4abec YL |
474 | list_for_each_entry(dev_res, head, list) |
475 | if (dev_res->res->parent) | |
476 | release_resource(dev_res->res); | |
3e6e0d80 | 477 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
478 | list_for_each_entry(save_res, &save_head, list) { |
479 | struct resource *res = save_res->res; | |
3e6e0d80 | 480 | |
b9b0bba9 YL |
481 | res->start = save_res->start; |
482 | res->end = save_res->end; | |
483 | res->flags = save_res->flags; | |
3e6e0d80 | 484 | } |
bffc56d4 | 485 | free_list(&save_head); |
3e6e0d80 YL |
486 | |
487 | requested_and_reassign: | |
c8adf9a3 RP |
488 | /* Satisfy the must-have resource requests */ |
489 | assign_requested_resources_sorted(head, fail_head); | |
490 | ||
0a2daa1c | 491 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 492 | requests */ |
9e8bf93a RP |
493 | if (realloc_head) |
494 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 495 | free_list(head); |
c8adf9a3 RP |
496 | } |
497 | ||
6841ec68 | 498 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
499 | struct list_head *add_head, |
500 | struct list_head *fail_head) | |
6841ec68 | 501 | { |
bdc4abec | 502 | LIST_HEAD(head); |
6841ec68 | 503 | |
6841ec68 | 504 | __dev_sort_resources(dev, &head); |
8424d759 | 505 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
506 | |
507 | } | |
508 | ||
509 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
510 | struct list_head *realloc_head, |
511 | struct list_head *fail_head) | |
6841ec68 YL |
512 | { |
513 | struct pci_dev *dev; | |
bdc4abec | 514 | LIST_HEAD(head); |
6841ec68 | 515 | |
6841ec68 YL |
516 | list_for_each_entry(dev, &bus->devices, bus_list) |
517 | __dev_sort_resources(dev, &head); | |
518 | ||
9e8bf93a | 519 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
520 | } |
521 | ||
b3743fa4 | 522 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
523 | { |
524 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 525 | struct resource *res; |
1da177e4 LT |
526 | struct pci_bus_region region; |
527 | ||
b918c62e YL |
528 | dev_info(&bridge->dev, "CardBus bridge to %pR\n", |
529 | &bus->busn_res); | |
1da177e4 | 530 | |
c7dabef8 | 531 | res = bus->resource[0]; |
fc279850 | 532 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 533 | if (res->flags & IORESOURCE_IO) { |
1da177e4 LT |
534 | /* |
535 | * The IO resource is allocated a range twice as large as it | |
536 | * would normally need. This allows us to set both IO regs. | |
537 | */ | |
c7dabef8 | 538 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
539 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
540 | region.start); | |
541 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
542 | region.end); | |
543 | } | |
544 | ||
c7dabef8 | 545 | res = bus->resource[1]; |
fc279850 | 546 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
547 | if (res->flags & IORESOURCE_IO) { |
548 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
549 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
550 | region.start); | |
551 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
552 | region.end); | |
553 | } | |
554 | ||
c7dabef8 | 555 | res = bus->resource[2]; |
fc279850 | 556 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
557 | if (res->flags & IORESOURCE_MEM) { |
558 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
559 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
560 | region.start); | |
561 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
562 | region.end); | |
563 | } | |
564 | ||
c7dabef8 | 565 | res = bus->resource[3]; |
fc279850 | 566 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
567 | if (res->flags & IORESOURCE_MEM) { |
568 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
569 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
570 | region.start); | |
571 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
572 | region.end); | |
573 | } | |
574 | } | |
b3743fa4 | 575 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
576 | |
577 | /* Initialize bridges with base/limit values we have collected. | |
578 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
579 | requires that if there is no I/O ports or memory behind the | |
580 | bridge, corresponding range must be turned off by writing base | |
581 | value greater than limit to the bridge's base/limit registers. | |
582 | ||
583 | Note: care must be taken when updating I/O base/limit registers | |
584 | of bridges which support 32-bit I/O. This update requires two | |
585 | config space writes, so it's quite possible that an I/O window of | |
586 | the bridge will have some undesirable address (e.g. 0) after the | |
587 | first write. Ditto 64-bit prefetchable MMIO. */ | |
3f2f4dc4 | 588 | static void pci_setup_bridge_io(struct pci_dev *bridge) |
1da177e4 | 589 | { |
c7dabef8 | 590 | struct resource *res; |
1da177e4 | 591 | struct pci_bus_region region; |
2b28ae19 BH |
592 | unsigned long io_mask; |
593 | u8 io_base_lo, io_limit_lo; | |
5b764b83 BH |
594 | u16 l; |
595 | u32 io_upper16; | |
1da177e4 | 596 | |
2b28ae19 BH |
597 | io_mask = PCI_IO_RANGE_MASK; |
598 | if (bridge->io_window_1k) | |
599 | io_mask = PCI_IO_1K_RANGE_MASK; | |
600 | ||
1da177e4 | 601 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
3f2f4dc4 | 602 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; |
fc279850 | 603 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 604 | if (res->flags & IORESOURCE_IO) { |
5b764b83 | 605 | pci_read_config_word(bridge, PCI_IO_BASE, &l); |
2b28ae19 BH |
606 | io_base_lo = (region.start >> 8) & io_mask; |
607 | io_limit_lo = (region.end >> 8) & io_mask; | |
5b764b83 | 608 | l = ((u16) io_limit_lo << 8) | io_base_lo; |
1da177e4 LT |
609 | /* Set up upper 16 bits of I/O base/limit. */ |
610 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 611 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 612 | } else { |
1da177e4 LT |
613 | /* Clear upper 16 bits of I/O base/limit. */ |
614 | io_upper16 = 0; | |
615 | l = 0x00f0; | |
1da177e4 LT |
616 | } |
617 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
618 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
619 | /* Update lower 16 bits of I/O base/limit. */ | |
5b764b83 | 620 | pci_write_config_word(bridge, PCI_IO_BASE, l); |
1da177e4 LT |
621 | /* Update upper 16 bits of I/O base/limit. */ |
622 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
623 | } |
624 | ||
3f2f4dc4 | 625 | static void pci_setup_bridge_mmio(struct pci_dev *bridge) |
7cc5997d | 626 | { |
7cc5997d YL |
627 | struct resource *res; |
628 | struct pci_bus_region region; | |
629 | u32 l; | |
1da177e4 | 630 | |
7cc5997d | 631 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
3f2f4dc4 | 632 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; |
fc279850 | 633 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 634 | if (res->flags & IORESOURCE_MEM) { |
1da177e4 LT |
635 | l = (region.start >> 16) & 0xfff0; |
636 | l |= region.end & 0xfff00000; | |
c7dabef8 | 637 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 638 | } else { |
1da177e4 | 639 | l = 0x0000fff0; |
1da177e4 LT |
640 | } |
641 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
642 | } |
643 | ||
3f2f4dc4 | 644 | static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) |
7cc5997d | 645 | { |
7cc5997d YL |
646 | struct resource *res; |
647 | struct pci_bus_region region; | |
648 | u32 l, bu, lu; | |
1da177e4 LT |
649 | |
650 | /* Clear out the upper 32 bits of PREF limit. | |
651 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
652 | disables PREF range, which is ok. */ | |
653 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
654 | ||
655 | /* Set up PREF base/limit. */ | |
c40a22e0 | 656 | bu = lu = 0; |
3f2f4dc4 | 657 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; |
fc279850 | 658 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 659 | if (res->flags & IORESOURCE_PREFETCH) { |
1da177e4 LT |
660 | l = (region.start >> 16) & 0xfff0; |
661 | l |= region.end & 0xfff00000; | |
c7dabef8 | 662 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
663 | bu = upper_32_bits(region.start); |
664 | lu = upper_32_bits(region.end); | |
1f82de10 | 665 | } |
c7dabef8 | 666 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 667 | } else { |
1da177e4 | 668 | l = 0x0000fff0; |
1da177e4 LT |
669 | } |
670 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
671 | ||
59353ea3 AW |
672 | /* Set the upper 32 bits of PREF base & limit. */ |
673 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
674 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
675 | } |
676 | ||
677 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
678 | { | |
679 | struct pci_dev *bridge = bus->self; | |
680 | ||
b918c62e YL |
681 | dev_info(&bridge->dev, "PCI bridge to %pR\n", |
682 | &bus->busn_res); | |
7cc5997d YL |
683 | |
684 | if (type & IORESOURCE_IO) | |
3f2f4dc4 | 685 | pci_setup_bridge_io(bridge); |
7cc5997d YL |
686 | |
687 | if (type & IORESOURCE_MEM) | |
3f2f4dc4 | 688 | pci_setup_bridge_mmio(bridge); |
7cc5997d YL |
689 | |
690 | if (type & IORESOURCE_PREFETCH) | |
3f2f4dc4 | 691 | pci_setup_bridge_mmio_pref(bridge); |
1da177e4 LT |
692 | |
693 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
694 | } | |
695 | ||
e2444273 | 696 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
697 | { |
698 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
699 | IORESOURCE_PREFETCH; | |
700 | ||
701 | __pci_setup_bridge(bus, type); | |
702 | } | |
703 | ||
8505e729 YL |
704 | |
705 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i) | |
706 | { | |
707 | if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) | |
708 | return 0; | |
709 | ||
710 | if (pci_claim_resource(bridge, i) == 0) | |
711 | return 0; /* claimed the window */ | |
712 | ||
713 | if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
714 | return 0; | |
715 | ||
716 | if (!pci_bus_clip_resource(bridge, i)) | |
717 | return -EINVAL; /* clipping didn't change anything */ | |
718 | ||
719 | switch (i - PCI_BRIDGE_RESOURCES) { | |
720 | case 0: | |
721 | pci_setup_bridge_io(bridge); | |
722 | break; | |
723 | case 1: | |
724 | pci_setup_bridge_mmio(bridge); | |
725 | break; | |
726 | case 2: | |
727 | pci_setup_bridge_mmio_pref(bridge); | |
728 | break; | |
729 | default: | |
730 | return -EINVAL; | |
731 | } | |
732 | ||
733 | if (pci_claim_resource(bridge, i) == 0) | |
734 | return 0; /* claimed a smaller window */ | |
735 | ||
736 | return -EINVAL; | |
737 | } | |
738 | ||
1da177e4 LT |
739 | /* Check whether the bridge supports optional I/O and |
740 | prefetchable memory ranges. If not, the respective | |
741 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 742 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
743 | { |
744 | u16 io; | |
745 | u32 pmem; | |
746 | struct pci_dev *bridge = bus->self; | |
747 | struct resource *b_res; | |
748 | ||
749 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
750 | b_res[1].flags |= IORESOURCE_MEM; | |
751 | ||
752 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
753 | if (!io) { | |
d2f54d9b | 754 | pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); |
1da177e4 | 755 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
f7625980 BH |
756 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); |
757 | } | |
758 | if (io) | |
1da177e4 | 759 | b_res[0].flags |= IORESOURCE_IO; |
d2f54d9b | 760 | |
1da177e4 LT |
761 | /* DECchip 21050 pass 2 errata: the bridge may miss an address |
762 | disconnect boundary by one PCI data phase. | |
763 | Workaround: do not use prefetching on this device. */ | |
764 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
765 | return; | |
d2f54d9b | 766 | |
1da177e4 LT |
767 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
768 | if (!pmem) { | |
769 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
d2f54d9b | 770 | 0xffe0fff0); |
1da177e4 LT |
771 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
772 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
773 | } | |
1f82de10 | 774 | if (pmem) { |
1da177e4 | 775 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
776 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
777 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 778 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
779 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
780 | } | |
1f82de10 YL |
781 | } |
782 | ||
783 | /* double check if bridge does support 64 bit pref */ | |
784 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
785 | u32 mem_base_hi, tmp; | |
786 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
787 | &mem_base_hi); | |
788 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
789 | 0xffffffff); | |
790 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
791 | if (!tmp) | |
792 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
793 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
794 | mem_base_hi); | |
795 | } | |
1da177e4 LT |
796 | } |
797 | ||
798 | /* Helper function for sizing routines: find first available | |
799 | bus resource of a given type. Note: we intentionally skip | |
800 | the bus resources which have already been assigned (that is, | |
801 | have non-NULL parent resource). */ | |
5b285415 YL |
802 | static struct resource *find_free_bus_resource(struct pci_bus *bus, |
803 | unsigned long type_mask, unsigned long type) | |
1da177e4 LT |
804 | { |
805 | int i; | |
806 | struct resource *r; | |
1da177e4 | 807 | |
89a74ecc | 808 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
809 | if (r == &ioport_resource || r == &iomem_resource) |
810 | continue; | |
55a10984 JB |
811 | if (r && (r->flags & type_mask) == type && !r->parent) |
812 | return r; | |
1da177e4 LT |
813 | } |
814 | return NULL; | |
815 | } | |
816 | ||
13583b16 RP |
817 | static resource_size_t calculate_iosize(resource_size_t size, |
818 | resource_size_t min_size, | |
819 | resource_size_t size1, | |
820 | resource_size_t old_size, | |
821 | resource_size_t align) | |
822 | { | |
823 | if (size < min_size) | |
824 | size = min_size; | |
3c78bc61 | 825 | if (old_size == 1) |
13583b16 RP |
826 | old_size = 0; |
827 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
828 | flag in the struct pci_bus. */ | |
829 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
830 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
831 | #endif | |
832 | size = ALIGN(size + size1, align); | |
833 | if (size < old_size) | |
834 | size = old_size; | |
835 | return size; | |
836 | } | |
837 | ||
838 | static resource_size_t calculate_memsize(resource_size_t size, | |
839 | resource_size_t min_size, | |
840 | resource_size_t size1, | |
841 | resource_size_t old_size, | |
842 | resource_size_t align) | |
843 | { | |
844 | if (size < min_size) | |
845 | size = min_size; | |
3c78bc61 | 846 | if (old_size == 1) |
13583b16 RP |
847 | old_size = 0; |
848 | if (size < old_size) | |
849 | size = old_size; | |
850 | size = ALIGN(size + size1, align); | |
851 | return size; | |
852 | } | |
853 | ||
ac5ad93e GS |
854 | resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, |
855 | unsigned long type) | |
856 | { | |
857 | return 1; | |
858 | } | |
859 | ||
860 | #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ | |
861 | #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ | |
862 | #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ | |
863 | ||
864 | static resource_size_t window_alignment(struct pci_bus *bus, | |
865 | unsigned long type) | |
866 | { | |
867 | resource_size_t align = 1, arch_align; | |
868 | ||
869 | if (type & IORESOURCE_MEM) | |
870 | align = PCI_P2P_DEFAULT_MEM_ALIGN; | |
871 | else if (type & IORESOURCE_IO) { | |
872 | /* | |
873 | * Per spec, I/O windows are 4K-aligned, but some | |
874 | * bridges have an extension to support 1K alignment. | |
875 | */ | |
876 | if (bus->self->io_window_1k) | |
877 | align = PCI_P2P_DEFAULT_IO_ALIGN_1K; | |
878 | else | |
879 | align = PCI_P2P_DEFAULT_IO_ALIGN; | |
880 | } | |
881 | ||
882 | arch_align = pcibios_window_alignment(bus, type); | |
883 | return max(align, arch_align); | |
884 | } | |
885 | ||
c8adf9a3 RP |
886 | /** |
887 | * pbus_size_io() - size the io window of a given bus | |
888 | * | |
889 | * @bus : the bus | |
890 | * @min_size : the minimum io window that must to be allocated | |
891 | * @add_size : additional optional io window | |
9e8bf93a | 892 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
893 | * |
894 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
fd591341 | 895 | * since these windows have 1K or 4K granularity and the IO ranges |
c8adf9a3 RP |
896 | * of non-bridge PCI devices are limited to 256 bytes. |
897 | * We must be careful with the ISA aliasing though. | |
898 | */ | |
899 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 900 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
901 | { |
902 | struct pci_dev *dev; | |
5b285415 YL |
903 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO, |
904 | IORESOURCE_IO); | |
11251a86 | 905 | resource_size_t size = 0, size0 = 0, size1 = 0; |
be768912 | 906 | resource_size_t children_add_size = 0; |
2d1d6678 | 907 | resource_size_t min_align, align; |
1da177e4 LT |
908 | |
909 | if (!b_res) | |
f7625980 | 910 | return; |
1da177e4 | 911 | |
2d1d6678 | 912 | min_align = window_alignment(bus, IORESOURCE_IO); |
1da177e4 LT |
913 | list_for_each_entry(dev, &bus->devices, bus_list) { |
914 | int i; | |
915 | ||
916 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
917 | struct resource *r = &dev->resource[i]; | |
918 | unsigned long r_size; | |
919 | ||
920 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
921 | continue; | |
022edd86 | 922 | r_size = resource_size(r); |
1da177e4 LT |
923 | |
924 | if (r_size < 0x400) | |
925 | /* Might be re-aligned for ISA */ | |
926 | size += r_size; | |
927 | else | |
928 | size1 += r_size; | |
be768912 | 929 | |
fd591341 YL |
930 | align = pci_resource_alignment(dev, r); |
931 | if (align > min_align) | |
932 | min_align = align; | |
933 | ||
9e8bf93a RP |
934 | if (realloc_head) |
935 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
936 | } |
937 | } | |
fd591341 | 938 | |
c8adf9a3 | 939 | size0 = calculate_iosize(size, min_size, size1, |
fd591341 | 940 | resource_size(b_res), min_align); |
be768912 YL |
941 | if (children_add_size > add_size) |
942 | add_size = children_add_size; | |
9e8bf93a | 943 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 944 | calculate_iosize(size, min_size, add_size + size1, |
fd591341 | 945 | resource_size(b_res), min_align); |
c8adf9a3 | 946 | if (!size0 && !size1) { |
865df576 | 947 | if (b_res->start || b_res->end) |
227f0647 RD |
948 | dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", |
949 | b_res, &bus->busn_res); | |
1da177e4 LT |
950 | b_res->flags = 0; |
951 | return; | |
952 | } | |
fd591341 YL |
953 | |
954 | b_res->start = min_align; | |
c8adf9a3 | 955 | b_res->end = b_res->start + size0 - 1; |
88452565 | 956 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 957 | if (size1 > size0 && realloc_head) { |
fd591341 YL |
958 | add_to_list(realloc_head, bus->self, b_res, size1-size0, |
959 | min_align); | |
227f0647 RD |
960 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n", |
961 | b_res, &bus->busn_res, | |
962 | (unsigned long long)size1-size0); | |
b592443d | 963 | } |
1da177e4 LT |
964 | } |
965 | ||
c121504e GS |
966 | static inline resource_size_t calculate_mem_align(resource_size_t *aligns, |
967 | int max_order) | |
968 | { | |
969 | resource_size_t align = 0; | |
970 | resource_size_t min_align = 0; | |
971 | int order; | |
972 | ||
973 | for (order = 0; order <= max_order; order++) { | |
974 | resource_size_t align1 = 1; | |
975 | ||
976 | align1 <<= (order + 20); | |
977 | ||
978 | if (!align) | |
979 | min_align = align1; | |
980 | else if (ALIGN(align + min_align, min_align) < align1) | |
981 | min_align = align1 >> 1; | |
982 | align += aligns[order]; | |
983 | } | |
984 | ||
985 | return min_align; | |
986 | } | |
987 | ||
c8adf9a3 RP |
988 | /** |
989 | * pbus_size_mem() - size the memory window of a given bus | |
990 | * | |
991 | * @bus : the bus | |
496f70cf WY |
992 | * @mask: mask the resource flag, then compare it with type |
993 | * @type: the type of free resource from bridge | |
5b285415 YL |
994 | * @type2: second match type |
995 | * @type3: third match type | |
c8adf9a3 RP |
996 | * @min_size : the minimum memory window that must to be allocated |
997 | * @add_size : additional optional memory window | |
9e8bf93a | 998 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
999 | * |
1000 | * Calculate the size of the bus and minimal alignment which | |
1001 | * guarantees that all child resources fit in this size. | |
30afe8d0 BH |
1002 | * |
1003 | * Returns -ENOSPC if there's no available bus resource of the desired type. | |
1004 | * Otherwise, sets the bus resource start/end to indicate the required | |
1005 | * size, adds things to realloc_head (if supplied), and returns 0. | |
c8adf9a3 | 1006 | */ |
28760489 | 1007 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
5b285415 YL |
1008 | unsigned long type, unsigned long type2, |
1009 | unsigned long type3, | |
1010 | resource_size_t min_size, resource_size_t add_size, | |
1011 | struct list_head *realloc_head) | |
1da177e4 LT |
1012 | { |
1013 | struct pci_dev *dev; | |
c8adf9a3 | 1014 | resource_size_t min_align, align, size, size0, size1; |
096d4221 | 1015 | resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */ |
1da177e4 | 1016 | int order, max_order; |
5b285415 YL |
1017 | struct resource *b_res = find_free_bus_resource(bus, |
1018 | mask | IORESOURCE_PREFETCH, type); | |
be768912 | 1019 | resource_size_t children_add_size = 0; |
d74b9027 WY |
1020 | resource_size_t children_add_align = 0; |
1021 | resource_size_t add_align = 0; | |
1da177e4 LT |
1022 | |
1023 | if (!b_res) | |
30afe8d0 | 1024 | return -ENOSPC; |
1da177e4 LT |
1025 | |
1026 | memset(aligns, 0, sizeof(aligns)); | |
1027 | max_order = 0; | |
1028 | size = 0; | |
1029 | ||
1030 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1031 | int i; | |
1f82de10 | 1032 | |
1da177e4 LT |
1033 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
1034 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 1035 | resource_size_t r_size; |
1da177e4 | 1036 | |
5b285415 YL |
1037 | if (r->parent || ((r->flags & mask) != type && |
1038 | (r->flags & mask) != type2 && | |
1039 | (r->flags & mask) != type3)) | |
1da177e4 | 1040 | continue; |
022edd86 | 1041 | r_size = resource_size(r); |
2aceefcb YL |
1042 | #ifdef CONFIG_PCI_IOV |
1043 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 1044 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb | 1045 | i <= PCI_IOV_RESOURCE_END) { |
d74b9027 | 1046 | add_align = max(pci_resource_alignment(dev, r), add_align); |
2aceefcb | 1047 | r->end = r->start - 1; |
f7625980 | 1048 | add_to_list(realloc_head, dev, r, r_size, 0/* don't care */); |
2aceefcb YL |
1049 | children_add_size += r_size; |
1050 | continue; | |
1051 | } | |
1052 | #endif | |
14c8530d A |
1053 | /* |
1054 | * aligns[0] is for 1MB (since bridge memory | |
1055 | * windows are always at least 1MB aligned), so | |
1056 | * keep "order" from being negative for smaller | |
1057 | * resources. | |
1058 | */ | |
6faf17f6 | 1059 | align = pci_resource_alignment(dev, r); |
1da177e4 | 1060 | order = __ffs(align) - 20; |
14c8530d A |
1061 | if (order < 0) |
1062 | order = 0; | |
1063 | if (order >= ARRAY_SIZE(aligns)) { | |
227f0647 RD |
1064 | dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", |
1065 | i, r, (unsigned long long) align); | |
1da177e4 LT |
1066 | r->flags = 0; |
1067 | continue; | |
1068 | } | |
1069 | size += r_size; | |
1da177e4 LT |
1070 | /* Exclude ranges with size > align from |
1071 | calculation of the alignment. */ | |
1072 | if (r_size == align) | |
1073 | aligns[order] += align; | |
1074 | if (order > max_order) | |
1075 | max_order = order; | |
be768912 | 1076 | |
d74b9027 | 1077 | if (realloc_head) { |
9e8bf93a | 1078 | children_add_size += get_res_add_size(realloc_head, r); |
d74b9027 WY |
1079 | children_add_align = get_res_add_align(realloc_head, r); |
1080 | add_align = max(add_align, children_add_align); | |
1081 | } | |
1da177e4 LT |
1082 | } |
1083 | } | |
462d9303 | 1084 | |
c121504e | 1085 | min_align = calculate_mem_align(aligns, max_order); |
3ad94b0d | 1086 | min_align = max(min_align, window_alignment(bus, b_res->flags)); |
b42282e5 | 1087 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
d74b9027 | 1088 | add_align = max(min_align, add_align); |
be768912 YL |
1089 | if (children_add_size > add_size) |
1090 | add_size = children_add_size; | |
9e8bf93a | 1091 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 1092 | calculate_memsize(size, min_size, add_size, |
d74b9027 | 1093 | resource_size(b_res), add_align); |
c8adf9a3 | 1094 | if (!size0 && !size1) { |
865df576 | 1095 | if (b_res->start || b_res->end) |
227f0647 RD |
1096 | dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", |
1097 | b_res, &bus->busn_res); | |
1da177e4 | 1098 | b_res->flags = 0; |
30afe8d0 | 1099 | return 0; |
1da177e4 LT |
1100 | } |
1101 | b_res->start = min_align; | |
c8adf9a3 | 1102 | b_res->end = size0 + min_align - 1; |
5b285415 | 1103 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 1104 | if (size1 > size0 && realloc_head) { |
d74b9027 WY |
1105 | add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); |
1106 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n", | |
227f0647 | 1107 | b_res, &bus->busn_res, |
d74b9027 WY |
1108 | (unsigned long long) (size1 - size0), |
1109 | (unsigned long long) add_align); | |
b592443d | 1110 | } |
30afe8d0 | 1111 | return 0; |
1da177e4 LT |
1112 | } |
1113 | ||
0a2daa1c RP |
1114 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
1115 | { | |
1116 | if (res->flags & IORESOURCE_IO) | |
1117 | return pci_cardbus_io_size; | |
1118 | if (res->flags & IORESOURCE_MEM) | |
1119 | return pci_cardbus_mem_size; | |
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 1124 | struct list_head *realloc_head) |
1da177e4 LT |
1125 | { |
1126 | struct pci_dev *bridge = bus->self; | |
1127 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
11848934 | 1128 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
1da177e4 LT |
1129 | u16 ctrl; |
1130 | ||
3796f1e2 YL |
1131 | if (b_res[0].parent) |
1132 | goto handle_b_res_1; | |
1da177e4 LT |
1133 | /* |
1134 | * Reserve some resources for CardBus. We reserve | |
1135 | * a fixed amount of bus space for CardBus bridges. | |
1136 | */ | |
11848934 YL |
1137 | b_res[0].start = pci_cardbus_io_size; |
1138 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; | |
1139 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1140 | if (realloc_head) { | |
1141 | b_res[0].end -= pci_cardbus_io_size; | |
1142 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, | |
1143 | pci_cardbus_io_size); | |
1144 | } | |
1da177e4 | 1145 | |
3796f1e2 YL |
1146 | handle_b_res_1: |
1147 | if (b_res[1].parent) | |
1148 | goto handle_b_res_2; | |
11848934 YL |
1149 | b_res[1].start = pci_cardbus_io_size; |
1150 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; | |
1151 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1152 | if (realloc_head) { | |
1153 | b_res[1].end -= pci_cardbus_io_size; | |
1154 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, | |
1155 | pci_cardbus_io_size); | |
1156 | } | |
1da177e4 | 1157 | |
3796f1e2 | 1158 | handle_b_res_2: |
dcef0d06 YL |
1159 | /* MEM1 must not be pref mmio */ |
1160 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1161 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { | |
1162 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; | |
1163 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1164 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1165 | } | |
1166 | ||
1da177e4 LT |
1167 | /* |
1168 | * Check whether prefetchable memory is supported | |
1169 | * by this bridge. | |
1170 | */ | |
1171 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1172 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
1173 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
1174 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1175 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1176 | } | |
1177 | ||
3796f1e2 YL |
1178 | if (b_res[2].parent) |
1179 | goto handle_b_res_3; | |
1da177e4 LT |
1180 | /* |
1181 | * If we have prefetchable memory support, allocate | |
1182 | * two regions. Otherwise, allocate one region of | |
1183 | * twice the size. | |
1184 | */ | |
1185 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
11848934 YL |
1186 | b_res[2].start = pci_cardbus_mem_size; |
1187 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; | |
1188 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | | |
1189 | IORESOURCE_STARTALIGN; | |
1190 | if (realloc_head) { | |
1191 | b_res[2].end -= pci_cardbus_mem_size; | |
1192 | add_to_list(realloc_head, bridge, b_res+2, | |
1193 | pci_cardbus_mem_size, pci_cardbus_mem_size); | |
1194 | } | |
1195 | ||
1196 | /* reduce that to half */ | |
1197 | b_res_3_size = pci_cardbus_mem_size; | |
1198 | } | |
1199 | ||
3796f1e2 YL |
1200 | handle_b_res_3: |
1201 | if (b_res[3].parent) | |
1202 | goto handle_done; | |
11848934 YL |
1203 | b_res[3].start = pci_cardbus_mem_size; |
1204 | b_res[3].end = b_res[3].start + b_res_3_size - 1; | |
1205 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; | |
1206 | if (realloc_head) { | |
1207 | b_res[3].end -= b_res_3_size; | |
1208 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, | |
1209 | pci_cardbus_mem_size); | |
1210 | } | |
3796f1e2 YL |
1211 | |
1212 | handle_done: | |
1213 | ; | |
1da177e4 LT |
1214 | } |
1215 | ||
10874f5a | 1216 | void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) |
1da177e4 LT |
1217 | { |
1218 | struct pci_dev *dev; | |
5b285415 | 1219 | unsigned long mask, prefmask, type2 = 0, type3 = 0; |
c8adf9a3 | 1220 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
5b285415 | 1221 | struct resource *b_res; |
30afe8d0 | 1222 | int ret; |
1da177e4 LT |
1223 | |
1224 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1225 | struct pci_bus *b = dev->subordinate; | |
1226 | if (!b) | |
1227 | continue; | |
1228 | ||
1229 | switch (dev->class >> 8) { | |
1230 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 1231 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
1232 | break; |
1233 | ||
1234 | case PCI_CLASS_BRIDGE_PCI: | |
1235 | default: | |
9e8bf93a | 1236 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
1237 | break; |
1238 | } | |
1239 | } | |
1240 | ||
1241 | /* The root bus? */ | |
2ba29e27 | 1242 | if (pci_is_root_bus(bus)) |
1da177e4 LT |
1243 | return; |
1244 | ||
1245 | switch (bus->self->class >> 8) { | |
1246 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1247 | /* don't size cardbuses yet. */ | |
1248 | break; | |
1249 | ||
1250 | case PCI_CLASS_BRIDGE_PCI: | |
1251 | pci_bridge_check_ranges(bus); | |
28760489 | 1252 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
1253 | additional_io_size = pci_hotplug_io_size; |
1254 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 1255 | } |
67d29b5c | 1256 | /* Fall through */ |
1da177e4 | 1257 | default: |
19aa7ee4 YL |
1258 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1259 | additional_io_size, realloc_head); | |
67d29b5c BH |
1260 | |
1261 | /* | |
1262 | * If there's a 64-bit prefetchable MMIO window, compute | |
1263 | * the size required to put all 64-bit prefetchable | |
1264 | * resources in it. | |
1265 | */ | |
5b285415 | 1266 | b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES]; |
1da177e4 LT |
1267 | mask = IORESOURCE_MEM; |
1268 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
5b285415 YL |
1269 | if (b_res[2].flags & IORESOURCE_MEM_64) { |
1270 | prefmask |= IORESOURCE_MEM_64; | |
30afe8d0 | 1271 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 | 1272 | prefmask, prefmask, |
19aa7ee4 | 1273 | realloc_head ? 0 : additional_mem_size, |
30afe8d0 | 1274 | additional_mem_size, realloc_head); |
67d29b5c BH |
1275 | |
1276 | /* | |
1277 | * If successful, all non-prefetchable resources | |
1278 | * and any 32-bit prefetchable resources will go in | |
1279 | * the non-prefetchable window. | |
1280 | */ | |
30afe8d0 | 1281 | if (ret == 0) { |
30afe8d0 BH |
1282 | mask = prefmask; |
1283 | type2 = prefmask & ~IORESOURCE_MEM_64; | |
1284 | type3 = prefmask & ~IORESOURCE_PREFETCH; | |
5b285415 YL |
1285 | } |
1286 | } | |
67d29b5c BH |
1287 | |
1288 | /* | |
1289 | * If there is no 64-bit prefetchable window, compute the | |
1290 | * size required to put all prefetchable resources in the | |
1291 | * 32-bit prefetchable window (if there is one). | |
1292 | */ | |
5b285415 YL |
1293 | if (!type2) { |
1294 | prefmask &= ~IORESOURCE_MEM_64; | |
30afe8d0 | 1295 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 YL |
1296 | prefmask, prefmask, |
1297 | realloc_head ? 0 : additional_mem_size, | |
30afe8d0 | 1298 | additional_mem_size, realloc_head); |
67d29b5c BH |
1299 | |
1300 | /* | |
1301 | * If successful, only non-prefetchable resources | |
1302 | * will go in the non-prefetchable window. | |
1303 | */ | |
1304 | if (ret == 0) | |
5b285415 | 1305 | mask = prefmask; |
67d29b5c | 1306 | else |
5b285415 | 1307 | additional_mem_size += additional_mem_size; |
67d29b5c | 1308 | |
5b285415 YL |
1309 | type2 = type3 = IORESOURCE_MEM; |
1310 | } | |
67d29b5c BH |
1311 | |
1312 | /* | |
1313 | * Compute the size required to put everything else in the | |
1314 | * non-prefetchable window. This includes: | |
1315 | * | |
1316 | * - all non-prefetchable resources | |
1317 | * - 32-bit prefetchable resources if there's a 64-bit | |
1318 | * prefetchable window or no prefetchable window at all | |
1319 | * - 64-bit prefetchable resources if there's no | |
1320 | * prefetchable window at all | |
1321 | * | |
1322 | * Note that the strategy in __pci_assign_resource() must | |
1323 | * match that used here. Specifically, we cannot put a | |
1324 | * 32-bit prefetchable resource in a 64-bit prefetchable | |
1325 | * window. | |
1326 | */ | |
5b285415 | 1327 | pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, |
19aa7ee4 YL |
1328 | realloc_head ? 0 : additional_mem_size, |
1329 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1330 | break; |
1331 | } | |
1332 | } | |
c8adf9a3 | 1333 | |
10874f5a | 1334 | void pci_bus_size_bridges(struct pci_bus *bus) |
c8adf9a3 RP |
1335 | { |
1336 | __pci_bus_size_bridges(bus, NULL); | |
1337 | } | |
1da177e4 LT |
1338 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1339 | ||
10874f5a BH |
1340 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
1341 | struct list_head *realloc_head, | |
1342 | struct list_head *fail_head) | |
1da177e4 LT |
1343 | { |
1344 | struct pci_bus *b; | |
1345 | struct pci_dev *dev; | |
1346 | ||
9e8bf93a | 1347 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1348 | |
1da177e4 LT |
1349 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1350 | b = dev->subordinate; | |
1351 | if (!b) | |
1352 | continue; | |
1353 | ||
9e8bf93a | 1354 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1355 | |
1356 | switch (dev->class >> 8) { | |
1357 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1358 | if (!pci_is_enabled(dev)) |
1359 | pci_setup_bridge(b); | |
1da177e4 LT |
1360 | break; |
1361 | ||
1362 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1363 | pci_setup_cardbus(b); | |
1364 | break; | |
1365 | ||
1366 | default: | |
227f0647 RD |
1367 | dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n", |
1368 | pci_domain_nr(b), b->number); | |
1da177e4 LT |
1369 | break; |
1370 | } | |
1371 | } | |
1372 | } | |
568ddef8 | 1373 | |
10874f5a | 1374 | void pci_bus_assign_resources(const struct pci_bus *bus) |
568ddef8 | 1375 | { |
c8adf9a3 | 1376 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1377 | } |
1da177e4 LT |
1378 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1379 | ||
10874f5a BH |
1380 | static void __pci_bridge_assign_resources(const struct pci_dev *bridge, |
1381 | struct list_head *add_head, | |
1382 | struct list_head *fail_head) | |
6841ec68 YL |
1383 | { |
1384 | struct pci_bus *b; | |
1385 | ||
8424d759 YL |
1386 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1387 | add_head, fail_head); | |
6841ec68 YL |
1388 | |
1389 | b = bridge->subordinate; | |
1390 | if (!b) | |
1391 | return; | |
1392 | ||
8424d759 | 1393 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1394 | |
1395 | switch (bridge->class >> 8) { | |
1396 | case PCI_CLASS_BRIDGE_PCI: | |
1397 | pci_setup_bridge(b); | |
1398 | break; | |
1399 | ||
1400 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1401 | pci_setup_cardbus(b); | |
1402 | break; | |
1403 | ||
1404 | default: | |
227f0647 RD |
1405 | dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n", |
1406 | pci_domain_nr(b), b->number); | |
6841ec68 YL |
1407 | break; |
1408 | } | |
1409 | } | |
5009b460 YL |
1410 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1411 | unsigned long type) | |
1412 | { | |
5b285415 | 1413 | struct pci_dev *dev = bus->self; |
5009b460 YL |
1414 | struct resource *r; |
1415 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
5b285415 YL |
1416 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64; |
1417 | unsigned old_flags = 0; | |
1418 | struct resource *b_res; | |
1419 | int idx = 1; | |
5009b460 | 1420 | |
5b285415 YL |
1421 | b_res = &dev->resource[PCI_BRIDGE_RESOURCES]; |
1422 | ||
1423 | /* | |
1424 | * 1. if there is io port assign fail, will release bridge | |
1425 | * io port. | |
1426 | * 2. if there is non pref mmio assign fail, release bridge | |
1427 | * nonpref mmio. | |
1428 | * 3. if there is 64bit pref mmio assign fail, and bridge pref | |
1429 | * is 64bit, release bridge pref mmio. | |
1430 | * 4. if there is pref mmio assign fail, and bridge pref is | |
1431 | * 32bit mmio, release bridge pref mmio | |
1432 | * 5. if there is pref mmio assign fail, and bridge pref is not | |
1433 | * assigned, release bridge nonpref mmio. | |
1434 | */ | |
1435 | if (type & IORESOURCE_IO) | |
1436 | idx = 0; | |
1437 | else if (!(type & IORESOURCE_PREFETCH)) | |
1438 | idx = 1; | |
1439 | else if ((type & IORESOURCE_MEM_64) && | |
1440 | (b_res[2].flags & IORESOURCE_MEM_64)) | |
1441 | idx = 2; | |
1442 | else if (!(b_res[2].flags & IORESOURCE_MEM_64) && | |
1443 | (b_res[2].flags & IORESOURCE_PREFETCH)) | |
1444 | idx = 2; | |
1445 | else | |
1446 | idx = 1; | |
1447 | ||
1448 | r = &b_res[idx]; | |
1449 | ||
1450 | if (!r->parent) | |
1451 | return; | |
1452 | ||
1453 | /* | |
1454 | * if there are children under that, we should release them | |
1455 | * all | |
1456 | */ | |
1457 | release_child_resources(r); | |
1458 | if (!release_resource(r)) { | |
1459 | type = old_flags = r->flags & type_mask; | |
1460 | dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n", | |
1461 | PCI_BRIDGE_RESOURCES + idx, r); | |
1462 | /* keep the old size */ | |
1463 | r->end = resource_size(r) - 1; | |
1464 | r->start = 0; | |
1465 | r->flags = 0; | |
5009b460 | 1466 | |
5009b460 YL |
1467 | /* avoiding touch the one without PREF */ |
1468 | if (type & IORESOURCE_PREFETCH) | |
1469 | type = IORESOURCE_PREFETCH; | |
1470 | __pci_setup_bridge(bus, type); | |
5b285415 YL |
1471 | /* for next child res under same bridge */ |
1472 | r->flags = old_flags; | |
5009b460 YL |
1473 | } |
1474 | } | |
1475 | ||
1476 | enum release_type { | |
1477 | leaf_only, | |
1478 | whole_subtree, | |
1479 | }; | |
1480 | /* | |
1481 | * try to release pci bridge resources that is from leaf bridge, | |
1482 | * so we can allocate big new one later | |
1483 | */ | |
10874f5a BH |
1484 | static void pci_bus_release_bridge_resources(struct pci_bus *bus, |
1485 | unsigned long type, | |
1486 | enum release_type rel_type) | |
5009b460 YL |
1487 | { |
1488 | struct pci_dev *dev; | |
1489 | bool is_leaf_bridge = true; | |
1490 | ||
1491 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1492 | struct pci_bus *b = dev->subordinate; | |
1493 | if (!b) | |
1494 | continue; | |
1495 | ||
1496 | is_leaf_bridge = false; | |
1497 | ||
1498 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1499 | continue; | |
1500 | ||
1501 | if (rel_type == whole_subtree) | |
1502 | pci_bus_release_bridge_resources(b, type, | |
1503 | whole_subtree); | |
1504 | } | |
1505 | ||
1506 | if (pci_is_root_bus(bus)) | |
1507 | return; | |
1508 | ||
1509 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1510 | return; | |
1511 | ||
1512 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1513 | pci_bridge_release_resources(bus, type); | |
1514 | } | |
1515 | ||
76fbc263 YL |
1516 | static void pci_bus_dump_res(struct pci_bus *bus) |
1517 | { | |
89a74ecc BH |
1518 | struct resource *res; |
1519 | int i; | |
7c9342b8 | 1520 | |
89a74ecc | 1521 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1522 | if (!res || !res->end || !res->flags) |
3c78bc61 | 1523 | continue; |
76fbc263 | 1524 | |
c7dabef8 | 1525 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
3c78bc61 | 1526 | } |
76fbc263 YL |
1527 | } |
1528 | ||
1529 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1530 | { | |
1531 | struct pci_bus *b; | |
1532 | struct pci_dev *dev; | |
1533 | ||
1534 | ||
1535 | pci_bus_dump_res(bus); | |
1536 | ||
1537 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1538 | b = dev->subordinate; | |
1539 | if (!b) | |
1540 | continue; | |
1541 | ||
1542 | pci_bus_dump_resources(b); | |
1543 | } | |
1544 | } | |
1545 | ||
ff35147c | 1546 | static int pci_bus_get_depth(struct pci_bus *bus) |
da7822e5 YL |
1547 | { |
1548 | int depth = 0; | |
f2a230bd | 1549 | struct pci_bus *child_bus; |
da7822e5 | 1550 | |
3c78bc61 | 1551 | list_for_each_entry(child_bus, &bus->children, node) { |
da7822e5 | 1552 | int ret; |
da7822e5 | 1553 | |
f2a230bd | 1554 | ret = pci_bus_get_depth(child_bus); |
da7822e5 YL |
1555 | if (ret + 1 > depth) |
1556 | depth = ret + 1; | |
1557 | } | |
1558 | ||
1559 | return depth; | |
1560 | } | |
da7822e5 | 1561 | |
b55438fd YL |
1562 | /* |
1563 | * -1: undefined, will auto detect later | |
1564 | * 0: disabled by user | |
1565 | * 1: disabled by auto detect | |
1566 | * 2: enabled by user | |
1567 | * 3: enabled by auto detect | |
1568 | */ | |
1569 | enum enable_type { | |
1570 | undefined = -1, | |
1571 | user_disabled, | |
1572 | auto_disabled, | |
1573 | user_enabled, | |
1574 | auto_enabled, | |
1575 | }; | |
1576 | ||
ff35147c | 1577 | static enum enable_type pci_realloc_enable = undefined; |
b55438fd YL |
1578 | void __init pci_realloc_get_opt(char *str) |
1579 | { | |
1580 | if (!strncmp(str, "off", 3)) | |
1581 | pci_realloc_enable = user_disabled; | |
1582 | else if (!strncmp(str, "on", 2)) | |
1583 | pci_realloc_enable = user_enabled; | |
1584 | } | |
ff35147c | 1585 | static bool pci_realloc_enabled(enum enable_type enable) |
b55438fd | 1586 | { |
967260cd | 1587 | return enable >= user_enabled; |
b55438fd | 1588 | } |
f483d392 | 1589 | |
b07f2ebc | 1590 | #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) |
ff35147c | 1591 | static int iov_resources_unassigned(struct pci_dev *dev, void *data) |
223d96fc YL |
1592 | { |
1593 | int i; | |
1594 | bool *unassigned = data; | |
b07f2ebc | 1595 | |
223d96fc YL |
1596 | for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { |
1597 | struct resource *r = &dev->resource[i]; | |
fa216bf4 | 1598 | struct pci_bus_region region; |
b07f2ebc | 1599 | |
223d96fc | 1600 | /* Not assigned or rejected by kernel? */ |
fa216bf4 YL |
1601 | if (!r->flags) |
1602 | continue; | |
b07f2ebc | 1603 | |
fc279850 | 1604 | pcibios_resource_to_bus(dev->bus, ®ion, r); |
fa216bf4 | 1605 | if (!region.start) { |
223d96fc YL |
1606 | *unassigned = true; |
1607 | return 1; /* return early from pci_walk_bus() */ | |
b07f2ebc YL |
1608 | } |
1609 | } | |
b07f2ebc | 1610 | |
223d96fc | 1611 | return 0; |
b07f2ebc YL |
1612 | } |
1613 | ||
ff35147c | 1614 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd | 1615 | enum enable_type enable_local) |
223d96fc YL |
1616 | { |
1617 | bool unassigned = false; | |
b07f2ebc | 1618 | |
967260cd YL |
1619 | if (enable_local != undefined) |
1620 | return enable_local; | |
223d96fc | 1621 | |
967260cd YL |
1622 | pci_walk_bus(bus, iov_resources_unassigned, &unassigned); |
1623 | if (unassigned) | |
1624 | return auto_enabled; | |
1625 | ||
1626 | return enable_local; | |
b07f2ebc | 1627 | } |
223d96fc | 1628 | #else |
ff35147c | 1629 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd YL |
1630 | enum enable_type enable_local) |
1631 | { | |
1632 | return enable_local; | |
b07f2ebc | 1633 | } |
223d96fc | 1634 | #endif |
b07f2ebc | 1635 | |
da7822e5 YL |
1636 | /* |
1637 | * first try will not touch pci bridge res | |
f7625980 BH |
1638 | * second and later try will clear small leaf bridge res |
1639 | * will stop till to the max depth if can not find good one | |
da7822e5 | 1640 | */ |
39772038 | 1641 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) |
1da177e4 | 1642 | { |
bdc4abec | 1643 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1644 | want additional resources */ |
bdc4abec | 1645 | struct list_head *add_list = NULL; |
da7822e5 YL |
1646 | int tried_times = 0; |
1647 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1648 | LIST_HEAD(fail_head); |
b9b0bba9 | 1649 | struct pci_dev_resource *fail_res; |
da7822e5 | 1650 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
5b285415 | 1651 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64; |
19aa7ee4 | 1652 | int pci_try_num = 1; |
55ed83a6 | 1653 | enum enable_type enable_local; |
da7822e5 | 1654 | |
19aa7ee4 | 1655 | /* don't realloc if asked to do so */ |
55ed83a6 | 1656 | enable_local = pci_realloc_detect(bus, pci_realloc_enable); |
967260cd | 1657 | if (pci_realloc_enabled(enable_local)) { |
55ed83a6 | 1658 | int max_depth = pci_bus_get_depth(bus); |
19aa7ee4 YL |
1659 | |
1660 | pci_try_num = max_depth + 1; | |
55ed83a6 YL |
1661 | dev_printk(KERN_DEBUG, &bus->dev, |
1662 | "max bus depth: %d pci_try_num: %d\n", | |
1663 | max_depth, pci_try_num); | |
19aa7ee4 | 1664 | } |
da7822e5 YL |
1665 | |
1666 | again: | |
19aa7ee4 YL |
1667 | /* |
1668 | * last try will use add_list, otherwise will try good to have as | |
1669 | * must have, so can realloc parent bridge resource | |
1670 | */ | |
1671 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1672 | add_list = &realloc_head; |
1da177e4 LT |
1673 | /* Depth first, calculate sizes and alignments of all |
1674 | subordinate buses. */ | |
55ed83a6 | 1675 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1676 | |
1da177e4 | 1677 | /* Depth last, allocate resources and update the hardware. */ |
55ed83a6 | 1678 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1679 | if (add_list) |
bdc4abec | 1680 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1681 | tried_times++; |
1682 | ||
1683 | /* any device complain? */ | |
bdc4abec | 1684 | if (list_empty(&fail_head)) |
928bea96 | 1685 | goto dump; |
f483d392 | 1686 | |
0c5be0cb | 1687 | if (tried_times >= pci_try_num) { |
967260cd | 1688 | if (enable_local == undefined) |
55ed83a6 | 1689 | dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); |
967260cd | 1690 | else if (enable_local == auto_enabled) |
55ed83a6 | 1691 | dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); |
eb572e7c | 1692 | |
bffc56d4 | 1693 | free_list(&fail_head); |
928bea96 | 1694 | goto dump; |
da7822e5 YL |
1695 | } |
1696 | ||
55ed83a6 YL |
1697 | dev_printk(KERN_DEBUG, &bus->dev, |
1698 | "No. %d try to assign unassigned res\n", tried_times + 1); | |
da7822e5 YL |
1699 | |
1700 | /* third times and later will not check if it is leaf */ | |
1701 | if ((tried_times + 1) > 2) | |
1702 | rel_type = whole_subtree; | |
1703 | ||
1704 | /* | |
1705 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1706 | * child device under that bridge | |
1707 | */ | |
61e83cdd YL |
1708 | list_for_each_entry(fail_res, &fail_head, list) |
1709 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
b9b0bba9 | 1710 | fail_res->flags & type_mask, |
bdc4abec | 1711 | rel_type); |
61e83cdd | 1712 | |
da7822e5 | 1713 | /* restore size and flags */ |
b9b0bba9 YL |
1714 | list_for_each_entry(fail_res, &fail_head, list) { |
1715 | struct resource *res = fail_res->res; | |
da7822e5 | 1716 | |
b9b0bba9 YL |
1717 | res->start = fail_res->start; |
1718 | res->end = fail_res->end; | |
1719 | res->flags = fail_res->flags; | |
1720 | if (fail_res->dev->subordinate) | |
da7822e5 | 1721 | res->flags = 0; |
da7822e5 | 1722 | } |
bffc56d4 | 1723 | free_list(&fail_head); |
da7822e5 YL |
1724 | |
1725 | goto again; | |
1726 | ||
928bea96 | 1727 | dump: |
76fbc263 | 1728 | /* dump the resource on buses */ |
55ed83a6 YL |
1729 | pci_bus_dump_resources(bus); |
1730 | } | |
1731 | ||
1732 | void __init pci_assign_unassigned_resources(void) | |
1733 | { | |
1734 | struct pci_bus *root_bus; | |
1735 | ||
1736 | list_for_each_entry(root_bus, &pci_root_buses, node) | |
1737 | pci_assign_unassigned_root_bus_resources(root_bus); | |
1da177e4 | 1738 | } |
6841ec68 YL |
1739 | |
1740 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1741 | { | |
1742 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1743 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1744 | want additional resources */ |
32180e40 | 1745 | int tried_times = 0; |
bdc4abec | 1746 | LIST_HEAD(fail_head); |
b9b0bba9 | 1747 | struct pci_dev_resource *fail_res; |
6841ec68 | 1748 | int retval; |
32180e40 | 1749 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
d61b0e87 | 1750 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64; |
32180e40 | 1751 | |
32180e40 | 1752 | again: |
8424d759 | 1753 | __pci_bus_size_bridges(parent, &add_list); |
bdc4abec YL |
1754 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1755 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
1756 | tried_times++; |
1757 | ||
bdc4abec | 1758 | if (list_empty(&fail_head)) |
3f579c34 | 1759 | goto enable_all; |
32180e40 YL |
1760 | |
1761 | if (tried_times >= 2) { | |
1762 | /* still fail, don't need to try more */ | |
bffc56d4 | 1763 | free_list(&fail_head); |
3f579c34 | 1764 | goto enable_all; |
32180e40 YL |
1765 | } |
1766 | ||
1767 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1768 | tried_times + 1); | |
1769 | ||
1770 | /* | |
1771 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1772 | * child device under that bridge | |
1773 | */ | |
61e83cdd YL |
1774 | list_for_each_entry(fail_res, &fail_head, list) |
1775 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
1776 | fail_res->flags & type_mask, | |
32180e40 | 1777 | whole_subtree); |
61e83cdd | 1778 | |
32180e40 | 1779 | /* restore size and flags */ |
b9b0bba9 YL |
1780 | list_for_each_entry(fail_res, &fail_head, list) { |
1781 | struct resource *res = fail_res->res; | |
32180e40 | 1782 | |
b9b0bba9 YL |
1783 | res->start = fail_res->start; |
1784 | res->end = fail_res->end; | |
1785 | res->flags = fail_res->flags; | |
1786 | if (fail_res->dev->subordinate) | |
32180e40 | 1787 | res->flags = 0; |
32180e40 | 1788 | } |
bffc56d4 | 1789 | free_list(&fail_head); |
32180e40 YL |
1790 | |
1791 | goto again; | |
3f579c34 YL |
1792 | |
1793 | enable_all: | |
1794 | retval = pci_reenable_device(bridge); | |
9fc9eea0 BH |
1795 | if (retval) |
1796 | dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval); | |
3f579c34 | 1797 | pci_set_master(bridge); |
6841ec68 YL |
1798 | } |
1799 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f | 1800 | |
17787940 | 1801 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus) |
9b03088f | 1802 | { |
9b03088f | 1803 | struct pci_dev *dev; |
bdc4abec | 1804 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
1805 | want additional resources */ |
1806 | ||
9b03088f YL |
1807 | down_read(&pci_bus_sem); |
1808 | list_for_each_entry(dev, &bus->devices, bus_list) | |
6788a51f | 1809 | if (pci_is_bridge(dev) && pci_has_subordinate(dev)) |
9b03088f YL |
1810 | __pci_bus_size_bridges(dev->subordinate, |
1811 | &add_list); | |
1812 | up_read(&pci_bus_sem); | |
1813 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 1814 | BUG_ON(!list_empty(&add_list)); |
17787940 | 1815 | } |
e6b29dea | 1816 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); |