Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
47087700 | 28 | #include <asm-generic/pci-bridge.h> |
6faf17f6 | 29 | #include "pci.h" |
1da177e4 | 30 | |
844393f4 | 31 | unsigned int pci_flags; |
47087700 | 32 | |
bdc4abec YL |
33 | struct pci_dev_resource { |
34 | struct list_head list; | |
2934a0de YL |
35 | struct resource *res; |
36 | struct pci_dev *dev; | |
568ddef8 YL |
37 | resource_size_t start; |
38 | resource_size_t end; | |
c8adf9a3 | 39 | resource_size_t add_size; |
2bbc6942 | 40 | resource_size_t min_align; |
568ddef8 YL |
41 | unsigned long flags; |
42 | }; | |
43 | ||
bffc56d4 YL |
44 | static void free_list(struct list_head *head) |
45 | { | |
46 | struct pci_dev_resource *dev_res, *tmp; | |
47 | ||
48 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
49 | list_del(&dev_res->list); | |
50 | kfree(dev_res); | |
51 | } | |
52 | } | |
094732a5 | 53 | |
c8adf9a3 RP |
54 | /** |
55 | * add_to_list() - add a new resource tracker to the list | |
56 | * @head: Head of the list | |
57 | * @dev: device corresponding to which the resource | |
58 | * belongs | |
59 | * @res: The resource to be tracked | |
60 | * @add_size: additional size to be optionally added | |
61 | * to the resource | |
62 | */ | |
bdc4abec | 63 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 64 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 65 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 66 | { |
764242a0 | 67 | struct pci_dev_resource *tmp; |
568ddef8 | 68 | |
bdc4abec | 69 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 70 | if (!tmp) { |
3c78bc61 | 71 | pr_warn("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 72 | return -ENOMEM; |
568ddef8 YL |
73 | } |
74 | ||
568ddef8 YL |
75 | tmp->res = res; |
76 | tmp->dev = dev; | |
77 | tmp->start = res->start; | |
78 | tmp->end = res->end; | |
79 | tmp->flags = res->flags; | |
c8adf9a3 | 80 | tmp->add_size = add_size; |
2bbc6942 | 81 | tmp->min_align = min_align; |
bdc4abec YL |
82 | |
83 | list_add(&tmp->list, head); | |
ef62dfef YL |
84 | |
85 | return 0; | |
568ddef8 YL |
86 | } |
87 | ||
b9b0bba9 | 88 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
89 | struct resource *res) |
90 | { | |
b9b0bba9 | 91 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 92 | |
b9b0bba9 YL |
93 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
94 | if (dev_res->res == res) { | |
95 | list_del(&dev_res->list); | |
96 | kfree(dev_res); | |
bdc4abec | 97 | break; |
3e6e0d80 | 98 | } |
3e6e0d80 YL |
99 | } |
100 | } | |
101 | ||
b9b0bba9 | 102 | static resource_size_t get_res_add_size(struct list_head *head, |
1c372353 YL |
103 | struct resource *res) |
104 | { | |
b9b0bba9 | 105 | struct pci_dev_resource *dev_res; |
bdc4abec | 106 | |
b9b0bba9 YL |
107 | list_for_each_entry(dev_res, head, list) { |
108 | if (dev_res->res == res) { | |
b592443d YL |
109 | int idx = res - &dev_res->dev->resource[0]; |
110 | ||
b9b0bba9 | 111 | dev_printk(KERN_DEBUG, &dev_res->dev->dev, |
b592443d YL |
112 | "res[%d]=%pR get_res_add_size add_size %llx\n", |
113 | idx, dev_res->res, | |
b9b0bba9 | 114 | (unsigned long long)dev_res->add_size); |
b592443d | 115 | |
b9b0bba9 | 116 | return dev_res->add_size; |
bdc4abec | 117 | } |
3e6e0d80 | 118 | } |
1c372353 YL |
119 | |
120 | return 0; | |
121 | } | |
122 | ||
78c3b329 | 123 | /* Sort resources by alignment */ |
bdc4abec | 124 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
125 | { |
126 | int i; | |
127 | ||
128 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
129 | struct resource *r; | |
bdc4abec | 130 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 131 | resource_size_t r_align; |
bdc4abec | 132 | struct list_head *n; |
78c3b329 YL |
133 | |
134 | r = &dev->resource[i]; | |
135 | ||
136 | if (r->flags & IORESOURCE_PCI_FIXED) | |
137 | continue; | |
138 | ||
139 | if (!(r->flags) || r->parent) | |
140 | continue; | |
141 | ||
142 | r_align = pci_resource_alignment(dev, r); | |
143 | if (!r_align) { | |
144 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
145 | i, r); | |
146 | continue; | |
147 | } | |
78c3b329 | 148 | |
bdc4abec YL |
149 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
150 | if (!tmp) | |
227f0647 | 151 | panic("pdev_sort_resources(): kmalloc() failed!\n"); |
bdc4abec YL |
152 | tmp->res = r; |
153 | tmp->dev = dev; | |
154 | ||
155 | /* fallback is smallest one or list is empty*/ | |
156 | n = head; | |
157 | list_for_each_entry(dev_res, head, list) { | |
158 | resource_size_t align; | |
159 | ||
160 | align = pci_resource_alignment(dev_res->dev, | |
161 | dev_res->res); | |
78c3b329 YL |
162 | |
163 | if (r_align > align) { | |
bdc4abec | 164 | n = &dev_res->list; |
78c3b329 YL |
165 | break; |
166 | } | |
167 | } | |
bdc4abec YL |
168 | /* Insert it just before n*/ |
169 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
170 | } |
171 | } | |
172 | ||
6841ec68 | 173 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 174 | struct list_head *head) |
1da177e4 | 175 | { |
6841ec68 | 176 | u16 class = dev->class >> 8; |
1da177e4 | 177 | |
6841ec68 YL |
178 | /* Don't touch classless devices or host bridges or ioapics. */ |
179 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
180 | return; | |
1da177e4 | 181 | |
6841ec68 YL |
182 | /* Don't touch ioapic devices already enabled by firmware */ |
183 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
184 | u16 command; | |
185 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
186 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
187 | return; | |
188 | } | |
1da177e4 | 189 | |
6841ec68 YL |
190 | pdev_sort_resources(dev, head); |
191 | } | |
23186279 | 192 | |
fc075e1d RP |
193 | static inline void reset_resource(struct resource *res) |
194 | { | |
195 | res->start = 0; | |
196 | res->end = 0; | |
197 | res->flags = 0; | |
198 | } | |
199 | ||
c8adf9a3 | 200 | /** |
9e8bf93a | 201 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 202 | * |
9e8bf93a | 203 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
204 | * resources |
205 | * @head : head of the list tracking requests with allocated | |
206 | * resources | |
207 | * | |
9e8bf93a | 208 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
209 | * additional resources for the element, provided the element |
210 | * is in the head list. | |
211 | */ | |
bdc4abec YL |
212 | static void reassign_resources_sorted(struct list_head *realloc_head, |
213 | struct list_head *head) | |
6841ec68 YL |
214 | { |
215 | struct resource *res; | |
b9b0bba9 | 216 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 217 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 218 | resource_size_t add_size; |
6841ec68 | 219 | int idx; |
1da177e4 | 220 | |
b9b0bba9 | 221 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
222 | bool found_match = false; |
223 | ||
b9b0bba9 | 224 | res = add_res->res; |
c8adf9a3 RP |
225 | /* skip resource that has been reset */ |
226 | if (!res->flags) | |
227 | goto out; | |
228 | ||
229 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
230 | list_for_each_entry(dev_res, head, list) { |
231 | if (dev_res->res == res) { | |
232 | found_match = true; | |
233 | break; | |
234 | } | |
c8adf9a3 | 235 | } |
bdc4abec YL |
236 | if (!found_match)/* just skip */ |
237 | continue; | |
c8adf9a3 | 238 | |
b9b0bba9 YL |
239 | idx = res - &add_res->dev->resource[0]; |
240 | add_size = add_res->add_size; | |
2bbc6942 | 241 | if (!resource_size(res)) { |
b9b0bba9 | 242 | res->start = add_res->start; |
2bbc6942 | 243 | res->end = res->start + add_size - 1; |
b9b0bba9 | 244 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 245 | reset_resource(res); |
2bbc6942 | 246 | } else { |
b9b0bba9 YL |
247 | resource_size_t align = add_res->min_align; |
248 | res->flags |= add_res->flags & | |
bdc4abec | 249 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 250 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 251 | add_size, align)) |
b9b0bba9 | 252 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
b592443d YL |
253 | "failed to add %llx res[%d]=%pR\n", |
254 | (unsigned long long)add_size, | |
255 | idx, res); | |
c8adf9a3 RP |
256 | } |
257 | out: | |
b9b0bba9 YL |
258 | list_del(&add_res->list); |
259 | kfree(add_res); | |
c8adf9a3 RP |
260 | } |
261 | } | |
262 | ||
263 | /** | |
264 | * assign_requested_resources_sorted() - satisfy resource requests | |
265 | * | |
266 | * @head : head of the list tracking requests for resources | |
8356aad4 | 267 | * @fail_head : head of the list tracking requests that could |
c8adf9a3 RP |
268 | * not be allocated |
269 | * | |
270 | * Satisfy resource requests of each element in the list. Add | |
271 | * requests that could not satisfied to the failed_list. | |
272 | */ | |
bdc4abec YL |
273 | static void assign_requested_resources_sorted(struct list_head *head, |
274 | struct list_head *fail_head) | |
c8adf9a3 RP |
275 | { |
276 | struct resource *res; | |
bdc4abec | 277 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 278 | int idx; |
9a928660 | 279 | |
bdc4abec YL |
280 | list_for_each_entry(dev_res, head, list) { |
281 | res = dev_res->res; | |
282 | idx = res - &dev_res->dev->resource[0]; | |
283 | if (resource_size(res) && | |
284 | pci_assign_resource(dev_res->dev, idx)) { | |
a3cb999d | 285 | if (fail_head) { |
9a928660 YL |
286 | /* |
287 | * if the failed res is for ROM BAR, and it will | |
288 | * be enabled later, don't add it to the list | |
289 | */ | |
290 | if (!((idx == PCI_ROM_RESOURCE) && | |
291 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
67cc7e26 YL |
292 | add_to_list(fail_head, |
293 | dev_res->dev, res, | |
f7625980 BH |
294 | 0 /* don't care */, |
295 | 0 /* don't care */); | |
9a928660 | 296 | } |
fc075e1d | 297 | reset_resource(res); |
542df5de | 298 | } |
1da177e4 LT |
299 | } |
300 | } | |
301 | ||
aa914f5e YL |
302 | static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) |
303 | { | |
304 | struct pci_dev_resource *fail_res; | |
305 | unsigned long mask = 0; | |
306 | ||
307 | /* check failed type */ | |
308 | list_for_each_entry(fail_res, fail_head, list) | |
309 | mask |= fail_res->flags; | |
310 | ||
311 | /* | |
312 | * one pref failed resource will set IORESOURCE_MEM, | |
313 | * as we can allocate pref in non-pref range. | |
314 | * Will release all assigned non-pref sibling resources | |
315 | * according to that bit. | |
316 | */ | |
317 | return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
318 | } | |
319 | ||
320 | static bool pci_need_to_release(unsigned long mask, struct resource *res) | |
321 | { | |
322 | if (res->flags & IORESOURCE_IO) | |
323 | return !!(mask & IORESOURCE_IO); | |
324 | ||
325 | /* check pref at first */ | |
326 | if (res->flags & IORESOURCE_PREFETCH) { | |
327 | if (mask & IORESOURCE_PREFETCH) | |
328 | return true; | |
329 | /* count pref if its parent is non-pref */ | |
330 | else if ((mask & IORESOURCE_MEM) && | |
331 | !(res->parent->flags & IORESOURCE_PREFETCH)) | |
332 | return true; | |
333 | else | |
334 | return false; | |
335 | } | |
336 | ||
337 | if (res->flags & IORESOURCE_MEM) | |
338 | return !!(mask & IORESOURCE_MEM); | |
339 | ||
340 | return false; /* should not get here */ | |
341 | } | |
342 | ||
bdc4abec YL |
343 | static void __assign_resources_sorted(struct list_head *head, |
344 | struct list_head *realloc_head, | |
345 | struct list_head *fail_head) | |
c8adf9a3 | 346 | { |
3e6e0d80 YL |
347 | /* |
348 | * Should not assign requested resources at first. | |
349 | * they could be adjacent, so later reassign can not reallocate | |
350 | * them one by one in parent resource window. | |
367fa982 | 351 | * Try to assign requested + add_size at beginning |
3e6e0d80 YL |
352 | * if could do that, could get out early. |
353 | * if could not do that, we still try to assign requested at first, | |
354 | * then try to reassign add_size for some resources. | |
aa914f5e YL |
355 | * |
356 | * Separate three resource type checking if we need to release | |
357 | * assigned resource after requested + add_size try. | |
358 | * 1. if there is io port assign fail, will release assigned | |
359 | * io port. | |
360 | * 2. if there is pref mmio assign fail, release assigned | |
361 | * pref mmio. | |
362 | * if assigned pref mmio's parent is non-pref mmio and there | |
363 | * is non-pref mmio assign fail, will release that assigned | |
364 | * pref mmio. | |
365 | * 3. if there is non-pref mmio assign fail or pref mmio | |
366 | * assigned fail, will release assigned non-pref mmio. | |
3e6e0d80 | 367 | */ |
bdc4abec YL |
368 | LIST_HEAD(save_head); |
369 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 370 | struct pci_dev_resource *save_res; |
aa914f5e YL |
371 | struct pci_dev_resource *dev_res, *tmp_res; |
372 | unsigned long fail_type; | |
3e6e0d80 YL |
373 | |
374 | /* Check if optional add_size is there */ | |
bdc4abec | 375 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
376 | goto requested_and_reassign; |
377 | ||
378 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
379 | list_for_each_entry(dev_res, head, list) { |
380 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 381 | free_list(&save_head); |
3e6e0d80 YL |
382 | goto requested_and_reassign; |
383 | } | |
bdc4abec | 384 | } |
3e6e0d80 YL |
385 | |
386 | /* Update res in head list with add_size in realloc_head list */ | |
bdc4abec YL |
387 | list_for_each_entry(dev_res, head, list) |
388 | dev_res->res->end += get_res_add_size(realloc_head, | |
389 | dev_res->res); | |
3e6e0d80 YL |
390 | |
391 | /* Try updated head list with add_size added */ | |
3e6e0d80 YL |
392 | assign_requested_resources_sorted(head, &local_fail_head); |
393 | ||
394 | /* all assigned with add_size ? */ | |
bdc4abec | 395 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 396 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
397 | list_for_each_entry(dev_res, head, list) |
398 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
399 | free_list(&save_head); |
400 | free_list(head); | |
3e6e0d80 YL |
401 | return; |
402 | } | |
403 | ||
aa914f5e YL |
404 | /* check failed type */ |
405 | fail_type = pci_fail_res_type_mask(&local_fail_head); | |
406 | /* remove not need to be released assigned res from head list etc */ | |
407 | list_for_each_entry_safe(dev_res, tmp_res, head, list) | |
408 | if (dev_res->res->parent && | |
409 | !pci_need_to_release(fail_type, dev_res->res)) { | |
410 | /* remove it from realloc_head list */ | |
411 | remove_from_list(realloc_head, dev_res->res); | |
412 | remove_from_list(&save_head, dev_res->res); | |
413 | list_del(&dev_res->list); | |
414 | kfree(dev_res); | |
415 | } | |
416 | ||
bffc56d4 | 417 | free_list(&local_fail_head); |
3e6e0d80 | 418 | /* Release assigned resource */ |
bdc4abec YL |
419 | list_for_each_entry(dev_res, head, list) |
420 | if (dev_res->res->parent) | |
421 | release_resource(dev_res->res); | |
3e6e0d80 | 422 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
423 | list_for_each_entry(save_res, &save_head, list) { |
424 | struct resource *res = save_res->res; | |
3e6e0d80 | 425 | |
b9b0bba9 YL |
426 | res->start = save_res->start; |
427 | res->end = save_res->end; | |
428 | res->flags = save_res->flags; | |
3e6e0d80 | 429 | } |
bffc56d4 | 430 | free_list(&save_head); |
3e6e0d80 YL |
431 | |
432 | requested_and_reassign: | |
c8adf9a3 RP |
433 | /* Satisfy the must-have resource requests */ |
434 | assign_requested_resources_sorted(head, fail_head); | |
435 | ||
0a2daa1c | 436 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 437 | requests */ |
9e8bf93a RP |
438 | if (realloc_head) |
439 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 440 | free_list(head); |
c8adf9a3 RP |
441 | } |
442 | ||
6841ec68 | 443 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
444 | struct list_head *add_head, |
445 | struct list_head *fail_head) | |
6841ec68 | 446 | { |
bdc4abec | 447 | LIST_HEAD(head); |
6841ec68 | 448 | |
6841ec68 | 449 | __dev_sort_resources(dev, &head); |
8424d759 | 450 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
451 | |
452 | } | |
453 | ||
454 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
455 | struct list_head *realloc_head, |
456 | struct list_head *fail_head) | |
6841ec68 YL |
457 | { |
458 | struct pci_dev *dev; | |
bdc4abec | 459 | LIST_HEAD(head); |
6841ec68 | 460 | |
6841ec68 YL |
461 | list_for_each_entry(dev, &bus->devices, bus_list) |
462 | __dev_sort_resources(dev, &head); | |
463 | ||
9e8bf93a | 464 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
465 | } |
466 | ||
b3743fa4 | 467 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
468 | { |
469 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 470 | struct resource *res; |
1da177e4 LT |
471 | struct pci_bus_region region; |
472 | ||
b918c62e YL |
473 | dev_info(&bridge->dev, "CardBus bridge to %pR\n", |
474 | &bus->busn_res); | |
1da177e4 | 475 | |
c7dabef8 | 476 | res = bus->resource[0]; |
fc279850 | 477 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 478 | if (res->flags & IORESOURCE_IO) { |
1da177e4 LT |
479 | /* |
480 | * The IO resource is allocated a range twice as large as it | |
481 | * would normally need. This allows us to set both IO regs. | |
482 | */ | |
c7dabef8 | 483 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
484 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
485 | region.start); | |
486 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
487 | region.end); | |
488 | } | |
489 | ||
c7dabef8 | 490 | res = bus->resource[1]; |
fc279850 | 491 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
492 | if (res->flags & IORESOURCE_IO) { |
493 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
494 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
495 | region.start); | |
496 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
497 | region.end); | |
498 | } | |
499 | ||
c7dabef8 | 500 | res = bus->resource[2]; |
fc279850 | 501 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
502 | if (res->flags & IORESOURCE_MEM) { |
503 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
504 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
505 | region.start); | |
506 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
507 | region.end); | |
508 | } | |
509 | ||
c7dabef8 | 510 | res = bus->resource[3]; |
fc279850 | 511 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
512 | if (res->flags & IORESOURCE_MEM) { |
513 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
514 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
515 | region.start); | |
516 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
517 | region.end); | |
518 | } | |
519 | } | |
b3743fa4 | 520 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
521 | |
522 | /* Initialize bridges with base/limit values we have collected. | |
523 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
524 | requires that if there is no I/O ports or memory behind the | |
525 | bridge, corresponding range must be turned off by writing base | |
526 | value greater than limit to the bridge's base/limit registers. | |
527 | ||
528 | Note: care must be taken when updating I/O base/limit registers | |
529 | of bridges which support 32-bit I/O. This update requires two | |
530 | config space writes, so it's quite possible that an I/O window of | |
531 | the bridge will have some undesirable address (e.g. 0) after the | |
532 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 533 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
534 | { |
535 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 536 | struct resource *res; |
1da177e4 | 537 | struct pci_bus_region region; |
2b28ae19 BH |
538 | unsigned long io_mask; |
539 | u8 io_base_lo, io_limit_lo; | |
5b764b83 BH |
540 | u16 l; |
541 | u32 io_upper16; | |
1da177e4 | 542 | |
2b28ae19 BH |
543 | io_mask = PCI_IO_RANGE_MASK; |
544 | if (bridge->io_window_1k) | |
545 | io_mask = PCI_IO_1K_RANGE_MASK; | |
546 | ||
1da177e4 | 547 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
c7dabef8 | 548 | res = bus->resource[0]; |
fc279850 | 549 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 550 | if (res->flags & IORESOURCE_IO) { |
5b764b83 | 551 | pci_read_config_word(bridge, PCI_IO_BASE, &l); |
2b28ae19 BH |
552 | io_base_lo = (region.start >> 8) & io_mask; |
553 | io_limit_lo = (region.end >> 8) & io_mask; | |
5b764b83 | 554 | l = ((u16) io_limit_lo << 8) | io_base_lo; |
1da177e4 LT |
555 | /* Set up upper 16 bits of I/O base/limit. */ |
556 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 557 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 558 | } else { |
1da177e4 LT |
559 | /* Clear upper 16 bits of I/O base/limit. */ |
560 | io_upper16 = 0; | |
561 | l = 0x00f0; | |
1da177e4 LT |
562 | } |
563 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
564 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
565 | /* Update lower 16 bits of I/O base/limit. */ | |
5b764b83 | 566 | pci_write_config_word(bridge, PCI_IO_BASE, l); |
1da177e4 LT |
567 | /* Update upper 16 bits of I/O base/limit. */ |
568 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
569 | } |
570 | ||
571 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
572 | { | |
573 | struct pci_dev *bridge = bus->self; | |
574 | struct resource *res; | |
575 | struct pci_bus_region region; | |
576 | u32 l; | |
1da177e4 | 577 | |
7cc5997d | 578 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 | 579 | res = bus->resource[1]; |
fc279850 | 580 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 581 | if (res->flags & IORESOURCE_MEM) { |
1da177e4 LT |
582 | l = (region.start >> 16) & 0xfff0; |
583 | l |= region.end & 0xfff00000; | |
c7dabef8 | 584 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 585 | } else { |
1da177e4 | 586 | l = 0x0000fff0; |
1da177e4 LT |
587 | } |
588 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
589 | } |
590 | ||
591 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
592 | { | |
593 | struct pci_dev *bridge = bus->self; | |
594 | struct resource *res; | |
595 | struct pci_bus_region region; | |
596 | u32 l, bu, lu; | |
1da177e4 LT |
597 | |
598 | /* Clear out the upper 32 bits of PREF limit. | |
599 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
600 | disables PREF range, which is ok. */ | |
601 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
602 | ||
603 | /* Set up PREF base/limit. */ | |
c40a22e0 | 604 | bu = lu = 0; |
c7dabef8 | 605 | res = bus->resource[2]; |
fc279850 | 606 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 607 | if (res->flags & IORESOURCE_PREFETCH) { |
1da177e4 LT |
608 | l = (region.start >> 16) & 0xfff0; |
609 | l |= region.end & 0xfff00000; | |
c7dabef8 | 610 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
611 | bu = upper_32_bits(region.start); |
612 | lu = upper_32_bits(region.end); | |
1f82de10 | 613 | } |
c7dabef8 | 614 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 615 | } else { |
1da177e4 | 616 | l = 0x0000fff0; |
1da177e4 LT |
617 | } |
618 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
619 | ||
59353ea3 AW |
620 | /* Set the upper 32 bits of PREF base & limit. */ |
621 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
622 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
623 | } |
624 | ||
625 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
626 | { | |
627 | struct pci_dev *bridge = bus->self; | |
628 | ||
b918c62e YL |
629 | dev_info(&bridge->dev, "PCI bridge to %pR\n", |
630 | &bus->busn_res); | |
7cc5997d YL |
631 | |
632 | if (type & IORESOURCE_IO) | |
633 | pci_setup_bridge_io(bus); | |
634 | ||
635 | if (type & IORESOURCE_MEM) | |
636 | pci_setup_bridge_mmio(bus); | |
637 | ||
638 | if (type & IORESOURCE_PREFETCH) | |
639 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
640 | |
641 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
642 | } | |
643 | ||
e2444273 | 644 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
645 | { |
646 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
647 | IORESOURCE_PREFETCH; | |
648 | ||
649 | __pci_setup_bridge(bus, type); | |
650 | } | |
651 | ||
1da177e4 LT |
652 | /* Check whether the bridge supports optional I/O and |
653 | prefetchable memory ranges. If not, the respective | |
654 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 655 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
656 | { |
657 | u16 io; | |
658 | u32 pmem; | |
659 | struct pci_dev *bridge = bus->self; | |
660 | struct resource *b_res; | |
661 | ||
662 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
663 | b_res[1].flags |= IORESOURCE_MEM; | |
664 | ||
665 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
666 | if (!io) { | |
d2f54d9b | 667 | pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); |
1da177e4 | 668 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
f7625980 BH |
669 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); |
670 | } | |
671 | if (io) | |
1da177e4 | 672 | b_res[0].flags |= IORESOURCE_IO; |
d2f54d9b | 673 | |
1da177e4 LT |
674 | /* DECchip 21050 pass 2 errata: the bridge may miss an address |
675 | disconnect boundary by one PCI data phase. | |
676 | Workaround: do not use prefetching on this device. */ | |
677 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
678 | return; | |
d2f54d9b | 679 | |
1da177e4 LT |
680 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
681 | if (!pmem) { | |
682 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
d2f54d9b | 683 | 0xffe0fff0); |
1da177e4 LT |
684 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
685 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
686 | } | |
1f82de10 | 687 | if (pmem) { |
1da177e4 | 688 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
689 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
690 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 691 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
692 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
693 | } | |
1f82de10 YL |
694 | } |
695 | ||
696 | /* double check if bridge does support 64 bit pref */ | |
697 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
698 | u32 mem_base_hi, tmp; | |
699 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
700 | &mem_base_hi); | |
701 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
702 | 0xffffffff); | |
703 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
704 | if (!tmp) | |
705 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
706 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
707 | mem_base_hi); | |
708 | } | |
1da177e4 LT |
709 | } |
710 | ||
711 | /* Helper function for sizing routines: find first available | |
712 | bus resource of a given type. Note: we intentionally skip | |
713 | the bus resources which have already been assigned (that is, | |
714 | have non-NULL parent resource). */ | |
5b285415 YL |
715 | static struct resource *find_free_bus_resource(struct pci_bus *bus, |
716 | unsigned long type_mask, unsigned long type) | |
1da177e4 LT |
717 | { |
718 | int i; | |
719 | struct resource *r; | |
1da177e4 | 720 | |
89a74ecc | 721 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
722 | if (r == &ioport_resource || r == &iomem_resource) |
723 | continue; | |
55a10984 JB |
724 | if (r && (r->flags & type_mask) == type && !r->parent) |
725 | return r; | |
1da177e4 LT |
726 | } |
727 | return NULL; | |
728 | } | |
729 | ||
13583b16 RP |
730 | static resource_size_t calculate_iosize(resource_size_t size, |
731 | resource_size_t min_size, | |
732 | resource_size_t size1, | |
733 | resource_size_t old_size, | |
734 | resource_size_t align) | |
735 | { | |
736 | if (size < min_size) | |
737 | size = min_size; | |
3c78bc61 | 738 | if (old_size == 1) |
13583b16 RP |
739 | old_size = 0; |
740 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
741 | flag in the struct pci_bus. */ | |
742 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
743 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
744 | #endif | |
745 | size = ALIGN(size + size1, align); | |
746 | if (size < old_size) | |
747 | size = old_size; | |
748 | return size; | |
749 | } | |
750 | ||
751 | static resource_size_t calculate_memsize(resource_size_t size, | |
752 | resource_size_t min_size, | |
753 | resource_size_t size1, | |
754 | resource_size_t old_size, | |
755 | resource_size_t align) | |
756 | { | |
757 | if (size < min_size) | |
758 | size = min_size; | |
3c78bc61 | 759 | if (old_size == 1) |
13583b16 RP |
760 | old_size = 0; |
761 | if (size < old_size) | |
762 | size = old_size; | |
763 | size = ALIGN(size + size1, align); | |
764 | return size; | |
765 | } | |
766 | ||
ac5ad93e GS |
767 | resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, |
768 | unsigned long type) | |
769 | { | |
770 | return 1; | |
771 | } | |
772 | ||
773 | #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ | |
774 | #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ | |
775 | #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ | |
776 | ||
777 | static resource_size_t window_alignment(struct pci_bus *bus, | |
778 | unsigned long type) | |
779 | { | |
780 | resource_size_t align = 1, arch_align; | |
781 | ||
782 | if (type & IORESOURCE_MEM) | |
783 | align = PCI_P2P_DEFAULT_MEM_ALIGN; | |
784 | else if (type & IORESOURCE_IO) { | |
785 | /* | |
786 | * Per spec, I/O windows are 4K-aligned, but some | |
787 | * bridges have an extension to support 1K alignment. | |
788 | */ | |
789 | if (bus->self->io_window_1k) | |
790 | align = PCI_P2P_DEFAULT_IO_ALIGN_1K; | |
791 | else | |
792 | align = PCI_P2P_DEFAULT_IO_ALIGN; | |
793 | } | |
794 | ||
795 | arch_align = pcibios_window_alignment(bus, type); | |
796 | return max(align, arch_align); | |
797 | } | |
798 | ||
c8adf9a3 RP |
799 | /** |
800 | * pbus_size_io() - size the io window of a given bus | |
801 | * | |
802 | * @bus : the bus | |
803 | * @min_size : the minimum io window that must to be allocated | |
804 | * @add_size : additional optional io window | |
9e8bf93a | 805 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
806 | * |
807 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
fd591341 | 808 | * since these windows have 1K or 4K granularity and the IO ranges |
c8adf9a3 RP |
809 | * of non-bridge PCI devices are limited to 256 bytes. |
810 | * We must be careful with the ISA aliasing though. | |
811 | */ | |
812 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 813 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
814 | { |
815 | struct pci_dev *dev; | |
5b285415 YL |
816 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO, |
817 | IORESOURCE_IO); | |
11251a86 | 818 | resource_size_t size = 0, size0 = 0, size1 = 0; |
be768912 | 819 | resource_size_t children_add_size = 0; |
2d1d6678 | 820 | resource_size_t min_align, align; |
1da177e4 LT |
821 | |
822 | if (!b_res) | |
f7625980 | 823 | return; |
1da177e4 | 824 | |
2d1d6678 | 825 | min_align = window_alignment(bus, IORESOURCE_IO); |
1da177e4 LT |
826 | list_for_each_entry(dev, &bus->devices, bus_list) { |
827 | int i; | |
828 | ||
829 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
830 | struct resource *r = &dev->resource[i]; | |
831 | unsigned long r_size; | |
832 | ||
833 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
834 | continue; | |
022edd86 | 835 | r_size = resource_size(r); |
1da177e4 LT |
836 | |
837 | if (r_size < 0x400) | |
838 | /* Might be re-aligned for ISA */ | |
839 | size += r_size; | |
840 | else | |
841 | size1 += r_size; | |
be768912 | 842 | |
fd591341 YL |
843 | align = pci_resource_alignment(dev, r); |
844 | if (align > min_align) | |
845 | min_align = align; | |
846 | ||
9e8bf93a RP |
847 | if (realloc_head) |
848 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
849 | } |
850 | } | |
fd591341 | 851 | |
c8adf9a3 | 852 | size0 = calculate_iosize(size, min_size, size1, |
fd591341 | 853 | resource_size(b_res), min_align); |
be768912 YL |
854 | if (children_add_size > add_size) |
855 | add_size = children_add_size; | |
9e8bf93a | 856 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 857 | calculate_iosize(size, min_size, add_size + size1, |
fd591341 | 858 | resource_size(b_res), min_align); |
c8adf9a3 | 859 | if (!size0 && !size1) { |
865df576 | 860 | if (b_res->start || b_res->end) |
227f0647 RD |
861 | dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", |
862 | b_res, &bus->busn_res); | |
1da177e4 LT |
863 | b_res->flags = 0; |
864 | return; | |
865 | } | |
fd591341 YL |
866 | |
867 | b_res->start = min_align; | |
c8adf9a3 | 868 | b_res->end = b_res->start + size0 - 1; |
88452565 | 869 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 870 | if (size1 > size0 && realloc_head) { |
fd591341 YL |
871 | add_to_list(realloc_head, bus->self, b_res, size1-size0, |
872 | min_align); | |
227f0647 RD |
873 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n", |
874 | b_res, &bus->busn_res, | |
875 | (unsigned long long)size1-size0); | |
b592443d | 876 | } |
1da177e4 LT |
877 | } |
878 | ||
c121504e GS |
879 | static inline resource_size_t calculate_mem_align(resource_size_t *aligns, |
880 | int max_order) | |
881 | { | |
882 | resource_size_t align = 0; | |
883 | resource_size_t min_align = 0; | |
884 | int order; | |
885 | ||
886 | for (order = 0; order <= max_order; order++) { | |
887 | resource_size_t align1 = 1; | |
888 | ||
889 | align1 <<= (order + 20); | |
890 | ||
891 | if (!align) | |
892 | min_align = align1; | |
893 | else if (ALIGN(align + min_align, min_align) < align1) | |
894 | min_align = align1 >> 1; | |
895 | align += aligns[order]; | |
896 | } | |
897 | ||
898 | return min_align; | |
899 | } | |
900 | ||
c8adf9a3 RP |
901 | /** |
902 | * pbus_size_mem() - size the memory window of a given bus | |
903 | * | |
904 | * @bus : the bus | |
496f70cf WY |
905 | * @mask: mask the resource flag, then compare it with type |
906 | * @type: the type of free resource from bridge | |
5b285415 YL |
907 | * @type2: second match type |
908 | * @type3: third match type | |
c8adf9a3 RP |
909 | * @min_size : the minimum memory window that must to be allocated |
910 | * @add_size : additional optional memory window | |
9e8bf93a | 911 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
912 | * |
913 | * Calculate the size of the bus and minimal alignment which | |
914 | * guarantees that all child resources fit in this size. | |
30afe8d0 BH |
915 | * |
916 | * Returns -ENOSPC if there's no available bus resource of the desired type. | |
917 | * Otherwise, sets the bus resource start/end to indicate the required | |
918 | * size, adds things to realloc_head (if supplied), and returns 0. | |
c8adf9a3 | 919 | */ |
28760489 | 920 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
5b285415 YL |
921 | unsigned long type, unsigned long type2, |
922 | unsigned long type3, | |
923 | resource_size_t min_size, resource_size_t add_size, | |
924 | struct list_head *realloc_head) | |
1da177e4 LT |
925 | { |
926 | struct pci_dev *dev; | |
c8adf9a3 | 927 | resource_size_t min_align, align, size, size0, size1; |
096d4221 | 928 | resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */ |
1da177e4 | 929 | int order, max_order; |
5b285415 YL |
930 | struct resource *b_res = find_free_bus_resource(bus, |
931 | mask | IORESOURCE_PREFETCH, type); | |
be768912 | 932 | resource_size_t children_add_size = 0; |
1da177e4 LT |
933 | |
934 | if (!b_res) | |
30afe8d0 | 935 | return -ENOSPC; |
1da177e4 LT |
936 | |
937 | memset(aligns, 0, sizeof(aligns)); | |
938 | max_order = 0; | |
939 | size = 0; | |
940 | ||
941 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
942 | int i; | |
1f82de10 | 943 | |
1da177e4 LT |
944 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
945 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 946 | resource_size_t r_size; |
1da177e4 | 947 | |
5b285415 YL |
948 | if (r->parent || ((r->flags & mask) != type && |
949 | (r->flags & mask) != type2 && | |
950 | (r->flags & mask) != type3)) | |
1da177e4 | 951 | continue; |
022edd86 | 952 | r_size = resource_size(r); |
2aceefcb YL |
953 | #ifdef CONFIG_PCI_IOV |
954 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 955 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb YL |
956 | i <= PCI_IOV_RESOURCE_END) { |
957 | r->end = r->start - 1; | |
f7625980 | 958 | add_to_list(realloc_head, dev, r, r_size, 0/* don't care */); |
2aceefcb YL |
959 | children_add_size += r_size; |
960 | continue; | |
961 | } | |
962 | #endif | |
14c8530d A |
963 | /* |
964 | * aligns[0] is for 1MB (since bridge memory | |
965 | * windows are always at least 1MB aligned), so | |
966 | * keep "order" from being negative for smaller | |
967 | * resources. | |
968 | */ | |
6faf17f6 | 969 | align = pci_resource_alignment(dev, r); |
1da177e4 | 970 | order = __ffs(align) - 20; |
14c8530d A |
971 | if (order < 0) |
972 | order = 0; | |
973 | if (order >= ARRAY_SIZE(aligns)) { | |
227f0647 RD |
974 | dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", |
975 | i, r, (unsigned long long) align); | |
1da177e4 LT |
976 | r->flags = 0; |
977 | continue; | |
978 | } | |
979 | size += r_size; | |
1da177e4 LT |
980 | /* Exclude ranges with size > align from |
981 | calculation of the alignment. */ | |
982 | if (r_size == align) | |
983 | aligns[order] += align; | |
984 | if (order > max_order) | |
985 | max_order = order; | |
be768912 | 986 | |
9e8bf93a RP |
987 | if (realloc_head) |
988 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
989 | } |
990 | } | |
462d9303 | 991 | |
c121504e | 992 | min_align = calculate_mem_align(aligns, max_order); |
3ad94b0d | 993 | min_align = max(min_align, window_alignment(bus, b_res->flags)); |
b42282e5 | 994 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
be768912 YL |
995 | if (children_add_size > add_size) |
996 | add_size = children_add_size; | |
9e8bf93a | 997 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 998 | calculate_memsize(size, min_size, add_size, |
b42282e5 | 999 | resource_size(b_res), min_align); |
c8adf9a3 | 1000 | if (!size0 && !size1) { |
865df576 | 1001 | if (b_res->start || b_res->end) |
227f0647 RD |
1002 | dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", |
1003 | b_res, &bus->busn_res); | |
1da177e4 | 1004 | b_res->flags = 0; |
30afe8d0 | 1005 | return 0; |
1da177e4 LT |
1006 | } |
1007 | b_res->start = min_align; | |
c8adf9a3 | 1008 | b_res->end = size0 + min_align - 1; |
5b285415 | 1009 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 1010 | if (size1 > size0 && realloc_head) { |
9e8bf93a | 1011 | add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); |
227f0647 RD |
1012 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n", |
1013 | b_res, &bus->busn_res, | |
1014 | (unsigned long long)size1-size0); | |
b592443d | 1015 | } |
30afe8d0 | 1016 | return 0; |
1da177e4 LT |
1017 | } |
1018 | ||
0a2daa1c RP |
1019 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
1020 | { | |
1021 | if (res->flags & IORESOURCE_IO) | |
1022 | return pci_cardbus_io_size; | |
1023 | if (res->flags & IORESOURCE_MEM) | |
1024 | return pci_cardbus_mem_size; | |
1025 | return 0; | |
1026 | } | |
1027 | ||
1028 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 1029 | struct list_head *realloc_head) |
1da177e4 LT |
1030 | { |
1031 | struct pci_dev *bridge = bus->self; | |
1032 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
11848934 | 1033 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
1da177e4 LT |
1034 | u16 ctrl; |
1035 | ||
3796f1e2 YL |
1036 | if (b_res[0].parent) |
1037 | goto handle_b_res_1; | |
1da177e4 LT |
1038 | /* |
1039 | * Reserve some resources for CardBus. We reserve | |
1040 | * a fixed amount of bus space for CardBus bridges. | |
1041 | */ | |
11848934 YL |
1042 | b_res[0].start = pci_cardbus_io_size; |
1043 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; | |
1044 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1045 | if (realloc_head) { | |
1046 | b_res[0].end -= pci_cardbus_io_size; | |
1047 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, | |
1048 | pci_cardbus_io_size); | |
1049 | } | |
1da177e4 | 1050 | |
3796f1e2 YL |
1051 | handle_b_res_1: |
1052 | if (b_res[1].parent) | |
1053 | goto handle_b_res_2; | |
11848934 YL |
1054 | b_res[1].start = pci_cardbus_io_size; |
1055 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; | |
1056 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1057 | if (realloc_head) { | |
1058 | b_res[1].end -= pci_cardbus_io_size; | |
1059 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, | |
1060 | pci_cardbus_io_size); | |
1061 | } | |
1da177e4 | 1062 | |
3796f1e2 | 1063 | handle_b_res_2: |
dcef0d06 YL |
1064 | /* MEM1 must not be pref mmio */ |
1065 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1066 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { | |
1067 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; | |
1068 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1069 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1070 | } | |
1071 | ||
1da177e4 LT |
1072 | /* |
1073 | * Check whether prefetchable memory is supported | |
1074 | * by this bridge. | |
1075 | */ | |
1076 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1077 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
1078 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
1079 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1080 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1081 | } | |
1082 | ||
3796f1e2 YL |
1083 | if (b_res[2].parent) |
1084 | goto handle_b_res_3; | |
1da177e4 LT |
1085 | /* |
1086 | * If we have prefetchable memory support, allocate | |
1087 | * two regions. Otherwise, allocate one region of | |
1088 | * twice the size. | |
1089 | */ | |
1090 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
11848934 YL |
1091 | b_res[2].start = pci_cardbus_mem_size; |
1092 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; | |
1093 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | | |
1094 | IORESOURCE_STARTALIGN; | |
1095 | if (realloc_head) { | |
1096 | b_res[2].end -= pci_cardbus_mem_size; | |
1097 | add_to_list(realloc_head, bridge, b_res+2, | |
1098 | pci_cardbus_mem_size, pci_cardbus_mem_size); | |
1099 | } | |
1100 | ||
1101 | /* reduce that to half */ | |
1102 | b_res_3_size = pci_cardbus_mem_size; | |
1103 | } | |
1104 | ||
3796f1e2 YL |
1105 | handle_b_res_3: |
1106 | if (b_res[3].parent) | |
1107 | goto handle_done; | |
11848934 YL |
1108 | b_res[3].start = pci_cardbus_mem_size; |
1109 | b_res[3].end = b_res[3].start + b_res_3_size - 1; | |
1110 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; | |
1111 | if (realloc_head) { | |
1112 | b_res[3].end -= b_res_3_size; | |
1113 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, | |
1114 | pci_cardbus_mem_size); | |
1115 | } | |
3796f1e2 YL |
1116 | |
1117 | handle_done: | |
1118 | ; | |
1da177e4 LT |
1119 | } |
1120 | ||
10874f5a | 1121 | void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) |
1da177e4 LT |
1122 | { |
1123 | struct pci_dev *dev; | |
5b285415 | 1124 | unsigned long mask, prefmask, type2 = 0, type3 = 0; |
c8adf9a3 | 1125 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
5b285415 | 1126 | struct resource *b_res; |
30afe8d0 | 1127 | int ret; |
1da177e4 LT |
1128 | |
1129 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1130 | struct pci_bus *b = dev->subordinate; | |
1131 | if (!b) | |
1132 | continue; | |
1133 | ||
1134 | switch (dev->class >> 8) { | |
1135 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 1136 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
1137 | break; |
1138 | ||
1139 | case PCI_CLASS_BRIDGE_PCI: | |
1140 | default: | |
9e8bf93a | 1141 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
1142 | break; |
1143 | } | |
1144 | } | |
1145 | ||
1146 | /* The root bus? */ | |
2ba29e27 | 1147 | if (pci_is_root_bus(bus)) |
1da177e4 LT |
1148 | return; |
1149 | ||
1150 | switch (bus->self->class >> 8) { | |
1151 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1152 | /* don't size cardbuses yet. */ | |
1153 | break; | |
1154 | ||
1155 | case PCI_CLASS_BRIDGE_PCI: | |
1156 | pci_bridge_check_ranges(bus); | |
28760489 | 1157 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
1158 | additional_io_size = pci_hotplug_io_size; |
1159 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 1160 | } |
67d29b5c | 1161 | /* Fall through */ |
1da177e4 | 1162 | default: |
19aa7ee4 YL |
1163 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1164 | additional_io_size, realloc_head); | |
67d29b5c BH |
1165 | |
1166 | /* | |
1167 | * If there's a 64-bit prefetchable MMIO window, compute | |
1168 | * the size required to put all 64-bit prefetchable | |
1169 | * resources in it. | |
1170 | */ | |
5b285415 | 1171 | b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES]; |
1da177e4 LT |
1172 | mask = IORESOURCE_MEM; |
1173 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
5b285415 YL |
1174 | if (b_res[2].flags & IORESOURCE_MEM_64) { |
1175 | prefmask |= IORESOURCE_MEM_64; | |
30afe8d0 | 1176 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 | 1177 | prefmask, prefmask, |
19aa7ee4 | 1178 | realloc_head ? 0 : additional_mem_size, |
30afe8d0 | 1179 | additional_mem_size, realloc_head); |
67d29b5c BH |
1180 | |
1181 | /* | |
1182 | * If successful, all non-prefetchable resources | |
1183 | * and any 32-bit prefetchable resources will go in | |
1184 | * the non-prefetchable window. | |
1185 | */ | |
30afe8d0 | 1186 | if (ret == 0) { |
30afe8d0 BH |
1187 | mask = prefmask; |
1188 | type2 = prefmask & ~IORESOURCE_MEM_64; | |
1189 | type3 = prefmask & ~IORESOURCE_PREFETCH; | |
5b285415 YL |
1190 | } |
1191 | } | |
67d29b5c BH |
1192 | |
1193 | /* | |
1194 | * If there is no 64-bit prefetchable window, compute the | |
1195 | * size required to put all prefetchable resources in the | |
1196 | * 32-bit prefetchable window (if there is one). | |
1197 | */ | |
5b285415 YL |
1198 | if (!type2) { |
1199 | prefmask &= ~IORESOURCE_MEM_64; | |
30afe8d0 | 1200 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 YL |
1201 | prefmask, prefmask, |
1202 | realloc_head ? 0 : additional_mem_size, | |
30afe8d0 | 1203 | additional_mem_size, realloc_head); |
67d29b5c BH |
1204 | |
1205 | /* | |
1206 | * If successful, only non-prefetchable resources | |
1207 | * will go in the non-prefetchable window. | |
1208 | */ | |
1209 | if (ret == 0) | |
5b285415 | 1210 | mask = prefmask; |
67d29b5c | 1211 | else |
5b285415 | 1212 | additional_mem_size += additional_mem_size; |
67d29b5c | 1213 | |
5b285415 YL |
1214 | type2 = type3 = IORESOURCE_MEM; |
1215 | } | |
67d29b5c BH |
1216 | |
1217 | /* | |
1218 | * Compute the size required to put everything else in the | |
1219 | * non-prefetchable window. This includes: | |
1220 | * | |
1221 | * - all non-prefetchable resources | |
1222 | * - 32-bit prefetchable resources if there's a 64-bit | |
1223 | * prefetchable window or no prefetchable window at all | |
1224 | * - 64-bit prefetchable resources if there's no | |
1225 | * prefetchable window at all | |
1226 | * | |
1227 | * Note that the strategy in __pci_assign_resource() must | |
1228 | * match that used here. Specifically, we cannot put a | |
1229 | * 32-bit prefetchable resource in a 64-bit prefetchable | |
1230 | * window. | |
1231 | */ | |
5b285415 | 1232 | pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, |
19aa7ee4 YL |
1233 | realloc_head ? 0 : additional_mem_size, |
1234 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1235 | break; |
1236 | } | |
1237 | } | |
c8adf9a3 | 1238 | |
10874f5a | 1239 | void pci_bus_size_bridges(struct pci_bus *bus) |
c8adf9a3 RP |
1240 | { |
1241 | __pci_bus_size_bridges(bus, NULL); | |
1242 | } | |
1da177e4 LT |
1243 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1244 | ||
10874f5a BH |
1245 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
1246 | struct list_head *realloc_head, | |
1247 | struct list_head *fail_head) | |
1da177e4 LT |
1248 | { |
1249 | struct pci_bus *b; | |
1250 | struct pci_dev *dev; | |
1251 | ||
9e8bf93a | 1252 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1253 | |
1da177e4 LT |
1254 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1255 | b = dev->subordinate; | |
1256 | if (!b) | |
1257 | continue; | |
1258 | ||
9e8bf93a | 1259 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1260 | |
1261 | switch (dev->class >> 8) { | |
1262 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1263 | if (!pci_is_enabled(dev)) |
1264 | pci_setup_bridge(b); | |
1da177e4 LT |
1265 | break; |
1266 | ||
1267 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1268 | pci_setup_cardbus(b); | |
1269 | break; | |
1270 | ||
1271 | default: | |
227f0647 RD |
1272 | dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n", |
1273 | pci_domain_nr(b), b->number); | |
1da177e4 LT |
1274 | break; |
1275 | } | |
1276 | } | |
1277 | } | |
568ddef8 | 1278 | |
10874f5a | 1279 | void pci_bus_assign_resources(const struct pci_bus *bus) |
568ddef8 | 1280 | { |
c8adf9a3 | 1281 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1282 | } |
1da177e4 LT |
1283 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1284 | ||
10874f5a BH |
1285 | static void __pci_bridge_assign_resources(const struct pci_dev *bridge, |
1286 | struct list_head *add_head, | |
1287 | struct list_head *fail_head) | |
6841ec68 YL |
1288 | { |
1289 | struct pci_bus *b; | |
1290 | ||
8424d759 YL |
1291 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1292 | add_head, fail_head); | |
6841ec68 YL |
1293 | |
1294 | b = bridge->subordinate; | |
1295 | if (!b) | |
1296 | return; | |
1297 | ||
8424d759 | 1298 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1299 | |
1300 | switch (bridge->class >> 8) { | |
1301 | case PCI_CLASS_BRIDGE_PCI: | |
1302 | pci_setup_bridge(b); | |
1303 | break; | |
1304 | ||
1305 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1306 | pci_setup_cardbus(b); | |
1307 | break; | |
1308 | ||
1309 | default: | |
227f0647 RD |
1310 | dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n", |
1311 | pci_domain_nr(b), b->number); | |
6841ec68 YL |
1312 | break; |
1313 | } | |
1314 | } | |
5009b460 YL |
1315 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1316 | unsigned long type) | |
1317 | { | |
5b285415 | 1318 | struct pci_dev *dev = bus->self; |
5009b460 YL |
1319 | struct resource *r; |
1320 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
5b285415 YL |
1321 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64; |
1322 | unsigned old_flags = 0; | |
1323 | struct resource *b_res; | |
1324 | int idx = 1; | |
5009b460 | 1325 | |
5b285415 YL |
1326 | b_res = &dev->resource[PCI_BRIDGE_RESOURCES]; |
1327 | ||
1328 | /* | |
1329 | * 1. if there is io port assign fail, will release bridge | |
1330 | * io port. | |
1331 | * 2. if there is non pref mmio assign fail, release bridge | |
1332 | * nonpref mmio. | |
1333 | * 3. if there is 64bit pref mmio assign fail, and bridge pref | |
1334 | * is 64bit, release bridge pref mmio. | |
1335 | * 4. if there is pref mmio assign fail, and bridge pref is | |
1336 | * 32bit mmio, release bridge pref mmio | |
1337 | * 5. if there is pref mmio assign fail, and bridge pref is not | |
1338 | * assigned, release bridge nonpref mmio. | |
1339 | */ | |
1340 | if (type & IORESOURCE_IO) | |
1341 | idx = 0; | |
1342 | else if (!(type & IORESOURCE_PREFETCH)) | |
1343 | idx = 1; | |
1344 | else if ((type & IORESOURCE_MEM_64) && | |
1345 | (b_res[2].flags & IORESOURCE_MEM_64)) | |
1346 | idx = 2; | |
1347 | else if (!(b_res[2].flags & IORESOURCE_MEM_64) && | |
1348 | (b_res[2].flags & IORESOURCE_PREFETCH)) | |
1349 | idx = 2; | |
1350 | else | |
1351 | idx = 1; | |
1352 | ||
1353 | r = &b_res[idx]; | |
1354 | ||
1355 | if (!r->parent) | |
1356 | return; | |
1357 | ||
1358 | /* | |
1359 | * if there are children under that, we should release them | |
1360 | * all | |
1361 | */ | |
1362 | release_child_resources(r); | |
1363 | if (!release_resource(r)) { | |
1364 | type = old_flags = r->flags & type_mask; | |
1365 | dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n", | |
1366 | PCI_BRIDGE_RESOURCES + idx, r); | |
1367 | /* keep the old size */ | |
1368 | r->end = resource_size(r) - 1; | |
1369 | r->start = 0; | |
1370 | r->flags = 0; | |
5009b460 | 1371 | |
5009b460 YL |
1372 | /* avoiding touch the one without PREF */ |
1373 | if (type & IORESOURCE_PREFETCH) | |
1374 | type = IORESOURCE_PREFETCH; | |
1375 | __pci_setup_bridge(bus, type); | |
5b285415 YL |
1376 | /* for next child res under same bridge */ |
1377 | r->flags = old_flags; | |
5009b460 YL |
1378 | } |
1379 | } | |
1380 | ||
1381 | enum release_type { | |
1382 | leaf_only, | |
1383 | whole_subtree, | |
1384 | }; | |
1385 | /* | |
1386 | * try to release pci bridge resources that is from leaf bridge, | |
1387 | * so we can allocate big new one later | |
1388 | */ | |
10874f5a BH |
1389 | static void pci_bus_release_bridge_resources(struct pci_bus *bus, |
1390 | unsigned long type, | |
1391 | enum release_type rel_type) | |
5009b460 YL |
1392 | { |
1393 | struct pci_dev *dev; | |
1394 | bool is_leaf_bridge = true; | |
1395 | ||
1396 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1397 | struct pci_bus *b = dev->subordinate; | |
1398 | if (!b) | |
1399 | continue; | |
1400 | ||
1401 | is_leaf_bridge = false; | |
1402 | ||
1403 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1404 | continue; | |
1405 | ||
1406 | if (rel_type == whole_subtree) | |
1407 | pci_bus_release_bridge_resources(b, type, | |
1408 | whole_subtree); | |
1409 | } | |
1410 | ||
1411 | if (pci_is_root_bus(bus)) | |
1412 | return; | |
1413 | ||
1414 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1415 | return; | |
1416 | ||
1417 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1418 | pci_bridge_release_resources(bus, type); | |
1419 | } | |
1420 | ||
76fbc263 YL |
1421 | static void pci_bus_dump_res(struct pci_bus *bus) |
1422 | { | |
89a74ecc BH |
1423 | struct resource *res; |
1424 | int i; | |
7c9342b8 | 1425 | |
89a74ecc | 1426 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1427 | if (!res || !res->end || !res->flags) |
3c78bc61 | 1428 | continue; |
76fbc263 | 1429 | |
c7dabef8 | 1430 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
3c78bc61 | 1431 | } |
76fbc263 YL |
1432 | } |
1433 | ||
1434 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1435 | { | |
1436 | struct pci_bus *b; | |
1437 | struct pci_dev *dev; | |
1438 | ||
1439 | ||
1440 | pci_bus_dump_res(bus); | |
1441 | ||
1442 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1443 | b = dev->subordinate; | |
1444 | if (!b) | |
1445 | continue; | |
1446 | ||
1447 | pci_bus_dump_resources(b); | |
1448 | } | |
1449 | } | |
1450 | ||
ff35147c | 1451 | static int pci_bus_get_depth(struct pci_bus *bus) |
da7822e5 YL |
1452 | { |
1453 | int depth = 0; | |
f2a230bd | 1454 | struct pci_bus *child_bus; |
da7822e5 | 1455 | |
3c78bc61 | 1456 | list_for_each_entry(child_bus, &bus->children, node) { |
da7822e5 | 1457 | int ret; |
da7822e5 | 1458 | |
f2a230bd | 1459 | ret = pci_bus_get_depth(child_bus); |
da7822e5 YL |
1460 | if (ret + 1 > depth) |
1461 | depth = ret + 1; | |
1462 | } | |
1463 | ||
1464 | return depth; | |
1465 | } | |
da7822e5 | 1466 | |
b55438fd YL |
1467 | /* |
1468 | * -1: undefined, will auto detect later | |
1469 | * 0: disabled by user | |
1470 | * 1: disabled by auto detect | |
1471 | * 2: enabled by user | |
1472 | * 3: enabled by auto detect | |
1473 | */ | |
1474 | enum enable_type { | |
1475 | undefined = -1, | |
1476 | user_disabled, | |
1477 | auto_disabled, | |
1478 | user_enabled, | |
1479 | auto_enabled, | |
1480 | }; | |
1481 | ||
ff35147c | 1482 | static enum enable_type pci_realloc_enable = undefined; |
b55438fd YL |
1483 | void __init pci_realloc_get_opt(char *str) |
1484 | { | |
1485 | if (!strncmp(str, "off", 3)) | |
1486 | pci_realloc_enable = user_disabled; | |
1487 | else if (!strncmp(str, "on", 2)) | |
1488 | pci_realloc_enable = user_enabled; | |
1489 | } | |
ff35147c | 1490 | static bool pci_realloc_enabled(enum enable_type enable) |
b55438fd | 1491 | { |
967260cd | 1492 | return enable >= user_enabled; |
b55438fd | 1493 | } |
f483d392 | 1494 | |
b07f2ebc | 1495 | #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) |
ff35147c | 1496 | static int iov_resources_unassigned(struct pci_dev *dev, void *data) |
223d96fc YL |
1497 | { |
1498 | int i; | |
1499 | bool *unassigned = data; | |
b07f2ebc | 1500 | |
223d96fc YL |
1501 | for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { |
1502 | struct resource *r = &dev->resource[i]; | |
fa216bf4 | 1503 | struct pci_bus_region region; |
b07f2ebc | 1504 | |
223d96fc | 1505 | /* Not assigned or rejected by kernel? */ |
fa216bf4 YL |
1506 | if (!r->flags) |
1507 | continue; | |
b07f2ebc | 1508 | |
fc279850 | 1509 | pcibios_resource_to_bus(dev->bus, ®ion, r); |
fa216bf4 | 1510 | if (!region.start) { |
223d96fc YL |
1511 | *unassigned = true; |
1512 | return 1; /* return early from pci_walk_bus() */ | |
b07f2ebc YL |
1513 | } |
1514 | } | |
b07f2ebc | 1515 | |
223d96fc | 1516 | return 0; |
b07f2ebc YL |
1517 | } |
1518 | ||
ff35147c | 1519 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd | 1520 | enum enable_type enable_local) |
223d96fc YL |
1521 | { |
1522 | bool unassigned = false; | |
b07f2ebc | 1523 | |
967260cd YL |
1524 | if (enable_local != undefined) |
1525 | return enable_local; | |
223d96fc | 1526 | |
967260cd YL |
1527 | pci_walk_bus(bus, iov_resources_unassigned, &unassigned); |
1528 | if (unassigned) | |
1529 | return auto_enabled; | |
1530 | ||
1531 | return enable_local; | |
b07f2ebc | 1532 | } |
223d96fc | 1533 | #else |
ff35147c | 1534 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd YL |
1535 | enum enable_type enable_local) |
1536 | { | |
1537 | return enable_local; | |
b07f2ebc | 1538 | } |
223d96fc | 1539 | #endif |
b07f2ebc | 1540 | |
da7822e5 YL |
1541 | /* |
1542 | * first try will not touch pci bridge res | |
f7625980 BH |
1543 | * second and later try will clear small leaf bridge res |
1544 | * will stop till to the max depth if can not find good one | |
da7822e5 | 1545 | */ |
39772038 | 1546 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) |
1da177e4 | 1547 | { |
bdc4abec | 1548 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1549 | want additional resources */ |
bdc4abec | 1550 | struct list_head *add_list = NULL; |
da7822e5 YL |
1551 | int tried_times = 0; |
1552 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1553 | LIST_HEAD(fail_head); |
b9b0bba9 | 1554 | struct pci_dev_resource *fail_res; |
da7822e5 | 1555 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
5b285415 | 1556 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64; |
19aa7ee4 | 1557 | int pci_try_num = 1; |
55ed83a6 | 1558 | enum enable_type enable_local; |
da7822e5 | 1559 | |
19aa7ee4 | 1560 | /* don't realloc if asked to do so */ |
55ed83a6 | 1561 | enable_local = pci_realloc_detect(bus, pci_realloc_enable); |
967260cd | 1562 | if (pci_realloc_enabled(enable_local)) { |
55ed83a6 | 1563 | int max_depth = pci_bus_get_depth(bus); |
19aa7ee4 YL |
1564 | |
1565 | pci_try_num = max_depth + 1; | |
55ed83a6 YL |
1566 | dev_printk(KERN_DEBUG, &bus->dev, |
1567 | "max bus depth: %d pci_try_num: %d\n", | |
1568 | max_depth, pci_try_num); | |
19aa7ee4 | 1569 | } |
da7822e5 YL |
1570 | |
1571 | again: | |
19aa7ee4 YL |
1572 | /* |
1573 | * last try will use add_list, otherwise will try good to have as | |
1574 | * must have, so can realloc parent bridge resource | |
1575 | */ | |
1576 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1577 | add_list = &realloc_head; |
1da177e4 LT |
1578 | /* Depth first, calculate sizes and alignments of all |
1579 | subordinate buses. */ | |
55ed83a6 | 1580 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1581 | |
1da177e4 | 1582 | /* Depth last, allocate resources and update the hardware. */ |
55ed83a6 | 1583 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1584 | if (add_list) |
bdc4abec | 1585 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1586 | tried_times++; |
1587 | ||
1588 | /* any device complain? */ | |
bdc4abec | 1589 | if (list_empty(&fail_head)) |
928bea96 | 1590 | goto dump; |
f483d392 | 1591 | |
0c5be0cb | 1592 | if (tried_times >= pci_try_num) { |
967260cd | 1593 | if (enable_local == undefined) |
55ed83a6 | 1594 | dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); |
967260cd | 1595 | else if (enable_local == auto_enabled) |
55ed83a6 | 1596 | dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); |
eb572e7c | 1597 | |
bffc56d4 | 1598 | free_list(&fail_head); |
928bea96 | 1599 | goto dump; |
da7822e5 YL |
1600 | } |
1601 | ||
55ed83a6 YL |
1602 | dev_printk(KERN_DEBUG, &bus->dev, |
1603 | "No. %d try to assign unassigned res\n", tried_times + 1); | |
da7822e5 YL |
1604 | |
1605 | /* third times and later will not check if it is leaf */ | |
1606 | if ((tried_times + 1) > 2) | |
1607 | rel_type = whole_subtree; | |
1608 | ||
1609 | /* | |
1610 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1611 | * child device under that bridge | |
1612 | */ | |
61e83cdd YL |
1613 | list_for_each_entry(fail_res, &fail_head, list) |
1614 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
b9b0bba9 | 1615 | fail_res->flags & type_mask, |
bdc4abec | 1616 | rel_type); |
61e83cdd | 1617 | |
da7822e5 | 1618 | /* restore size and flags */ |
b9b0bba9 YL |
1619 | list_for_each_entry(fail_res, &fail_head, list) { |
1620 | struct resource *res = fail_res->res; | |
da7822e5 | 1621 | |
b9b0bba9 YL |
1622 | res->start = fail_res->start; |
1623 | res->end = fail_res->end; | |
1624 | res->flags = fail_res->flags; | |
1625 | if (fail_res->dev->subordinate) | |
da7822e5 | 1626 | res->flags = 0; |
da7822e5 | 1627 | } |
bffc56d4 | 1628 | free_list(&fail_head); |
da7822e5 YL |
1629 | |
1630 | goto again; | |
1631 | ||
928bea96 | 1632 | dump: |
76fbc263 | 1633 | /* dump the resource on buses */ |
55ed83a6 YL |
1634 | pci_bus_dump_resources(bus); |
1635 | } | |
1636 | ||
1637 | void __init pci_assign_unassigned_resources(void) | |
1638 | { | |
1639 | struct pci_bus *root_bus; | |
1640 | ||
1641 | list_for_each_entry(root_bus, &pci_root_buses, node) | |
1642 | pci_assign_unassigned_root_bus_resources(root_bus); | |
1da177e4 | 1643 | } |
6841ec68 YL |
1644 | |
1645 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1646 | { | |
1647 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1648 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1649 | want additional resources */ |
32180e40 | 1650 | int tried_times = 0; |
bdc4abec | 1651 | LIST_HEAD(fail_head); |
b9b0bba9 | 1652 | struct pci_dev_resource *fail_res; |
6841ec68 | 1653 | int retval; |
32180e40 | 1654 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
d61b0e87 | 1655 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64; |
32180e40 | 1656 | |
32180e40 | 1657 | again: |
8424d759 | 1658 | __pci_bus_size_bridges(parent, &add_list); |
bdc4abec YL |
1659 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1660 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
1661 | tried_times++; |
1662 | ||
bdc4abec | 1663 | if (list_empty(&fail_head)) |
3f579c34 | 1664 | goto enable_all; |
32180e40 YL |
1665 | |
1666 | if (tried_times >= 2) { | |
1667 | /* still fail, don't need to try more */ | |
bffc56d4 | 1668 | free_list(&fail_head); |
3f579c34 | 1669 | goto enable_all; |
32180e40 YL |
1670 | } |
1671 | ||
1672 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1673 | tried_times + 1); | |
1674 | ||
1675 | /* | |
1676 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1677 | * child device under that bridge | |
1678 | */ | |
61e83cdd YL |
1679 | list_for_each_entry(fail_res, &fail_head, list) |
1680 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
1681 | fail_res->flags & type_mask, | |
32180e40 | 1682 | whole_subtree); |
61e83cdd | 1683 | |
32180e40 | 1684 | /* restore size and flags */ |
b9b0bba9 YL |
1685 | list_for_each_entry(fail_res, &fail_head, list) { |
1686 | struct resource *res = fail_res->res; | |
32180e40 | 1687 | |
b9b0bba9 YL |
1688 | res->start = fail_res->start; |
1689 | res->end = fail_res->end; | |
1690 | res->flags = fail_res->flags; | |
1691 | if (fail_res->dev->subordinate) | |
32180e40 | 1692 | res->flags = 0; |
32180e40 | 1693 | } |
bffc56d4 | 1694 | free_list(&fail_head); |
32180e40 YL |
1695 | |
1696 | goto again; | |
3f579c34 YL |
1697 | |
1698 | enable_all: | |
1699 | retval = pci_reenable_device(bridge); | |
9fc9eea0 BH |
1700 | if (retval) |
1701 | dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval); | |
3f579c34 | 1702 | pci_set_master(bridge); |
6841ec68 YL |
1703 | } |
1704 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f | 1705 | |
17787940 | 1706 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus) |
9b03088f | 1707 | { |
9b03088f | 1708 | struct pci_dev *dev; |
bdc4abec | 1709 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
1710 | want additional resources */ |
1711 | ||
9b03088f YL |
1712 | down_read(&pci_bus_sem); |
1713 | list_for_each_entry(dev, &bus->devices, bus_list) | |
6788a51f | 1714 | if (pci_is_bridge(dev) && pci_has_subordinate(dev)) |
9b03088f YL |
1715 | __pci_bus_size_bridges(dev->subordinate, |
1716 | &add_list); | |
1717 | up_read(&pci_bus_sem); | |
1718 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 1719 | BUG_ON(!list_empty(&add_list)); |
17787940 | 1720 | } |