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PCI: Use class for quirk for intel e100 interrupt fixup
[linux-2.6-block.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
363c75db 20#include <linux/export.h>
1da177e4
LT		 21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/delay.h>
25be5e6c 24#include <linux/acpi.h>
9f23ed3b 25#include <linux/kallsyms.h>
75e07fc3 26#include <linux/dmi.h>
649426ef 27#include <linux/pci-aspm.h>
32a9a682 28#include <linux/ioport.h>
3209874a
AV		 29#include <linux/sched.h>
30#include <linux/ktime.h>
93177a74 31#include <asm/dma.h> /* isa_dma_bridge_buggy */
bc56b9e0 32#include "pci.h"
1da177e4 33
32a9a682 34/*
0cdbe30f
YS		 35 * This quirk function disables memory decoding and releases memory resources
36 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
32a9a682
YS		 37 * It also rounds up size to specified alignment.
38 * Later on, the kernel will assign page-aligned memory resource back
0cdbe30f 39 * to the device.
32a9a682
YS		 40 */
41static void __devinit quirk_resource_alignment(struct pci_dev *dev)
42{
43 int i;
44 struct resource *r;
45 resource_size_t align, size;
0cdbe30f 46 u16 command;
32a9a682
YS		 47
48 if (!pci_is_reassigndev(dev))
49 return;
50
51 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
52 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
53 dev_warn(&dev->dev,
54 "Can't reassign resources to host bridge.\n");
55 return;
56 }
57
0cdbe30f
YS		 58 dev_info(&dev->dev,
59 "Disabling memory decoding and releasing memory resources.\n");
60 pci_read_config_word(dev, PCI_COMMAND, &command);
61 command &= ~PCI_COMMAND_MEMORY;
62 pci_write_config_word(dev, PCI_COMMAND, command);
32a9a682
YS		 63
64 align = pci_specified_resource_alignment(dev);
65 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
66 r = &dev->resource[i];
67 if (!(r->flags & IORESOURCE_MEM))
68 continue;
69 size = resource_size(r);
70 if (size < align) {
71 size = align;
72 dev_info(&dev->dev,
73 "Rounding up size of resource #%d to %#llx.\n",
74 i, (unsigned long long)size);
75 }
76 r->end = size - 1;
77 r->start = 0;
78 }
79 /* Need to disable bridge's resource window,
80 * to enable the kernel to reassign new resource
81 * window later on.
82 */
83 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
84 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
85 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
86 r = &dev->resource[i];
87 if (!(r->flags & IORESOURCE_MEM))
88 continue;
89 r->end = resource_size(r) - 1;
90 r->start = 0;
91 }
92 pci_disable_bridge_window(dev);
93 }
94}
95DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
96
253d2e54
JP		 97/*
98 * Decoding should be disabled for a PCI device during BAR sizing to avoid
99 * conflict. But doing so may cause problems on host bridge and perhaps other
100 * key system devices. For devices that need to have mmio decoding always-on,
101 * we need to set the dev->mmio_always_on bit.
102 */
103static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
104{
52d21b5e 105 dev->mmio_always_on = 1;
253d2e54 106}
52d21b5e
YL		 107DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
108 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
253d2e54 109
bd8481e1
DT		 110/* The Mellanox Tavor device gives false positive parity errors
111 * Mark this device with a broken_parity_status, to allow
112 * PCI scanning code to "skip" this now blacklisted device.
113 */
114static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
115{
116 dev->broken_parity_status = 1; /* This device gives false positives */
117}
118DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
119DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
120
1da177e4
LT		 121/* Deal with broken BIOS'es that neglect to enable passive release,
122 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 123static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 124{
125 struct pci_dev *d = NULL;
126 unsigned char dlc;
127
128 /* We have to make sure a particular bit is set in the PIIX3
129 ISA bridge, so we have to go out and find it. */
130 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
131 pci_read_config_byte(d, 0x82, &dlc);
132 if (!(dlc & 1<<1)) {
999da9fd 133 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 134 dlc |= 1<<1;
135 pci_write_config_byte(d, 0x82, dlc);
136 }
137 }
138}
652c538e
AM		 139DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
140DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 141
142/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
143 but VIA don't answer queries. If you happen to have good contacts at VIA
144 ask them for me please -- Alan
145
146 This appears to be BIOS not version dependent. So presumably there is a
147 chipset level fix */
1da177e4
LT		 148
149static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
150{
151 if (!isa_dma_bridge_buggy) {
152 isa_dma_bridge_buggy=1;
f0fda801 153 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 154 }
155}
156 /*
157 * Its not totally clear which chipsets are the problematic ones
158 * We know 82C586 and 82C596 variants are affected.
159 */
652c538e
AM		 160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
164DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
166DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 167
4731fdcf
LB		 168/*
169 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
170 * for some HT machines to use C4 w/o hanging.
171 */
172static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
173{
174 u32 pmbase;
175 u16 pm1a;
176
177 pci_read_config_dword(dev, 0x40, &pmbase);
178 pmbase = pmbase & 0xff80;
179 pm1a = inw(pmbase);
180
181 if (pm1a & 0x10) {
182 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
183 outw(0x10, pmbase);
184 }
185}
186DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
187
1da177e4
LT		 188/*
189 * Chipsets where PCI->PCI transfers vanish or hang
190 */
191static void __devinit quirk_nopcipci(struct pci_dev *dev)
192{
193 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 194 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 195 pci_pci_problems |= PCIPCI_FAIL;
196 }
197}
652c538e
AM		 198DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
199DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5
AC		 200
201static void __devinit quirk_nopciamd(struct pci_dev *dev)
202{
203 u8 rev;
204 pci_read_config_byte(dev, 0x08, &rev);
205 if (rev == 0x13) {
206 /* Erratum 24 */
f0fda801 207 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 208 pci_pci_problems |= PCIAGP_FAIL;
209 }
210}
652c538e 211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 212
213/*
214 * Triton requires workarounds to be used by the drivers
215 */
216static void __devinit quirk_triton(struct pci_dev *dev)
217{
218 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 219 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 220 pci_pci_problems |= PCIPCI_TRITON;
221 }
222}
652c538e
AM		 223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 227
228/*
229 * VIA Apollo KT133 needs PCI latency patch
230 * Made according to a windows driver based patch by George E. Breese
231 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
631dd1a8 232 * and http://www.georgebreese.com/net/software/#PCI
1da177e4
LT		 233 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
234 * the info on which Mr Breese based his work.
235 *
236 * Updated based on further information from the site and also on
237 * information provided by VIA
238 */
1597cacb 239static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 240{
241 struct pci_dev *p;
1da177e4
LT		 242 u8 busarb;
243 /* Ok we have a potential problem chipset here. Now see if we have
244 a buggy southbridge */
245
246 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
247 if (p!=NULL) {
1da177e4
LT		 248 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
249 /* Check for buggy part revisions */
2b1afa87 250 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 251 goto exit;
252 } else {
253 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
254 if (p==NULL) /* No problem parts */
255 goto exit;
1da177e4 256 /* Check for buggy part revisions */
2b1afa87 257 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 258 goto exit;
259 }
260
261 /*
262 * Ok we have the problem. Now set the PCI master grant to
263 * occur every master grant. The apparent bug is that under high
264 * PCI load (quite common in Linux of course) you can get data
265 * loss when the CPU is held off the bus for 3 bus master requests
266 * This happens to include the IDE controllers....
267 *
268 * VIA only apply this fix when an SB Live! is present but under
25985edc 269 * both Linux and Windows this isn't enough, and we have seen
1da177e4
LT		 270 * corruption without SB Live! but with things like 3 UDMA IDE
271 * controllers. So we ignore that bit of the VIA recommendation..
272 */
273
274 pci_read_config_byte(dev, 0x76, &busarb);
275 /* Set bit 4 and bi 5 of byte 76 to 0x01
276 "Master priority rotation on every PCI master grant */
277 busarb &= ~(1<<5);
278 busarb |= (1<<4);
279 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 280 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 281exit:
282 pci_dev_put(p);
283}
652c538e
AM		 284DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
285DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
286DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 287/* Must restore this on a resume from RAM */
652c538e
AM		 288DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
289DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
290DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 291
292/*
293 * VIA Apollo VP3 needs ETBF on BT848/878
294 */
295static void __devinit quirk_viaetbf(struct pci_dev *dev)
296{
297 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 298 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 299 pci_pci_problems |= PCIPCI_VIAETBF;
300 }
301}
652c538e 302DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4
LT		 303
304static void __devinit quirk_vsfx(struct pci_dev *dev)
305{
306 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 307 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 308 pci_pci_problems |= PCIPCI_VSFX;
309 }
310}
652c538e 311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 312
313/*
314 * Ali Magik requires workarounds to be used by the drivers
315 * that DMA to AGP space. Latency must be set to 0xA and triton
316 * workaround applied too
317 * [Info kindly provided by ALi]
318 */
319static void __init quirk_alimagik(struct pci_dev *dev)
320{
321 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 322 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 323 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
324 }
325}
652c538e
AM		 326DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
327DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 328
329/*
330 * Natoma has some interesting boundary conditions with Zoran stuff
331 * at least
332 */
333static void __devinit quirk_natoma(struct pci_dev *dev)
334{
335 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 336 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 337 pci_pci_problems |= PCIPCI_NATOMA;
338 }
339}
652c538e
AM		 340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
342DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
343DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
344DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
345DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 346
347/*
348 * This chip can cause PCI parity errors if config register 0xA0 is read
349 * while DMAs are occurring.
350 */
351static void __devinit quirk_citrine(struct pci_dev *dev)
352{
353 dev->cfg_size = 0xA0;
354}
652c538e 355DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 356
357/*
358 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
359 * If it's needed, re-allocate the region.
360 */
361static void __devinit quirk_s3_64M(struct pci_dev *dev)
362{
363 struct resource *r = &dev->resource[0];
364
365 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
366 r->start = 0;
367 r->end = 0x3ffffff;
368 }
369}
652c538e
AM		 370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
371DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 372
73d2eaac
AS		 373/*
374 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
375 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
376 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
377 * (which conflicts w/ BAR1's memory range).
378 */
379static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
380{
381 if (pci_resource_len(dev, 0) != 8) {
382 struct resource *res = &dev->resource[0];
383 res->end = res->start + 8 - 1;
384 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
385 "(incorrect header); workaround applied.\n");
386 }
387}
388DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
389
6693e74a
LT		 390static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
391 unsigned size, int nr, const char *name)
1da177e4
LT		 392{
393 region &= ~(size-1);
394 if (region) {
085ae41f 395 struct pci_bus_region bus_region;
1da177e4
LT		 396 struct resource *res = dev->resource + nr;
397
398 res->name = pci_name(dev);
399 res->start = region;
400 res->end = region + size - 1;
401 res->flags = IORESOURCE_IO;
085ae41f
DM		 402
403 /* Convert from PCI bus to resource space. */
404 bus_region.start = res->start;
405 bus_region.end = res->end;
406 pcibios_bus_to_resource(dev, res, &bus_region);
407
f967a443
BH		 408 if (pci_claim_resource(dev, nr) == 0)
409 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
410 res, name);
1da177e4
LT		 411 }
412}
413
414/*
415 * ATI Northbridge setups MCE the processor if you even
416 * read somewhere between 0x3b0->0x3bb or read 0x3d3
417 */
418static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
419{
f0fda801 420 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 421 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
422 request_region(0x3b0, 0x0C, "RadeonIGP");
423 request_region(0x3d3, 0x01, "RadeonIGP");
424}
652c538e 425DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 426
427/*
428 * Let's make the southbridge information explicit instead
429 * of having to worry about people probing the ACPI areas,
430 * for example.. (Yes, it happens, and if you read the wrong
431 * ACPI register it will put the machine to sleep with no
432 * way of waking it up again. Bummer).
433 *
434 * ALI M7101: Two IO regions pointed to by words at
435 * 0xE0 (64 bytes of ACPI registers)
436 * 0xE2 (32 bytes of SMB registers)
437 */
438static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
439{
440 u16 region;
441
442 pci_read_config_word(dev, 0xE0, &region);
6693e74a 443 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 444 pci_read_config_word(dev, 0xE2, &region);
6693e74a 445 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 446}
652c538e 447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 448
6693e74a
LT		 449static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
450{
451 u32 devres;
452 u32 mask, size, base;
453
454 pci_read_config_dword(dev, port, &devres);
455 if ((devres & enable) != enable)
456 return;
457 mask = (devres >> 16) & 15;
458 base = devres & 0xffff;
459 size = 16;
460 for (;;) {
461 unsigned bit = size >> 1;
462 if ((bit & mask) == bit)
463 break;
464 size = bit;
465 }
466 /*
467 * For now we only print it out. Eventually we'll want to
468 * reserve it (at least if it's in the 0x1000+ range), but
469 * let's get enough confirmation reports first.
470 */
471 base &= -size;
f0fda801 472 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 473}
474
475static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
476{
477 u32 devres;
478 u32 mask, size, base;
479
480 pci_read_config_dword(dev, port, &devres);
481 if ((devres & enable) != enable)
482 return;
483 base = devres & 0xffff0000;
484 mask = (devres & 0x3f) << 16;
485 size = 128 << 16;
486 for (;;) {
487 unsigned bit = size >> 1;
488 if ((bit & mask) == bit)
489 break;
490 size = bit;
491 }
492 /*
493 * For now we only print it out. Eventually we'll want to
494 * reserve it, but let's get enough confirmation reports first.
495 */
496 base &= -size;
f0fda801 497 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 498}
499
1da177e4
LT		 500/*
501 * PIIX4 ACPI: Two IO regions pointed to by longwords at
502 * 0x40 (64 bytes of ACPI registers)
08db2a70 503 * 0x90 (16 bytes of SMB registers)
6693e74a 504 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 505 */
506static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
507{
6693e74a 508 u32 region, res_a;
1da177e4
LT		 509
510 pci_read_config_dword(dev, 0x40, &region);
6693e74a 511 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 512 pci_read_config_dword(dev, 0x90, &region);
08db2a70 513 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 514
515 /* Device resource A has enables for some of the other ones */
516 pci_read_config_dword(dev, 0x5c, &res_a);
517
518 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
519 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
520
521 /* Device resource D is just bitfields for static resources */
522
523 /* Device 12 enabled? */
524 if (res_a & (1 << 29)) {
525 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
526 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
527 }
528 /* Device 13 enabled? */
529 if (res_a & (1 << 30)) {
530 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
531 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
532 }
533 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
534 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 535}
652c538e
AM		 536DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
537DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4 538
cdb97558
JS		 539#define ICH_PMBASE 0x40
540#define ICH_ACPI_CNTL 0x44
541#define ICH4_ACPI_EN 0x10
542#define ICH6_ACPI_EN 0x80
543#define ICH4_GPIOBASE 0x58
544#define ICH4_GPIO_CNTL 0x5c
545#define ICH4_GPIO_EN 0x10
546#define ICH6_GPIOBASE 0x48
547#define ICH6_GPIO_CNTL 0x4c
548#define ICH6_GPIO_EN 0x10
549
1da177e4
LT		 550/*
551 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
552 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
553 * 0x58 (64 bytes of GPIO I/O space)
554 */
555static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
556{
557 u32 region;
cdb97558 558 u8 enable;
1da177e4 559
87e3dc38
JS		 560 /*
561 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
562 * with low legacy (and fixed) ports. We don't know the decoding
563 * priority and can't tell whether the legacy device or the one created
564 * here is really at that address. This happens on boards with broken
565 * BIOSes.
566 */
567
cdb97558
JS		 568 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
569 if (enable & ICH4_ACPI_EN) {
570 pci_read_config_dword(dev, ICH_PMBASE, &region);
87e3dc38
JS		 571 region &= PCI_BASE_ADDRESS_IO_MASK;
572 if (region >= PCIBIOS_MIN_IO)
573 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
574 "ICH4 ACPI/GPIO/TCO");
cdb97558 575 }
1da177e4 576
cdb97558
JS		 577 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
578 if (enable & ICH4_GPIO_EN) {
579 pci_read_config_dword(dev, ICH4_GPIOBASE, &region);
87e3dc38
JS		 580 region &= PCI_BASE_ADDRESS_IO_MASK;
581 if (region >= PCIBIOS_MIN_IO)
582 quirk_io_region(dev, region, 64,
583 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
cdb97558 584 }
1da177e4 585}
652c538e
AM		 586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
587DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
588DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
590DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
593DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
594DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 596
894886e5 597static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
2cea752f
M		 598{
599 u32 region;
cdb97558 600 u8 enable;
2cea752f 601
cdb97558
JS		 602 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
603 if (enable & ICH6_ACPI_EN) {
604 pci_read_config_dword(dev, ICH_PMBASE, &region);
87e3dc38
JS		 605 region &= PCI_BASE_ADDRESS_IO_MASK;
606 if (region >= PCIBIOS_MIN_IO)
607 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
608 "ICH6 ACPI/GPIO/TCO");
cdb97558 609 }
2cea752f 610
cdb97558 611 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
b6d95bb6 612 if (enable & ICH6_GPIO_EN) {
cdb97558 613 pci_read_config_dword(dev, ICH6_GPIOBASE, &region);
87e3dc38
JS		 614 region &= PCI_BASE_ADDRESS_IO_MASK;
615 if (region >= PCIBIOS_MIN_IO)
616 quirk_io_region(dev, region, 64,
617 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
cdb97558 618 }
2cea752f 619}
894886e5
LT		 620
621static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
622{
623 u32 val;
624 u32 size, base;
625
626 pci_read_config_dword(dev, reg, &val);
627
628 /* Enabled? */
629 if (!(val & 1))
630 return;
631 base = val & 0xfffc;
632 if (dynsize) {
633 /*
634 * This is not correct. It is 16, 32 or 64 bytes depending on
635 * register D31:F0:ADh bits 5:4.
636 *
637 * But this gets us at least _part_ of it.
638 */
639 size = 16;
640 } else {
641 size = 128;
642 }
643 base &= ~(size-1);
644
645 /* Just print it out for now. We should reserve it after more debugging */
646 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
647}
648
649static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
650{
651 /* Shared ACPI/GPIO decode with all ICH6+ */
652 ich6_lpc_acpi_gpio(dev);
653
654 /* ICH6-specific generic IO decode */
655 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
656 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
657}
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
659DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
660
661static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
662{
663 u32 val;
664 u32 mask, base;
665
666 pci_read_config_dword(dev, reg, &val);
667
668 /* Enabled? */
669 if (!(val & 1))
670 return;
671
672 /*
673 * IO base in bits 15:2, mask in bits 23:18, both
674 * are dword-based
675 */
676 base = val & 0xfffc;
677 mask = (val >> 16) & 0xfc;
678 mask |= 3;
679
680 /* Just print it out for now. We should reserve it after more debugging */
681 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
682}
683
684/* ICH7-10 has the same common LPC generic IO decode registers */
685static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
686{
5d9c0a79 687 /* We share the common ACPI/GPIO decode with ICH6 */
894886e5
LT		 688 ich6_lpc_acpi_gpio(dev);
689
690 /* And have 4 ICH7+ generic decodes */
691 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
692 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
693 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
694 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
695}
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
708DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
2cea752f 709
1da177e4
LT		 710/*
711 * VIA ACPI: One IO region pointed to by longword at
712 * 0x48 or 0x20 (256 bytes of ACPI registers)
713 */
714static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
715{
1da177e4
LT		 716 u32 region;
717
651472fb 718 if (dev->revision & 0x10) {
1da177e4
LT		 719 pci_read_config_dword(dev, 0x48, &region);
720 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 721 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 722 }
723}
652c538e 724DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 725
726/*
727 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
728 * 0x48 (256 bytes of ACPI registers)
729 * 0x70 (128 bytes of hardware monitoring register)
730 * 0x90 (16 bytes of SMB registers)
731 */
732static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
733{
734 u16 hm;
735 u32 smb;
736
737 quirk_vt82c586_acpi(dev);
738
739 pci_read_config_word(dev, 0x70, &hm);
740 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 741 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 742
743 pci_read_config_dword(dev, 0x90, &smb);
744 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 745 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4 746}
652c538e 747DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 748
6d85f29b
IK		 749/*
750 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
751 * 0x88 (128 bytes of power management registers)
752 * 0xd0 (16 bytes of SMB registers)
753 */
754static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
755{
756 u16 pm, smb;
757
758 pci_read_config_word(dev, 0x88, &pm);
759 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 760 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 761
762 pci_read_config_word(dev, 0xd0, &smb);
763 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 764 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 765}
766DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
767
1f56f4a2
GB		 768/*
769 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
770 * Disable fast back-to-back on the secondary bus segment
771 */
772static void __devinit quirk_xio2000a(struct pci_dev *dev)
773{
774 struct pci_dev *pdev;
775 u16 command;
776
777 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
778 "secondary bus fast back-to-back transfers disabled\n");
779 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
780 pci_read_config_word(pdev, PCI_COMMAND, &command);
781 if (command & PCI_COMMAND_FAST_BACK)
782 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
783 }
784}
785DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
786 quirk_xio2000a);
1da177e4
LT		 787
788#ifdef CONFIG_X86_IO_APIC
789
790#include <asm/io_apic.h>
791
792/*
793 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
794 * devices to the external APIC.
795 *
796 * TODO: When we have device-specific interrupt routers,
797 * this code will go away from quirks.
798 */
1597cacb 799static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 800{
801 u8 tmp;
802
803 if (nr_ioapics < 1)
804 tmp = 0; /* nothing routed to external APIC */
805 else
806 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
807
f0fda801 808 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 809 tmp == 0 ? "Disa" : "Ena");
810
811 /* Offset 0x58: External APIC IRQ output control */
812 pci_write_config_byte (dev, 0x58, tmp);
813}
652c538e 814DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 815DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 816
a1740913
KW		 817/*
818 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
819 * This leads to doubled level interrupt rates.
820 * Set this bit to get rid of cycle wastage.
821 * Otherwise uncritical.
822 */
1597cacb 823static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 824{
825 u8 misc_control2;
826#define BYPASS_APIC_DEASSERT 8
827
828 pci_read_config_byte(dev, 0x5B, &misc_control2);
829 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 830 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 831 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
832 }
833}
834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 835DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 836
1da177e4
LT		 837/*
838 * The AMD io apic can hang the box when an apic irq is masked.
839 * We check all revs >= B0 (yet not in the pre production!) as the bug
840 * is currently marked NoFix
841 *
842 * We have multiple reports of hangs with this chipset that went away with
236561e5 843 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 844 * of course. However the advice is demonstrably good even if so..
845 */
846static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
847{
44c10138 848 if (dev->revision >= 0x02) {
f0fda801 849 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
850 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 851 }
852}
652c538e 853DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4
LT		 854
855static void __init quirk_ioapic_rmw(struct pci_dev *dev)
856{
857 if (dev->devfn == 0 && dev->bus->number == 0)
858 sis_apic_bug = 1;
859}
652c538e 860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4
LT		 861#endif /* CONFIG_X86_IO_APIC */
862
d556ad4b
PO		 863/*
864 * Some settings of MMRBC can lead to data corruption so block changes.
865 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
866 */
867static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
868{
aa288d4d 869 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 870 dev_info(&dev->dev, "AMD8131 rev %x detected; "
871 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 872 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
873 }
874}
875DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 876
1da177e4
LT		 877/*
878 * FIXME: it is questionable that quirk_via_acpi
879 * is needed. It shows up as an ISA bridge, and does not
880 * support the PCI_INTERRUPT_LINE register at all. Therefore
881 * it seems like setting the pci_dev's 'irq' to the
882 * value of the ACPI SCI interrupt is only done for convenience.
883 * -jgarzik
884 */
885static void __devinit quirk_via_acpi(struct pci_dev *d)
886{
887 /*
888 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
889 */
890 u8 irq;
891 pci_read_config_byte(d, 0x42, &irq);
892 irq &= 0xf;
893 if (irq && (irq != 2))
894 d->irq = irq;
895}
652c538e
AM		 896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 898
09d6029f
DD		 899
900/*
1597cacb 901 * VIA bridges which have VLink
09d6029f 902 */
1597cacb 903
c06bb5d4
JD		 904static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
905
906static void quirk_via_bridge(struct pci_dev *dev)
907{
908 /* See what bridge we have and find the device ranges */
909 switch (dev->device) {
910 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 911 /* The VT82C686 is special, it attaches to PCI and can have
912 any device number. All its subdevices are functions of
913 that single device. */
914 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
915 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 916 break;
917 case PCI_DEVICE_ID_VIA_8237:
918 case PCI_DEVICE_ID_VIA_8237A:
919 via_vlink_dev_lo = 15;
920 break;
921 case PCI_DEVICE_ID_VIA_8235:
922 via_vlink_dev_lo = 16;
923 break;
924 case PCI_DEVICE_ID_VIA_8231:
925 case PCI_DEVICE_ID_VIA_8233_0:
926 case PCI_DEVICE_ID_VIA_8233A:
927 case PCI_DEVICE_ID_VIA_8233C_0:
928 via_vlink_dev_lo = 17;
929 break;
930 }
931}
932DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
936DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
937DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
938DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
939DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 940
1597cacb
AC		 941/**
942 * quirk_via_vlink - VIA VLink IRQ number update
943 * @dev: PCI device
944 *
945 * If the device we are dealing with is on a PIC IRQ we need to
946 * ensure that the IRQ line register which usually is not relevant
947 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 948 * to the right place.
949 * We only do this on systems where a VIA south bridge was detected,
950 * and only for VIA devices on the motherboard (see quirk_via_bridge
951 * above).
1597cacb
AC		 952 */
953
954static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 955{
956 u8 irq, new_irq;
957
c06bb5d4
JD		 958 /* Check if we have VLink at all */
959 if (via_vlink_dev_lo == -1)
09d6029f
DD		 960 return;
961
962 new_irq = dev->irq;
963
964 /* Don't quirk interrupts outside the legacy IRQ range */
965 if (!new_irq || new_irq > 15)
966 return;
967
1597cacb 968 /* Internal device ? */
c06bb5d4
JD		 969 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
970 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 971 return;
972
973 /* This is an internal VLink device on a PIC interrupt. The BIOS
974 ought to have set this but may not have, so we redo it */
975
25be5e6c
LB		 976 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
977 if (new_irq != irq) {
f0fda801 978 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
979 irq, new_irq);
25be5e6c
LB		 980 udelay(15); /* unknown if delay really needed */
981 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
982 }
983}
1597cacb 984DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 985
1da177e4
LT		 986/*
987 * VIA VT82C598 has its device ID settable and many BIOSes
988 * set it to the ID of VT82C597 for backward compatibility.
989 * We need to switch it off to be able to recognize the real
990 * type of the chip.
991 */
992static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
993{
994 pci_write_config_byte(dev, 0xfc, 0);
995 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
996}
652c538e 997DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 998
999/*
1000 * CardBus controllers have a legacy base address that enables them
1001 * to respond as i82365 pcmcia controllers. We don't want them to
1002 * do this even if the Linux CardBus driver is not loaded, because
1003 * the Linux i82365 driver does not (and should not) handle CardBus.
1004 */
1597cacb 1005static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4 1006{
1da177e4
LT		 1007 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1008}
ae9de56b
YL		 1009DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1010 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1011DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1012 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1da177e4
LT		 1013
1014/*
1015 * Following the PCI ordering rules is optional on the AMD762. I'm not
1016 * sure what the designers were smoking but let's not inhale...
1017 *
1018 * To be fair to AMD, it follows the spec by default, its BIOS people
1019 * who turn it off!
1020 */
1597cacb 1021static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 1022{
1023 u32 pcic;
1024 pci_read_config_dword(dev, 0x4C, &pcic);
1025 if ((pcic&6)!=6) {
1026 pcic |= 6;
f0fda801 1027 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 1028 pci_write_config_dword(dev, 0x4C, pcic);
1029 pci_read_config_dword(dev, 0x84, &pcic);
1030 pcic |= (1<<23); /* Required in this mode */
1031 pci_write_config_dword(dev, 0x84, pcic);
1032 }
1033}
652c538e 1034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 1035DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 1036
1037/*
1038 * DreamWorks provided workaround for Dunord I-3000 problem
1039 *
1040 * This card decodes and responds to addresses not apparently
1041 * assigned to it. We force a larger allocation to ensure that
1042 * nothing gets put too close to it.
1043 */
1044static void __devinit quirk_dunord ( struct pci_dev * dev )
1045{
1046 struct resource *r = &dev->resource [1];
1047 r->start = 0;
1048 r->end = 0xffffff;
1049}
652c538e 1050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 1051
1052/*
1053 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1054 * is subtractive decoding (transparent), and does indicate this
1055 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1056 * instead of 0x01.
1057 */
1058static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
1059{
1060 dev->transparent = 1;
1061}
652c538e
AM		 1062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 1064
1065/*
1066 * Common misconfiguration of the MediaGX/Geode PCI master that will
1067 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
631dd1a8 1068 * datasheets found at http://www.national.com/analog for info on what
1da177e4
LT		 1069 * these bits do. <christer@weinigel.se>
1070 */
1597cacb 1071static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 1072{
1073 u8 reg;
1074 pci_read_config_byte(dev, 0x41, &reg);
1075 if (reg & 2) {
1076 reg &= ~2;
f0fda801 1077 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 1078 pci_write_config_byte(dev, 0x41, reg);
1079 }
1080}
652c538e
AM		 1081DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1082DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 1083
1da177e4
LT		 1084/*
1085 * Ensure C0 rev restreaming is off. This is normally done by
1086 * the BIOS but in the odd case it is not the results are corruption
1087 * hence the presence of a Linux check
1088 */
1597cacb 1089static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 1090{
1091 u16 config;
1da177e4 1092
44c10138 1093 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 1094 return;
1095 pci_read_config_word(pdev, 0x40, &config);
1096 if (config & (1<<6)) {
1097 config &= ~(1<<6);
1098 pci_write_config_word(pdev, 0x40, config);
f0fda801 1099 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 1100 }
1101}
652c538e 1102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 1103DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 1104
05a7d22b 1105static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 1106{
5deab536 1107 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
05a7d22b 1108 u8 tmp;
ab17443a 1109
05a7d22b
CC		 1110 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1111 if (tmp == 0x01) {
ab17443a
CH		 1112 pci_read_config_byte(pdev, 0x40, &tmp);
1113 pci_write_config_byte(pdev, 0x40, tmp|1);
1114 pci_write_config_byte(pdev, 0x9, 1);
1115 pci_write_config_byte(pdev, 0xa, 6);
1116 pci_write_config_byte(pdev, 0x40, tmp);
1117
c9f89475 1118 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 1119 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 1120 }
1121}
05a7d22b 1122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 1123DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 1124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 1125DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
5deab536
SH		 1126DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1127DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
ab17443a 1128
1da177e4
LT		 1129/*
1130 * Serverworks CSB5 IDE does not fully support native mode
1131 */
1132static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1133{
1134 u8 prog;
1135 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1136 if (prog & 5) {
1137 prog &= ~5;
1138 pdev->class &= ~5;
1139 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 1140 /* PCI layer will sort out resources */
1da177e4
LT		 1141 }
1142}
652c538e 1143DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 1144
1145/*
1146 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1147 */
1148static void __init quirk_ide_samemode(struct pci_dev *pdev)
1149{
1150 u8 prog;
1151
1152 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1153
1154 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 1155 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 1156 prog &= ~5;
1157 pdev->class &= ~5;
1158 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 1159 }
1160}
368c73d4 1161DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 1162
979b1791
AC		 1163/*
1164 * Some ATA devices break if put into D3
1165 */
1166
1167static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1168{
faa738bb 1169 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
979b1791 1170}
faa738bb
YL		 1171/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1172DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1173 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1174DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1175 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
7a661c6f 1176/* ALi loses some register settings that we cannot then restore */
faa738bb
YL		 1177DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1178 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
7a661c6f
AC		 1179/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1180 occur when mode detecting */
faa738bb
YL		 1181DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1182 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
979b1791 1183
1da177e4
LT		 1184/* This was originally an Alpha specific thing, but it really fits here.
1185 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1186 */
1187static void __init quirk_eisa_bridge(struct pci_dev *dev)
1188{
1189 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1190}
652c538e 1191DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 1192
7daa0c4f 1193
1da177e4
LT		 1194/*
1195 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1196 * is not activated. The myth is that Asus said that they do not want the
1197 * users to be irritated by just another PCI Device in the Win98 device
1198 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1199 * package 2.7.0 for details)
1200 *
1201 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1202 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 1203 * becomes necessary to do this tweak in two steps -- the chosen trigger
1204 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 1205 *
1206 * Note that we used to unhide the SMBus that way on Toshiba laptops
1207 * (Satellite A40 and Tecra M2) but then found that the thermal management
1208 * was done by SMM code, which could cause unsynchronized concurrent
1209 * accesses to the SMBus registers, with potentially bad effects. Thus you
1210 * should be very careful when adding new entries: if SMM is accessing the
1211 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 1212 *
1213 * Likewise, many recent laptops use ACPI for thermal management. If the
1214 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1215 * natively, and keeping the SMBus hidden is the right thing to do. If you
1216 * are about to add an entry in the table below, please first disassemble
1217 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 1218 */
9d24a81e 1219static int asus_hides_smbus;
1da177e4
LT		 1220
1221static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1222{
1223 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1224 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1225 switch(dev->subsystem_device) {
a00db371 1226 case 0x8025: /* P4B-LX */
1da177e4
LT		 1227 case 0x8070: /* P4B */
1228 case 0x8088: /* P4B533 */
1229 case 0x1626: /* L3C notebook */
1230 asus_hides_smbus = 1;
1231 }
2f2d39d2 1232 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 1233 switch(dev->subsystem_device) {
1234 case 0x80b1: /* P4GE-V */
1235 case 0x80b2: /* P4PE */
1236 case 0x8093: /* P4B533-V */
1237 asus_hides_smbus = 1;
1238 }
2f2d39d2 1239 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 1240 switch(dev->subsystem_device) {
1241 case 0x8030: /* P4T533 */
1242 asus_hides_smbus = 1;
1243 }
2f2d39d2 1244 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1245 switch (dev->subsystem_device) {
1246 case 0x8070: /* P4G8X Deluxe */
1247 asus_hides_smbus = 1;
1248 }
2f2d39d2 1249 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1250 switch (dev->subsystem_device) {
1251 case 0x80c9: /* PU-DLS */
1252 asus_hides_smbus = 1;
1253 }
2f2d39d2 1254 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1255 switch (dev->subsystem_device) {
1256 case 0x1751: /* M2N notebook */
1257 case 0x1821: /* M5N notebook */
4096ed0f 1258 case 0x1897: /* A6L notebook */
1da177e4
LT		 1259 asus_hides_smbus = 1;
1260 }
2f2d39d2 1261 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1262 switch (dev->subsystem_device) {
1263 case 0x184b: /* W1N notebook */
1264 case 0x186a: /* M6Ne notebook */
1265 asus_hides_smbus = 1;
1266 }
2f2d39d2 1267 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1268 switch (dev->subsystem_device) {
1269 case 0x80f2: /* P4P800-X */
1270 asus_hides_smbus = 1;
1271 }
2f2d39d2 1272 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
M		 1273 switch (dev->subsystem_device) {
1274 case 0x1882: /* M6V notebook */
2d1e1c75 1275 case 0x1977: /* A6VA notebook */
acc06632
M		 1276 asus_hides_smbus = 1;
1277 }
1da177e4
LT		 1278 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1279 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1280 switch(dev->subsystem_device) {
1281 case 0x088C: /* HP Compaq nc8000 */
1282 case 0x0890: /* HP Compaq nc6000 */
1283 asus_hides_smbus = 1;
1284 }
2f2d39d2 1285 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1286 switch (dev->subsystem_device) {
1287 case 0x12bc: /* HP D330L */
e3b1bd57 1288 case 0x12bd: /* HP D530 */
74c57428 1289 case 0x006a: /* HP Compaq nx9500 */
1da177e4
LT		 1290 asus_hides_smbus = 1;
1291 }
677cc644
JD		 1292 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1293 switch (dev->subsystem_device) {
1294 case 0x12bf: /* HP xw4100 */
1295 asus_hides_smbus = 1;
1296 }
1da177e4
LT		 1297 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1298 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1299 switch(dev->subsystem_device) {
1300 case 0xC00C: /* Samsung P35 notebook */
1301 asus_hides_smbus = 1;
1302 }
c87f883e
RIZ		 1303 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1304 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1305 switch(dev->subsystem_device) {
1306 case 0x0058: /* Compaq Evo N620c */
1307 asus_hides_smbus = 1;
1308 }
d7698edc 1309 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1310 switch(dev->subsystem_device) {
1311 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1312 /* Motherboard doesn't have Host bridge
1313 * subvendor/subdevice IDs, therefore checking
1314 * its on-board VGA controller */
1315 asus_hides_smbus = 1;
1316 }
8293b0f6 1317 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
10260d9a
JD		 1318 switch(dev->subsystem_device) {
1319 case 0x00b8: /* Compaq Evo D510 CMT */
1320 case 0x00b9: /* Compaq Evo D510 SFF */
6b5096e4 1321 case 0x00ba: /* Compaq Evo D510 USDT */
8293b0f6
DS		 1322 /* Motherboard doesn't have Host bridge
1323 * subvendor/subdevice IDs and on-board VGA
1324 * controller is disabled if an AGP card is
1325 * inserted, therefore checking USB UHCI
1326 * Controller #1 */
10260d9a
JD		 1327 asus_hides_smbus = 1;
1328 }
27e46859
KH		 1329 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1330 switch (dev->subsystem_device) {
1331 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1332 /* Motherboard doesn't have host bridge
1333 * subvendor/subdevice IDs, therefore checking
1334 * its on-board VGA controller */
1335 asus_hides_smbus = 1;
1336 }
1da177e4
LT		 1337 }
1338}
652c538e
AM		 1339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1341DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1349
1350DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
8293b0f6 1351DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
27e46859 1352DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1353
1597cacb 1354static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1355{
1356 u16 val;
1357
1358 if (likely(!asus_hides_smbus))
1359 return;
1360
1361 pci_read_config_word(dev, 0xF2, &val);
1362 if (val & 0x8) {
1363 pci_write_config_word(dev, 0xF2, val & (~0x8));
1364 pci_read_config_word(dev, 0xF2, &val);
1365 if (val & 0x8)
f0fda801 1366 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1367 else
f0fda801 1368 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1369 }
1370}
652c538e
AM		 1371DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1372DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1373DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1374DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1375DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1376DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1377DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1378DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1379DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1380DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1381DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1382DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1383DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1384DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1385
e1a2a51e
RW		 1386/* It appears we just have one such device. If not, we have a warning */
1387static void __iomem *asus_rcba_base;
1388static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1389{
e1a2a51e 1390 u32 rcba;
acc06632
M		 1391
1392 if (likely(!asus_hides_smbus))
1393 return;
e1a2a51e
RW		 1394 WARN_ON(asus_rcba_base);
1395
acc06632 1396 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1397 /* use bits 31:14, 16 kB aligned */
1398 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1399 if (asus_rcba_base == NULL)
1400 return;
1401}
1402
1403static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1404{
1405 u32 val;
1406
1407 if (likely(!asus_hides_smbus || !asus_rcba_base))
1408 return;
1409 /* read the Function Disable register, dword mode only */
1410 val = readl(asus_rcba_base + 0x3418);
1411 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1412}
1413
1414static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1415{
1416 if (likely(!asus_hides_smbus || !asus_rcba_base))
1417 return;
1418 iounmap(asus_rcba_base);
1419 asus_rcba_base = NULL;
f0fda801 1420 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1421}
e1a2a51e
RW		 1422
1423static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1424{
1425 asus_hides_smbus_lpc_ich6_suspend(dev);
1426 asus_hides_smbus_lpc_ich6_resume_early(dev);
1427 asus_hides_smbus_lpc_ich6_resume(dev);
1428}
652c538e 1429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1430DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1431DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1432DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1433
1da177e4
LT		 1434/*
1435 * SiS 96x south bridge: BIOS typically hides SMBus device...
1436 */
1597cacb 1437static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1438{
1439 u8 val = 0;
1da177e4 1440 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1441 if (val & 0x10) {
f0fda801 1442 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1443 pci_write_config_byte(dev, 0x77, val & ~0x10);
1444 }
1da177e4 1445}
652c538e
AM		 1446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1450DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1451DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1452DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1453DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1454
1da177e4
LT		 1455/*
1456 * ... This is further complicated by the fact that some SiS96x south
1457 * bridges pretend to be 85C503/5513 instead. In that case see if we
1458 * spotted a compatible north bridge to make sure.
1459 * (pci_find_device doesn't work yet)
1460 *
1461 * We can also enable the sis96x bit in the discovery register..
1462 */
1da177e4
LT		 1463#define SIS_DETECT_REGISTER 0x40
1464
1597cacb 1465static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1466{
1467 u8 reg;
1468 u16 devid;
1469
1470 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1471 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1472 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1473 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1474 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1475 return;
1476 }
1477
1da177e4 1478 /*
2f5c33b3
MH		 1479 * Ok, it now shows up as a 96x.. run the 96x quirk by
1480 * hand in case it has already been processed.
1481 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1482 */
1483 dev->device = devid;
2f5c33b3 1484 quirk_sis_96x_smbus(dev);
1da177e4 1485}
652c538e 1486DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1487DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1488
1da177e4 1489
e5548e96
BJD		 1490/*
1491 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1492 * and MC97 modem controller are disabled when a second PCI soundcard is
1493 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1494 * -- bjd
1495 */
1597cacb 1496static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1497{
1498 u8 val;
1499 int asus_hides_ac97 = 0;
1500
1501 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1502 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1503 asus_hides_ac97 = 1;
1504 }
1505
1506 if (!asus_hides_ac97)
1507 return;
1508
1509 pci_read_config_byte(dev, 0x50, &val);
1510 if (val & 0xc0) {
1511 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1512 pci_read_config_byte(dev, 0x50, &val);
1513 if (val & 0xc0)
f0fda801 1514 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1515 else
f0fda801 1516 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1517 }
1518}
652c538e 1519DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1520DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1521
77967052 1522#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1523
1524/*
1525 * If we are using libata we can drive this chip properly but must
1526 * do this early on to make the additional device appear during
1527 * the PCI scanning.
1528 */
5ee2ae7f 1529static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1530{
e34bb370 1531 u32 conf1, conf5, class;
15e0c694
AC		 1532 u8 hdr;
1533
1534 /* Only poke fn 0 */
1535 if (PCI_FUNC(pdev->devfn))
1536 return;
1537
5ee2ae7f
TH		 1538 pci_read_config_dword(pdev, 0x40, &conf1);
1539 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1540
5ee2ae7f
TH		 1541 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1542 conf5 &= ~(1 << 24); /* Clear bit 24 */
1543
1544 switch (pdev->device) {
4daedcfe
TH		 1545 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1546 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
5b6ae5ba 1547 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
5ee2ae7f
TH		 1548 /* The controller should be in single function ahci mode */
1549 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1550 break;
1551
1552 case PCI_DEVICE_ID_JMICRON_JMB365:
1553 case PCI_DEVICE_ID_JMICRON_JMB366:
1554 /* Redirect IDE second PATA port to the right spot */
1555 conf5 |= (1 << 24);
1556 /* Fall through */
1557 case PCI_DEVICE_ID_JMICRON_JMB361:
1558 case PCI_DEVICE_ID_JMICRON_JMB363:
5b6ae5ba 1559 case PCI_DEVICE_ID_JMICRON_JMB369:
5ee2ae7f
TH		 1560 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1561 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1562 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1563 break;
1564
1565 case PCI_DEVICE_ID_JMICRON_JMB368:
1566 /* The controller should be in single function IDE mode */
1567 conf1 |= 0x00C00000; /* Set 22, 23 */
1568 break;
15e0c694 1569 }
5ee2ae7f
TH		 1570
1571 pci_write_config_dword(pdev, 0x40, conf1);
1572 pci_write_config_dword(pdev, 0x80, conf5);
1573
1574 /* Update pdev accordingly */
1575 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1576 pdev->hdr_type = hdr & 0x7f;
1577 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1578
1579 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1580 pdev->class = class >> 8;
15e0c694 1581}
5ee2ae7f
TH		 1582DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1583DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
5ee2ae7f 1585DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1586DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
5ee2ae7f
TH		 1587DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1588DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1589DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1590DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
e1a2a51e
RW		 1591DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1592DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
4daedcfe 1593DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
e1a2a51e 1594DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
5b6ae5ba 1595DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
e1a2a51e
RW		 1596DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1597DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1598DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
5b6ae5ba 1599DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
15e0c694
AC		 1600
1601#endif
1602
1da177e4
LT		 1603#ifdef CONFIG_X86_IO_APIC
1604static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1605{
1606 int i;
1607
1608 if ((pdev->class >> 8) != 0xff00)
1609 return;
1610
1611 /* the first BAR is the location of the IO APIC...we must
1612 * not touch this (and it's already covered by the fixmap), so
1613 * forcibly insert it into the resource tree */
1614 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1615 insert_resource(&iomem_resource, &pdev->resource[0]);
1616
1617 /* The next five BARs all seem to be rubbish, so just clean
1618 * them out */
1619 for (i=1; i < 6; i++) {
1620 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1621 }
1622
1623}
652c538e 1624DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1625#endif
1626
1da177e4
LT		 1627static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1628{
0ba379ec
EB		 1629 pci_msi_off(pdev);
1630 pdev->no_msi = 1;
1da177e4 1631}
652c538e
AM		 1632DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1633DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1635
4602b88d
KA		 1636
1637/*
1638 * It's possible for the MSI to get corrupted if shpc and acpi
1639 * are used together on certain PXH-based systems.
1640 */
1641static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1642{
f5f2b131 1643 pci_msi_off(dev);
4602b88d 1644 dev->no_msi = 1;
f0fda801 1645 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1646}
1647DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1648DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1649DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1650DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1651DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1652
ffadcc2f
KCA		 1653/*
1654 * Some Intel PCI Express chipsets have trouble with downstream
1655 * device power management.
1656 */
1657static void quirk_intel_pcie_pm(struct pci_dev * dev)
1658{
1659 pci_pm_d3_delay = 120;
1660 dev->no_d1d2 = 1;
1661}
1662
1663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1677DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1678DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1679DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1680DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1684
426b3b8d 1685#ifdef CONFIG_X86_IO_APIC
e1d3a908
SA		 1686/*
1687 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1688 * remap the original interrupt in the linux kernel to the boot interrupt, so
1689 * that a PCI device's interrupt handler is installed on the boot interrupt
1690 * line instead.
1691 */
1692static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1693{
41b9eb26 1694 if (noioapicquirk || noioapicreroute)
e1d3a908
SA		 1695 return;
1696
1697 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
fdcdaf6c
BH		 1698 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1699 dev->vendor, dev->device);
e1d3a908 1700}
88d1dce3
OD		 1701DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1703DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1704DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1706DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1709DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1710DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1711DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1712DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1713DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1714DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1715DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1716DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
e1d3a908 1717
426b3b8d
SA		 1718/*
1719 * On some chipsets we can disable the generation of legacy INTx boot
1720 * interrupts.
1721 */
1722
1723/*
1724 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1725 * 300641-004US, section 5.7.3.
1726 */
1727#define INTEL_6300_IOAPIC_ABAR 0x40
1728#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1729
1730static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1731{
1732 u16 pci_config_word;
1733
1734 if (noioapicquirk)
1735 return;
1736
1737 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1738 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1739 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1740
fdcdaf6c
BH		 1741 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1742 dev->vendor, dev->device);
426b3b8d 1743}
88d1dce3
OD		 1744DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1745DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
77251188
OD		 1746
1747/*
1748 * disable boot interrupts on HT-1000
1749 */
1750#define BC_HT1000_FEATURE_REG 0x64
1751#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1752#define BC_HT1000_MAP_IDX 0xC00
1753#define BC_HT1000_MAP_DATA 0xC01
1754
1755static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1756{
1757 u32 pci_config_dword;
1758 u8 irq;
1759
1760 if (noioapicquirk)
1761 return;
1762
1763 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1764 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1765 BC_HT1000_PIC_REGS_ENABLE);
1766
1767 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1768 outb(irq, BC_HT1000_MAP_IDX);
1769 outb(0x00, BC_HT1000_MAP_DATA);
1770 }
1771
1772 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1773
fdcdaf6c
BH		 1774 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1775 dev->vendor, dev->device);
77251188 1776}
88d1dce3
OD		 1777DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1778DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
542622da
OD		 1779
1780/*
1781 * disable boot interrupts on AMD and ATI chipsets
1782 */
1783/*
1784 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1785 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1786 * (due to an erratum).
1787 */
1788#define AMD_813X_MISC 0x40
1789#define AMD_813X_NOIOAMODE (1<<0)
4fd8bdc5 1790#define AMD_813X_REV_B1 0x12
bbe19443 1791#define AMD_813X_REV_B2 0x13
542622da
OD		 1792
1793static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1794{
1795 u32 pci_config_dword;
1796
1797 if (noioapicquirk)
1798 return;
4fd8bdc5
SA		 1799 if ((dev->revision == AMD_813X_REV_B1) ||
1800 (dev->revision == AMD_813X_REV_B2))
bbe19443 1801 return;
542622da
OD		 1802
1803 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1804 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1805 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1806
fdcdaf6c
BH		 1807 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1808 dev->vendor, dev->device);
542622da 1809}
4fd8bdc5
SA		 1810DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1811DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1813DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
542622da
OD		 1814
1815#define AMD_8111_PCI_IRQ_ROUTING 0x56
1816
1817static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1818{
1819 u16 pci_config_word;
1820
1821 if (noioapicquirk)
1822 return;
1823
1824 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1825 if (!pci_config_word) {
fdcdaf6c
BH		 1826 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1827 "already disabled\n", dev->vendor, dev->device);
542622da
OD		 1828 return;
1829 }
1830 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
fdcdaf6c
BH		 1831 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1832 dev->vendor, dev->device);
542622da 1833}
88d1dce3
OD		 1834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1835DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
426b3b8d
SA		 1836#endif /* CONFIG_X86_IO_APIC */
1837
33dced2e
SS		 1838/*
1839 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1840 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1841 * Re-allocate the region if needed...
1842 */
1843static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1844{
1845 struct resource *r = &dev->resource[0];
1846
1847 if (r->start & 0x8) {
1848 r->start = 0;
1849 r->end = 0xf;
1850 }
1851}
1852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1853 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1854 quirk_tc86c001_ide);
1855
1da177e4
LT		 1856static void __devinit quirk_netmos(struct pci_dev *dev)
1857{
1858 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1859 unsigned int num_serial = dev->subsystem_device & 0xf;
1860
1861 /*
1862 * These Netmos parts are multiport serial devices with optional
1863 * parallel ports. Even when parallel ports are present, they
1864 * are identified as class SERIAL, which means the serial driver
1865 * will claim them. To prevent this, mark them as class OTHER.
1866 * These combo devices should be claimed by parport_serial.
1867 *
1868 * The subdevice ID is of the form 0x00PS, where <P> is the number
1869 * of parallel ports and <S> is the number of serial ports.
1870 */
1871 switch (dev->device) {
4c9c1686
JS		 1872 case PCI_DEVICE_ID_NETMOS_9835:
1873 /* Well, this rule doesn't hold for the following 9835 device */
1874 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1875 dev->subsystem_device == 0x0299)
1876 return;
1da177e4
LT		 1877 case PCI_DEVICE_ID_NETMOS_9735:
1878 case PCI_DEVICE_ID_NETMOS_9745:
1da177e4
LT		 1879 case PCI_DEVICE_ID_NETMOS_9845:
1880 case PCI_DEVICE_ID_NETMOS_9855:
08803efe 1881 if (num_parallel) {
f0fda801 1882 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1883 "%u serial); changing class SERIAL to OTHER "
1884 "(use parport_serial)\n",
1885 dev->device, num_parallel, num_serial);
1886 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1887 (dev->class & 0xff);
1888 }
1889 }
1890}
08803efe
YL		 1891DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1892 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1da177e4 1893
16a74744
BH		 1894static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1895{
e64aeccb 1896 u16 command, pmcsr;
16a74744
BH		 1897 u8 __iomem *csr;
1898 u8 cmd_hi;
e64aeccb 1899 int pm;
16a74744
BH		 1900
1901 switch (dev->device) {
1902 /* PCI IDs taken from drivers/net/e100.c */
1903 case 0x1029:
1904 case 0x1030 ... 0x1034:
1905 case 0x1038 ... 0x103E:
1906 case 0x1050 ... 0x1057:
1907 case 0x1059:
1908 case 0x1064 ... 0x106B:
1909 case 0x1091 ... 0x1095:
1910 case 0x1209:
1911 case 0x1229:
1912 case 0x2449:
1913 case 0x2459:
1914 case 0x245D:
1915 case 0x27DC:
1916 break;
1917 default:
1918 return;
1919 }
1920
1921 /*
1922 * Some firmware hands off the e100 with interrupts enabled,
1923 * which can cause a flood of interrupts if packets are
1924 * received before the driver attaches to the device. So
1925 * disable all e100 interrupts here. The driver will
1926 * re-enable them when it's ready.
1927 */
1928 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1929
1bef7dc0 1930 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1931 return;
1932
e64aeccb
IK		 1933 /*
1934 * Check that the device is in the D0 power state. If it's not,
1935 * there is no point to look any further.
1936 */
1937 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1938 if (pm) {
1939 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1940 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1941 return;
1942 }
1943
1bef7dc0
BH		 1944 /* Convert from PCI bus to resource space. */
1945 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1946 if (!csr) {
f0fda801 1947 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1948 return;
1949 }
1950
1951 cmd_hi = readb(csr + 3);
1952 if (cmd_hi == 0) {
f0fda801 1953 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1954 "disabling\n");
16a74744
BH		 1955 writeb(1, csr + 3);
1956 }
1957
1958 iounmap(csr);
1959}
4c5b28e2
YL		 1960DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1961 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
a5312e28 1962
649426ef
AD		 1963/*
1964 * The 82575 and 82598 may experience data corruption issues when transitioning
1965 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1966 */
1967static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1968{
1969 dev_info(&dev->dev, "Disabling L0s\n");
1970 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1971}
1972DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1973DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1974DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1975DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1976DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1977DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1979DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1980DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1981DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1982DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1983DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1984DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1985DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1986
a5312e28
IK		 1987static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1988{
1989 /* rev 1 ncr53c810 chips don't set the class at all which means
1990 * they don't get their resources remapped. Fix that here.
1991 */
1992
1993 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1994 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1995 dev->class = PCI_CLASS_STORAGE_SCSI;
1996 }
1997}
1998DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1999
9d265124
DY		 2000/* Enable 1k I/O space granularity on the Intel P64H2 */
2001static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
2002{
2003 u16 en1k;
2004 u8 io_base_lo, io_limit_lo;
2005 unsigned long base, limit;
2006 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2007
2008 pci_read_config_word(dev, 0x40, &en1k);
2009
2010 if (en1k & 0x200) {
f0fda801 2011 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
9d265124
DY		 2012
2013 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
2014 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
2015 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2016 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2017
2018 if (base <= limit) {
2019 res->start = base;
2020 res->end = limit + 0x3ff;
2021 }
2022 }
2023}
2024DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2025
15a260d5
DY		 2026/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
2027 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
2028 * in drivers/pci/setup-bus.c
2029 */
2030static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
2031{
2032 u16 en1k, iobl_adr, iobl_adr_1k;
2033 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2034
2035 pci_read_config_word(dev, 0x40, &en1k);
2036
2037 if (en1k & 0x200) {
2038 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
2039
2040 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
2041
2042 if (iobl_adr != iobl_adr_1k) {
f0fda801 2043 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
15a260d5
DY		 2044 iobl_adr,iobl_adr_1k);
2045 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
2046 }
2047 }
2048}
2049DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
2050
cf34a8e0
BG		 2051/* Under some circumstances, AER is not linked with extended capabilities.
2052 * Force it to be linked by setting the corresponding control bit in the
2053 * config space.
2054 */
1597cacb 2055static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 2056{
2057 uint8_t b;
2058 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2059 if (!(b & 0x20)) {
2060 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 2061 dev_info(&dev->dev,
2062 "Linking AER extended capability\n");
cf34a8e0
BG		 2063 }
2064 }
2065}
2066DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2067 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 2068DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 2069 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 2070
53a9bf42
TY		 2071static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2072{
2073 /*
2074 * Disable PCI Bus Parking and PCI Master read caching on CX700
2075 * which causes unspecified timing errors with a VT6212L on the PCI
ca846392
TY		 2076 * bus leading to USB2.0 packet loss.
2077 *
2078 * This quirk is only enabled if a second (on the external PCI bus)
2079 * VT6212L is found -- the CX700 core itself also contains a USB
2080 * host controller with the same PCI ID as the VT6212L.
53a9bf42
TY		 2081 */
2082
ca846392
TY		 2083 /* Count VT6212L instances */
2084 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2085 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
53a9bf42 2086 uint8_t b;
ca846392
TY		 2087
2088 /* p should contain the first (internal) VT6212L -- see if we have
2089 an external one by searching again */
2090 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2091 if (!p)
2092 return;
2093 pci_dev_put(p);
2094
53a9bf42
TY		 2095 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2096 if (b & 0x40) {
2097 /* Turn off PCI Bus Parking */
2098 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2099
bc043274
TY		 2100 dev_info(&dev->dev,
2101 "Disabling VIA CX700 PCI parking\n");
2102 }
2103 }
2104
2105 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2106 if (b != 0) {
53a9bf42
TY		 2107 /* Turn off PCI Master read caching */
2108 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 2109
2110 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 2111 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 2112
2113 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 2114 pci_write_config_byte(dev, 0x77, 0x0);
2115
d6505a52 2116 dev_info(&dev->dev,
bc043274 2117 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 2118 }
2119 }
2120}
ca846392 2121DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
53a9bf42 2122
99cb233d
BL		 2123/*
2124 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2125 * VPD end tag will hang the device. This problem was initially
2126 * observed when a vpd entry was created in sysfs
2127 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2128 * will dump 32k of data. Reading a full 32k will cause an access
2129 * beyond the VPD end tag causing the device to hang. Once the device
2130 * is hung, the bnx2 driver will not be able to reset the device.
2131 * We believe that it is legal to read beyond the end tag and
2132 * therefore the solution is to limit the read/write length.
2133 */
2134static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2135{
9d82d8ea 2136 /*
35405f25
DH		 2137 * Only disable the VPD capability for 5706, 5706S, 5708,
2138 * 5708S and 5709 rev. A
9d82d8ea 2139 */
99cb233d 2140 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
35405f25 2141 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
99cb233d 2142 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
9d82d8ea 2143 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
99cb233d
BL		 2144 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2145 (dev->revision & 0xf0) == 0x0)) {
2146 if (dev->vpd)
2147 dev->vpd->len = 0x80;
2148 }
2149}
2150
bffadffd
YZ		 2151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2152 PCI_DEVICE_ID_NX2_5706,
2153 quirk_brcm_570x_limit_vpd);
2154DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2155 PCI_DEVICE_ID_NX2_5706S,
2156 quirk_brcm_570x_limit_vpd);
2157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2158 PCI_DEVICE_ID_NX2_5708,
2159 quirk_brcm_570x_limit_vpd);
2160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2161 PCI_DEVICE_ID_NX2_5708S,
2162 quirk_brcm_570x_limit_vpd);
2163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2164 PCI_DEVICE_ID_NX2_5709,
2165 quirk_brcm_570x_limit_vpd);
2166DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2167 PCI_DEVICE_ID_NX2_5709S,
2168 quirk_brcm_570x_limit_vpd);
99cb233d 2169
26c56dc0
MM		 2170/* Originally in EDAC sources for i82875P:
2171 * Intel tells BIOS developers to hide device 6 which
2172 * configures the overflow device access containing
2173 * the DRBs - this is where we expose device 6.
2174 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2175 */
2176static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2177{
2178 u8 reg;
2179
2180 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2181 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2182 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2183 }
2184}
2185
2186DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2187 quirk_unhide_mch_dev6);
2188DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2189 quirk_unhide_mch_dev6);
2190
f02cbbe6
CM		 2191#ifdef CONFIG_TILE
2192/*
2193 * The Tilera TILEmpower platform needs to set the link speed
2194 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2195 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2196 * capability register of the PEX8624 PCIe switch. The switch
2197 * supports link speed auto negotiation, but falsely sets
2198 * the link speed to 5GT/s.
2199 */
2200static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2201{
2202 if (tile_plx_gen1) {
2203 pci_write_config_dword(dev, 0x98, 0x1);
2204 mdelay(50);
2205 }
2206}
2207DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2208#endif /* CONFIG_TILE */
26c56dc0 2209
3f79e107 2210#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 2211/* Some chipsets do not support MSI. We cannot easily rely on setting
2212 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2213 * some other busses controlled by the chipset even if Linux is not
2214 * aware of it. Instead of setting the flag on all busses in the
2215 * machine, simply disable MSI globally.
3f79e107 2216 */
ebdf7d39 2217static void __init quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 2218{
88187dfa 2219 pci_no_msi();
f0fda801 2220 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 2221}
ebdf7d39
TH		 2222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 2225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 2226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
162dedd3 2227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
549e1561 2228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
3f79e107
BG		 2229
2230/* Disable MSI on chipsets that are known to not support it */
2231static void __devinit quirk_disable_msi(struct pci_dev *dev)
2232{
2233 if (dev->subordinate) {
f0fda801 2234 dev_warn(&dev->dev, "MSI quirk detected; "
2235 "subordinate MSI disabled\n");
3f79e107
BG		 2236 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2237 }
2238}
2239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
134b3450 2240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
9313ff45 2241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
6397c75c 2242
aff61369
CL		 2243/*
2244 * The APC bridge device in AMD 780 family northbridges has some random
2245 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2246 * we use the possible vendor/device IDs of the host bridge for the
2247 * declared quirk, and search for the APC bridge by slot number.
2248 */
2249static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2250{
2251 struct pci_dev *apc_bridge;
2252
2253 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2254 if (apc_bridge) {
2255 if (apc_bridge->device == 0x9602)
2256 quirk_disable_msi(apc_bridge);
2257 pci_dev_put(apc_bridge);
2258 }
2259}
2260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2262
6397c75c
BG		 2263/* Go through the list of Hypertransport capabilities and
2264 * return 1 if a HT MSI capability is found and enabled */
2265static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2266{
7a380507
ME		 2267 int pos, ttl = 48;
2268
2269 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2270 while (pos && ttl--) {
2271 u8 flags;
2272
2273 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2274 &flags) == 0)
2275 {
f0fda801 2276 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 2277 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 2278 "enabled" : "disabled");
7a380507 2279 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 2280 }
7a380507
ME		 2281
2282 pos = pci_find_next_ht_capability(dev, pos,
2283 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 2284 }
2285 return 0;
2286}
2287
2288/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2289static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2290{
2291 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 2292 dev_warn(&dev->dev, "MSI quirk detected; "
2293 "subordinate MSI disabled\n");
6397c75c
BG		 2294 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2295 }
2296}
2297DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2298 quirk_msi_ht_cap);
6bae1d96 2299
6397c75c
BG		 2300/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2301 * MSI are supported if the MSI capability set in any of these mappings.
2302 */
2303static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2304{
2305 struct pci_dev *pdev;
2306
2307 if (!dev->subordinate)
2308 return;
2309
2310 /* check HT MSI cap on this chipset and the root one.
2311 * a single one having MSI is enough to be sure that MSI are supported.
2312 */
11f242f0 2313 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 2314 if (!pdev)
2315 return;
0c875c28 2316 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 2317 dev_warn(&dev->dev, "MSI quirk detected; "
2318 "subordinate MSI disabled\n");
6397c75c
BG		 2319 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2320 }
11f242f0 2321 pci_dev_put(pdev);
6397c75c
BG		 2322}
2323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2324 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 2325
415b6d0e
BH		 2326/* Force enable MSI mapping capability on HT bridges */
2327static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2328{
2329 int pos, ttl = 48;
2330
2331 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2332 while (pos && ttl--) {
2333 u8 flags;
2334
2335 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2336 &flags) == 0) {
2337 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2338
2339 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2340 flags | HT_MSI_FLAGS_ENABLE);
2341 }
2342 pos = pci_find_next_ht_capability(dev, pos,
2343 HT_CAPTYPE_MSI_MAPPING);
2344 }
2345}
415b6d0e
BH		 2346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2347 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2348 ht_enable_msi_mapping);
9dc625e7 2349
e0ae4f55
YL		 2350DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2351 ht_enable_msi_mapping);
2352
e4146bb9 2353/* The P5N32-SLI motherboards from Asus have a problem with msi
75e07fc3
AP		 2354 * for the MCP55 NIC. It is not yet determined whether the msi problem
2355 * also affects other devices. As for now, turn off msi for this device.
2356 */
2357static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2358{
9251bac9
JD		 2359 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2360
2361 if (board_name &&
2362 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2363 strstr(board_name, "P5N32-E SLI"))) {
75e07fc3 2364 dev_info(&dev->dev,
e4146bb9 2365 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
75e07fc3
AP		 2366 dev->no_msi = 1;
2367 }
2368}
2369DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2370 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2371 nvenet_msi_disable);
2372
66db60ea
NH		 2373/*
2374 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2375 * config register. This register controls the routing of legacy interrupts
2376 * from devices that route through the MCP55. If this register is misprogramed
2377 * interrupts are only sent to the bsp, unlike conventional systems where the
2378 * irq is broadxast to all online cpus. Not having this register set
2379 * properly prevents kdump from booting up properly, so lets make sure that
2380 * we have it set correctly.
2381 * Note this is an undocumented register.
2382 */
2383static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2384{
2385 u32 cfg;
2386
49c2fa08
NH		 2387 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2388 return;
2389
66db60ea
NH		 2390 pci_read_config_dword(dev, 0x74, &cfg);
2391
2392 if (cfg & ((1 << 2) | (1 << 15))) {
2393 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2394 cfg &= ~((1 << 2) | (1 << 15));
2395 pci_write_config_dword(dev, 0x74, cfg);
2396 }
2397}
2398
2399DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2400 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2401 nvbridge_check_legacy_irq_routing);
2402
2403DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2404 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2405 nvbridge_check_legacy_irq_routing);
2406
de745306
YL		 2407static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2408{
2409 int pos, ttl = 48;
2410 int found = 0;
2411
2412 /* check if there is HT MSI cap or enabled on this device */
2413 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2414 while (pos && ttl--) {
2415 u8 flags;
2416
2417 if (found < 1)
2418 found = 1;
2419 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2420 &flags) == 0) {
2421 if (flags & HT_MSI_FLAGS_ENABLE) {
2422 if (found < 2) {
2423 found = 2;
2424 break;
2425 }
2426 }
2427 }
2428 pos = pci_find_next_ht_capability(dev, pos,
2429 HT_CAPTYPE_MSI_MAPPING);
2430 }
2431
2432 return found;
2433}
2434
2435static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2436{
2437 struct pci_dev *dev;
2438 int pos;
2439 int i, dev_no;
2440 int found = 0;
2441
2442 dev_no = host_bridge->devfn >> 3;
2443 for (i = dev_no + 1; i < 0x20; i++) {
2444 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2445 if (!dev)
2446 continue;
2447
2448 /* found next host bridge ?*/
2449 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2450 if (pos != 0) {
2451 pci_dev_put(dev);
2452 break;
2453 }
2454
2455 if (ht_check_msi_mapping(dev)) {
2456 found = 1;
2457 pci_dev_put(dev);
2458 break;
2459 }
2460 pci_dev_put(dev);
2461 }
2462
2463 return found;
2464}
2465
eeafda70
YL		 2466#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2467#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2468
2469static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2470{
2471 int pos, ctrl_off;
2472 int end = 0;
2473 u16 flags, ctrl;
2474
2475 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2476
2477 if (!pos)
2478 goto out;
2479
2480 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2481
2482 ctrl_off = ((flags >> 10) & 1) ?
2483 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2484 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2485
2486 if (ctrl & (1 << 6))
2487 end = 1;
2488
2489out:
2490 return end;
2491}
2492
1dec6b05 2493static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2494{
2495 struct pci_dev *host_bridge;
1dec6b05
YL		 2496 int pos;
2497 int i, dev_no;
2498 int found = 0;
2499
2500 dev_no = dev->devfn >> 3;
2501 for (i = dev_no; i >= 0; i--) {
2502 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2503 if (!host_bridge)
2504 continue;
2505
2506 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2507 if (pos != 0) {
2508 found = 1;
2509 break;
2510 }
2511 pci_dev_put(host_bridge);
2512 }
2513
2514 if (!found)
2515 return;
2516
eeafda70
YL		 2517 /* don't enable end_device/host_bridge with leaf directly here */
2518 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2519 host_bridge_with_leaf(host_bridge))
de745306
YL		 2520 goto out;
2521
1dec6b05
YL		 2522 /* root did that ! */
2523 if (msi_ht_cap_enabled(host_bridge))
2524 goto out;
2525
2526 ht_enable_msi_mapping(dev);
2527
2528out:
2529 pci_dev_put(host_bridge);
2530}
2531
2532static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2533{
2534 int pos, ttl = 48;
2535
2536 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2537 while (pos && ttl--) {
2538 u8 flags;
2539
2540 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2541 &flags) == 0) {
6a958d5b 2542 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
1dec6b05
YL		 2543
2544 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2545 flags & ~HT_MSI_FLAGS_ENABLE);
2546 }
2547 pos = pci_find_next_ht_capability(dev, pos,
2548 HT_CAPTYPE_MSI_MAPPING);
2549 }
2550}
2551
de745306 2552static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
1dec6b05
YL		 2553{
2554 struct pci_dev *host_bridge;
2555 int pos;
2556 int found;
2557
3d2a5318
RW		 2558 if (!pci_msi_enabled())
2559 return;
2560
1dec6b05
YL		 2561 /* check if there is HT MSI cap or enabled on this device */
2562 found = ht_check_msi_mapping(dev);
2563
2564 /* no HT MSI CAP */
2565 if (found == 0)
2566 return;
9dc625e7
PC		 2567
2568 /*
2569 * HT MSI mapping should be disabled on devices that are below
2570 * a non-Hypertransport host bridge. Locate the host bridge...
2571 */
2572 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2573 if (host_bridge == NULL) {
2574 dev_warn(&dev->dev,
2575 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2576 return;
2577 }
2578
2579 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2580 if (pos != 0) {
2581 /* Host bridge is to HT */
1dec6b05
YL		 2582 if (found == 1) {
2583 /* it is not enabled, try to enable it */
de745306
YL		 2584 if (all)
2585 ht_enable_msi_mapping(dev);
2586 else
2587 nv_ht_enable_msi_mapping(dev);
1dec6b05 2588 }
9dc625e7
PC		 2589 return;
2590 }
2591
1dec6b05
YL		 2592 /* HT MSI is not enabled */
2593 if (found == 1)
2594 return;
9dc625e7 2595
1dec6b05
YL		 2596 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2597 ht_disable_msi_mapping(dev);
9dc625e7 2598}
de745306
YL		 2599
2600static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2601{
2602 return __nv_msi_ht_cap_quirk(dev, 1);
2603}
2604
2605static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2606{
2607 return __nv_msi_ht_cap_quirk(dev, 0);
2608}
2609
2610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
6dab62ee 2611DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
de745306
YL		 2612
2613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
6dab62ee 2614DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
9dc625e7 2615
ba698ad4
DM		 2616static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2617{
2618 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2619}
4600c9d7
SH		 2620static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2621{
2622 struct pci_dev *p;
2623
2624 /* SB700 MSI issue will be fixed at HW level from revision A21,
2625 * we need check PCI REVISION ID of SMBus controller to get SB700
2626 * revision.
2627 */
2628 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2629 NULL);
2630 if (!p)
2631 return;
2632
2633 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2634 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2635 pci_dev_put(p);
2636}
ba698ad4
DM		 2637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2638 PCI_DEVICE_ID_TIGON3_5780,
2639 quirk_msi_intx_disable_bug);
2640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2641 PCI_DEVICE_ID_TIGON3_5780S,
2642 quirk_msi_intx_disable_bug);
2643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2644 PCI_DEVICE_ID_TIGON3_5714,
2645 quirk_msi_intx_disable_bug);
2646DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2647 PCI_DEVICE_ID_TIGON3_5714S,
2648 quirk_msi_intx_disable_bug);
2649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2650 PCI_DEVICE_ID_TIGON3_5715,
2651 quirk_msi_intx_disable_bug);
2652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2653 PCI_DEVICE_ID_TIGON3_5715S,
2654 quirk_msi_intx_disable_bug);
2655
bc38b411 2656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 2657 quirk_msi_intx_disable_ati_bug);
bc38b411 2658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 2659 quirk_msi_intx_disable_ati_bug);
bc38b411 2660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 2661 quirk_msi_intx_disable_ati_bug);
bc38b411 2662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 2663 quirk_msi_intx_disable_ati_bug);
bc38b411 2664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 2665 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 2666
2667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2668 quirk_msi_intx_disable_bug);
2669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2670 quirk_msi_intx_disable_bug);
2671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2672 quirk_msi_intx_disable_bug);
2673
3f79e107 2674#endif /* CONFIG_PCI_MSI */
3d137310 2675
3322340a
FR		 2676/* Allow manual resource allocation for PCI hotplug bridges
2677 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2678 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2679 * kernel fails to allocate resources when hotplug device is
2680 * inserted and PCI bus is rescanned.
2681 */
2682static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2683{
2684 dev->is_hotplug_bridge = 1;
2685}
2686
2687DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2688
03cd8f7e
ML		 2689/*
2690 * This is a quirk for the Ricoh MMC controller found as a part of
2691 * some mulifunction chips.
2692
25985edc 2693 * This is very similar and based on the ricoh_mmc driver written by
03cd8f7e
ML		 2694 * Philip Langdale. Thank you for these magic sequences.
2695 *
2696 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2697 * and one or both of cardbus or firewire.
2698 *
2699 * It happens that they implement SD and MMC
2700 * support as separate controllers (and PCI functions). The linux SDHCI
2701 * driver supports MMC cards but the chip detects MMC cards in hardware
2702 * and directs them to the MMC controller - so the SDHCI driver never sees
2703 * them.
2704 *
2705 * To get around this, we must disable the useless MMC controller.
2706 * At that point, the SDHCI controller will start seeing them
2707 * It seems to be the case that the relevant PCI registers to deactivate the
2708 * MMC controller live on PCI function 0, which might be the cardbus controller
2709 * or the firewire controller, depending on the particular chip in question
2710 *
2711 * This has to be done early, because as soon as we disable the MMC controller
2712 * other pci functions shift up one level, e.g. function #2 becomes function
2713 * #1, and this will confuse the pci core.
2714 */
2715
2716#ifdef CONFIG_MMC_RICOH_MMC
2717static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2718{
2719 /* disable via cardbus interface */
2720 u8 write_enable;
2721 u8 write_target;
2722 u8 disable;
2723
2724 /* disable must be done via function #0 */
2725 if (PCI_FUNC(dev->devfn))
2726 return;
2727
2728 pci_read_config_byte(dev, 0xB7, &disable);
2729 if (disable & 0x02)
2730 return;
2731
2732 pci_read_config_byte(dev, 0x8E, &write_enable);
2733 pci_write_config_byte(dev, 0x8E, 0xAA);
2734 pci_read_config_byte(dev, 0x8D, &write_target);
2735 pci_write_config_byte(dev, 0x8D, 0xB7);
2736 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2737 pci_write_config_byte(dev, 0x8E, write_enable);
2738 pci_write_config_byte(dev, 0x8D, write_target);
2739
2740 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2741 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2742}
2743DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2744DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2745
2746static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2747{
2748 /* disable via firewire interface */
2749 u8 write_enable;
2750 u8 disable;
2751
2752 /* disable must be done via function #0 */
2753 if (PCI_FUNC(dev->devfn))
2754 return;
15bed0f2
MI		 2755 /*
2756 * RICOH 0xe823 SD/MMC card reader fails to recognize
2757 * certain types of SD/MMC cards. Lowering the SD base
2758 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2759 *
2760 * 0x150 - SD2.0 mode enable for changing base clock
2761 * frequency to 50Mhz
2762 * 0xe1 - Base clock frequency
2763 * 0x32 - 50Mhz new clock frequency
2764 * 0xf9 - Key register for 0x150
2765 * 0xfc - key register for 0xe1
2766 */
2767 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2768 pci_write_config_byte(dev, 0xf9, 0xfc);
2769 pci_write_config_byte(dev, 0x150, 0x10);
2770 pci_write_config_byte(dev, 0xf9, 0x00);
2771 pci_write_config_byte(dev, 0xfc, 0x01);
2772 pci_write_config_byte(dev, 0xe1, 0x32);
2773 pci_write_config_byte(dev, 0xfc, 0x00);
2774
2775 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2776 }
3e309cdf
JB		 2777
2778 pci_read_config_byte(dev, 0xCB, &disable);
2779
2780 if (disable & 0x02)
2781 return;
2782
2783 pci_read_config_byte(dev, 0xCA, &write_enable);
2784 pci_write_config_byte(dev, 0xCA, 0x57);
2785 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2786 pci_write_config_byte(dev, 0xCA, write_enable);
2787
2788 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2789 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2790
03cd8f7e
ML		 2791}
2792DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2793DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
be98ca65
MI		 2794DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2795DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
03cd8f7e
ML		 2796#endif /*CONFIG_MMC_RICOH_MMC*/
2797
d3f13810 2798#ifdef CONFIG_DMAR_TABLE
254e4200
SS		 2799#define VTUNCERRMSK_REG 0x1ac
2800#define VTD_MSK_SPEC_ERRORS (1 << 31)
2801/*
2802 * This is a quirk for masking vt-d spec defined errors to platform error
2803 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2804 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2805 * on the RAS config settings of the platform) when a vt-d fault happens.
2806 * The resulting SMI caused the system to hang.
2807 *
2808 * VT-d spec related errors are already handled by the VT-d OS code, so no
2809 * need to report the same error through other channels.
2810 */
2811static void vtd_mask_spec_errors(struct pci_dev *dev)
2812{
2813 u32 word;
2814
2815 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2816 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2817}
2818DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2819DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2820#endif
03cd8f7e 2821
63c44080
HP		 2822static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2823{
2824 /* TI 816x devices do not have class code set when in PCIe boot mode */
2825 if (dev->class == PCI_CLASS_NOT_DEFINED) {
2826 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2827 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2828 }
2829}
2830DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class);
2831
a94d072b
BH		 2832/* Some PCIe devices do not work reliably with the claimed maximum
2833 * payload size supported.
2834 */
2835static void __devinit fixup_mpss_256(struct pci_dev *dev)
2836{
2837 dev->pcie_mpss = 1; /* 256 bytes */
2838}
2839DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2840 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2841DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2842 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2843DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2844 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2845
d387a8d6
JM		 2846/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2847 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2848 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2849 * until all of the devices are discovered and buses walked, read completion
2850 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2851 * it is possible to hotplug a device with MPS of 256B.
2852 */
2853static void __devinit quirk_intel_mc_errata(struct pci_dev *dev)
2854{
2855 int err;
2856 u16 rcc;
2857
2858 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2859 return;
2860
2861 /* Intel errata specifies bits to change but does not say what they are.
2862 * Keeping them magical until such time as the registers and values can
2863 * be explained.
2864 */
2865 err = pci_read_config_word(dev, 0x48, &rcc);
2866 if (err) {
2867 dev_err(&dev->dev, "Error attempting to read the read "
2868 "completion coalescing register.\n");
2869 return;
2870 }
2871
2872 if (!(rcc & (1 << 10)))
2873 return;
2874
2875 rcc &= ~(1 << 10);
2876
2877 err = pci_write_config_word(dev, 0x48, rcc);
2878 if (err) {
2879 dev_err(&dev->dev, "Error attempting to write the read "
2880 "completion coalescing register.\n");
2881 return;
2882 }
2883
2884 pr_info_once("Read completion coalescing disabled due to hardware "
2885 "errata relating to 256B MPS.\n");
2886}
2887/* Intel 5000 series memory controllers and ports 2-7 */
2888DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2889DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2890DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2892DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2902/* Intel 5100 series memory controllers and ports 2-7 */
2903DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2904DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2905DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2906DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2907DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2908DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2909DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2910DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2911DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2912DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2913DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2914
3209874a
AV		 2915
2916static void do_one_fixup_debug(void (*fn)(struct pci_dev *dev), struct pci_dev *dev)
2917{
2918 ktime_t calltime, delta, rettime;
2919 unsigned long long duration;
2920
2921 printk(KERN_DEBUG "calling %pF @ %i\n", fn, task_pid_nr(current));
2922 calltime = ktime_get();
2923 fn(dev);
2924 rettime = ktime_get();
2925 delta = ktime_sub(rettime, calltime);
2926 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2927 printk(KERN_DEBUG "pci fixup %pF returned after %lld usecs\n", fn,
2928 duration);
2929}
2930
f67fd55f
TJ		 2931/*
2932 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2933 * even though no one is handling them (f.e. i915 driver is never loaded).
2934 * Additionally the interrupt destination is not set up properly
2935 * and the interrupt ends up -somewhere-.
2936 *
2937 * These spurious interrupts are "sticky" and the kernel disables
2938 * the (shared) interrupt line after 100.000+ generated interrupts.
2939 *
2940 * Fix it by disabling the still enabled interrupts.
2941 * This resolves crashes often seen on monitor unplug.
2942 */
2943#define I915_DEIER_REG 0x4400c
2944static void __devinit disable_igfx_irq(struct pci_dev *dev)
2945{
2946 void __iomem *regs = pci_iomap(dev, 0, 0);
2947 if (regs == NULL) {
2948 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2949 return;
2950 }
2951
2952 /* Check if any interrupt line is still enabled */
2953 if (readl(regs + I915_DEIER_REG) != 0) {
2954 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2955 "disabling\n");
2956
2957 writel(0, regs + I915_DEIER_REG);
2958 }
2959
2960 pci_iounmap(dev, regs);
2961}
2962DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2963DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2964
bfb0f330
JB		 2965static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2966 struct pci_fixup *end)
3d137310 2967{
f4ca5c6a
YL		 2968 for (; f < end; f++)
2969 if ((f->class == (u32) (dev->class >> f->class_shift) ||
2970 f->class == (u32) PCI_ANY_ID) &&
2971 (f->vendor == dev->vendor ||
2972 f->vendor == (u16) PCI_ANY_ID) &&
2973 (f->device == dev->device ||
2974 f->device == (u16) PCI_ANY_ID)) {
c9bbb4ab 2975 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
3209874a
AV		 2976 if (initcall_debug)
2977 do_one_fixup_debug(f->hook, dev);
2978 else
2979 f->hook(dev);
3d137310 2980 }
3d137310
TP		 2981}
2982
2983extern struct pci_fixup __start_pci_fixups_early[];
2984extern struct pci_fixup __end_pci_fixups_early[];
2985extern struct pci_fixup __start_pci_fixups_header[];
2986extern struct pci_fixup __end_pci_fixups_header[];
2987extern struct pci_fixup __start_pci_fixups_final[];
2988extern struct pci_fixup __end_pci_fixups_final[];
2989extern struct pci_fixup __start_pci_fixups_enable[];
2990extern struct pci_fixup __end_pci_fixups_enable[];
2991extern struct pci_fixup __start_pci_fixups_resume[];
2992extern struct pci_fixup __end_pci_fixups_resume[];
2993extern struct pci_fixup __start_pci_fixups_resume_early[];
2994extern struct pci_fixup __end_pci_fixups_resume_early[];
2995extern struct pci_fixup __start_pci_fixups_suspend[];
2996extern struct pci_fixup __end_pci_fixups_suspend[];
2997
2998
2999void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3000{
3001 struct pci_fixup *start, *end;
3002
3003 switch(pass) {
3004 case pci_fixup_early:
3005 start = __start_pci_fixups_early;
3006 end = __end_pci_fixups_early;
3007 break;
3008
3009 case pci_fixup_header:
3010 start = __start_pci_fixups_header;
3011 end = __end_pci_fixups_header;
3012 break;
3013
3014 case pci_fixup_final:
3015 start = __start_pci_fixups_final;
3016 end = __end_pci_fixups_final;
3017 break;
3018
3019 case pci_fixup_enable:
3020 start = __start_pci_fixups_enable;
3021 end = __end_pci_fixups_enable;
3022 break;
3023
3024 case pci_fixup_resume:
3025 start = __start_pci_fixups_resume;
3026 end = __end_pci_fixups_resume;
3027 break;
3028
3029 case pci_fixup_resume_early:
3030 start = __start_pci_fixups_resume_early;
3031 end = __end_pci_fixups_resume_early;
3032 break;
3033
3034 case pci_fixup_suspend:
3035 start = __start_pci_fixups_suspend;
3036 end = __end_pci_fixups_suspend;
3037 break;
3038
3039 default:
3040 /* stupid compiler warning, you would think with an enum... */
3041 return;
3042 }
3043 pci_do_fixups(dev, start, end);
3044}
93177a74 3045EXPORT_SYMBOL(pci_fixup_device);
8d86fb2c 3046
00010268 3047static int __init pci_apply_final_quirks(void)
8d86fb2c
DW		 3048{
3049 struct pci_dev *dev = NULL;
ac1aa47b
JB		 3050 u8 cls = 0;
3051 u8 tmp;
3052
3053 if (pci_cache_line_size)
3054 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3055 pci_cache_line_size << 2);
8d86fb2c 3056
4e344b1c 3057 for_each_pci_dev(dev) {
8d86fb2c 3058 pci_fixup_device(pci_fixup_final, dev);
ac1aa47b
JB		 3059 /*
3060 * If arch hasn't set it explicitly yet, use the CLS
3061 * value shared by all PCI devices. If there's a
3062 * mismatch, fall back to the default value.
3063 */
3064 if (!pci_cache_line_size) {
3065 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3066 if (!cls)
3067 cls = tmp;
3068 if (!tmp || cls == tmp)
3069 continue;
3070
3071 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3072 "using %u bytes\n", cls << 2, tmp << 2,
3073 pci_dfl_cache_line_size << 2);
3074 pci_cache_line_size = pci_dfl_cache_line_size;
3075 }
3076 }
3077 if (!pci_cache_line_size) {
3078 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3079 cls << 2, pci_dfl_cache_line_size << 2);
2820f333 3080 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
8d86fb2c
DW		 3081 }
3082
3083 return 0;
3084}
3085
cf6f3bf7 3086fs_initcall_sync(pci_apply_final_quirks);
b9c3b266
DC		 3087
3088/*
3089 * Followings are device-specific reset methods which can be used to
3090 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3091 * not available.
3092 */
aeb30016
DC		 3093static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3094{
3095 int pos;
3096
3097 /* only implement PCI_CLASS_SERIAL_USB at present */
3098 if (dev->class == PCI_CLASS_SERIAL_USB) {
3099 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3100 if (!pos)
3101 return -ENOTTY;
3102
3103 if (probe)
3104 return 0;
3105
3106 pci_write_config_byte(dev, pos + 0x4, 1);
3107 msleep(100);
3108
3109 return 0;
3110 } else {
3111 return -ENOTTY;
3112 }
3113}
3114
c763e7b5
DC		 3115static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3116{
3117 int pos;
3118
3119 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
3120 if (!pos)
3121 return -ENOTTY;
3122
3123 if (probe)
3124 return 0;
3125
3126 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
3127 PCI_EXP_DEVCTL_BCR_FLR);
3128 msleep(100);
3129
3130 return 0;
3131}
3132
3133#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3134
5b889bf2 3135static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
c763e7b5
DC		 3136 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3137 reset_intel_82599_sfp_virtfn },
aeb30016
DC		 3138 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3139 reset_intel_generic_dev },
b9c3b266
DC		 3140 { 0 }
3141};
5b889bf2
RW		 3142
3143int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3144{
df9d1e8a 3145 const struct pci_dev_reset_methods *i;
5b889bf2
RW		 3146
3147 for (i = pci_dev_reset_methods; i->reset; i++) {
3148 if ((i->vendor == dev->vendor ||
3149 i->vendor == (u16)PCI_ANY_ID) &&
3150 (i->device == dev->device ||
3151 i->device == (u16)PCI_ANY_ID))
3152 return i->reset(dev, probe);
3153 }
3154
3155 return -ENOTTY;
3156}
Linux 6.x block layer and io_uring tree(s)