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ricoh_mmc: port from driver to pci quirk
[linux-2.6-block.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
9f23ed3b 24#include <linux/kallsyms.h>
75e07fc3 25#include <linux/dmi.h>
649426ef 26#include <linux/pci-aspm.h>
32a9a682 27#include <linux/ioport.h>
93177a74 28#include <asm/dma.h> /* isa_dma_bridge_buggy */
bc56b9e0 29#include "pci.h"
1da177e4 30
32a9a682 31/*
0cdbe30f
YS		 32 * This quirk function disables memory decoding and releases memory resources
33 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
32a9a682
YS		 34 * It also rounds up size to specified alignment.
35 * Later on, the kernel will assign page-aligned memory resource back
0cdbe30f 36 * to the device.
32a9a682
YS		 37 */
38static void __devinit quirk_resource_alignment(struct pci_dev *dev)
39{
40 int i;
41 struct resource *r;
42 resource_size_t align, size;
0cdbe30f 43 u16 command;
32a9a682
YS		 44
45 if (!pci_is_reassigndev(dev))
46 return;
47
48 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
49 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
50 dev_warn(&dev->dev,
51 "Can't reassign resources to host bridge.\n");
52 return;
53 }
54
0cdbe30f
YS		 55 dev_info(&dev->dev,
56 "Disabling memory decoding and releasing memory resources.\n");
57 pci_read_config_word(dev, PCI_COMMAND, &command);
58 command &= ~PCI_COMMAND_MEMORY;
59 pci_write_config_word(dev, PCI_COMMAND, command);
32a9a682
YS		 60
61 align = pci_specified_resource_alignment(dev);
62 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
63 r = &dev->resource[i];
64 if (!(r->flags & IORESOURCE_MEM))
65 continue;
66 size = resource_size(r);
67 if (size < align) {
68 size = align;
69 dev_info(&dev->dev,
70 "Rounding up size of resource #%d to %#llx.\n",
71 i, (unsigned long long)size);
72 }
73 r->end = size - 1;
74 r->start = 0;
75 }
76 /* Need to disable bridge's resource window,
77 * to enable the kernel to reassign new resource
78 * window later on.
79 */
80 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
81 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
82 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
83 r = &dev->resource[i];
84 if (!(r->flags & IORESOURCE_MEM))
85 continue;
86 r->end = resource_size(r) - 1;
87 r->start = 0;
88 }
89 pci_disable_bridge_window(dev);
90 }
91}
92DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
93
bd8481e1
DT		 94/* The Mellanox Tavor device gives false positive parity errors
95 * Mark this device with a broken_parity_status, to allow
96 * PCI scanning code to "skip" this now blacklisted device.
97 */
98static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
99{
100 dev->broken_parity_status = 1; /* This device gives false positives */
101}
102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
103DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
104
1da177e4
LT		 105/* Deal with broken BIOS'es that neglect to enable passive release,
106 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 107static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 108{
109 struct pci_dev *d = NULL;
110 unsigned char dlc;
111
112 /* We have to make sure a particular bit is set in the PIIX3
113 ISA bridge, so we have to go out and find it. */
114 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
115 pci_read_config_byte(d, 0x82, &dlc);
116 if (!(dlc & 1<<1)) {
999da9fd 117 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 118 dlc |= 1<<1;
119 pci_write_config_byte(d, 0x82, dlc);
120 }
121 }
122}
652c538e
AM		 123DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
124DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 125
126/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
127 but VIA don't answer queries. If you happen to have good contacts at VIA
128 ask them for me please -- Alan
129
130 This appears to be BIOS not version dependent. So presumably there is a
131 chipset level fix */
1da177e4
LT		 132
133static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
134{
135 if (!isa_dma_bridge_buggy) {
136 isa_dma_bridge_buggy=1;
f0fda801 137 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 138 }
139}
140 /*
141 * Its not totally clear which chipsets are the problematic ones
142 * We know 82C586 and 82C596 variants are affected.
143 */
652c538e
AM		 144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
146DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
147DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
149DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
150DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 151
1da177e4
LT		 152/*
153 * Chipsets where PCI->PCI transfers vanish or hang
154 */
155static void __devinit quirk_nopcipci(struct pci_dev *dev)
156{
157 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 158 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 159 pci_pci_problems |= PCIPCI_FAIL;
160 }
161}
652c538e
AM		 162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5
AC		 164
165static void __devinit quirk_nopciamd(struct pci_dev *dev)
166{
167 u8 rev;
168 pci_read_config_byte(dev, 0x08, &rev);
169 if (rev == 0x13) {
170 /* Erratum 24 */
f0fda801 171 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 172 pci_pci_problems |= PCIAGP_FAIL;
173 }
174}
652c538e 175DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 176
177/*
178 * Triton requires workarounds to be used by the drivers
179 */
180static void __devinit quirk_triton(struct pci_dev *dev)
181{
182 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 183 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 184 pci_pci_problems |= PCIPCI_TRITON;
185 }
186}
652c538e
AM		 187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
188DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 191
192/*
193 * VIA Apollo KT133 needs PCI latency patch
194 * Made according to a windows driver based patch by George E. Breese
195 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
196 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
197 * the info on which Mr Breese based his work.
198 *
199 * Updated based on further information from the site and also on
200 * information provided by VIA
201 */
1597cacb 202static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 203{
204 struct pci_dev *p;
1da177e4
LT		 205 u8 busarb;
206 /* Ok we have a potential problem chipset here. Now see if we have
207 a buggy southbridge */
208
209 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
210 if (p!=NULL) {
1da177e4
LT		 211 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
212 /* Check for buggy part revisions */
2b1afa87 213 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 214 goto exit;
215 } else {
216 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
217 if (p==NULL) /* No problem parts */
218 goto exit;
1da177e4 219 /* Check for buggy part revisions */
2b1afa87 220 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 221 goto exit;
222 }
223
224 /*
225 * Ok we have the problem. Now set the PCI master grant to
226 * occur every master grant. The apparent bug is that under high
227 * PCI load (quite common in Linux of course) you can get data
228 * loss when the CPU is held off the bus for 3 bus master requests
229 * This happens to include the IDE controllers....
230 *
231 * VIA only apply this fix when an SB Live! is present but under
232 * both Linux and Windows this isnt enough, and we have seen
233 * corruption without SB Live! but with things like 3 UDMA IDE
234 * controllers. So we ignore that bit of the VIA recommendation..
235 */
236
237 pci_read_config_byte(dev, 0x76, &busarb);
238 /* Set bit 4 and bi 5 of byte 76 to 0x01
239 "Master priority rotation on every PCI master grant */
240 busarb &= ~(1<<5);
241 busarb |= (1<<4);
242 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 243 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 244exit:
245 pci_dev_put(p);
246}
652c538e
AM		 247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
249DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 250/* Must restore this on a resume from RAM */
652c538e
AM		 251DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
252DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
253DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 254
255/*
256 * VIA Apollo VP3 needs ETBF on BT848/878
257 */
258static void __devinit quirk_viaetbf(struct pci_dev *dev)
259{
260 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 261 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 262 pci_pci_problems |= PCIPCI_VIAETBF;
263 }
264}
652c538e 265DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4
LT		 266
267static void __devinit quirk_vsfx(struct pci_dev *dev)
268{
269 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 271 pci_pci_problems |= PCIPCI_VSFX;
272 }
273}
652c538e 274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 275
276/*
277 * Ali Magik requires workarounds to be used by the drivers
278 * that DMA to AGP space. Latency must be set to 0xA and triton
279 * workaround applied too
280 * [Info kindly provided by ALi]
281 */
282static void __init quirk_alimagik(struct pci_dev *dev)
283{
284 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 285 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 286 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
287 }
288}
652c538e
AM		 289DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
290DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 291
292/*
293 * Natoma has some interesting boundary conditions with Zoran stuff
294 * at least
295 */
296static void __devinit quirk_natoma(struct pci_dev *dev)
297{
298 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 299 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 300 pci_pci_problems |= PCIPCI_NATOMA;
301 }
302}
652c538e
AM		 303DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
304DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
305DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
306DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
307DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 309
310/*
311 * This chip can cause PCI parity errors if config register 0xA0 is read
312 * while DMAs are occurring.
313 */
314static void __devinit quirk_citrine(struct pci_dev *dev)
315{
316 dev->cfg_size = 0xA0;
317}
652c538e 318DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 319
320/*
321 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
322 * If it's needed, re-allocate the region.
323 */
324static void __devinit quirk_s3_64M(struct pci_dev *dev)
325{
326 struct resource *r = &dev->resource[0];
327
328 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
329 r->start = 0;
330 r->end = 0x3ffffff;
331 }
332}
652c538e
AM		 333DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 335
73d2eaac
AS		 336/*
337 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
338 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
339 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
340 * (which conflicts w/ BAR1's memory range).
341 */
342static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
343{
344 if (pci_resource_len(dev, 0) != 8) {
345 struct resource *res = &dev->resource[0];
346 res->end = res->start + 8 - 1;
347 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
348 "(incorrect header); workaround applied.\n");
349 }
350}
351DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
352
6693e74a
LT		 353static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
354 unsigned size, int nr, const char *name)
1da177e4
LT		 355{
356 region &= ~(size-1);
357 if (region) {
085ae41f 358 struct pci_bus_region bus_region;
1da177e4
LT		 359 struct resource *res = dev->resource + nr;
360
361 res->name = pci_name(dev);
362 res->start = region;
363 res->end = region + size - 1;
364 res->flags = IORESOURCE_IO;
085ae41f
DM		 365
366 /* Convert from PCI bus to resource space. */
367 bus_region.start = res->start;
368 bus_region.end = res->end;
369 pcibios_bus_to_resource(dev, res, &bus_region);
370
1da177e4 371 pci_claim_resource(dev, nr);
c7dabef8 372 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
1da177e4
LT		 373 }
374}
375
376/*
377 * ATI Northbridge setups MCE the processor if you even
378 * read somewhere between 0x3b0->0x3bb or read 0x3d3
379 */
380static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
381{
f0fda801 382 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 383 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
384 request_region(0x3b0, 0x0C, "RadeonIGP");
385 request_region(0x3d3, 0x01, "RadeonIGP");
386}
652c538e 387DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 388
389/*
390 * Let's make the southbridge information explicit instead
391 * of having to worry about people probing the ACPI areas,
392 * for example.. (Yes, it happens, and if you read the wrong
393 * ACPI register it will put the machine to sleep with no
394 * way of waking it up again. Bummer).
395 *
396 * ALI M7101: Two IO regions pointed to by words at
397 * 0xE0 (64 bytes of ACPI registers)
398 * 0xE2 (32 bytes of SMB registers)
399 */
400static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
401{
402 u16 region;
403
404 pci_read_config_word(dev, 0xE0, &region);
6693e74a 405 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 406 pci_read_config_word(dev, 0xE2, &region);
6693e74a 407 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 408}
652c538e 409DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 410
6693e74a
LT		 411static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
412{
413 u32 devres;
414 u32 mask, size, base;
415
416 pci_read_config_dword(dev, port, &devres);
417 if ((devres & enable) != enable)
418 return;
419 mask = (devres >> 16) & 15;
420 base = devres & 0xffff;
421 size = 16;
422 for (;;) {
423 unsigned bit = size >> 1;
424 if ((bit & mask) == bit)
425 break;
426 size = bit;
427 }
428 /*
429 * For now we only print it out. Eventually we'll want to
430 * reserve it (at least if it's in the 0x1000+ range), but
431 * let's get enough confirmation reports first.
432 */
433 base &= -size;
f0fda801 434 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 435}
436
437static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
438{
439 u32 devres;
440 u32 mask, size, base;
441
442 pci_read_config_dword(dev, port, &devres);
443 if ((devres & enable) != enable)
444 return;
445 base = devres & 0xffff0000;
446 mask = (devres & 0x3f) << 16;
447 size = 128 << 16;
448 for (;;) {
449 unsigned bit = size >> 1;
450 if ((bit & mask) == bit)
451 break;
452 size = bit;
453 }
454 /*
455 * For now we only print it out. Eventually we'll want to
456 * reserve it, but let's get enough confirmation reports first.
457 */
458 base &= -size;
f0fda801 459 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 460}
461
1da177e4
LT		 462/*
463 * PIIX4 ACPI: Two IO regions pointed to by longwords at
464 * 0x40 (64 bytes of ACPI registers)
08db2a70 465 * 0x90 (16 bytes of SMB registers)
6693e74a 466 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 467 */
468static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
469{
6693e74a 470 u32 region, res_a;
1da177e4
LT		 471
472 pci_read_config_dword(dev, 0x40, &region);
6693e74a 473 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 474 pci_read_config_dword(dev, 0x90, &region);
08db2a70 475 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 476
477 /* Device resource A has enables for some of the other ones */
478 pci_read_config_dword(dev, 0x5c, &res_a);
479
480 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
481 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
482
483 /* Device resource D is just bitfields for static resources */
484
485 /* Device 12 enabled? */
486 if (res_a & (1 << 29)) {
487 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
488 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
489 }
490 /* Device 13 enabled? */
491 if (res_a & (1 << 30)) {
492 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
493 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
494 }
495 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
496 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 497}
652c538e
AM		 498DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
499DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4
LT		 500
501/*
502 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
503 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
504 * 0x58 (64 bytes of GPIO I/O space)
505 */
506static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
507{
508 u32 region;
509
510 pci_read_config_dword(dev, 0x40, &region);
6693e74a 511 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 512
513 pci_read_config_dword(dev, 0x58, &region);
6693e74a 514 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4 515}
652c538e
AM		 516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
519DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
520DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
521DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
522DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
524DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
525DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 526
894886e5 527static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
2cea752f
M		 528{
529 u32 region;
530
531 pci_read_config_dword(dev, 0x40, &region);
532 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
533
534 pci_read_config_dword(dev, 0x48, &region);
535 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
536}
894886e5
LT		 537
538static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
539{
540 u32 val;
541 u32 size, base;
542
543 pci_read_config_dword(dev, reg, &val);
544
545 /* Enabled? */
546 if (!(val & 1))
547 return;
548 base = val & 0xfffc;
549 if (dynsize) {
550 /*
551 * This is not correct. It is 16, 32 or 64 bytes depending on
552 * register D31:F0:ADh bits 5:4.
553 *
554 * But this gets us at least _part_ of it.
555 */
556 size = 16;
557 } else {
558 size = 128;
559 }
560 base &= ~(size-1);
561
562 /* Just print it out for now. We should reserve it after more debugging */
563 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
564}
565
566static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
567{
568 /* Shared ACPI/GPIO decode with all ICH6+ */
569 ich6_lpc_acpi_gpio(dev);
570
571 /* ICH6-specific generic IO decode */
572 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
573 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
574}
575DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
576DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
577
578static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
579{
580 u32 val;
581 u32 mask, base;
582
583 pci_read_config_dword(dev, reg, &val);
584
585 /* Enabled? */
586 if (!(val & 1))
587 return;
588
589 /*
590 * IO base in bits 15:2, mask in bits 23:18, both
591 * are dword-based
592 */
593 base = val & 0xfffc;
594 mask = (val >> 16) & 0xfc;
595 mask |= 3;
596
597 /* Just print it out for now. We should reserve it after more debugging */
598 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
599}
600
601/* ICH7-10 has the same common LPC generic IO decode registers */
602static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
603{
604 /* We share the common ACPI/DPIO decode with ICH6 */
605 ich6_lpc_acpi_gpio(dev);
606
607 /* And have 4 ICH7+ generic decodes */
608 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
609 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
610 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
611 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
612}
613DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
614DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
616DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
617DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
618DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
619DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
620DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
621DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
622DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
623DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
624DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
625DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
2cea752f 626
1da177e4
LT		 627/*
628 * VIA ACPI: One IO region pointed to by longword at
629 * 0x48 or 0x20 (256 bytes of ACPI registers)
630 */
631static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
632{
1da177e4
LT		 633 u32 region;
634
651472fb 635 if (dev->revision & 0x10) {
1da177e4
LT		 636 pci_read_config_dword(dev, 0x48, &region);
637 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 638 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 639 }
640}
652c538e 641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 642
643/*
644 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
645 * 0x48 (256 bytes of ACPI registers)
646 * 0x70 (128 bytes of hardware monitoring register)
647 * 0x90 (16 bytes of SMB registers)
648 */
649static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
650{
651 u16 hm;
652 u32 smb;
653
654 quirk_vt82c586_acpi(dev);
655
656 pci_read_config_word(dev, 0x70, &hm);
657 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 658 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 659
660 pci_read_config_dword(dev, 0x90, &smb);
661 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 662 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4 663}
652c538e 664DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 665
6d85f29b
IK		 666/*
667 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
668 * 0x88 (128 bytes of power management registers)
669 * 0xd0 (16 bytes of SMB registers)
670 */
671static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
672{
673 u16 pm, smb;
674
675 pci_read_config_word(dev, 0x88, &pm);
676 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 677 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 678
679 pci_read_config_word(dev, 0xd0, &smb);
680 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 681 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 682}
683DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
684
1f56f4a2
GB		 685/*
686 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
687 * Disable fast back-to-back on the secondary bus segment
688 */
689static void __devinit quirk_xio2000a(struct pci_dev *dev)
690{
691 struct pci_dev *pdev;
692 u16 command;
693
694 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
695 "secondary bus fast back-to-back transfers disabled\n");
696 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
697 pci_read_config_word(pdev, PCI_COMMAND, &command);
698 if (command & PCI_COMMAND_FAST_BACK)
699 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
700 }
701}
702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
703 quirk_xio2000a);
1da177e4
LT		 704
705#ifdef CONFIG_X86_IO_APIC
706
707#include <asm/io_apic.h>
708
709/*
710 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
711 * devices to the external APIC.
712 *
713 * TODO: When we have device-specific interrupt routers,
714 * this code will go away from quirks.
715 */
1597cacb 716static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 717{
718 u8 tmp;
719
720 if (nr_ioapics < 1)
721 tmp = 0; /* nothing routed to external APIC */
722 else
723 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
724
f0fda801 725 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 726 tmp == 0 ? "Disa" : "Ena");
727
728 /* Offset 0x58: External APIC IRQ output control */
729 pci_write_config_byte (dev, 0x58, tmp);
730}
652c538e 731DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 732DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 733
a1740913
KW		 734/*
735 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
736 * This leads to doubled level interrupt rates.
737 * Set this bit to get rid of cycle wastage.
738 * Otherwise uncritical.
739 */
1597cacb 740static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 741{
742 u8 misc_control2;
743#define BYPASS_APIC_DEASSERT 8
744
745 pci_read_config_byte(dev, 0x5B, &misc_control2);
746 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 747 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 748 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
749 }
750}
751DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 752DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 753
1da177e4
LT		 754/*
755 * The AMD io apic can hang the box when an apic irq is masked.
756 * We check all revs >= B0 (yet not in the pre production!) as the bug
757 * is currently marked NoFix
758 *
759 * We have multiple reports of hangs with this chipset that went away with
236561e5 760 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 761 * of course. However the advice is demonstrably good even if so..
762 */
763static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
764{
44c10138 765 if (dev->revision >= 0x02) {
f0fda801 766 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
767 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 768 }
769}
652c538e 770DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4
LT		 771
772static void __init quirk_ioapic_rmw(struct pci_dev *dev)
773{
774 if (dev->devfn == 0 && dev->bus->number == 0)
775 sis_apic_bug = 1;
776}
652c538e 777DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4
LT		 778#endif /* CONFIG_X86_IO_APIC */
779
d556ad4b
PO		 780/*
781 * Some settings of MMRBC can lead to data corruption so block changes.
782 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
783 */
784static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
785{
aa288d4d 786 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 787 dev_info(&dev->dev, "AMD8131 rev %x detected; "
788 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 789 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
790 }
791}
792DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 793
1da177e4
LT		 794/*
795 * FIXME: it is questionable that quirk_via_acpi
796 * is needed. It shows up as an ISA bridge, and does not
797 * support the PCI_INTERRUPT_LINE register at all. Therefore
798 * it seems like setting the pci_dev's 'irq' to the
799 * value of the ACPI SCI interrupt is only done for convenience.
800 * -jgarzik
801 */
802static void __devinit quirk_via_acpi(struct pci_dev *d)
803{
804 /*
805 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
806 */
807 u8 irq;
808 pci_read_config_byte(d, 0x42, &irq);
809 irq &= 0xf;
810 if (irq && (irq != 2))
811 d->irq = irq;
812}
652c538e
AM		 813DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
814DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 815
09d6029f
DD		 816
817/*
1597cacb 818 * VIA bridges which have VLink
09d6029f 819 */
1597cacb 820
c06bb5d4
JD		 821static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
822
823static void quirk_via_bridge(struct pci_dev *dev)
824{
825 /* See what bridge we have and find the device ranges */
826 switch (dev->device) {
827 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 828 /* The VT82C686 is special, it attaches to PCI and can have
829 any device number. All its subdevices are functions of
830 that single device. */
831 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
832 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 833 break;
834 case PCI_DEVICE_ID_VIA_8237:
835 case PCI_DEVICE_ID_VIA_8237A:
836 via_vlink_dev_lo = 15;
837 break;
838 case PCI_DEVICE_ID_VIA_8235:
839 via_vlink_dev_lo = 16;
840 break;
841 case PCI_DEVICE_ID_VIA_8231:
842 case PCI_DEVICE_ID_VIA_8233_0:
843 case PCI_DEVICE_ID_VIA_8233A:
844 case PCI_DEVICE_ID_VIA_8233C_0:
845 via_vlink_dev_lo = 17;
846 break;
847 }
848}
849DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
850DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
851DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
853DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
855DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 857
1597cacb
AC		 858/**
859 * quirk_via_vlink - VIA VLink IRQ number update
860 * @dev: PCI device
861 *
862 * If the device we are dealing with is on a PIC IRQ we need to
863 * ensure that the IRQ line register which usually is not relevant
864 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 865 * to the right place.
866 * We only do this on systems where a VIA south bridge was detected,
867 * and only for VIA devices on the motherboard (see quirk_via_bridge
868 * above).
1597cacb
AC		 869 */
870
871static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 872{
873 u8 irq, new_irq;
874
c06bb5d4
JD		 875 /* Check if we have VLink at all */
876 if (via_vlink_dev_lo == -1)
09d6029f
DD		 877 return;
878
879 new_irq = dev->irq;
880
881 /* Don't quirk interrupts outside the legacy IRQ range */
882 if (!new_irq || new_irq > 15)
883 return;
884
1597cacb 885 /* Internal device ? */
c06bb5d4
JD		 886 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
887 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 888 return;
889
890 /* This is an internal VLink device on a PIC interrupt. The BIOS
891 ought to have set this but may not have, so we redo it */
892
25be5e6c
LB		 893 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
894 if (new_irq != irq) {
f0fda801 895 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
896 irq, new_irq);
25be5e6c
LB		 897 udelay(15); /* unknown if delay really needed */
898 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
899 }
900}
1597cacb 901DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 902
1da177e4
LT		 903/*
904 * VIA VT82C598 has its device ID settable and many BIOSes
905 * set it to the ID of VT82C597 for backward compatibility.
906 * We need to switch it off to be able to recognize the real
907 * type of the chip.
908 */
909static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
910{
911 pci_write_config_byte(dev, 0xfc, 0);
912 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
913}
652c538e 914DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 915
916/*
917 * CardBus controllers have a legacy base address that enables them
918 * to respond as i82365 pcmcia controllers. We don't want them to
919 * do this even if the Linux CardBus driver is not loaded, because
920 * the Linux i82365 driver does not (and should not) handle CardBus.
921 */
1597cacb 922static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4
LT		 923{
924 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
925 return;
926 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
927}
928DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
e1a2a51e 929DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1da177e4
LT		 930
931/*
932 * Following the PCI ordering rules is optional on the AMD762. I'm not
933 * sure what the designers were smoking but let's not inhale...
934 *
935 * To be fair to AMD, it follows the spec by default, its BIOS people
936 * who turn it off!
937 */
1597cacb 938static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 939{
940 u32 pcic;
941 pci_read_config_dword(dev, 0x4C, &pcic);
942 if ((pcic&6)!=6) {
943 pcic |= 6;
f0fda801 944 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 945 pci_write_config_dword(dev, 0x4C, pcic);
946 pci_read_config_dword(dev, 0x84, &pcic);
947 pcic |= (1<<23); /* Required in this mode */
948 pci_write_config_dword(dev, 0x84, pcic);
949 }
950}
652c538e 951DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 952DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 953
954/*
955 * DreamWorks provided workaround for Dunord I-3000 problem
956 *
957 * This card decodes and responds to addresses not apparently
958 * assigned to it. We force a larger allocation to ensure that
959 * nothing gets put too close to it.
960 */
961static void __devinit quirk_dunord ( struct pci_dev * dev )
962{
963 struct resource *r = &dev->resource [1];
964 r->start = 0;
965 r->end = 0xffffff;
966}
652c538e 967DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 968
969/*
970 * i82380FB mobile docking controller: its PCI-to-PCI bridge
971 * is subtractive decoding (transparent), and does indicate this
972 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
973 * instead of 0x01.
974 */
975static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
976{
977 dev->transparent = 1;
978}
652c538e
AM		 979DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
980DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 981
982/*
983 * Common misconfiguration of the MediaGX/Geode PCI master that will
984 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
985 * datasheets found at http://www.national.com/ds/GX for info on what
986 * these bits do. <christer@weinigel.se>
987 */
1597cacb 988static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 989{
990 u8 reg;
991 pci_read_config_byte(dev, 0x41, &reg);
992 if (reg & 2) {
993 reg &= ~2;
f0fda801 994 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 995 pci_write_config_byte(dev, 0x41, reg);
996 }
997}
652c538e
AM		 998DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
999DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 1000
1da177e4
LT		 1001/*
1002 * Ensure C0 rev restreaming is off. This is normally done by
1003 * the BIOS but in the odd case it is not the results are corruption
1004 * hence the presence of a Linux check
1005 */
1597cacb 1006static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 1007{
1008 u16 config;
1da177e4 1009
44c10138 1010 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 1011 return;
1012 pci_read_config_word(pdev, 0x40, &config);
1013 if (config & (1<<6)) {
1014 config &= ~(1<<6);
1015 pci_write_config_word(pdev, 0x40, config);
f0fda801 1016 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 1017 }
1018}
652c538e 1019DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 1020DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 1021
05a7d22b 1022static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 1023{
5deab536 1024 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
05a7d22b 1025 u8 tmp;
ab17443a 1026
05a7d22b
CC		 1027 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1028 if (tmp == 0x01) {
ab17443a
CH		 1029 pci_read_config_byte(pdev, 0x40, &tmp);
1030 pci_write_config_byte(pdev, 0x40, tmp|1);
1031 pci_write_config_byte(pdev, 0x9, 1);
1032 pci_write_config_byte(pdev, 0xa, 6);
1033 pci_write_config_byte(pdev, 0x40, tmp);
1034
c9f89475 1035 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 1036 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 1037 }
1038}
05a7d22b 1039DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 1040DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 1041DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 1042DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
5deab536
SH		 1043DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1044DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
ab17443a 1045
1da177e4
LT		 1046/*
1047 * Serverworks CSB5 IDE does not fully support native mode
1048 */
1049static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1050{
1051 u8 prog;
1052 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1053 if (prog & 5) {
1054 prog &= ~5;
1055 pdev->class &= ~5;
1056 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 1057 /* PCI layer will sort out resources */
1da177e4
LT		 1058 }
1059}
652c538e 1060DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 1061
1062/*
1063 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1064 */
1065static void __init quirk_ide_samemode(struct pci_dev *pdev)
1066{
1067 u8 prog;
1068
1069 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1070
1071 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 1072 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 1073 prog &= ~5;
1074 pdev->class &= ~5;
1075 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 1076 }
1077}
368c73d4 1078DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 1079
979b1791
AC		 1080/*
1081 * Some ATA devices break if put into D3
1082 */
1083
1084static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1085{
1086 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1087 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1088 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1089}
1090DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1091DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
7a661c6f
AC		 1092/* ALi loses some register settings that we cannot then restore */
1093DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1094/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1095 occur when mode detecting */
1096DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
979b1791 1097
1da177e4
LT		 1098/* This was originally an Alpha specific thing, but it really fits here.
1099 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1100 */
1101static void __init quirk_eisa_bridge(struct pci_dev *dev)
1102{
1103 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1104}
652c538e 1105DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 1106
7daa0c4f 1107
1da177e4
LT		 1108/*
1109 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1110 * is not activated. The myth is that Asus said that they do not want the
1111 * users to be irritated by just another PCI Device in the Win98 device
1112 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1113 * package 2.7.0 for details)
1114 *
1115 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1116 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 1117 * becomes necessary to do this tweak in two steps -- the chosen trigger
1118 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 1119 *
1120 * Note that we used to unhide the SMBus that way on Toshiba laptops
1121 * (Satellite A40 and Tecra M2) but then found that the thermal management
1122 * was done by SMM code, which could cause unsynchronized concurrent
1123 * accesses to the SMBus registers, with potentially bad effects. Thus you
1124 * should be very careful when adding new entries: if SMM is accessing the
1125 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 1126 *
1127 * Likewise, many recent laptops use ACPI for thermal management. If the
1128 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1129 * natively, and keeping the SMBus hidden is the right thing to do. If you
1130 * are about to add an entry in the table below, please first disassemble
1131 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 1132 */
9d24a81e 1133static int asus_hides_smbus;
1da177e4
LT		 1134
1135static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1136{
1137 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1138 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1139 switch(dev->subsystem_device) {
a00db371 1140 case 0x8025: /* P4B-LX */
1da177e4
LT		 1141 case 0x8070: /* P4B */
1142 case 0x8088: /* P4B533 */
1143 case 0x1626: /* L3C notebook */
1144 asus_hides_smbus = 1;
1145 }
2f2d39d2 1146 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 1147 switch(dev->subsystem_device) {
1148 case 0x80b1: /* P4GE-V */
1149 case 0x80b2: /* P4PE */
1150 case 0x8093: /* P4B533-V */
1151 asus_hides_smbus = 1;
1152 }
2f2d39d2 1153 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 1154 switch(dev->subsystem_device) {
1155 case 0x8030: /* P4T533 */
1156 asus_hides_smbus = 1;
1157 }
2f2d39d2 1158 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1159 switch (dev->subsystem_device) {
1160 case 0x8070: /* P4G8X Deluxe */
1161 asus_hides_smbus = 1;
1162 }
2f2d39d2 1163 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1164 switch (dev->subsystem_device) {
1165 case 0x80c9: /* PU-DLS */
1166 asus_hides_smbus = 1;
1167 }
2f2d39d2 1168 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1169 switch (dev->subsystem_device) {
1170 case 0x1751: /* M2N notebook */
1171 case 0x1821: /* M5N notebook */
4096ed0f 1172 case 0x1897: /* A6L notebook */
1da177e4
LT		 1173 asus_hides_smbus = 1;
1174 }
2f2d39d2 1175 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1176 switch (dev->subsystem_device) {
1177 case 0x184b: /* W1N notebook */
1178 case 0x186a: /* M6Ne notebook */
1179 asus_hides_smbus = 1;
1180 }
2f2d39d2 1181 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1182 switch (dev->subsystem_device) {
1183 case 0x80f2: /* P4P800-X */
1184 asus_hides_smbus = 1;
1185 }
2f2d39d2 1186 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
M		 1187 switch (dev->subsystem_device) {
1188 case 0x1882: /* M6V notebook */
2d1e1c75 1189 case 0x1977: /* A6VA notebook */
acc06632
M		 1190 asus_hides_smbus = 1;
1191 }
1da177e4
LT		 1192 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1193 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1194 switch(dev->subsystem_device) {
1195 case 0x088C: /* HP Compaq nc8000 */
1196 case 0x0890: /* HP Compaq nc6000 */
1197 asus_hides_smbus = 1;
1198 }
2f2d39d2 1199 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1200 switch (dev->subsystem_device) {
1201 case 0x12bc: /* HP D330L */
e3b1bd57 1202 case 0x12bd: /* HP D530 */
74c57428 1203 case 0x006a: /* HP Compaq nx9500 */
1da177e4
LT		 1204 asus_hides_smbus = 1;
1205 }
677cc644
JD		 1206 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1207 switch (dev->subsystem_device) {
1208 case 0x12bf: /* HP xw4100 */
1209 asus_hides_smbus = 1;
1210 }
1da177e4
LT		 1211 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1212 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1213 switch(dev->subsystem_device) {
1214 case 0xC00C: /* Samsung P35 notebook */
1215 asus_hides_smbus = 1;
1216 }
c87f883e
RIZ		 1217 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1218 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1219 switch(dev->subsystem_device) {
1220 case 0x0058: /* Compaq Evo N620c */
1221 asus_hides_smbus = 1;
1222 }
d7698edc 1223 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1224 switch(dev->subsystem_device) {
1225 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1226 /* Motherboard doesn't have Host bridge
1227 * subvendor/subdevice IDs, therefore checking
1228 * its on-board VGA controller */
1229 asus_hides_smbus = 1;
1230 }
8293b0f6 1231 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
10260d9a
JD		 1232 switch(dev->subsystem_device) {
1233 case 0x00b8: /* Compaq Evo D510 CMT */
1234 case 0x00b9: /* Compaq Evo D510 SFF */
6b5096e4 1235 case 0x00ba: /* Compaq Evo D510 USDT */
8293b0f6
DS		 1236 /* Motherboard doesn't have Host bridge
1237 * subvendor/subdevice IDs and on-board VGA
1238 * controller is disabled if an AGP card is
1239 * inserted, therefore checking USB UHCI
1240 * Controller #1 */
10260d9a
JD		 1241 asus_hides_smbus = 1;
1242 }
27e46859
KH		 1243 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1244 switch (dev->subsystem_device) {
1245 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1246 /* Motherboard doesn't have host bridge
1247 * subvendor/subdevice IDs, therefore checking
1248 * its on-board VGA controller */
1249 asus_hides_smbus = 1;
1250 }
1da177e4
LT		 1251 }
1252}
652c538e
AM		 1253DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1255DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1256DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1257DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1258DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1259DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1260DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1261DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1262DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1263
1264DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
8293b0f6 1265DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
27e46859 1266DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1267
1597cacb 1268static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1269{
1270 u16 val;
1271
1272 if (likely(!asus_hides_smbus))
1273 return;
1274
1275 pci_read_config_word(dev, 0xF2, &val);
1276 if (val & 0x8) {
1277 pci_write_config_word(dev, 0xF2, val & (~0x8));
1278 pci_read_config_word(dev, 0xF2, &val);
1279 if (val & 0x8)
f0fda801 1280 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1281 else
f0fda801 1282 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1283 }
1284}
652c538e
AM		 1285DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1286DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1287DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1289DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1292DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1293DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1294DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1295DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1296DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1297DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1298DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1299
e1a2a51e
RW		 1300/* It appears we just have one such device. If not, we have a warning */
1301static void __iomem *asus_rcba_base;
1302static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1303{
e1a2a51e 1304 u32 rcba;
acc06632
M		 1305
1306 if (likely(!asus_hides_smbus))
1307 return;
e1a2a51e
RW		 1308 WARN_ON(asus_rcba_base);
1309
acc06632 1310 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1311 /* use bits 31:14, 16 kB aligned */
1312 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1313 if (asus_rcba_base == NULL)
1314 return;
1315}
1316
1317static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1318{
1319 u32 val;
1320
1321 if (likely(!asus_hides_smbus || !asus_rcba_base))
1322 return;
1323 /* read the Function Disable register, dword mode only */
1324 val = readl(asus_rcba_base + 0x3418);
1325 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1326}
1327
1328static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1329{
1330 if (likely(!asus_hides_smbus || !asus_rcba_base))
1331 return;
1332 iounmap(asus_rcba_base);
1333 asus_rcba_base = NULL;
f0fda801 1334 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1335}
e1a2a51e
RW		 1336
1337static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1338{
1339 asus_hides_smbus_lpc_ich6_suspend(dev);
1340 asus_hides_smbus_lpc_ich6_resume_early(dev);
1341 asus_hides_smbus_lpc_ich6_resume(dev);
1342}
652c538e 1343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1344DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1345DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1346DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1347
1da177e4
LT		 1348/*
1349 * SiS 96x south bridge: BIOS typically hides SMBus device...
1350 */
1597cacb 1351static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1352{
1353 u8 val = 0;
1da177e4 1354 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1355 if (val & 0x10) {
f0fda801 1356 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1357 pci_write_config_byte(dev, 0x77, val & ~0x10);
1358 }
1da177e4 1359}
652c538e
AM		 1360DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1361DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1362DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1363DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1364DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1365DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1366DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1367DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1368
1da177e4
LT		 1369/*
1370 * ... This is further complicated by the fact that some SiS96x south
1371 * bridges pretend to be 85C503/5513 instead. In that case see if we
1372 * spotted a compatible north bridge to make sure.
1373 * (pci_find_device doesn't work yet)
1374 *
1375 * We can also enable the sis96x bit in the discovery register..
1376 */
1da177e4
LT		 1377#define SIS_DETECT_REGISTER 0x40
1378
1597cacb 1379static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1380{
1381 u8 reg;
1382 u16 devid;
1383
1384 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1385 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1386 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1387 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1388 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1389 return;
1390 }
1391
1da177e4 1392 /*
2f5c33b3
MH		 1393 * Ok, it now shows up as a 96x.. run the 96x quirk by
1394 * hand in case it has already been processed.
1395 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1396 */
1397 dev->device = devid;
2f5c33b3 1398 quirk_sis_96x_smbus(dev);
1da177e4 1399}
652c538e 1400DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1401DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1402
1da177e4 1403
e5548e96
BJD		 1404/*
1405 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1406 * and MC97 modem controller are disabled when a second PCI soundcard is
1407 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1408 * -- bjd
1409 */
1597cacb 1410static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1411{
1412 u8 val;
1413 int asus_hides_ac97 = 0;
1414
1415 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1416 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1417 asus_hides_ac97 = 1;
1418 }
1419
1420 if (!asus_hides_ac97)
1421 return;
1422
1423 pci_read_config_byte(dev, 0x50, &val);
1424 if (val & 0xc0) {
1425 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1426 pci_read_config_byte(dev, 0x50, &val);
1427 if (val & 0xc0)
f0fda801 1428 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1429 else
f0fda801 1430 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1431 }
1432}
652c538e 1433DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1434DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1435
77967052 1436#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1437
1438/*
1439 * If we are using libata we can drive this chip properly but must
1440 * do this early on to make the additional device appear during
1441 * the PCI scanning.
1442 */
5ee2ae7f 1443static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1444{
e34bb370 1445 u32 conf1, conf5, class;
15e0c694
AC		 1446 u8 hdr;
1447
1448 /* Only poke fn 0 */
1449 if (PCI_FUNC(pdev->devfn))
1450 return;
1451
5ee2ae7f
TH		 1452 pci_read_config_dword(pdev, 0x40, &conf1);
1453 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1454
5ee2ae7f
TH		 1455 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1456 conf5 &= ~(1 << 24); /* Clear bit 24 */
1457
1458 switch (pdev->device) {
1459 case PCI_DEVICE_ID_JMICRON_JMB360:
1460 /* The controller should be in single function ahci mode */
1461 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1462 break;
1463
1464 case PCI_DEVICE_ID_JMICRON_JMB365:
1465 case PCI_DEVICE_ID_JMICRON_JMB366:
1466 /* Redirect IDE second PATA port to the right spot */
1467 conf5 |= (1 << 24);
1468 /* Fall through */
1469 case PCI_DEVICE_ID_JMICRON_JMB361:
1470 case PCI_DEVICE_ID_JMICRON_JMB363:
1471 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1472 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1473 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1474 break;
1475
1476 case PCI_DEVICE_ID_JMICRON_JMB368:
1477 /* The controller should be in single function IDE mode */
1478 conf1 |= 0x00C00000; /* Set 22, 23 */
1479 break;
15e0c694 1480 }
5ee2ae7f
TH		 1481
1482 pci_write_config_dword(pdev, 0x40, conf1);
1483 pci_write_config_dword(pdev, 0x80, conf5);
1484
1485 /* Update pdev accordingly */
1486 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1487 pdev->hdr_type = hdr & 0x7f;
1488 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1489
1490 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1491 pdev->class = class >> 8;
15e0c694 1492}
5ee2ae7f
TH		 1493DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1494DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1495DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1496DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1497DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1498DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
e1a2a51e
RW		 1499DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1500DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1501DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1502DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1503DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1504DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
15e0c694
AC		 1505
1506#endif
1507
1da177e4
LT		 1508#ifdef CONFIG_X86_IO_APIC
1509static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1510{
1511 int i;
1512
1513 if ((pdev->class >> 8) != 0xff00)
1514 return;
1515
1516 /* the first BAR is the location of the IO APIC...we must
1517 * not touch this (and it's already covered by the fixmap), so
1518 * forcibly insert it into the resource tree */
1519 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1520 insert_resource(&iomem_resource, &pdev->resource[0]);
1521
1522 /* The next five BARs all seem to be rubbish, so just clean
1523 * them out */
1524 for (i=1; i < 6; i++) {
1525 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1526 }
1527
1528}
652c538e 1529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1530#endif
1531
1da177e4
LT		 1532static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1533{
0ba379ec
EB		 1534 pci_msi_off(pdev);
1535 pdev->no_msi = 1;
1da177e4 1536}
652c538e
AM		 1537DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1538DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1539DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1540
4602b88d
KA		 1541
1542/*
1543 * It's possible for the MSI to get corrupted if shpc and acpi
1544 * are used together on certain PXH-based systems.
1545 */
1546static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1547{
f5f2b131 1548 pci_msi_off(dev);
4602b88d 1549 dev->no_msi = 1;
f0fda801 1550 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1551}
1552DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1553DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1554DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1555DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1556DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1557
ffadcc2f
KCA		 1558/*
1559 * Some Intel PCI Express chipsets have trouble with downstream
1560 * device power management.
1561 */
1562static void quirk_intel_pcie_pm(struct pci_dev * dev)
1563{
1564 pci_pm_d3_delay = 120;
1565 dev->no_d1d2 = 1;
1566}
1567
1568DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1572DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1573DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1575DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1577DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1579DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1584DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1585DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1586DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1587DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1588DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1589
426b3b8d 1590#ifdef CONFIG_X86_IO_APIC
e1d3a908
SA		 1591/*
1592 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1593 * remap the original interrupt in the linux kernel to the boot interrupt, so
1594 * that a PCI device's interrupt handler is installed on the boot interrupt
1595 * line instead.
1596 */
1597static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1598{
41b9eb26 1599 if (noioapicquirk || noioapicreroute)
e1d3a908
SA		 1600 return;
1601
1602 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
fdcdaf6c
BH		 1603 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1604 dev->vendor, dev->device);
e1d3a908 1605}
88d1dce3
OD		 1606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1609DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1614DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1615DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1616DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1617DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1618DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1619DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1620DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1621DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
e1d3a908 1622
426b3b8d
SA		 1623/*
1624 * On some chipsets we can disable the generation of legacy INTx boot
1625 * interrupts.
1626 */
1627
1628/*
1629 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1630 * 300641-004US, section 5.7.3.
1631 */
1632#define INTEL_6300_IOAPIC_ABAR 0x40
1633#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1634
1635static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1636{
1637 u16 pci_config_word;
1638
1639 if (noioapicquirk)
1640 return;
1641
1642 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1643 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1644 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1645
fdcdaf6c
BH		 1646 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1647 dev->vendor, dev->device);
426b3b8d 1648}
88d1dce3
OD		 1649DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1650DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
77251188
OD		 1651
1652/*
1653 * disable boot interrupts on HT-1000
1654 */
1655#define BC_HT1000_FEATURE_REG 0x64
1656#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1657#define BC_HT1000_MAP_IDX 0xC00
1658#define BC_HT1000_MAP_DATA 0xC01
1659
1660static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1661{
1662 u32 pci_config_dword;
1663 u8 irq;
1664
1665 if (noioapicquirk)
1666 return;
1667
1668 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1669 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1670 BC_HT1000_PIC_REGS_ENABLE);
1671
1672 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1673 outb(irq, BC_HT1000_MAP_IDX);
1674 outb(0x00, BC_HT1000_MAP_DATA);
1675 }
1676
1677 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1678
fdcdaf6c
BH		 1679 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1680 dev->vendor, dev->device);
77251188 1681}
88d1dce3
OD		 1682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1683DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
542622da
OD		 1684
1685/*
1686 * disable boot interrupts on AMD and ATI chipsets
1687 */
1688/*
1689 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1690 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1691 * (due to an erratum).
1692 */
1693#define AMD_813X_MISC 0x40
1694#define AMD_813X_NOIOAMODE (1<<0)
4fd8bdc5 1695#define AMD_813X_REV_B1 0x12
bbe19443 1696#define AMD_813X_REV_B2 0x13
542622da
OD		 1697
1698static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1699{
1700 u32 pci_config_dword;
1701
1702 if (noioapicquirk)
1703 return;
4fd8bdc5
SA		 1704 if ((dev->revision == AMD_813X_REV_B1) ||
1705 (dev->revision == AMD_813X_REV_B2))
bbe19443 1706 return;
542622da
OD		 1707
1708 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1709 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1710 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1711
fdcdaf6c
BH		 1712 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1713 dev->vendor, dev->device);
542622da 1714}
4fd8bdc5
SA		 1715DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1716DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1717DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1718DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
542622da
OD		 1719
1720#define AMD_8111_PCI_IRQ_ROUTING 0x56
1721
1722static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1723{
1724 u16 pci_config_word;
1725
1726 if (noioapicquirk)
1727 return;
1728
1729 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1730 if (!pci_config_word) {
fdcdaf6c
BH		 1731 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1732 "already disabled\n", dev->vendor, dev->device);
542622da
OD		 1733 return;
1734 }
1735 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
fdcdaf6c
BH		 1736 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1737 dev->vendor, dev->device);
542622da 1738}
88d1dce3
OD		 1739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1740DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
426b3b8d
SA		 1741#endif /* CONFIG_X86_IO_APIC */
1742
33dced2e
SS		 1743/*
1744 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1745 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1746 * Re-allocate the region if needed...
1747 */
1748static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1749{
1750 struct resource *r = &dev->resource[0];
1751
1752 if (r->start & 0x8) {
1753 r->start = 0;
1754 r->end = 0xf;
1755 }
1756}
1757DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1758 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1759 quirk_tc86c001_ide);
1760
1da177e4
LT		 1761static void __devinit quirk_netmos(struct pci_dev *dev)
1762{
1763 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1764 unsigned int num_serial = dev->subsystem_device & 0xf;
1765
1766 /*
1767 * These Netmos parts are multiport serial devices with optional
1768 * parallel ports. Even when parallel ports are present, they
1769 * are identified as class SERIAL, which means the serial driver
1770 * will claim them. To prevent this, mark them as class OTHER.
1771 * These combo devices should be claimed by parport_serial.
1772 *
1773 * The subdevice ID is of the form 0x00PS, where <P> is the number
1774 * of parallel ports and <S> is the number of serial ports.
1775 */
1776 switch (dev->device) {
4c9c1686
JS		 1777 case PCI_DEVICE_ID_NETMOS_9835:
1778 /* Well, this rule doesn't hold for the following 9835 device */
1779 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1780 dev->subsystem_device == 0x0299)
1781 return;
1da177e4
LT		 1782 case PCI_DEVICE_ID_NETMOS_9735:
1783 case PCI_DEVICE_ID_NETMOS_9745:
1da177e4
LT		 1784 case PCI_DEVICE_ID_NETMOS_9845:
1785 case PCI_DEVICE_ID_NETMOS_9855:
1786 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1787 num_parallel) {
f0fda801 1788 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1789 "%u serial); changing class SERIAL to OTHER "
1790 "(use parport_serial)\n",
1791 dev->device, num_parallel, num_serial);
1792 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1793 (dev->class & 0xff);
1794 }
1795 }
1796}
1797DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1798
16a74744
BH		 1799static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1800{
e64aeccb 1801 u16 command, pmcsr;
16a74744
BH		 1802 u8 __iomem *csr;
1803 u8 cmd_hi;
e64aeccb 1804 int pm;
16a74744
BH		 1805
1806 switch (dev->device) {
1807 /* PCI IDs taken from drivers/net/e100.c */
1808 case 0x1029:
1809 case 0x1030 ... 0x1034:
1810 case 0x1038 ... 0x103E:
1811 case 0x1050 ... 0x1057:
1812 case 0x1059:
1813 case 0x1064 ... 0x106B:
1814 case 0x1091 ... 0x1095:
1815 case 0x1209:
1816 case 0x1229:
1817 case 0x2449:
1818 case 0x2459:
1819 case 0x245D:
1820 case 0x27DC:
1821 break;
1822 default:
1823 return;
1824 }
1825
1826 /*
1827 * Some firmware hands off the e100 with interrupts enabled,
1828 * which can cause a flood of interrupts if packets are
1829 * received before the driver attaches to the device. So
1830 * disable all e100 interrupts here. The driver will
1831 * re-enable them when it's ready.
1832 */
1833 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1834
1bef7dc0 1835 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1836 return;
1837
e64aeccb
IK		 1838 /*
1839 * Check that the device is in the D0 power state. If it's not,
1840 * there is no point to look any further.
1841 */
1842 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1843 if (pm) {
1844 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1845 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1846 return;
1847 }
1848
1bef7dc0
BH		 1849 /* Convert from PCI bus to resource space. */
1850 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1851 if (!csr) {
f0fda801 1852 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1853 return;
1854 }
1855
1856 cmd_hi = readb(csr + 3);
1857 if (cmd_hi == 0) {
f0fda801 1858 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1859 "disabling\n");
16a74744
BH		 1860 writeb(1, csr + 3);
1861 }
1862
1863 iounmap(csr);
1864}
4e68fc97 1865DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28 1866
649426ef
AD		 1867/*
1868 * The 82575 and 82598 may experience data corruption issues when transitioning
1869 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1870 */
1871static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1872{
1873 dev_info(&dev->dev, "Disabling L0s\n");
1874 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1875}
1876DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1877DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1878DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1879DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1880DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1881DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1882DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1883DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1884DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1885DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1886DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1887DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1888DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1889DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1890
a5312e28
IK		 1891static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1892{
1893 /* rev 1 ncr53c810 chips don't set the class at all which means
1894 * they don't get their resources remapped. Fix that here.
1895 */
1896
1897 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1898 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1899 dev->class = PCI_CLASS_STORAGE_SCSI;
1900 }
1901}
1902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1903
9d265124
DY		 1904/* Enable 1k I/O space granularity on the Intel P64H2 */
1905static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1906{
1907 u16 en1k;
1908 u8 io_base_lo, io_limit_lo;
1909 unsigned long base, limit;
1910 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1911
1912 pci_read_config_word(dev, 0x40, &en1k);
1913
1914 if (en1k & 0x200) {
f0fda801 1915 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
9d265124
DY		 1916
1917 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1918 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1919 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1920 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1921
1922 if (base <= limit) {
1923 res->start = base;
1924 res->end = limit + 0x3ff;
1925 }
1926 }
1927}
1928DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1929
15a260d5
DY		 1930/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1931 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1932 * in drivers/pci/setup-bus.c
1933 */
1934static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1935{
1936 u16 en1k, iobl_adr, iobl_adr_1k;
1937 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1938
1939 pci_read_config_word(dev, 0x40, &en1k);
1940
1941 if (en1k & 0x200) {
1942 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1943
1944 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1945
1946 if (iobl_adr != iobl_adr_1k) {
f0fda801 1947 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
15a260d5
DY		 1948 iobl_adr,iobl_adr_1k);
1949 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1950 }
1951 }
1952}
1953DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1954
cf34a8e0
BG		 1955/* Under some circumstances, AER is not linked with extended capabilities.
1956 * Force it to be linked by setting the corresponding control bit in the
1957 * config space.
1958 */
1597cacb 1959static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 1960{
1961 uint8_t b;
1962 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1963 if (!(b & 0x20)) {
1964 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 1965 dev_info(&dev->dev,
1966 "Linking AER extended capability\n");
cf34a8e0
BG		 1967 }
1968 }
1969}
1970DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1971 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 1972DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 1973 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 1974
53a9bf42
TY		 1975static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1976{
1977 /*
1978 * Disable PCI Bus Parking and PCI Master read caching on CX700
1979 * which causes unspecified timing errors with a VT6212L on the PCI
1980 * bus leading to USB2.0 packet loss. The defaults are that these
1981 * features are turned off but some BIOSes turn them on.
1982 */
1983
1984 uint8_t b;
1985 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1986 if (b & 0x40) {
1987 /* Turn off PCI Bus Parking */
1988 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1989
bc043274
TY		 1990 dev_info(&dev->dev,
1991 "Disabling VIA CX700 PCI parking\n");
1992 }
1993 }
1994
1995 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1996 if (b != 0) {
53a9bf42
TY		 1997 /* Turn off PCI Master read caching */
1998 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 1999
2000 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 2001 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 2002
2003 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 2004 pci_write_config_byte(dev, 0x77, 0x0);
2005
d6505a52 2006 dev_info(&dev->dev,
bc043274 2007 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 2008 }
2009 }
2010}
2011DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2012
99cb233d
BL		 2013/*
2014 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2015 * VPD end tag will hang the device. This problem was initially
2016 * observed when a vpd entry was created in sysfs
2017 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2018 * will dump 32k of data. Reading a full 32k will cause an access
2019 * beyond the VPD end tag causing the device to hang. Once the device
2020 * is hung, the bnx2 driver will not be able to reset the device.
2021 * We believe that it is legal to read beyond the end tag and
2022 * therefore the solution is to limit the read/write length.
2023 */
2024static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2025{
9d82d8ea 2026 /*
35405f25
DH		 2027 * Only disable the VPD capability for 5706, 5706S, 5708,
2028 * 5708S and 5709 rev. A
9d82d8ea 2029 */
99cb233d 2030 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
35405f25 2031 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
99cb233d 2032 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
9d82d8ea 2033 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
99cb233d
BL		 2034 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2035 (dev->revision & 0xf0) == 0x0)) {
2036 if (dev->vpd)
2037 dev->vpd->len = 0x80;
2038 }
2039}
2040
bffadffd
YZ		 2041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2042 PCI_DEVICE_ID_NX2_5706,
2043 quirk_brcm_570x_limit_vpd);
2044DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2045 PCI_DEVICE_ID_NX2_5706S,
2046 quirk_brcm_570x_limit_vpd);
2047DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2048 PCI_DEVICE_ID_NX2_5708,
2049 quirk_brcm_570x_limit_vpd);
2050DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2051 PCI_DEVICE_ID_NX2_5708S,
2052 quirk_brcm_570x_limit_vpd);
2053DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2054 PCI_DEVICE_ID_NX2_5709,
2055 quirk_brcm_570x_limit_vpd);
2056DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2057 PCI_DEVICE_ID_NX2_5709S,
2058 quirk_brcm_570x_limit_vpd);
99cb233d 2059
26c56dc0
MM		 2060/* Originally in EDAC sources for i82875P:
2061 * Intel tells BIOS developers to hide device 6 which
2062 * configures the overflow device access containing
2063 * the DRBs - this is where we expose device 6.
2064 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2065 */
2066static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2067{
2068 u8 reg;
2069
2070 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2071 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2072 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2073 }
2074}
2075
2076DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2077 quirk_unhide_mch_dev6);
2078DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2079 quirk_unhide_mch_dev6);
2080
2081
3f79e107 2082#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 2083/* Some chipsets do not support MSI. We cannot easily rely on setting
2084 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2085 * some other busses controlled by the chipset even if Linux is not
2086 * aware of it. Instead of setting the flag on all busses in the
2087 * machine, simply disable MSI globally.
3f79e107 2088 */
ebdf7d39 2089static void __init quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 2090{
88187dfa 2091 pci_no_msi();
f0fda801 2092 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 2093}
ebdf7d39
TH		 2094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2095DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2096DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 2097DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 2098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
162dedd3 2099DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
3f79e107
BG		 2100
2101/* Disable MSI on chipsets that are known to not support it */
2102static void __devinit quirk_disable_msi(struct pci_dev *dev)
2103{
2104 if (dev->subordinate) {
f0fda801 2105 dev_warn(&dev->dev, "MSI quirk detected; "
2106 "subordinate MSI disabled\n");
3f79e107
BG		 2107 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2108 }
2109}
2110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
6397c75c
BG		 2111
2112/* Go through the list of Hypertransport capabilities and
2113 * return 1 if a HT MSI capability is found and enabled */
2114static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2115{
7a380507
ME		 2116 int pos, ttl = 48;
2117
2118 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2119 while (pos && ttl--) {
2120 u8 flags;
2121
2122 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2123 &flags) == 0)
2124 {
f0fda801 2125 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 2126 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 2127 "enabled" : "disabled");
7a380507 2128 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 2129 }
7a380507
ME		 2130
2131 pos = pci_find_next_ht_capability(dev, pos,
2132 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 2133 }
2134 return 0;
2135}
2136
2137/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2138static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2139{
2140 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 2141 dev_warn(&dev->dev, "MSI quirk detected; "
2142 "subordinate MSI disabled\n");
6397c75c
BG		 2143 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2144 }
2145}
2146DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2147 quirk_msi_ht_cap);
6bae1d96 2148
6397c75c
BG		 2149/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2150 * MSI are supported if the MSI capability set in any of these mappings.
2151 */
2152static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2153{
2154 struct pci_dev *pdev;
2155
2156 if (!dev->subordinate)
2157 return;
2158
2159 /* check HT MSI cap on this chipset and the root one.
2160 * a single one having MSI is enough to be sure that MSI are supported.
2161 */
11f242f0 2162 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 2163 if (!pdev)
2164 return;
0c875c28 2165 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 2166 dev_warn(&dev->dev, "MSI quirk detected; "
2167 "subordinate MSI disabled\n");
6397c75c
BG		 2168 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2169 }
11f242f0 2170 pci_dev_put(pdev);
6397c75c
BG		 2171}
2172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2173 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 2174
415b6d0e
BH		 2175/* Force enable MSI mapping capability on HT bridges */
2176static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2177{
2178 int pos, ttl = 48;
2179
2180 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2181 while (pos && ttl--) {
2182 u8 flags;
2183
2184 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2185 &flags) == 0) {
2186 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2187
2188 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2189 flags | HT_MSI_FLAGS_ENABLE);
2190 }
2191 pos = pci_find_next_ht_capability(dev, pos,
2192 HT_CAPTYPE_MSI_MAPPING);
2193 }
2194}
415b6d0e
BH		 2195DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2196 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2197 ht_enable_msi_mapping);
9dc625e7 2198
e0ae4f55
YL		 2199DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2200 ht_enable_msi_mapping);
2201
75e07fc3
AP		 2202/* The P5N32-SLI Premium motherboard from Asus has a problem with msi
2203 * for the MCP55 NIC. It is not yet determined whether the msi problem
2204 * also affects other devices. As for now, turn off msi for this device.
2205 */
2206static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2207{
2208 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
2209 dev_info(&dev->dev,
2210 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
2211 dev->no_msi = 1;
2212 }
2213}
2214DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2215 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2216 nvenet_msi_disable);
2217
de745306
YL		 2218static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2219{
2220 int pos, ttl = 48;
2221 int found = 0;
2222
2223 /* check if there is HT MSI cap or enabled on this device */
2224 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2225 while (pos && ttl--) {
2226 u8 flags;
2227
2228 if (found < 1)
2229 found = 1;
2230 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2231 &flags) == 0) {
2232 if (flags & HT_MSI_FLAGS_ENABLE) {
2233 if (found < 2) {
2234 found = 2;
2235 break;
2236 }
2237 }
2238 }
2239 pos = pci_find_next_ht_capability(dev, pos,
2240 HT_CAPTYPE_MSI_MAPPING);
2241 }
2242
2243 return found;
2244}
2245
2246static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2247{
2248 struct pci_dev *dev;
2249 int pos;
2250 int i, dev_no;
2251 int found = 0;
2252
2253 dev_no = host_bridge->devfn >> 3;
2254 for (i = dev_no + 1; i < 0x20; i++) {
2255 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2256 if (!dev)
2257 continue;
2258
2259 /* found next host bridge ?*/
2260 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2261 if (pos != 0) {
2262 pci_dev_put(dev);
2263 break;
2264 }
2265
2266 if (ht_check_msi_mapping(dev)) {
2267 found = 1;
2268 pci_dev_put(dev);
2269 break;
2270 }
2271 pci_dev_put(dev);
2272 }
2273
2274 return found;
2275}
2276
eeafda70
YL		 2277#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2278#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2279
2280static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2281{
2282 int pos, ctrl_off;
2283 int end = 0;
2284 u16 flags, ctrl;
2285
2286 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2287
2288 if (!pos)
2289 goto out;
2290
2291 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2292
2293 ctrl_off = ((flags >> 10) & 1) ?
2294 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2295 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2296
2297 if (ctrl & (1 << 6))
2298 end = 1;
2299
2300out:
2301 return end;
2302}
2303
1dec6b05 2304static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2305{
2306 struct pci_dev *host_bridge;
1dec6b05
YL		 2307 int pos;
2308 int i, dev_no;
2309 int found = 0;
2310
2311 dev_no = dev->devfn >> 3;
2312 for (i = dev_no; i >= 0; i--) {
2313 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2314 if (!host_bridge)
2315 continue;
2316
2317 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2318 if (pos != 0) {
2319 found = 1;
2320 break;
2321 }
2322 pci_dev_put(host_bridge);
2323 }
2324
2325 if (!found)
2326 return;
2327
eeafda70
YL		 2328 /* don't enable end_device/host_bridge with leaf directly here */
2329 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2330 host_bridge_with_leaf(host_bridge))
de745306
YL		 2331 goto out;
2332
1dec6b05
YL		 2333 /* root did that ! */
2334 if (msi_ht_cap_enabled(host_bridge))
2335 goto out;
2336
2337 ht_enable_msi_mapping(dev);
2338
2339out:
2340 pci_dev_put(host_bridge);
2341}
2342
2343static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2344{
2345 int pos, ttl = 48;
2346
2347 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2348 while (pos && ttl--) {
2349 u8 flags;
2350
2351 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2352 &flags) == 0) {
6a958d5b 2353 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
1dec6b05
YL		 2354
2355 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2356 flags & ~HT_MSI_FLAGS_ENABLE);
2357 }
2358 pos = pci_find_next_ht_capability(dev, pos,
2359 HT_CAPTYPE_MSI_MAPPING);
2360 }
2361}
2362
de745306 2363static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
1dec6b05
YL		 2364{
2365 struct pci_dev *host_bridge;
2366 int pos;
2367 int found;
2368
2369 /* check if there is HT MSI cap or enabled on this device */
2370 found = ht_check_msi_mapping(dev);
2371
2372 /* no HT MSI CAP */
2373 if (found == 0)
2374 return;
9dc625e7
PC		 2375
2376 /*
2377 * HT MSI mapping should be disabled on devices that are below
2378 * a non-Hypertransport host bridge. Locate the host bridge...
2379 */
2380 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2381 if (host_bridge == NULL) {
2382 dev_warn(&dev->dev,
2383 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2384 return;
2385 }
2386
2387 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2388 if (pos != 0) {
2389 /* Host bridge is to HT */
1dec6b05
YL		 2390 if (found == 1) {
2391 /* it is not enabled, try to enable it */
de745306
YL		 2392 if (all)
2393 ht_enable_msi_mapping(dev);
2394 else
2395 nv_ht_enable_msi_mapping(dev);
1dec6b05 2396 }
9dc625e7
PC		 2397 return;
2398 }
2399
1dec6b05
YL		 2400 /* HT MSI is not enabled */
2401 if (found == 1)
2402 return;
9dc625e7 2403
1dec6b05
YL		 2404 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2405 ht_disable_msi_mapping(dev);
9dc625e7 2406}
de745306
YL		 2407
2408static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2409{
2410 return __nv_msi_ht_cap_quirk(dev, 1);
2411}
2412
2413static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2414{
2415 return __nv_msi_ht_cap_quirk(dev, 0);
2416}
2417
2418DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
6dab62ee 2419DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
de745306
YL		 2420
2421DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
6dab62ee 2422DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
9dc625e7 2423
ba698ad4
DM		 2424static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2425{
2426 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2427}
4600c9d7
SH		 2428static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2429{
2430 struct pci_dev *p;
2431
2432 /* SB700 MSI issue will be fixed at HW level from revision A21,
2433 * we need check PCI REVISION ID of SMBus controller to get SB700
2434 * revision.
2435 */
2436 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2437 NULL);
2438 if (!p)
2439 return;
2440
2441 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2442 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2443 pci_dev_put(p);
2444}
ba698ad4
DM		 2445DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2446 PCI_DEVICE_ID_TIGON3_5780,
2447 quirk_msi_intx_disable_bug);
2448DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2449 PCI_DEVICE_ID_TIGON3_5780S,
2450 quirk_msi_intx_disable_bug);
2451DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2452 PCI_DEVICE_ID_TIGON3_5714,
2453 quirk_msi_intx_disable_bug);
2454DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2455 PCI_DEVICE_ID_TIGON3_5714S,
2456 quirk_msi_intx_disable_bug);
2457DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2458 PCI_DEVICE_ID_TIGON3_5715,
2459 quirk_msi_intx_disable_bug);
2460DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2461 PCI_DEVICE_ID_TIGON3_5715S,
2462 quirk_msi_intx_disable_bug);
2463
bc38b411 2464DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 2465 quirk_msi_intx_disable_ati_bug);
bc38b411 2466DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 2467 quirk_msi_intx_disable_ati_bug);
bc38b411 2468DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 2469 quirk_msi_intx_disable_ati_bug);
bc38b411 2470DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 2471 quirk_msi_intx_disable_ati_bug);
bc38b411 2472DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 2473 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 2474
2475DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2476 quirk_msi_intx_disable_bug);
2477DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2478 quirk_msi_intx_disable_bug);
2479DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2480 quirk_msi_intx_disable_bug);
2481
3f79e107 2482#endif /* CONFIG_PCI_MSI */
3d137310 2483
7eb93b17
YZ		 2484#ifdef CONFIG_PCI_IOV
2485
2486/*
2487 * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the
2488 * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
2489 * old Flash Memory Space.
2490 */
2491static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
2492{
2493 int pos, flags;
2494 u32 bar, start, size;
2495
2496 if (PAGE_SIZE > 0x10000)
2497 return;
2498
2499 flags = pci_resource_flags(dev, 0);
2500 if ((flags & PCI_BASE_ADDRESS_SPACE) !=
2501 PCI_BASE_ADDRESS_SPACE_MEMORY ||
2502 (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !=
2503 PCI_BASE_ADDRESS_MEM_TYPE_32)
2504 return;
2505
2506 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
2507 if (!pos)
2508 return;
2509
2510 pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
2511 if (bar & PCI_BASE_ADDRESS_MEM_MASK)
2512 return;
2513
2514 start = pci_resource_start(dev, 1);
2515 size = pci_resource_len(dev, 1);
2516 if (!start || size != 0x400000 || start & (size - 1))
2517 return;
2518
2519 pci_resource_flags(dev, 1) = 0;
2520 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
2521 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
2522 pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
2523
2524 dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n");
2525}
2526DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
2527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
2528DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
dcb4ea2e
AD		 2529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov);
2530DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov);
6f1186be 2531DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov);
7a0deb6b 2532DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov);
7eb93b17
YZ		 2533
2534#endif /* CONFIG_PCI_IOV */
2535
03cd8f7e
ML		 2536/*
2537 * This is a quirk for the Ricoh MMC controller found as a part of
2538 * some mulifunction chips.
2539
2540 * This is very similiar and based on the ricoh_mmc driver written by
2541 * Philip Langdale. Thank you for these magic sequences.
2542 *
2543 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2544 * and one or both of cardbus or firewire.
2545 *
2546 * It happens that they implement SD and MMC
2547 * support as separate controllers (and PCI functions). The linux SDHCI
2548 * driver supports MMC cards but the chip detects MMC cards in hardware
2549 * and directs them to the MMC controller - so the SDHCI driver never sees
2550 * them.
2551 *
2552 * To get around this, we must disable the useless MMC controller.
2553 * At that point, the SDHCI controller will start seeing them
2554 * It seems to be the case that the relevant PCI registers to deactivate the
2555 * MMC controller live on PCI function 0, which might be the cardbus controller
2556 * or the firewire controller, depending on the particular chip in question
2557 *
2558 * This has to be done early, because as soon as we disable the MMC controller
2559 * other pci functions shift up one level, e.g. function #2 becomes function
2560 * #1, and this will confuse the pci core.
2561 */
2562
2563#ifdef CONFIG_MMC_RICOH_MMC
2564static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2565{
2566 /* disable via cardbus interface */
2567 u8 write_enable;
2568 u8 write_target;
2569 u8 disable;
2570
2571 /* disable must be done via function #0 */
2572 if (PCI_FUNC(dev->devfn))
2573 return;
2574
2575 pci_read_config_byte(dev, 0xB7, &disable);
2576 if (disable & 0x02)
2577 return;
2578
2579 pci_read_config_byte(dev, 0x8E, &write_enable);
2580 pci_write_config_byte(dev, 0x8E, 0xAA);
2581 pci_read_config_byte(dev, 0x8D, &write_target);
2582 pci_write_config_byte(dev, 0x8D, 0xB7);
2583 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2584 pci_write_config_byte(dev, 0x8E, write_enable);
2585 pci_write_config_byte(dev, 0x8D, write_target);
2586
2587 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2588 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2589}
2590DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2591DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2592
2593static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2594{
2595 /* disable via firewire interface */
2596 u8 write_enable;
2597 u8 disable;
2598
2599 /* disable must be done via function #0 */
2600 if (PCI_FUNC(dev->devfn))
2601 return;
2602
2603 pci_read_config_byte(dev, 0xCB, &disable);
2604
2605 if (disable & 0x02)
2606 return;
2607
2608 pci_read_config_byte(dev, 0xCA, &write_enable);
2609 pci_write_config_byte(dev, 0xCA, 0x57);
2610 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2611 pci_write_config_byte(dev, 0xCA, write_enable);
2612
2613 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2614 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2615}
2616DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2617DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2618#endif /*CONFIG_MMC_RICOH_MMC*/
2619
2620
bfb0f330
JB		 2621static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2622 struct pci_fixup *end)
3d137310
TP		 2623{
2624 while (f < end) {
2625 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
bfb0f330 2626 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
c9bbb4ab 2627 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
3d137310
TP		 2628 f->hook(dev);
2629 }
2630 f++;
2631 }
2632}
2633
2634extern struct pci_fixup __start_pci_fixups_early[];
2635extern struct pci_fixup __end_pci_fixups_early[];
2636extern struct pci_fixup __start_pci_fixups_header[];
2637extern struct pci_fixup __end_pci_fixups_header[];
2638extern struct pci_fixup __start_pci_fixups_final[];
2639extern struct pci_fixup __end_pci_fixups_final[];
2640extern struct pci_fixup __start_pci_fixups_enable[];
2641extern struct pci_fixup __end_pci_fixups_enable[];
2642extern struct pci_fixup __start_pci_fixups_resume[];
2643extern struct pci_fixup __end_pci_fixups_resume[];
2644extern struct pci_fixup __start_pci_fixups_resume_early[];
2645extern struct pci_fixup __end_pci_fixups_resume_early[];
2646extern struct pci_fixup __start_pci_fixups_suspend[];
2647extern struct pci_fixup __end_pci_fixups_suspend[];
2648
2649
2650void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2651{
2652 struct pci_fixup *start, *end;
2653
2654 switch(pass) {
2655 case pci_fixup_early:
2656 start = __start_pci_fixups_early;
2657 end = __end_pci_fixups_early;
2658 break;
2659
2660 case pci_fixup_header:
2661 start = __start_pci_fixups_header;
2662 end = __end_pci_fixups_header;
2663 break;
2664
2665 case pci_fixup_final:
2666 start = __start_pci_fixups_final;
2667 end = __end_pci_fixups_final;
2668 break;
2669
2670 case pci_fixup_enable:
2671 start = __start_pci_fixups_enable;
2672 end = __end_pci_fixups_enable;
2673 break;
2674
2675 case pci_fixup_resume:
2676 start = __start_pci_fixups_resume;
2677 end = __end_pci_fixups_resume;
2678 break;
2679
2680 case pci_fixup_resume_early:
2681 start = __start_pci_fixups_resume_early;
2682 end = __end_pci_fixups_resume_early;
2683 break;
2684
2685 case pci_fixup_suspend:
2686 start = __start_pci_fixups_suspend;
2687 end = __end_pci_fixups_suspend;
2688 break;
2689
2690 default:
2691 /* stupid compiler warning, you would think with an enum... */
2692 return;
2693 }
2694 pci_do_fixups(dev, start, end);
2695}
93177a74 2696EXPORT_SYMBOL(pci_fixup_device);
8d86fb2c 2697
00010268 2698static int __init pci_apply_final_quirks(void)
8d86fb2c
DW		 2699{
2700 struct pci_dev *dev = NULL;
ac1aa47b
JB		 2701 u8 cls = 0;
2702 u8 tmp;
2703
2704 if (pci_cache_line_size)
2705 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2706 pci_cache_line_size << 2);
8d86fb2c
DW		 2707
2708 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2709 pci_fixup_device(pci_fixup_final, dev);
ac1aa47b
JB		 2710 /*
2711 * If arch hasn't set it explicitly yet, use the CLS
2712 * value shared by all PCI devices. If there's a
2713 * mismatch, fall back to the default value.
2714 */
2715 if (!pci_cache_line_size) {
2716 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
2717 if (!cls)
2718 cls = tmp;
2719 if (!tmp || cls == tmp)
2720 continue;
2721
2722 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
2723 "using %u bytes\n", cls << 2, tmp << 2,
2724 pci_dfl_cache_line_size << 2);
2725 pci_cache_line_size = pci_dfl_cache_line_size;
2726 }
2727 }
2728 if (!pci_cache_line_size) {
2729 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
2730 cls << 2, pci_dfl_cache_line_size << 2);
2820f333 2731 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
8d86fb2c
DW		 2732 }
2733
2734 return 0;
2735}
2736
cf6f3bf7 2737fs_initcall_sync(pci_apply_final_quirks);
b9c3b266
DC		 2738
2739/*
2740 * Followings are device-specific reset methods which can be used to
2741 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
2742 * not available.
2743 */
aeb30016
DC		 2744static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
2745{
2746 int pos;
2747
2748 /* only implement PCI_CLASS_SERIAL_USB at present */
2749 if (dev->class == PCI_CLASS_SERIAL_USB) {
2750 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
2751 if (!pos)
2752 return -ENOTTY;
2753
2754 if (probe)
2755 return 0;
2756
2757 pci_write_config_byte(dev, pos + 0x4, 1);
2758 msleep(100);
2759
2760 return 0;
2761 } else {
2762 return -ENOTTY;
2763 }
2764}
2765
c763e7b5
DC		 2766static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
2767{
2768 int pos;
2769
2770 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2771 if (!pos)
2772 return -ENOTTY;
2773
2774 if (probe)
2775 return 0;
2776
2777 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2778 PCI_EXP_DEVCTL_BCR_FLR);
2779 msleep(100);
2780
2781 return 0;
2782}
2783
2784#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
2785
5b889bf2 2786static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
c763e7b5
DC		 2787 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
2788 reset_intel_82599_sfp_virtfn },
aeb30016
DC		 2789 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2790 reset_intel_generic_dev },
b9c3b266
DC		 2791 { 0 }
2792};
5b889bf2
RW		 2793
2794int pci_dev_specific_reset(struct pci_dev *dev, int probe)
2795{
df9d1e8a 2796 const struct pci_dev_reset_methods *i;
5b889bf2
RW		 2797
2798 for (i = pci_dev_reset_methods; i->reset; i++) {
2799 if ((i->vendor == dev->vendor ||
2800 i->vendor == (u16)PCI_ANY_ID) &&
2801 (i->device == dev->device ||
2802 i->device == (u16)PCI_ANY_ID))
2803 return i->reset(dev, probe);
2804 }
2805
2806 return -ENOTTY;
2807}
Linux 6.x block layer and io_uring tree(s)