Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e BH |
3 | * This file contains work-arounds for many known PCI hardware bugs. |
4 | * Devices present only on certain architectures (host bridges et cetera) | |
5 | * should be handled in arch-specific code. | |
1da177e4 | 6 | * |
df62ab5e | 7 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. |
1da177e4 | 8 | * |
df62ab5e | 9 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> |
1da177e4 | 10 | * |
df62ab5e BH |
11 | * Init/reset quirks for USB host controllers should be in the USB quirks |
12 | * file, where their drivers can use them. | |
1da177e4 LT |
13 | */ |
14 | ||
03038d84 | 15 | #include <linux/bitfield.h> |
1da177e4 LT |
16 | #include <linux/types.h> |
17 | #include <linux/kernel.h> | |
363c75db | 18 | #include <linux/export.h> |
1da177e4 | 19 | #include <linux/pci.h> |
abb4970a | 20 | #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ |
1da177e4 LT |
21 | #include <linux/init.h> |
22 | #include <linux/delay.h> | |
25be5e6c | 23 | #include <linux/acpi.h> |
75e07fc3 | 24 | #include <linux/dmi.h> |
32a9a682 | 25 | #include <linux/ioport.h> |
3209874a AV |
26 | #include <linux/sched.h> |
27 | #include <linux/ktime.h> | |
9fe373f9 | 28 | #include <linux/mm.h> |
ffb08634 | 29 | #include <linux/nvme.h> |
630b3aff | 30 | #include <linux/platform_data/x86/apple.h> |
07f4f97d | 31 | #include <linux/pm_runtime.h> |
4694ae37 | 32 | #include <linux/suspend.h> |
ad281ecf | 33 | #include <linux/switchtec.h> |
bc56b9e0 | 34 | #include "pci.h" |
1da177e4 | 35 | |
a89c8224 MR |
36 | /* |
37 | * Retrain the link of a downstream PCIe port by hand if necessary. | |
38 | * | |
39 | * This is needed at least where a downstream port of the ASMedia ASM2824 | |
40 | * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 | |
41 | * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > | |
42 | * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched | |
43 | * board. | |
44 | * | |
45 | * In such a configuration the switches are supposed to negotiate the link | |
46 | * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link | |
47 | * continues switching between the two speeds indefinitely and the data | |
48 | * link layer never reaches the active state, with link training reported | |
49 | * repeatedly active ~84% of the time. Forcing the target link speed to | |
50 | * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to | |
51 | * each other correctly however. And more interestingly retraining with a | |
52 | * higher target link speed afterwards lets the two successfully negotiate | |
53 | * 5.0GT/s. | |
54 | * | |
55 | * With the ASM2824 we can rely on the otherwise optional Data Link Layer | |
56 | * Link Active status bit and in the failed link training scenario it will | |
57 | * be off along with the Link Bandwidth Management Status indicating that | |
58 | * hardware has changed the link speed or width in an attempt to correct | |
59 | * unreliable link operation. For a port that has been left unconnected | |
60 | * both bits will be clear. So use this information to detect the problem | |
61 | * rather than polling the Link Training bit and watching out for flips or | |
62 | * at least the active status. | |
63 | * | |
64 | * Since the exact nature of the problem isn't known and in principle this | |
65 | * could trigger where an ASM2824 device is downstream rather upstream, | |
66 | * apply this erratum workaround to any downstream ports as long as they | |
67 | * support Link Active reporting and have the Link Control 2 register. | |
68 | * Restrict the speed to 2.5GT/s then with the Target Link Speed field, | |
69 | * request a retrain and wait 200ms for the data link to go up. | |
70 | * | |
71 | * If this turns out successful and we know by the Vendor:Device ID it is | |
72 | * safe to do so, then lift the restriction, letting the devices negotiate | |
73 | * a higher speed. Also check for a similar 2.5GT/s speed restriction the | |
74 | * firmware may have already arranged and lift it with ports that already | |
75 | * report their data link being up. | |
76 | * | |
77 | * Return TRUE if the link has been successfully retrained, otherwise FALSE. | |
78 | */ | |
79 | bool pcie_failed_link_retrain(struct pci_dev *dev) | |
80 | { | |
81 | static const struct pci_device_id ids[] = { | |
82 | { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ | |
83 | {} | |
84 | }; | |
85 | u16 lnksta, lnkctl2; | |
86 | ||
87 | if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || | |
88 | !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) | |
89 | return false; | |
90 | ||
91 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); | |
92 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
93 | if ((lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) == | |
94 | PCI_EXP_LNKSTA_LBMS) { | |
95 | pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); | |
96 | ||
97 | lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; | |
98 | lnkctl2 |= PCI_EXP_LNKCTL2_TLS_2_5GT; | |
99 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); | |
100 | ||
1abb4739 | 101 | if (pcie_retrain_link(dev, false)) { |
a89c8224 MR |
102 | pci_info(dev, "retraining failed\n"); |
103 | return false; | |
104 | } | |
105 | ||
106 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
107 | } | |
108 | ||
109 | if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && | |
110 | (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && | |
111 | pci_match_id(ids, dev)) { | |
112 | u32 lnkcap; | |
113 | ||
114 | pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); | |
115 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
116 | lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; | |
117 | lnkctl2 |= lnkcap & PCI_EXP_LNKCAP_SLS; | |
118 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); | |
119 | ||
1abb4739 | 120 | if (pcie_retrain_link(dev, false)) { |
a89c8224 MR |
121 | pci_info(dev, "retraining failed\n"); |
122 | return false; | |
123 | } | |
124 | } | |
125 | ||
126 | return true; | |
127 | } | |
128 | ||
78047350 BH |
129 | static ktime_t fixup_debug_start(struct pci_dev *dev, |
130 | void (*fn)(struct pci_dev *dev)) | |
131 | { | |
132 | if (initcall_debug) | |
d75f773c | 133 | pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); |
78047350 BH |
134 | |
135 | return ktime_get(); | |
136 | } | |
137 | ||
138 | static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, | |
139 | void (*fn)(struct pci_dev *dev)) | |
140 | { | |
141 | ktime_t delta, rettime; | |
142 | unsigned long long duration; | |
143 | ||
144 | rettime = ktime_get(); | |
145 | delta = ktime_sub(rettime, calltime); | |
146 | duration = (unsigned long long) ktime_to_ns(delta) >> 10; | |
147 | if (initcall_debug || duration > 10000) | |
d75f773c | 148 | pci_info(dev, "%pS took %lld usecs\n", fn, duration); |
78047350 BH |
149 | } |
150 | ||
151 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, | |
152 | struct pci_fixup *end) | |
153 | { | |
154 | ktime_t calltime; | |
155 | ||
156 | for (; f < end; f++) | |
157 | if ((f->class == (u32) (dev->class >> f->class_shift) || | |
158 | f->class == (u32) PCI_ANY_ID) && | |
159 | (f->vendor == dev->vendor || | |
160 | f->vendor == (u16) PCI_ANY_ID) && | |
161 | (f->device == dev->device || | |
162 | f->device == (u16) PCI_ANY_ID)) { | |
c9d8b55f AB |
163 | void (*hook)(struct pci_dev *dev); |
164 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS | |
165 | hook = offset_to_ptr(&f->hook_offset); | |
166 | #else | |
167 | hook = f->hook; | |
168 | #endif | |
169 | calltime = fixup_debug_start(dev, hook); | |
170 | hook(dev); | |
171 | fixup_debug_report(dev, calltime, hook); | |
78047350 BH |
172 | } |
173 | } | |
174 | ||
175 | extern struct pci_fixup __start_pci_fixups_early[]; | |
176 | extern struct pci_fixup __end_pci_fixups_early[]; | |
177 | extern struct pci_fixup __start_pci_fixups_header[]; | |
178 | extern struct pci_fixup __end_pci_fixups_header[]; | |
179 | extern struct pci_fixup __start_pci_fixups_final[]; | |
180 | extern struct pci_fixup __end_pci_fixups_final[]; | |
181 | extern struct pci_fixup __start_pci_fixups_enable[]; | |
182 | extern struct pci_fixup __end_pci_fixups_enable[]; | |
183 | extern struct pci_fixup __start_pci_fixups_resume[]; | |
184 | extern struct pci_fixup __end_pci_fixups_resume[]; | |
185 | extern struct pci_fixup __start_pci_fixups_resume_early[]; | |
186 | extern struct pci_fixup __end_pci_fixups_resume_early[]; | |
187 | extern struct pci_fixup __start_pci_fixups_suspend[]; | |
188 | extern struct pci_fixup __end_pci_fixups_suspend[]; | |
189 | extern struct pci_fixup __start_pci_fixups_suspend_late[]; | |
190 | extern struct pci_fixup __end_pci_fixups_suspend_late[]; | |
191 | ||
192 | static bool pci_apply_fixup_final_quirks; | |
193 | ||
194 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) | |
195 | { | |
196 | struct pci_fixup *start, *end; | |
197 | ||
198 | switch (pass) { | |
199 | case pci_fixup_early: | |
200 | start = __start_pci_fixups_early; | |
201 | end = __end_pci_fixups_early; | |
202 | break; | |
203 | ||
204 | case pci_fixup_header: | |
205 | start = __start_pci_fixups_header; | |
206 | end = __end_pci_fixups_header; | |
207 | break; | |
208 | ||
209 | case pci_fixup_final: | |
210 | if (!pci_apply_fixup_final_quirks) | |
211 | return; | |
212 | start = __start_pci_fixups_final; | |
213 | end = __end_pci_fixups_final; | |
214 | break; | |
215 | ||
216 | case pci_fixup_enable: | |
217 | start = __start_pci_fixups_enable; | |
218 | end = __end_pci_fixups_enable; | |
219 | break; | |
220 | ||
221 | case pci_fixup_resume: | |
222 | start = __start_pci_fixups_resume; | |
223 | end = __end_pci_fixups_resume; | |
224 | break; | |
225 | ||
226 | case pci_fixup_resume_early: | |
227 | start = __start_pci_fixups_resume_early; | |
228 | end = __end_pci_fixups_resume_early; | |
229 | break; | |
230 | ||
231 | case pci_fixup_suspend: | |
232 | start = __start_pci_fixups_suspend; | |
233 | end = __end_pci_fixups_suspend; | |
234 | break; | |
235 | ||
236 | case pci_fixup_suspend_late: | |
237 | start = __start_pci_fixups_suspend_late; | |
238 | end = __end_pci_fixups_suspend_late; | |
239 | break; | |
240 | ||
241 | default: | |
242 | /* stupid compiler warning, you would think with an enum... */ | |
243 | return; | |
244 | } | |
245 | pci_do_fixups(dev, start, end); | |
246 | } | |
247 | EXPORT_SYMBOL(pci_fixup_device); | |
248 | ||
249 | static int __init pci_apply_final_quirks(void) | |
250 | { | |
251 | struct pci_dev *dev = NULL; | |
252 | u8 cls = 0; | |
253 | u8 tmp; | |
254 | ||
255 | if (pci_cache_line_size) | |
34c6b710 | 256 | pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); |
78047350 BH |
257 | |
258 | pci_apply_fixup_final_quirks = true; | |
259 | for_each_pci_dev(dev) { | |
260 | pci_fixup_device(pci_fixup_final, dev); | |
261 | /* | |
262 | * If arch hasn't set it explicitly yet, use the CLS | |
263 | * value shared by all PCI devices. If there's a | |
264 | * mismatch, fall back to the default value. | |
265 | */ | |
266 | if (!pci_cache_line_size) { | |
267 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); | |
268 | if (!cls) | |
269 | cls = tmp; | |
270 | if (!tmp || cls == tmp) | |
271 | continue; | |
272 | ||
34c6b710 MK |
273 | pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", |
274 | cls << 2, tmp << 2, | |
275 | pci_dfl_cache_line_size << 2); | |
78047350 BH |
276 | pci_cache_line_size = pci_dfl_cache_line_size; |
277 | } | |
278 | } | |
279 | ||
280 | if (!pci_cache_line_size) { | |
34c6b710 MK |
281 | pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, |
282 | pci_dfl_cache_line_size << 2); | |
78047350 BH |
283 | pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; |
284 | } | |
285 | ||
286 | return 0; | |
287 | } | |
288 | fs_initcall_sync(pci_apply_final_quirks); | |
289 | ||
253d2e54 JP |
290 | /* |
291 | * Decoding should be disabled for a PCI device during BAR sizing to avoid | |
292 | * conflict. But doing so may cause problems on host bridge and perhaps other | |
293 | * key system devices. For devices that need to have mmio decoding always-on, | |
294 | * we need to set the dev->mmio_always_on bit. | |
295 | */ | |
15856ad5 | 296 | static void quirk_mmio_always_on(struct pci_dev *dev) |
253d2e54 | 297 | { |
52d21b5e | 298 | dev->mmio_always_on = 1; |
253d2e54 | 299 | } |
52d21b5e YL |
300 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, |
301 | PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); | |
253d2e54 | 302 | |
82e1719c | 303 | /* |
d06a113f HK |
304 | * The Mellanox Tavor device gives false positive parity errors. Disable |
305 | * parity error reporting. | |
bd8481e1 | 306 | */ |
d06a113f HK |
307 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); |
308 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); | |
bd8481e1 | 309 | |
82e1719c BH |
310 | /* |
311 | * Deal with broken BIOSes that neglect to enable passive release, | |
312 | * which can cause problems in combination with the 82441FX/PPro MTRRs | |
313 | */ | |
1597cacb | 314 | static void quirk_passive_release(struct pci_dev *dev) |
1da177e4 LT |
315 | { |
316 | struct pci_dev *d = NULL; | |
317 | unsigned char dlc; | |
318 | ||
82e1719c BH |
319 | /* |
320 | * We have to make sure a particular bit is set in the PIIX3 | |
321 | * ISA bridge, so we have to go out and find it. | |
322 | */ | |
1da177e4 LT |
323 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { |
324 | pci_read_config_byte(d, 0x82, &dlc); | |
325 | if (!(dlc & 1<<1)) { | |
7506dc79 | 326 | pci_info(d, "PIIX3: Enabling Passive Release\n"); |
1da177e4 LT |
327 | dlc |= 1<<1; |
328 | pci_write_config_byte(d, 0x82, dlc); | |
329 | } | |
330 | } | |
331 | } | |
652c538e AM |
332 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
333 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); | |
1da177e4 | 334 | |
abb4970a | 335 | #ifdef CONFIG_X86_32 |
82e1719c BH |
336 | /* |
337 | * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a | |
338 | * workaround but VIA don't answer queries. If you happen to have good | |
339 | * contacts at VIA ask them for me please -- Alan | |
340 | * | |
341 | * This appears to be BIOS not version dependent. So presumably there is a | |
342 | * chipset level fix. | |
343 | */ | |
15856ad5 | 344 | static void quirk_isa_dma_hangs(struct pci_dev *dev) |
1da177e4 LT |
345 | { |
346 | if (!isa_dma_bridge_buggy) { | |
3c78bc61 | 347 | isa_dma_bridge_buggy = 1; |
7506dc79 | 348 | pci_info(dev, "Activating ISA DMA hang workarounds\n"); |
1da177e4 LT |
349 | } |
350 | } | |
82e1719c BH |
351 | /* |
352 | * It's not totally clear which chipsets are the problematic ones. We know | |
353 | * 82C586 and 82C596 variants are affected. | |
354 | */ | |
652c538e AM |
355 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); |
356 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); | |
357 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); | |
f7625980 | 358 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); |
652c538e AM |
359 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); |
360 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); | |
361 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); | |
abb4970a | 362 | #endif |
1da177e4 | 363 | |
f768c75d | 364 | #ifdef CONFIG_HAS_IOPORT |
4731fdcf | 365 | /* |
86b4ad7d | 366 | * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear |
4731fdcf LB |
367 | * for some HT machines to use C4 w/o hanging. |
368 | */ | |
15856ad5 | 369 | static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) |
4731fdcf LB |
370 | { |
371 | u32 pmbase; | |
372 | u16 pm1a; | |
373 | ||
374 | pci_read_config_dword(dev, 0x40, &pmbase); | |
375 | pmbase = pmbase & 0xff80; | |
376 | pm1a = inw(pmbase); | |
377 | ||
378 | if (pm1a & 0x10) { | |
86b4ad7d | 379 | pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); |
4731fdcf LB |
380 | outw(0x10, pmbase); |
381 | } | |
382 | } | |
383 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); | |
f768c75d | 384 | #endif |
4731fdcf | 385 | |
82e1719c | 386 | /* Chipsets where PCI->PCI transfers vanish or hang */ |
15856ad5 | 387 | static void quirk_nopcipci(struct pci_dev *dev) |
1da177e4 | 388 | { |
3c78bc61 | 389 | if ((pci_pci_problems & PCIPCI_FAIL) == 0) { |
7506dc79 | 390 | pci_info(dev, "Disabling direct PCI/PCI transfers\n"); |
1da177e4 LT |
391 | pci_pci_problems |= PCIPCI_FAIL; |
392 | } | |
393 | } | |
652c538e AM |
394 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); |
395 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); | |
236561e5 | 396 | |
15856ad5 | 397 | static void quirk_nopciamd(struct pci_dev *dev) |
236561e5 AC |
398 | { |
399 | u8 rev; | |
400 | pci_read_config_byte(dev, 0x08, &rev); | |
401 | if (rev == 0x13) { | |
402 | /* Erratum 24 */ | |
7506dc79 | 403 | pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); |
236561e5 AC |
404 | pci_pci_problems |= PCIAGP_FAIL; |
405 | } | |
406 | } | |
652c538e | 407 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); |
1da177e4 | 408 | |
82e1719c | 409 | /* Triton requires workarounds to be used by the drivers */ |
15856ad5 | 410 | static void quirk_triton(struct pci_dev *dev) |
1da177e4 | 411 | { |
3c78bc61 | 412 | if ((pci_pci_problems&PCIPCI_TRITON) == 0) { |
7506dc79 | 413 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
414 | pci_pci_problems |= PCIPCI_TRITON; |
415 | } | |
416 | } | |
f7625980 BH |
417 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); |
418 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); | |
419 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); | |
420 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); | |
1da177e4 LT |
421 | |
422 | /* | |
82e1719c BH |
423 | * VIA Apollo KT133 needs PCI latency patch |
424 | * Made according to a Windows driver-based patch by George E. Breese; | |
425 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm | |
426 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on | |
427 | * which Mr Breese based his work. | |
1da177e4 | 428 | * |
82e1719c BH |
429 | * Updated based on further information from the site and also on |
430 | * information provided by VIA | |
1da177e4 | 431 | */ |
1597cacb | 432 | static void quirk_vialatency(struct pci_dev *dev) |
1da177e4 LT |
433 | { |
434 | struct pci_dev *p; | |
1da177e4 | 435 | u8 busarb; |
f7625980 | 436 | |
82e1719c BH |
437 | /* |
438 | * Ok, we have a potential problem chipset here. Now see if we have | |
439 | * a buggy southbridge. | |
440 | */ | |
1da177e4 | 441 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); |
3c78bc61 | 442 | if (p != NULL) { |
82e1719c BH |
443 | |
444 | /* | |
445 | * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; | |
446 | * thanks Dan Hollis. | |
447 | * Check for buggy part revisions | |
448 | */ | |
2b1afa87 | 449 | if (p->revision < 0x40 || p->revision > 0x42) |
1da177e4 LT |
450 | goto exit; |
451 | } else { | |
452 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); | |
3c78bc61 | 453 | if (p == NULL) /* No problem parts */ |
1da177e4 | 454 | goto exit; |
82e1719c | 455 | |
1da177e4 | 456 | /* Check for buggy part revisions */ |
2b1afa87 | 457 | if (p->revision < 0x10 || p->revision > 0x12) |
1da177e4 LT |
458 | goto exit; |
459 | } | |
f7625980 | 460 | |
1da177e4 | 461 | /* |
82e1719c BH |
462 | * Ok we have the problem. Now set the PCI master grant to occur |
463 | * every master grant. The apparent bug is that under high PCI load | |
464 | * (quite common in Linux of course) you can get data loss when the | |
465 | * CPU is held off the bus for 3 bus master requests. This happens | |
466 | * to include the IDE controllers.... | |
1da177e4 | 467 | * |
82e1719c BH |
468 | * VIA only apply this fix when an SB Live! is present but under |
469 | * both Linux and Windows this isn't enough, and we have seen | |
470 | * corruption without SB Live! but with things like 3 UDMA IDE | |
471 | * controllers. So we ignore that bit of the VIA recommendation.. | |
1da177e4 | 472 | */ |
1da177e4 | 473 | pci_read_config_byte(dev, 0x76, &busarb); |
82e1719c BH |
474 | |
475 | /* | |
476 | * Set bit 4 and bit 5 of byte 76 to 0x01 | |
477 | * "Master priority rotation on every PCI master grant" | |
478 | */ | |
1da177e4 LT |
479 | busarb &= ~(1<<5); |
480 | busarb |= (1<<4); | |
481 | pci_write_config_byte(dev, 0x76, busarb); | |
7506dc79 | 482 | pci_info(dev, "Applying VIA southbridge workaround\n"); |
1da177e4 LT |
483 | exit: |
484 | pci_dev_put(p); | |
485 | } | |
652c538e AM |
486 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
487 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
488 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1597cacb | 489 | /* Must restore this on a resume from RAM */ |
652c538e AM |
490 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
491 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
492 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1da177e4 | 493 | |
82e1719c | 494 | /* VIA Apollo VP3 needs ETBF on BT848/878 */ |
15856ad5 | 495 | static void quirk_viaetbf(struct pci_dev *dev) |
1da177e4 | 496 | { |
3c78bc61 | 497 | if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { |
7506dc79 | 498 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
499 | pci_pci_problems |= PCIPCI_VIAETBF; |
500 | } | |
501 | } | |
652c538e | 502 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); |
1da177e4 | 503 | |
15856ad5 | 504 | static void quirk_vsfx(struct pci_dev *dev) |
1da177e4 | 505 | { |
3c78bc61 | 506 | if ((pci_pci_problems&PCIPCI_VSFX) == 0) { |
7506dc79 | 507 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
508 | pci_pci_problems |= PCIPCI_VSFX; |
509 | } | |
510 | } | |
652c538e | 511 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); |
1da177e4 LT |
512 | |
513 | /* | |
82e1719c BH |
514 | * ALi Magik requires workarounds to be used by the drivers that DMA to AGP |
515 | * space. Latency must be set to 0xA and Triton workaround applied too. | |
516 | * [Info kindly provided by ALi] | |
f7625980 | 517 | */ |
15856ad5 | 518 | static void quirk_alimagik(struct pci_dev *dev) |
1da177e4 | 519 | { |
3c78bc61 | 520 | if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { |
7506dc79 | 521 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
522 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
523 | } | |
524 | } | |
f7625980 BH |
525 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); |
526 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); | |
1da177e4 | 527 | |
82e1719c | 528 | /* Natoma has some interesting boundary conditions with Zoran stuff at least */ |
15856ad5 | 529 | static void quirk_natoma(struct pci_dev *dev) |
1da177e4 | 530 | { |
3c78bc61 | 531 | if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { |
7506dc79 | 532 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
533 | pci_pci_problems |= PCIPCI_NATOMA; |
534 | } | |
535 | } | |
f7625980 BH |
536 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); |
537 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); | |
538 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); | |
539 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); | |
540 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); | |
541 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); | |
1da177e4 LT |
542 | |
543 | /* | |
82e1719c BH |
544 | * This chip can cause PCI parity errors if config register 0xA0 is read |
545 | * while DMAs are occurring. | |
1da177e4 | 546 | */ |
15856ad5 | 547 | static void quirk_citrine(struct pci_dev *dev) |
1da177e4 LT |
548 | { |
549 | dev->cfg_size = 0xA0; | |
550 | } | |
652c538e | 551 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); |
1da177e4 | 552 | |
9f33a2ae JM |
553 | /* |
554 | * This chip can cause bus lockups if config addresses above 0x600 | |
555 | * are read or written. | |
556 | */ | |
557 | static void quirk_nfp6000(struct pci_dev *dev) | |
558 | { | |
559 | dev->cfg_size = 0x600; | |
560 | } | |
c2e771b0 | 561 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); |
9f33a2ae | 562 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); |
2538fb89 | 563 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); |
9f33a2ae JM |
564 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); |
565 | ||
9fe373f9 DL |
566 | /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ |
567 | static void quirk_extend_bar_to_page(struct pci_dev *dev) | |
568 | { | |
569 | int i; | |
570 | ||
c9c13ba4 | 571 | for (i = 0; i < PCI_STD_NUM_BARS; i++) { |
9fe373f9 DL |
572 | struct resource *r = &dev->resource[i]; |
573 | ||
574 | if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { | |
575 | r->end = PAGE_SIZE - 1; | |
576 | r->start = 0; | |
577 | r->flags |= IORESOURCE_UNSET; | |
7506dc79 | 578 | pci_info(dev, "expanded BAR %d to page size: %pR\n", |
9fe373f9 DL |
579 | i, r); |
580 | } | |
581 | } | |
582 | } | |
583 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); | |
584 | ||
1da177e4 | 585 | /* |
82e1719c BH |
586 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. |
587 | * If it's needed, re-allocate the region. | |
1da177e4 | 588 | */ |
15856ad5 | 589 | static void quirk_s3_64M(struct pci_dev *dev) |
1da177e4 LT |
590 | { |
591 | struct resource *r = &dev->resource[0]; | |
592 | ||
593 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { | |
bd064f0a | 594 | r->flags |= IORESOURCE_UNSET; |
1da177e4 LT |
595 | r->start = 0; |
596 | r->end = 0x3ffffff; | |
597 | } | |
598 | } | |
652c538e AM |
599 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); |
600 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); | |
1da177e4 | 601 | |
fd1ae23b | 602 | static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, |
06cf35f9 MS |
603 | const char *name) |
604 | { | |
605 | u32 region; | |
606 | struct pci_bus_region bus_region; | |
607 | struct resource *res = dev->resource + pos; | |
608 | ||
609 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); | |
610 | ||
611 | if (!region) | |
612 | return; | |
613 | ||
614 | res->name = pci_name(dev); | |
615 | res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; | |
616 | res->flags |= | |
617 | (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); | |
618 | region &= ~(size - 1); | |
619 | ||
620 | /* Convert from PCI bus to resource space */ | |
621 | bus_region.start = region; | |
622 | bus_region.end = region + size - 1; | |
623 | pcibios_bus_to_resource(dev->bus, res, &bus_region); | |
624 | ||
7506dc79 | 625 | pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", |
06cf35f9 MS |
626 | name, PCI_BASE_ADDRESS_0 + (pos << 2), res); |
627 | } | |
628 | ||
73d2eaac AS |
629 | /* |
630 | * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS | |
631 | * ver. 1.33 20070103) don't set the correct ISA PCI region header info. | |
632 | * BAR0 should be 8 bytes; instead, it may be set to something like 8k | |
633 | * (which conflicts w/ BAR1's memory range). | |
06cf35f9 MS |
634 | * |
635 | * CS553x's ISA PCI BARs may also be read-only (ref: | |
636 | * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). | |
73d2eaac | 637 | */ |
15856ad5 | 638 | static void quirk_cs5536_vsa(struct pci_dev *dev) |
73d2eaac | 639 | { |
06cf35f9 MS |
640 | static char *name = "CS5536 ISA bridge"; |
641 | ||
73d2eaac | 642 | if (pci_resource_len(dev, 0) != 8) { |
06cf35f9 MS |
643 | quirk_io(dev, 0, 8, name); /* SMB */ |
644 | quirk_io(dev, 1, 256, name); /* GPIO */ | |
645 | quirk_io(dev, 2, 64, name); /* MFGPT */ | |
7506dc79 | 646 | pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", |
06cf35f9 | 647 | name); |
73d2eaac AS |
648 | } |
649 | } | |
650 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); | |
651 | ||
65195c76 | 652 | static void quirk_io_region(struct pci_dev *dev, int port, |
fd1ae23b | 653 | unsigned int size, int nr, const char *name) |
65195c76 YL |
654 | { |
655 | u16 region; | |
656 | struct pci_bus_region bus_region; | |
657 | struct resource *res = dev->resource + nr; | |
658 | ||
659 | pci_read_config_word(dev, port, ®ion); | |
660 | region &= ~(size - 1); | |
661 | ||
662 | if (!region) | |
663 | return; | |
664 | ||
665 | res->name = pci_name(dev); | |
666 | res->flags = IORESOURCE_IO; | |
667 | ||
668 | /* Convert from PCI bus to resource space */ | |
669 | bus_region.start = region; | |
670 | bus_region.end = region + size - 1; | |
fc279850 | 671 | pcibios_bus_to_resource(dev->bus, res, &bus_region); |
65195c76 YL |
672 | |
673 | if (!pci_claim_resource(dev, nr)) | |
7506dc79 | 674 | pci_info(dev, "quirk: %pR claimed by %s\n", res, name); |
65195c76 | 675 | } |
1da177e4 LT |
676 | |
677 | /* | |
82e1719c BH |
678 | * ATI Northbridge setups MCE the processor if you even read somewhere |
679 | * between 0x3b0->0x3bb or read 0x3d3 | |
1da177e4 | 680 | */ |
15856ad5 | 681 | static void quirk_ati_exploding_mce(struct pci_dev *dev) |
1da177e4 | 682 | { |
7506dc79 | 683 | pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); |
1da177e4 LT |
684 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
685 | request_region(0x3b0, 0x0C, "RadeonIGP"); | |
686 | request_region(0x3d3, 0x01, "RadeonIGP"); | |
687 | } | |
652c538e | 688 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); |
1da177e4 | 689 | |
be6646bf HR |
690 | /* |
691 | * In the AMD NL platform, this device ([1022:7912]) has a class code of | |
692 | * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will | |
693 | * claim it. | |
82e1719c | 694 | * |
be6646bf HR |
695 | * But the dwc3 driver is a more specific driver for this device, and we'd |
696 | * prefer to use it instead of xhci. To prevent xhci from claiming the | |
697 | * device, change the class code to 0x0c03fe, which the PCI r3.0 spec | |
698 | * defines as "USB device (not host controller)". The dwc3 driver can then | |
699 | * claim it based on its Vendor and Device ID. | |
700 | */ | |
701 | static void quirk_amd_nl_class(struct pci_dev *pdev) | |
702 | { | |
cd76d10b BH |
703 | u32 class = pdev->class; |
704 | ||
705 | /* Use "USB Device (not host controller)" class */ | |
7b78f48a | 706 | pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; |
7506dc79 | 707 | pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", |
cd76d10b | 708 | class, pdev->class); |
be6646bf HR |
709 | } |
710 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, | |
711 | quirk_amd_nl_class); | |
712 | ||
03e67425 TN |
713 | /* |
714 | * Synopsys USB 3.x host HAPS platform has a class code of | |
715 | * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these | |
716 | * devices should use dwc3-haps driver. Change these devices' class code to | |
717 | * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming | |
718 | * them. | |
719 | */ | |
720 | static void quirk_synopsys_haps(struct pci_dev *pdev) | |
721 | { | |
722 | u32 class = pdev->class; | |
723 | ||
724 | switch (pdev->device) { | |
725 | case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: | |
726 | case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: | |
727 | case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: | |
728 | pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; | |
729 | pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", | |
730 | class, pdev->class); | |
731 | break; | |
732 | } | |
733 | } | |
f57a98e1 TN |
734 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, |
735 | PCI_CLASS_SERIAL_USB_XHCI, 0, | |
736 | quirk_synopsys_haps); | |
03e67425 | 737 | |
1da177e4 | 738 | /* |
82e1719c BH |
739 | * Let's make the southbridge information explicit instead of having to |
740 | * worry about people probing the ACPI areas, for example.. (Yes, it | |
741 | * happens, and if you read the wrong ACPI register it will put the machine | |
742 | * to sleep with no way of waking it up again. Bummer). | |
1da177e4 LT |
743 | * |
744 | * ALI M7101: Two IO regions pointed to by words at | |
745 | * 0xE0 (64 bytes of ACPI registers) | |
746 | * 0xE2 (32 bytes of SMB registers) | |
747 | */ | |
15856ad5 | 748 | static void quirk_ali7101_acpi(struct pci_dev *dev) |
1da177e4 | 749 | { |
65195c76 YL |
750 | quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
751 | quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); | |
1da177e4 | 752 | } |
652c538e | 753 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); |
1da177e4 | 754 | |
6693e74a LT |
755 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
756 | { | |
757 | u32 devres; | |
758 | u32 mask, size, base; | |
759 | ||
760 | pci_read_config_dword(dev, port, &devres); | |
761 | if ((devres & enable) != enable) | |
762 | return; | |
763 | mask = (devres >> 16) & 15; | |
764 | base = devres & 0xffff; | |
765 | size = 16; | |
766 | for (;;) { | |
fd1ae23b | 767 | unsigned int bit = size >> 1; |
6693e74a LT |
768 | if ((bit & mask) == bit) |
769 | break; | |
770 | size = bit; | |
771 | } | |
772 | /* | |
773 | * For now we only print it out. Eventually we'll want to | |
774 | * reserve it (at least if it's in the 0x1000+ range), but | |
f7625980 | 775 | * let's get enough confirmation reports first. |
6693e74a LT |
776 | */ |
777 | base &= -size; | |
7506dc79 | 778 | pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); |
6693e74a LT |
779 | } |
780 | ||
781 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) | |
782 | { | |
783 | u32 devres; | |
784 | u32 mask, size, base; | |
785 | ||
786 | pci_read_config_dword(dev, port, &devres); | |
787 | if ((devres & enable) != enable) | |
788 | return; | |
789 | base = devres & 0xffff0000; | |
790 | mask = (devres & 0x3f) << 16; | |
791 | size = 128 << 16; | |
792 | for (;;) { | |
fd1ae23b | 793 | unsigned int bit = size >> 1; |
6693e74a LT |
794 | if ((bit & mask) == bit) |
795 | break; | |
796 | size = bit; | |
797 | } | |
82e1719c | 798 | |
6693e74a LT |
799 | /* |
800 | * For now we only print it out. Eventually we'll want to | |
f7625980 | 801 | * reserve it, but let's get enough confirmation reports first. |
6693e74a LT |
802 | */ |
803 | base &= -size; | |
7506dc79 | 804 | pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); |
6693e74a LT |
805 | } |
806 | ||
1da177e4 LT |
807 | /* |
808 | * PIIX4 ACPI: Two IO regions pointed to by longwords at | |
809 | * 0x40 (64 bytes of ACPI registers) | |
08db2a70 | 810 | * 0x90 (16 bytes of SMB registers) |
6693e74a | 811 | * and a few strange programmable PIIX4 device resources. |
1da177e4 | 812 | */ |
15856ad5 | 813 | static void quirk_piix4_acpi(struct pci_dev *dev) |
1da177e4 | 814 | { |
65195c76 | 815 | u32 res_a; |
1da177e4 | 816 | |
65195c76 YL |
817 | quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
818 | quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); | |
6693e74a LT |
819 | |
820 | /* Device resource A has enables for some of the other ones */ | |
821 | pci_read_config_dword(dev, 0x5c, &res_a); | |
822 | ||
823 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); | |
824 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); | |
825 | ||
826 | /* Device resource D is just bitfields for static resources */ | |
827 | ||
828 | /* Device 12 enabled? */ | |
829 | if (res_a & (1 << 29)) { | |
830 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); | |
831 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); | |
832 | } | |
833 | /* Device 13 enabled? */ | |
834 | if (res_a & (1 << 30)) { | |
835 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); | |
836 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); | |
837 | } | |
838 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); | |
839 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); | |
1da177e4 | 840 | } |
652c538e AM |
841 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); |
842 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); | |
1da177e4 | 843 | |
cdb97558 JS |
844 | #define ICH_PMBASE 0x40 |
845 | #define ICH_ACPI_CNTL 0x44 | |
846 | #define ICH4_ACPI_EN 0x10 | |
847 | #define ICH6_ACPI_EN 0x80 | |
848 | #define ICH4_GPIOBASE 0x58 | |
849 | #define ICH4_GPIO_CNTL 0x5c | |
850 | #define ICH4_GPIO_EN 0x10 | |
851 | #define ICH6_GPIOBASE 0x48 | |
852 | #define ICH6_GPIO_CNTL 0x4c | |
853 | #define ICH6_GPIO_EN 0x10 | |
854 | ||
1da177e4 LT |
855 | /* |
856 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at | |
857 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) | |
858 | * 0x58 (64 bytes of GPIO I/O space) | |
859 | */ | |
15856ad5 | 860 | static void quirk_ich4_lpc_acpi(struct pci_dev *dev) |
1da177e4 | 861 | { |
cdb97558 | 862 | u8 enable; |
1da177e4 | 863 | |
87e3dc38 JS |
864 | /* |
865 | * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict | |
866 | * with low legacy (and fixed) ports. We don't know the decoding | |
867 | * priority and can't tell whether the legacy device or the one created | |
868 | * here is really at that address. This happens on boards with broken | |
869 | * BIOSes. | |
82e1719c | 870 | */ |
cdb97558 | 871 | pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); |
65195c76 YL |
872 | if (enable & ICH4_ACPI_EN) |
873 | quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, | |
874 | "ICH4 ACPI/GPIO/TCO"); | |
1da177e4 | 875 | |
cdb97558 | 876 | pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); |
65195c76 YL |
877 | if (enable & ICH4_GPIO_EN) |
878 | quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, | |
879 | "ICH4 GPIO"); | |
1da177e4 | 880 | } |
652c538e AM |
881 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); |
882 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); | |
883 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); | |
884 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); | |
885 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); | |
886 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); | |
887 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); | |
888 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); | |
889 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); | |
890 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); | |
1da177e4 | 891 | |
15856ad5 | 892 | static void ich6_lpc_acpi_gpio(struct pci_dev *dev) |
2cea752f | 893 | { |
cdb97558 | 894 | u8 enable; |
2cea752f | 895 | |
cdb97558 | 896 | pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); |
65195c76 YL |
897 | if (enable & ICH6_ACPI_EN) |
898 | quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, | |
899 | "ICH6 ACPI/GPIO/TCO"); | |
2cea752f | 900 | |
cdb97558 | 901 | pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); |
65195c76 YL |
902 | if (enable & ICH6_GPIO_EN) |
903 | quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, | |
904 | "ICH6 GPIO"); | |
2cea752f | 905 | } |
894886e5 | 906 | |
fd1ae23b | 907 | static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, |
82e1719c | 908 | const char *name, int dynsize) |
894886e5 LT |
909 | { |
910 | u32 val; | |
911 | u32 size, base; | |
912 | ||
913 | pci_read_config_dword(dev, reg, &val); | |
914 | ||
915 | /* Enabled? */ | |
916 | if (!(val & 1)) | |
917 | return; | |
918 | base = val & 0xfffc; | |
919 | if (dynsize) { | |
920 | /* | |
921 | * This is not correct. It is 16, 32 or 64 bytes depending on | |
922 | * register D31:F0:ADh bits 5:4. | |
923 | * | |
924 | * But this gets us at least _part_ of it. | |
925 | */ | |
926 | size = 16; | |
927 | } else { | |
928 | size = 128; | |
929 | } | |
930 | base &= ~(size-1); | |
931 | ||
82e1719c BH |
932 | /* |
933 | * Just print it out for now. We should reserve it after more | |
934 | * debugging. | |
935 | */ | |
7506dc79 | 936 | pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); |
894886e5 LT |
937 | } |
938 | ||
15856ad5 | 939 | static void quirk_ich6_lpc(struct pci_dev *dev) |
894886e5 LT |
940 | { |
941 | /* Shared ACPI/GPIO decode with all ICH6+ */ | |
942 | ich6_lpc_acpi_gpio(dev); | |
943 | ||
944 | /* ICH6-specific generic IO decode */ | |
945 | ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); | |
946 | ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); | |
947 | } | |
948 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); | |
949 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); | |
950 | ||
fd1ae23b | 951 | static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, |
82e1719c | 952 | const char *name) |
894886e5 LT |
953 | { |
954 | u32 val; | |
955 | u32 mask, base; | |
956 | ||
957 | pci_read_config_dword(dev, reg, &val); | |
958 | ||
959 | /* Enabled? */ | |
960 | if (!(val & 1)) | |
961 | return; | |
962 | ||
82e1719c | 963 | /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ |
894886e5 LT |
964 | base = val & 0xfffc; |
965 | mask = (val >> 16) & 0xfc; | |
966 | mask |= 3; | |
967 | ||
82e1719c BH |
968 | /* |
969 | * Just print it out for now. We should reserve it after more | |
970 | * debugging. | |
971 | */ | |
7506dc79 | 972 | pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); |
894886e5 LT |
973 | } |
974 | ||
975 | /* ICH7-10 has the same common LPC generic IO decode registers */ | |
15856ad5 | 976 | static void quirk_ich7_lpc(struct pci_dev *dev) |
894886e5 | 977 | { |
5d9c0a79 | 978 | /* We share the common ACPI/GPIO decode with ICH6 */ |
894886e5 LT |
979 | ich6_lpc_acpi_gpio(dev); |
980 | ||
981 | /* And have 4 ICH7+ generic decodes */ | |
982 | ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); | |
983 | ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); | |
984 | ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); | |
985 | ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); | |
986 | } | |
987 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); | |
988 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); | |
989 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); | |
990 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); | |
991 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); | |
992 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); | |
993 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); | |
994 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); | |
995 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); | |
996 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); | |
997 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); | |
998 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); | |
999 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); | |
2cea752f | 1000 | |
1da177e4 LT |
1001 | /* |
1002 | * VIA ACPI: One IO region pointed to by longword at | |
1003 | * 0x48 or 0x20 (256 bytes of ACPI registers) | |
1004 | */ | |
15856ad5 | 1005 | static void quirk_vt82c586_acpi(struct pci_dev *dev) |
1da177e4 | 1006 | { |
65195c76 YL |
1007 | if (dev->revision & 0x10) |
1008 | quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, | |
1009 | "vt82c586 ACPI"); | |
1da177e4 | 1010 | } |
652c538e | 1011 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); |
1da177e4 LT |
1012 | |
1013 | /* | |
1014 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at | |
1015 | * 0x48 (256 bytes of ACPI registers) | |
1016 | * 0x70 (128 bytes of hardware monitoring register) | |
1017 | * 0x90 (16 bytes of SMB registers) | |
1018 | */ | |
15856ad5 | 1019 | static void quirk_vt82c686_acpi(struct pci_dev *dev) |
1da177e4 | 1020 | { |
1da177e4 LT |
1021 | quirk_vt82c586_acpi(dev); |
1022 | ||
65195c76 YL |
1023 | quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, |
1024 | "vt82c686 HW-mon"); | |
1da177e4 | 1025 | |
65195c76 | 1026 | quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); |
1da177e4 | 1027 | } |
652c538e | 1028 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); |
1da177e4 | 1029 | |
6d85f29b IK |
1030 | /* |
1031 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at | |
1032 | * 0x88 (128 bytes of power management registers) | |
1033 | * 0xd0 (16 bytes of SMB registers) | |
1034 | */ | |
15856ad5 | 1035 | static void quirk_vt8235_acpi(struct pci_dev *dev) |
6d85f29b | 1036 | { |
65195c76 YL |
1037 | quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
1038 | quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); | |
6d85f29b IK |
1039 | } |
1040 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); | |
1041 | ||
1f56f4a2 | 1042 | /* |
82e1719c BH |
1043 | * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast |
1044 | * back-to-back: Disable fast back-to-back on the secondary bus segment | |
1f56f4a2 | 1045 | */ |
15856ad5 | 1046 | static void quirk_xio2000a(struct pci_dev *dev) |
1f56f4a2 GB |
1047 | { |
1048 | struct pci_dev *pdev; | |
1049 | u16 command; | |
1050 | ||
7506dc79 | 1051 | pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); |
1f56f4a2 GB |
1052 | list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { |
1053 | pci_read_config_word(pdev, PCI_COMMAND, &command); | |
1054 | if (command & PCI_COMMAND_FAST_BACK) | |
1055 | pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); | |
1056 | } | |
1057 | } | |
1058 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, | |
1059 | quirk_xio2000a); | |
1da177e4 | 1060 | |
f7625980 | 1061 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
1062 | |
1063 | #include <asm/io_apic.h> | |
1064 | ||
1065 | /* | |
1066 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip | |
1067 | * devices to the external APIC. | |
1068 | * | |
82e1719c BH |
1069 | * TODO: When we have device-specific interrupt routers, this code will go |
1070 | * away from quirks. | |
1da177e4 | 1071 | */ |
1597cacb | 1072 | static void quirk_via_ioapic(struct pci_dev *dev) |
1da177e4 LT |
1073 | { |
1074 | u8 tmp; | |
f7625980 | 1075 | |
1da177e4 LT |
1076 | if (nr_ioapics < 1) |
1077 | tmp = 0; /* nothing routed to external APIC */ | |
1078 | else | |
1079 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ | |
f7625980 | 1080 | |
ccd36795 KW |
1081 | pci_info(dev, "%s VIA external APIC routing\n", |
1082 | tmp ? "Enabling" : "Disabling"); | |
1da177e4 LT |
1083 | |
1084 | /* Offset 0x58: External APIC IRQ output control */ | |
3c78bc61 | 1085 | pci_write_config_byte(dev, 0x58, tmp); |
1da177e4 | 1086 | } |
652c538e | 1087 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
e1a2a51e | 1088 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
1da177e4 | 1089 | |
a1740913 | 1090 | /* |
f7625980 | 1091 | * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. |
a1740913 KW |
1092 | * This leads to doubled level interrupt rates. |
1093 | * Set this bit to get rid of cycle wastage. | |
1094 | * Otherwise uncritical. | |
1095 | */ | |
1597cacb | 1096 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
a1740913 KW |
1097 | { |
1098 | u8 misc_control2; | |
1099 | #define BYPASS_APIC_DEASSERT 8 | |
1100 | ||
1101 | pci_read_config_byte(dev, 0x5B, &misc_control2); | |
1102 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { | |
7506dc79 | 1103 | pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); |
a1740913 KW |
1104 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); |
1105 | } | |
1106 | } | |
1107 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); | |
e1a2a51e | 1108 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
a1740913 | 1109 | |
1da177e4 | 1110 | /* |
82e1719c | 1111 | * The AMD IO-APIC can hang the box when an APIC IRQ is masked. |
1da177e4 LT |
1112 | * We check all revs >= B0 (yet not in the pre production!) as the bug |
1113 | * is currently marked NoFix | |
1114 | * | |
1115 | * We have multiple reports of hangs with this chipset that went away with | |
236561e5 | 1116 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
82e1719c | 1117 | * of course. However the advice is demonstrably good even if so. |
1da177e4 | 1118 | */ |
15856ad5 | 1119 | static void quirk_amd_ioapic(struct pci_dev *dev) |
1da177e4 | 1120 | { |
44c10138 | 1121 | if (dev->revision >= 0x02) { |
7506dc79 FL |
1122 | pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
1123 | pci_warn(dev, " : booting with the \"noapic\" option\n"); | |
1da177e4 LT |
1124 | } |
1125 | } | |
652c538e | 1126 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); |
1da177e4 LT |
1127 | #endif /* CONFIG_X86_IO_APIC */ |
1128 | ||
0bec9057 | 1129 | #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) |
21b5b8ee AJ |
1130 | |
1131 | static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) | |
1132 | { | |
82e1719c | 1133 | /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ |
21b5b8ee AJ |
1134 | if (dev->subsystem_device == 0xa118) |
1135 | dev->sriov->link = dev->devfn; | |
1136 | } | |
1137 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); | |
1138 | #endif | |
1139 | ||
d556ad4b PO |
1140 | /* |
1141 | * Some settings of MMRBC can lead to data corruption so block changes. | |
1142 | * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide | |
1143 | */ | |
15856ad5 | 1144 | static void quirk_amd_8131_mmrbc(struct pci_dev *dev) |
d556ad4b | 1145 | { |
aa288d4d | 1146 | if (dev->subordinate && dev->revision <= 0x12) { |
7506dc79 | 1147 | pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", |
227f0647 | 1148 | dev->revision); |
d556ad4b PO |
1149 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; |
1150 | } | |
1151 | } | |
1152 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); | |
1da177e4 | 1153 | |
1da177e4 | 1154 | /* |
82e1719c BH |
1155 | * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up |
1156 | * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register | |
1157 | * at all. Therefore it seems like setting the pci_dev's IRQ to the value | |
1158 | * of the ACPI SCI interrupt is only done for convenience. | |
1da177e4 LT |
1159 | * -jgarzik |
1160 | */ | |
15856ad5 | 1161 | static void quirk_via_acpi(struct pci_dev *d) |
1da177e4 | 1162 | { |
1da177e4 | 1163 | u8 irq; |
82e1719c BH |
1164 | |
1165 | /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ | |
1da177e4 LT |
1166 | pci_read_config_byte(d, 0x42, &irq); |
1167 | irq &= 0xf; | |
1168 | if (irq && (irq != 2)) | |
1169 | d->irq = irq; | |
1170 | } | |
652c538e AM |
1171 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); |
1172 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); | |
1da177e4 | 1173 | |
82e1719c | 1174 | /* VIA bridges which have VLink */ |
c06bb5d4 JD |
1175 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
1176 | ||
1177 | static void quirk_via_bridge(struct pci_dev *dev) | |
1178 | { | |
1179 | /* See what bridge we have and find the device ranges */ | |
1180 | switch (dev->device) { | |
1181 | case PCI_DEVICE_ID_VIA_82C686: | |
82e1719c BH |
1182 | /* |
1183 | * The VT82C686 is special; it attaches to PCI and can have | |
1184 | * any device number. All its subdevices are functions of | |
1185 | * that single device. | |
1186 | */ | |
cb7468ef JD |
1187 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); |
1188 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); | |
c06bb5d4 JD |
1189 | break; |
1190 | case PCI_DEVICE_ID_VIA_8237: | |
1191 | case PCI_DEVICE_ID_VIA_8237A: | |
1192 | via_vlink_dev_lo = 15; | |
1193 | break; | |
1194 | case PCI_DEVICE_ID_VIA_8235: | |
1195 | via_vlink_dev_lo = 16; | |
1196 | break; | |
1197 | case PCI_DEVICE_ID_VIA_8231: | |
1198 | case PCI_DEVICE_ID_VIA_8233_0: | |
1199 | case PCI_DEVICE_ID_VIA_8233A: | |
1200 | case PCI_DEVICE_ID_VIA_8233C_0: | |
1201 | via_vlink_dev_lo = 17; | |
1202 | break; | |
1203 | } | |
1204 | } | |
1205 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); | |
1206 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); | |
1207 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); | |
1208 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); | |
1209 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); | |
1210 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); | |
1211 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); | |
1212 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); | |
09d6029f | 1213 | |
82e1719c BH |
1214 | /* |
1215 | * quirk_via_vlink - VIA VLink IRQ number update | |
1216 | * @dev: PCI device | |
1597cacb | 1217 | * |
82e1719c BH |
1218 | * If the device we are dealing with is on a PIC IRQ we need to ensure that |
1219 | * the IRQ line register which usually is not relevant for PCI cards, is | |
1220 | * actually written so that interrupts get sent to the right place. | |
1221 | * | |
1222 | * We only do this on systems where a VIA south bridge was detected, and | |
1223 | * only for VIA devices on the motherboard (see quirk_via_bridge above). | |
1597cacb | 1224 | */ |
1597cacb | 1225 | static void quirk_via_vlink(struct pci_dev *dev) |
25be5e6c LB |
1226 | { |
1227 | u8 irq, new_irq; | |
1228 | ||
c06bb5d4 JD |
1229 | /* Check if we have VLink at all */ |
1230 | if (via_vlink_dev_lo == -1) | |
09d6029f DD |
1231 | return; |
1232 | ||
1233 | new_irq = dev->irq; | |
1234 | ||
1235 | /* Don't quirk interrupts outside the legacy IRQ range */ | |
1236 | if (!new_irq || new_irq > 15) | |
1237 | return; | |
1238 | ||
1597cacb | 1239 | /* Internal device ? */ |
c06bb5d4 JD |
1240 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
1241 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) | |
1597cacb AC |
1242 | return; |
1243 | ||
82e1719c BH |
1244 | /* |
1245 | * This is an internal VLink device on a PIC interrupt. The BIOS | |
1246 | * ought to have set this but may not have, so we redo it. | |
1247 | */ | |
25be5e6c LB |
1248 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
1249 | if (new_irq != irq) { | |
7506dc79 | 1250 | pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", |
f0fda801 | 1251 | irq, new_irq); |
25be5e6c LB |
1252 | udelay(15); /* unknown if delay really needed */ |
1253 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); | |
1254 | } | |
1255 | } | |
1597cacb | 1256 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
25be5e6c | 1257 | |
1da177e4 | 1258 | /* |
82e1719c BH |
1259 | * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID |
1260 | * of VT82C597 for backward compatibility. We need to switch it off to be | |
1261 | * able to recognize the real type of the chip. | |
1da177e4 | 1262 | */ |
15856ad5 | 1263 | static void quirk_vt82c598_id(struct pci_dev *dev) |
1da177e4 LT |
1264 | { |
1265 | pci_write_config_byte(dev, 0xfc, 0); | |
1266 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); | |
1267 | } | |
652c538e | 1268 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); |
1da177e4 LT |
1269 | |
1270 | /* | |
82e1719c BH |
1271 | * CardBus controllers have a legacy base address that enables them to |
1272 | * respond as i82365 pcmcia controllers. We don't want them to do this | |
1273 | * even if the Linux CardBus driver is not loaded, because the Linux i82365 | |
1274 | * driver does not (and should not) handle CardBus. | |
1da177e4 | 1275 | */ |
1597cacb | 1276 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
1da177e4 | 1277 | { |
1da177e4 LT |
1278 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); |
1279 | } | |
ae9de56b YL |
1280 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, |
1281 | PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); | |
1282 | DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, | |
1283 | PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); | |
1da177e4 LT |
1284 | |
1285 | /* | |
82e1719c BH |
1286 | * Following the PCI ordering rules is optional on the AMD762. I'm not sure |
1287 | * what the designers were smoking but let's not inhale... | |
1da177e4 | 1288 | * |
82e1719c BH |
1289 | * To be fair to AMD, it follows the spec by default, it's BIOS people who |
1290 | * turn it off! | |
1da177e4 | 1291 | */ |
1597cacb | 1292 | static void quirk_amd_ordering(struct pci_dev *dev) |
1da177e4 LT |
1293 | { |
1294 | u32 pcic; | |
1295 | pci_read_config_dword(dev, 0x4C, &pcic); | |
3c78bc61 | 1296 | if ((pcic & 6) != 6) { |
1da177e4 | 1297 | pcic |= 6; |
7506dc79 | 1298 | pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); |
1da177e4 LT |
1299 | pci_write_config_dword(dev, 0x4C, pcic); |
1300 | pci_read_config_dword(dev, 0x84, &pcic); | |
3c78bc61 | 1301 | pcic |= (1 << 23); /* Required in this mode */ |
1da177e4 LT |
1302 | pci_write_config_dword(dev, 0x84, pcic); |
1303 | } | |
1304 | } | |
652c538e | 1305 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
e1a2a51e | 1306 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
1da177e4 LT |
1307 | |
1308 | /* | |
82e1719c | 1309 | * DreamWorks-provided workaround for Dunord I-3000 problem |
1da177e4 | 1310 | * |
82e1719c BH |
1311 | * This card decodes and responds to addresses not apparently assigned to |
1312 | * it. We force a larger allocation to ensure that nothing gets put too | |
1313 | * close to it. | |
1da177e4 | 1314 | */ |
15856ad5 | 1315 | static void quirk_dunord(struct pci_dev *dev) |
1da177e4 | 1316 | { |
3c78bc61 | 1317 | struct resource *r = &dev->resource[1]; |
bd064f0a BH |
1318 | |
1319 | r->flags |= IORESOURCE_UNSET; | |
1da177e4 LT |
1320 | r->start = 0; |
1321 | r->end = 0xffffff; | |
1322 | } | |
652c538e | 1323 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); |
1da177e4 LT |
1324 | |
1325 | /* | |
82e1719c BH |
1326 | * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive |
1327 | * decoding (transparent), and does indicate this in the ProgIf. | |
1328 | * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. | |
1da177e4 | 1329 | */ |
15856ad5 | 1330 | static void quirk_transparent_bridge(struct pci_dev *dev) |
1da177e4 LT |
1331 | { |
1332 | dev->transparent = 1; | |
1333 | } | |
652c538e AM |
1334 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); |
1335 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); | |
1da177e4 LT |
1336 | |
1337 | /* | |
82e1719c BH |
1338 | * Common misconfiguration of the MediaGX/Geode PCI master that will reduce |
1339 | * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets | |
1340 | * found at http://www.national.com/analog for info on what these bits do. | |
1341 | * <christer@weinigel.se> | |
1da177e4 | 1342 | */ |
1597cacb | 1343 | static void quirk_mediagx_master(struct pci_dev *dev) |
1da177e4 LT |
1344 | { |
1345 | u8 reg; | |
3c78bc61 | 1346 | |
1da177e4 LT |
1347 | pci_read_config_byte(dev, 0x41, ®); |
1348 | if (reg & 2) { | |
1349 | reg &= ~2; | |
7506dc79 | 1350 | pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", |
227f0647 | 1351 | reg); |
3c78bc61 | 1352 | pci_write_config_byte(dev, 0x41, reg); |
1da177e4 LT |
1353 | } |
1354 | } | |
652c538e AM |
1355 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
1356 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); | |
1da177e4 | 1357 | |
1da177e4 | 1358 | /* |
82e1719c BH |
1359 | * Ensure C0 rev restreaming is off. This is normally done by the BIOS but |
1360 | * in the odd case it is not the results are corruption hence the presence | |
1361 | * of a Linux check. | |
1da177e4 | 1362 | */ |
1597cacb | 1363 | static void quirk_disable_pxb(struct pci_dev *pdev) |
1da177e4 LT |
1364 | { |
1365 | u16 config; | |
f7625980 | 1366 | |
44c10138 | 1367 | if (pdev->revision != 0x04) /* Only C0 requires this */ |
1da177e4 LT |
1368 | return; |
1369 | pci_read_config_word(pdev, 0x40, &config); | |
1370 | if (config & (1<<6)) { | |
1371 | config &= ~(1<<6); | |
1372 | pci_write_config_word(pdev, 0x40, config); | |
7506dc79 | 1373 | pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); |
1da177e4 LT |
1374 | } |
1375 | } | |
652c538e | 1376 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
e1a2a51e | 1377 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
1da177e4 | 1378 | |
25e742b2 | 1379 | static void quirk_amd_ide_mode(struct pci_dev *pdev) |
ab17443a | 1380 | { |
5deab536 | 1381 | /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ |
05a7d22b | 1382 | u8 tmp; |
ab17443a | 1383 | |
05a7d22b CC |
1384 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); |
1385 | if (tmp == 0x01) { | |
ab17443a CH |
1386 | pci_read_config_byte(pdev, 0x40, &tmp); |
1387 | pci_write_config_byte(pdev, 0x40, tmp|1); | |
1388 | pci_write_config_byte(pdev, 0x9, 1); | |
1389 | pci_write_config_byte(pdev, 0xa, 6); | |
1390 | pci_write_config_byte(pdev, 0x40, tmp); | |
1391 | ||
c9f89475 | 1392 | pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
7506dc79 | 1393 | pci_info(pdev, "set SATA to AHCI mode\n"); |
ab17443a CH |
1394 | } |
1395 | } | |
05a7d22b | 1396 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1397 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
05a7d22b | 1398 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1399 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
5deab536 SH |
1400 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); |
1401 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); | |
fafe5c3d SH |
1402 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); |
1403 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); | |
ab17443a | 1404 | |
82e1719c | 1405 | /* Serverworks CSB5 IDE does not fully support native mode */ |
15856ad5 | 1406 | static void quirk_svwks_csb5ide(struct pci_dev *pdev) |
1da177e4 LT |
1407 | { |
1408 | u8 prog; | |
1409 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1410 | if (prog & 5) { | |
1411 | prog &= ~5; | |
1412 | pdev->class &= ~5; | |
1413 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
368c73d4 | 1414 | /* PCI layer will sort out resources */ |
1da177e4 LT |
1415 | } |
1416 | } | |
652c538e | 1417 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); |
1da177e4 | 1418 | |
82e1719c | 1419 | /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ |
15856ad5 | 1420 | static void quirk_ide_samemode(struct pci_dev *pdev) |
1da177e4 LT |
1421 | { |
1422 | u8 prog; | |
1423 | ||
1424 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1425 | ||
1426 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { | |
7506dc79 | 1427 | pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); |
1da177e4 LT |
1428 | prog &= ~5; |
1429 | pdev->class &= ~5; | |
1430 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
1da177e4 LT |
1431 | } |
1432 | } | |
368c73d4 | 1433 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
1da177e4 | 1434 | |
82e1719c | 1435 | /* Some ATA devices break if put into D3 */ |
15856ad5 | 1436 | static void quirk_no_ata_d3(struct pci_dev *pdev) |
979b1791 | 1437 | { |
faa738bb | 1438 | pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; |
979b1791 | 1439 | } |
faa738bb YL |
1440 | /* Quirk the legacy ATA devices only. The AHCI ones are ok */ |
1441 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, | |
1442 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
1443 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, | |
1444 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
7a661c6f | 1445 | /* ALi loses some register settings that we cannot then restore */ |
faa738bb YL |
1446 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, |
1447 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
7a661c6f AC |
1448 | /* VIA comes back fine but we need to keep it alive or ACPI GTM failures |
1449 | occur when mode detecting */ | |
faa738bb YL |
1450 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, |
1451 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
979b1791 | 1452 | |
82e1719c BH |
1453 | /* |
1454 | * This was originally an Alpha-specific thing, but it really fits here. | |
1da177e4 LT |
1455 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. |
1456 | */ | |
15856ad5 | 1457 | static void quirk_eisa_bridge(struct pci_dev *dev) |
1da177e4 LT |
1458 | { |
1459 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; | |
1460 | } | |
652c538e | 1461 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); |
1da177e4 LT |
1462 | |
1463 | /* | |
1464 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge | |
1465 | * is not activated. The myth is that Asus said that they do not want the | |
1466 | * users to be irritated by just another PCI Device in the Win98 device | |
f7625980 | 1467 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors |
1da177e4 LT |
1468 | * package 2.7.0 for details) |
1469 | * | |
f7625980 BH |
1470 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC |
1471 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it | |
d7698edc | 1472 | * becomes necessary to do this tweak in two steps -- the chosen trigger |
1473 | * is either the Host bridge (preferred) or on-board VGA controller. | |
9208ee82 JD |
1474 | * |
1475 | * Note that we used to unhide the SMBus that way on Toshiba laptops | |
1476 | * (Satellite A40 and Tecra M2) but then found that the thermal management | |
1477 | * was done by SMM code, which could cause unsynchronized concurrent | |
1478 | * accesses to the SMBus registers, with potentially bad effects. Thus you | |
1479 | * should be very careful when adding new entries: if SMM is accessing the | |
1480 | * Intel SMBus, this is a very good reason to leave it hidden. | |
a99acc83 JD |
1481 | * |
1482 | * Likewise, many recent laptops use ACPI for thermal management. If the | |
1483 | * ACPI DSDT code accesses the SMBus, then Linux should not access it | |
1484 | * natively, and keeping the SMBus hidden is the right thing to do. If you | |
1485 | * are about to add an entry in the table below, please first disassemble | |
1486 | * the DSDT and double-check that there is no code accessing the SMBus. | |
1da177e4 | 1487 | */ |
9d24a81e | 1488 | static int asus_hides_smbus; |
1da177e4 | 1489 | |
15856ad5 | 1490 | static void asus_hides_smbus_hostbridge(struct pci_dev *dev) |
1da177e4 LT |
1491 | { |
1492 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1493 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) | |
3c78bc61 | 1494 | switch (dev->subsystem_device) { |
a00db371 | 1495 | case 0x8025: /* P4B-LX */ |
1da177e4 LT |
1496 | case 0x8070: /* P4B */ |
1497 | case 0x8088: /* P4B533 */ | |
1498 | case 0x1626: /* L3C notebook */ | |
1499 | asus_hides_smbus = 1; | |
1500 | } | |
2f2d39d2 | 1501 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
3c78bc61 | 1502 | switch (dev->subsystem_device) { |
1da177e4 LT |
1503 | case 0x80b1: /* P4GE-V */ |
1504 | case 0x80b2: /* P4PE */ | |
1505 | case 0x8093: /* P4B533-V */ | |
1506 | asus_hides_smbus = 1; | |
1507 | } | |
2f2d39d2 | 1508 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
3c78bc61 | 1509 | switch (dev->subsystem_device) { |
1da177e4 LT |
1510 | case 0x8030: /* P4T533 */ |
1511 | asus_hides_smbus = 1; | |
1512 | } | |
2f2d39d2 | 1513 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
1da177e4 LT |
1514 | switch (dev->subsystem_device) { |
1515 | case 0x8070: /* P4G8X Deluxe */ | |
1516 | asus_hides_smbus = 1; | |
1517 | } | |
2f2d39d2 | 1518 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
321311af JD |
1519 | switch (dev->subsystem_device) { |
1520 | case 0x80c9: /* PU-DLS */ | |
1521 | asus_hides_smbus = 1; | |
1522 | } | |
2f2d39d2 | 1523 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
1da177e4 LT |
1524 | switch (dev->subsystem_device) { |
1525 | case 0x1751: /* M2N notebook */ | |
1526 | case 0x1821: /* M5N notebook */ | |
4096ed0f | 1527 | case 0x1897: /* A6L notebook */ |
1da177e4 LT |
1528 | asus_hides_smbus = 1; |
1529 | } | |
2f2d39d2 | 1530 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1da177e4 LT |
1531 | switch (dev->subsystem_device) { |
1532 | case 0x184b: /* W1N notebook */ | |
1533 | case 0x186a: /* M6Ne notebook */ | |
1534 | asus_hides_smbus = 1; | |
1535 | } | |
2f2d39d2 | 1536 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
2e45785c JD |
1537 | switch (dev->subsystem_device) { |
1538 | case 0x80f2: /* P4P800-X */ | |
1539 | asus_hides_smbus = 1; | |
1540 | } | |
2f2d39d2 | 1541 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
acc06632 M |
1542 | switch (dev->subsystem_device) { |
1543 | case 0x1882: /* M6V notebook */ | |
2d1e1c75 | 1544 | case 0x1977: /* A6VA notebook */ |
acc06632 M |
1545 | asus_hides_smbus = 1; |
1546 | } | |
1da177e4 LT |
1547 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
1548 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
3c78bc61 | 1549 | switch (dev->subsystem_device) { |
1da177e4 LT |
1550 | case 0x088C: /* HP Compaq nc8000 */ |
1551 | case 0x0890: /* HP Compaq nc6000 */ | |
1552 | asus_hides_smbus = 1; | |
1553 | } | |
2f2d39d2 | 1554 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1da177e4 LT |
1555 | switch (dev->subsystem_device) { |
1556 | case 0x12bc: /* HP D330L */ | |
e3b1bd57 | 1557 | case 0x12bd: /* HP D530 */ |
74c57428 | 1558 | case 0x006a: /* HP Compaq nx9500 */ |
1da177e4 LT |
1559 | asus_hides_smbus = 1; |
1560 | } | |
677cc644 JD |
1561 | else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) |
1562 | switch (dev->subsystem_device) { | |
1563 | case 0x12bf: /* HP xw4100 */ | |
1564 | asus_hides_smbus = 1; | |
1565 | } | |
3c78bc61 RD |
1566 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
1567 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1568 | switch (dev->subsystem_device) { | |
1569 | case 0xC00C: /* Samsung P35 notebook */ | |
1570 | asus_hides_smbus = 1; | |
1571 | } | |
c87f883e RIZ |
1572 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
1573 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
3c78bc61 | 1574 | switch (dev->subsystem_device) { |
c87f883e RIZ |
1575 | case 0x0058: /* Compaq Evo N620c */ |
1576 | asus_hides_smbus = 1; | |
1577 | } | |
d7698edc | 1578 | else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) |
3c78bc61 | 1579 | switch (dev->subsystem_device) { |
d7698edc | 1580 | case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ |
1581 | /* Motherboard doesn't have Host bridge | |
1582 | * subvendor/subdevice IDs, therefore checking | |
1583 | * its on-board VGA controller */ | |
1584 | asus_hides_smbus = 1; | |
1585 | } | |
8293b0f6 | 1586 | else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) |
3c78bc61 | 1587 | switch (dev->subsystem_device) { |
10260d9a JD |
1588 | case 0x00b8: /* Compaq Evo D510 CMT */ |
1589 | case 0x00b9: /* Compaq Evo D510 SFF */ | |
6b5096e4 | 1590 | case 0x00ba: /* Compaq Evo D510 USDT */ |
8293b0f6 DS |
1591 | /* Motherboard doesn't have Host bridge |
1592 | * subvendor/subdevice IDs and on-board VGA | |
1593 | * controller is disabled if an AGP card is | |
1594 | * inserted, therefore checking USB UHCI | |
1595 | * Controller #1 */ | |
10260d9a JD |
1596 | asus_hides_smbus = 1; |
1597 | } | |
27e46859 KH |
1598 | else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) |
1599 | switch (dev->subsystem_device) { | |
1600 | case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ | |
1601 | /* Motherboard doesn't have host bridge | |
1602 | * subvendor/subdevice IDs, therefore checking | |
1603 | * its on-board VGA controller */ | |
1604 | asus_hides_smbus = 1; | |
1605 | } | |
1da177e4 LT |
1606 | } |
1607 | } | |
652c538e AM |
1608 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); |
1609 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); | |
1610 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); | |
1611 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); | |
677cc644 | 1612 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); |
652c538e AM |
1613 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); |
1614 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); | |
1615 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); | |
1616 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); | |
1617 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); | |
1618 | ||
1619 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); | |
8293b0f6 | 1620 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); |
27e46859 | 1621 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); |
d7698edc | 1622 | |
1597cacb | 1623 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
1da177e4 LT |
1624 | { |
1625 | u16 val; | |
f7625980 | 1626 | |
1da177e4 LT |
1627 | if (likely(!asus_hides_smbus)) |
1628 | return; | |
1629 | ||
1630 | pci_read_config_word(dev, 0xF2, &val); | |
1631 | if (val & 0x8) { | |
1632 | pci_write_config_word(dev, 0xF2, val & (~0x8)); | |
1633 | pci_read_config_word(dev, 0xF2, &val); | |
1634 | if (val & 0x8) | |
7506dc79 | 1635 | pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", |
227f0647 | 1636 | val); |
1da177e4 | 1637 | else |
7506dc79 | 1638 | pci_info(dev, "Enabled i801 SMBus device\n"); |
1da177e4 LT |
1639 | } |
1640 | } | |
652c538e AM |
1641 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1642 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1643 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1644 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1645 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1646 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1647 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
e1a2a51e RW |
1648 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1649 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1650 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1651 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1652 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1653 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1654 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
1597cacb | 1655 | |
e1a2a51e RW |
1656 | /* It appears we just have one such device. If not, we have a warning */ |
1657 | static void __iomem *asus_rcba_base; | |
1658 | static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) | |
acc06632 | 1659 | { |
e1a2a51e | 1660 | u32 rcba; |
acc06632 M |
1661 | |
1662 | if (likely(!asus_hides_smbus)) | |
1663 | return; | |
e1a2a51e RW |
1664 | WARN_ON(asus_rcba_base); |
1665 | ||
acc06632 | 1666 | pci_read_config_dword(dev, 0xF0, &rcba); |
e1a2a51e | 1667 | /* use bits 31:14, 16 kB aligned */ |
4bdc0d67 | 1668 | asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); |
e1a2a51e RW |
1669 | if (asus_rcba_base == NULL) |
1670 | return; | |
1671 | } | |
1672 | ||
1673 | static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) | |
1674 | { | |
1675 | u32 val; | |
1676 | ||
1677 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1678 | return; | |
82e1719c | 1679 | |
e1a2a51e RW |
1680 | /* read the Function Disable register, dword mode only */ |
1681 | val = readl(asus_rcba_base + 0x3418); | |
82e1719c BH |
1682 | |
1683 | /* enable the SMBus device */ | |
1684 | writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); | |
e1a2a51e RW |
1685 | } |
1686 | ||
1687 | static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) | |
1688 | { | |
1689 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1690 | return; | |
82e1719c | 1691 | |
e1a2a51e RW |
1692 | iounmap(asus_rcba_base); |
1693 | asus_rcba_base = NULL; | |
7506dc79 | 1694 | pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); |
acc06632 | 1695 | } |
e1a2a51e RW |
1696 | |
1697 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) | |
1698 | { | |
1699 | asus_hides_smbus_lpc_ich6_suspend(dev); | |
1700 | asus_hides_smbus_lpc_ich6_resume_early(dev); | |
1701 | asus_hides_smbus_lpc_ich6_resume(dev); | |
1702 | } | |
652c538e | 1703 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); |
e1a2a51e RW |
1704 | DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); |
1705 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); | |
1706 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); | |
ce007ea5 | 1707 | |
82e1719c | 1708 | /* SiS 96x south bridge: BIOS typically hides SMBus device... */ |
1597cacb | 1709 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
1da177e4 LT |
1710 | { |
1711 | u8 val = 0; | |
1da177e4 | 1712 | pci_read_config_byte(dev, 0x77, &val); |
2f5c33b3 | 1713 | if (val & 0x10) { |
7506dc79 | 1714 | pci_info(dev, "Enabling SiS 96x SMBus\n"); |
2f5c33b3 MH |
1715 | pci_write_config_byte(dev, 0x77, val & ~0x10); |
1716 | } | |
1da177e4 | 1717 | } |
652c538e AM |
1718 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1719 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1720 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1721 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
e1a2a51e RW |
1722 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1723 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1724 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1725 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
1da177e4 | 1726 | |
1da177e4 LT |
1727 | /* |
1728 | * ... This is further complicated by the fact that some SiS96x south | |
1729 | * bridges pretend to be 85C503/5513 instead. In that case see if we | |
1730 | * spotted a compatible north bridge to make sure. | |
82e1719c | 1731 | * (pci_find_device() doesn't work yet) |
1da177e4 LT |
1732 | * |
1733 | * We can also enable the sis96x bit in the discovery register.. | |
1734 | */ | |
1da177e4 LT |
1735 | #define SIS_DETECT_REGISTER 0x40 |
1736 | ||
1597cacb | 1737 | static void quirk_sis_503(struct pci_dev *dev) |
1da177e4 LT |
1738 | { |
1739 | u8 reg; | |
1740 | u16 devid; | |
1741 | ||
1742 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); | |
1743 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); | |
1744 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); | |
1745 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { | |
1746 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); | |
1747 | return; | |
1748 | } | |
1749 | ||
1da177e4 | 1750 | /* |
82e1719c BH |
1751 | * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case |
1752 | * it has already been processed. (Depends on link order, which is | |
1753 | * apparently not guaranteed) | |
1da177e4 LT |
1754 | */ |
1755 | dev->device = devid; | |
2f5c33b3 | 1756 | quirk_sis_96x_smbus(dev); |
1da177e4 | 1757 | } |
652c538e | 1758 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
e1a2a51e | 1759 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
1da177e4 | 1760 | |
e5548e96 BJD |
1761 | /* |
1762 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller | |
1763 | * and MC97 modem controller are disabled when a second PCI soundcard is | |
1764 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. | |
1765 | * -- bjd | |
1766 | */ | |
1597cacb | 1767 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
e5548e96 BJD |
1768 | { |
1769 | u8 val; | |
1770 | int asus_hides_ac97 = 0; | |
1771 | ||
1772 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1773 | if (dev->device == PCI_DEVICE_ID_VIA_8237) | |
1774 | asus_hides_ac97 = 1; | |
1775 | } | |
1776 | ||
1777 | if (!asus_hides_ac97) | |
1778 | return; | |
1779 | ||
1780 | pci_read_config_byte(dev, 0x50, &val); | |
1781 | if (val & 0xc0) { | |
1782 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); | |
1783 | pci_read_config_byte(dev, 0x50, &val); | |
1784 | if (val & 0xc0) | |
7506dc79 | 1785 | pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", |
227f0647 | 1786 | val); |
e5548e96 | 1787 | else |
7506dc79 | 1788 | pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); |
e5548e96 BJD |
1789 | } |
1790 | } | |
652c538e | 1791 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
e1a2a51e | 1792 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
1597cacb | 1793 | |
77967052 | 1794 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
15e0c694 AC |
1795 | |
1796 | /* | |
82e1719c BH |
1797 | * If we are using libata we can drive this chip properly but must do this |
1798 | * early on to make the additional device appear during the PCI scanning. | |
15e0c694 | 1799 | */ |
5ee2ae7f | 1800 | static void quirk_jmicron_ata(struct pci_dev *pdev) |
15e0c694 | 1801 | { |
e34bb370 | 1802 | u32 conf1, conf5, class; |
15e0c694 AC |
1803 | u8 hdr; |
1804 | ||
1805 | /* Only poke fn 0 */ | |
1806 | if (PCI_FUNC(pdev->devfn)) | |
1807 | return; | |
1808 | ||
5ee2ae7f TH |
1809 | pci_read_config_dword(pdev, 0x40, &conf1); |
1810 | pci_read_config_dword(pdev, 0x80, &conf5); | |
15e0c694 | 1811 | |
5ee2ae7f TH |
1812 | conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ |
1813 | conf5 &= ~(1 << 24); /* Clear bit 24 */ | |
1814 | ||
1815 | switch (pdev->device) { | |
4daedcfe TH |
1816 | case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ |
1817 | case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ | |
5b6ae5ba | 1818 | case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ |
5ee2ae7f TH |
1819 | /* The controller should be in single function ahci mode */ |
1820 | conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ | |
1821 | break; | |
1822 | ||
1823 | case PCI_DEVICE_ID_JMICRON_JMB365: | |
1824 | case PCI_DEVICE_ID_JMICRON_JMB366: | |
1825 | /* Redirect IDE second PATA port to the right spot */ | |
1826 | conf5 |= (1 << 24); | |
df561f66 | 1827 | fallthrough; |
5ee2ae7f TH |
1828 | case PCI_DEVICE_ID_JMICRON_JMB361: |
1829 | case PCI_DEVICE_ID_JMICRON_JMB363: | |
5b6ae5ba | 1830 | case PCI_DEVICE_ID_JMICRON_JMB369: |
5ee2ae7f TH |
1831 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ |
1832 | /* Set the class codes correctly and then direct IDE 0 */ | |
3a9e3a51 | 1833 | conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
5ee2ae7f TH |
1834 | break; |
1835 | ||
1836 | case PCI_DEVICE_ID_JMICRON_JMB368: | |
1837 | /* The controller should be in single function IDE mode */ | |
1838 | conf1 |= 0x00C00000; /* Set 22, 23 */ | |
1839 | break; | |
15e0c694 | 1840 | } |
5ee2ae7f TH |
1841 | |
1842 | pci_write_config_dword(pdev, 0x40, conf1); | |
1843 | pci_write_config_dword(pdev, 0x80, conf5); | |
1844 | ||
1845 | /* Update pdev accordingly */ | |
1846 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); | |
1847 | pdev->hdr_type = hdr & 0x7f; | |
1848 | pdev->multifunction = !!(hdr & 0x80); | |
e34bb370 TH |
1849 | |
1850 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); | |
1851 | pdev->class = class >> 8; | |
15e0c694 | 1852 | } |
5ee2ae7f TH |
1853 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1854 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
4daedcfe | 1855 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
5ee2ae7f | 1856 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
5b6ae5ba | 1857 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
5ee2ae7f TH |
1858 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
1859 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1860 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
5b6ae5ba | 1861 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
e1a2a51e RW |
1862 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1863 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
4daedcfe | 1864 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
e1a2a51e | 1865 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
5b6ae5ba | 1866 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
e1a2a51e RW |
1867 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
1868 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1869 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
5b6ae5ba | 1870 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
15e0c694 AC |
1871 | |
1872 | #endif | |
1873 | ||
91f15fb3 ZR |
1874 | static void quirk_jmicron_async_suspend(struct pci_dev *dev) |
1875 | { | |
1876 | if (dev->multifunction) { | |
1877 | device_disable_async_suspend(&dev->dev); | |
7506dc79 | 1878 | pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); |
91f15fb3 ZR |
1879 | } |
1880 | } | |
1881 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); | |
1882 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); | |
1883 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); | |
1884 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); | |
1885 | ||
1da177e4 | 1886 | #ifdef CONFIG_X86_IO_APIC |
15856ad5 | 1887 | static void quirk_alder_ioapic(struct pci_dev *pdev) |
1da177e4 LT |
1888 | { |
1889 | int i; | |
1890 | ||
1891 | if ((pdev->class >> 8) != 0xff00) | |
1892 | return; | |
1893 | ||
82e1719c BH |
1894 | /* |
1895 | * The first BAR is the location of the IO-APIC... we must | |
1da177e4 | 1896 | * not touch this (and it's already covered by the fixmap), so |
82e1719c BH |
1897 | * forcibly insert it into the resource tree. |
1898 | */ | |
1da177e4 LT |
1899 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) |
1900 | insert_resource(&iomem_resource, &pdev->resource[0]); | |
1901 | ||
82e1719c BH |
1902 | /* |
1903 | * The next five BARs all seem to be rubbish, so just clean | |
1904 | * them out. | |
1905 | */ | |
c9c13ba4 | 1906 | for (i = 1; i < PCI_STD_NUM_BARS; i++) |
1da177e4 | 1907 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); |
1da177e4 | 1908 | } |
652c538e | 1909 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); |
1da177e4 LT |
1910 | #endif |
1911 | ||
63cd736f BH |
1912 | static void quirk_no_msi(struct pci_dev *dev) |
1913 | { | |
1914 | pci_info(dev, "avoiding MSI to work around a hardware defect\n"); | |
1915 | dev->no_msi = 1; | |
1916 | } | |
1917 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); | |
1918 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); | |
1919 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); | |
1920 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); | |
1921 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); | |
1922 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); | |
1923 | ||
15856ad5 | 1924 | static void quirk_pcie_mch(struct pci_dev *pdev) |
1da177e4 | 1925 | { |
0ba379ec | 1926 | pdev->no_msi = 1; |
1da177e4 | 1927 | } |
652c538e AM |
1928 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); |
1929 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); | |
1930 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); | |
1da177e4 | 1931 | |
deb86999 | 1932 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); |
4602b88d | 1933 | |
8304a3a1 ZG |
1934 | /* |
1935 | * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are | |
1936 | * actually on the AMBA bus. These fake PCI devices can support SVA via | |
1937 | * SMMU stall feature, by setting dma-can-stall for ACPI platforms. | |
1938 | * | |
1939 | * Normally stalling must not be enabled for PCI devices, since it would | |
1940 | * break the PCI requirement for free-flowing writes and may lead to | |
1941 | * deadlock. We expect PCI devices to support ATS and PRI if they want to | |
1942 | * be fault-tolerant, so there's no ACPI binding to describe anything else, | |
1943 | * even when a "PCI" device turns out to be a regular old SoC device | |
1944 | * dressed up as a RCiEP and normal rules don't apply. | |
1945 | */ | |
8c09e896 ZG |
1946 | static void quirk_huawei_pcie_sva(struct pci_dev *pdev) |
1947 | { | |
8304a3a1 ZG |
1948 | struct property_entry properties[] = { |
1949 | PROPERTY_ENTRY_BOOL("dma-can-stall"), | |
1950 | {}, | |
1951 | }; | |
1952 | ||
8c09e896 ZG |
1953 | if (pdev->revision != 0x21 && pdev->revision != 0x30) |
1954 | return; | |
1955 | ||
1956 | pdev->pasid_no_tlp = 1; | |
8304a3a1 ZG |
1957 | |
1958 | /* | |
1959 | * Set the dma-can-stall property on ACPI platforms. Device tree | |
1960 | * can set it directly. | |
1961 | */ | |
1962 | if (!pdev->dev.of_node && | |
0c9e032a | 1963 | device_create_managed_software_node(&pdev->dev, properties, NULL)) |
8304a3a1 | 1964 | pci_warn(pdev, "could not add stall property"); |
8c09e896 ZG |
1965 | } |
1966 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); | |
1967 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); | |
1968 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); | |
1969 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); | |
1970 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); | |
1971 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); | |
1972 | ||
4602b88d | 1973 | /* |
82e1719c BH |
1974 | * It's possible for the MSI to get corrupted if SHPC and ACPI are used |
1975 | * together on certain PXH-based systems. | |
4602b88d | 1976 | */ |
15856ad5 | 1977 | static void quirk_pcie_pxh(struct pci_dev *dev) |
4602b88d | 1978 | { |
4602b88d | 1979 | dev->no_msi = 1; |
7506dc79 | 1980 | pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); |
4602b88d KA |
1981 | } |
1982 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); | |
1983 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); | |
1984 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); | |
1985 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); | |
1986 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); | |
1987 | ||
ffadcc2f | 1988 | /* |
82e1719c BH |
1989 | * Some Intel PCI Express chipsets have trouble with downstream device |
1990 | * power management. | |
ffadcc2f | 1991 | */ |
3c78bc61 | 1992 | static void quirk_intel_pcie_pm(struct pci_dev *dev) |
ffadcc2f | 1993 | { |
3789af9a | 1994 | pci_pm_d3hot_delay = 120; |
ffadcc2f KCA |
1995 | dev->no_d1d2 = 1; |
1996 | } | |
ffadcc2f KCA |
1997 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); |
1998 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); | |
1999 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); | |
2000 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); | |
2001 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); | |
2002 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); | |
2003 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); | |
2004 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); | |
2005 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); | |
2006 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); | |
2007 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); | |
2008 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); | |
2009 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); | |
2010 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); | |
2011 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); | |
2012 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); | |
2013 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); | |
2014 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); | |
2015 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); | |
2016 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); | |
2017 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); | |
4602b88d | 2018 | |
62fe23df DD |
2019 | static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) |
2020 | { | |
3789af9a | 2021 | if (dev->d3hot_delay >= delay) |
62fe23df DD |
2022 | return; |
2023 | ||
3789af9a | 2024 | dev->d3hot_delay = delay; |
62fe23df | 2025 | pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", |
3789af9a | 2026 | dev->d3hot_delay); |
62fe23df DD |
2027 | } |
2028 | ||
5938628c BH |
2029 | static void quirk_radeon_pm(struct pci_dev *dev) |
2030 | { | |
2031 | if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && | |
62fe23df DD |
2032 | dev->subsystem_device == 0x00e2) |
2033 | quirk_d3hot_delay(dev, 20); | |
5938628c BH |
2034 | } |
2035 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); | |
2036 | ||
a5a6dd26 AW |
2037 | /* |
2038 | * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus | |
2039 | * reset is performed too soon after transition to D0, extend d3hot_delay | |
2040 | * to previous effective default for all NVIDIA HDA controllers. | |
2041 | */ | |
2042 | static void quirk_nvidia_hda_pm(struct pci_dev *dev) | |
2043 | { | |
2044 | quirk_d3hot_delay(dev, 20); | |
2045 | } | |
2046 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, | |
2047 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, | |
2048 | quirk_nvidia_hda_pm); | |
2049 | ||
3030df20 DD |
2050 | /* |
2051 | * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. | |
2052 | * https://bugzilla.kernel.org/show_bug.cgi?id=205587 | |
2053 | * | |
2054 | * The kernel attempts to transition these devices to D3cold, but that seems | |
2055 | * to be ineffective on the platforms in question; the PCI device appears to | |
2056 | * remain on in D3hot state. The D3hot-to-D0 transition then requires an | |
2057 | * extended delay in order to succeed. | |
2058 | */ | |
2059 | static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) | |
2060 | { | |
2061 | quirk_d3hot_delay(dev, 20); | |
2062 | } | |
2063 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); | |
2064 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); | |
e0bff432 | 2065 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); |
3030df20 | 2066 | |
426b3b8d | 2067 | #ifdef CONFIG_X86_IO_APIC |
c4e649b0 SA |
2068 | static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) |
2069 | { | |
2070 | noioapicreroute = 1; | |
2071 | pr_info("%s detected: disable boot interrupt reroute\n", d->ident); | |
2072 | ||
2073 | return 0; | |
2074 | } | |
2075 | ||
6faadbbb | 2076 | static const struct dmi_system_id boot_interrupt_dmi_table[] = { |
c4e649b0 SA |
2077 | /* |
2078 | * Systems to exclude from boot interrupt reroute quirks | |
2079 | */ | |
2080 | { | |
2081 | .callback = dmi_disable_ioapicreroute, | |
2082 | .ident = "ASUSTek Computer INC. M2N-LR", | |
2083 | .matches = { | |
2084 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), | |
2085 | DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), | |
2086 | }, | |
2087 | }, | |
2088 | {} | |
2089 | }; | |
2090 | ||
e1d3a908 SA |
2091 | /* |
2092 | * Boot interrupts on some chipsets cannot be turned off. For these chipsets, | |
82e1719c | 2093 | * remap the original interrupt in the Linux kernel to the boot interrupt, so |
e1d3a908 SA |
2094 | * that a PCI device's interrupt handler is installed on the boot interrupt |
2095 | * line instead. | |
2096 | */ | |
2097 | static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) | |
2098 | { | |
c4e649b0 | 2099 | dmi_check_system(boot_interrupt_dmi_table); |
41b9eb26 | 2100 | if (noioapicquirk || noioapicreroute) |
e1d3a908 SA |
2101 | return; |
2102 | ||
2103 | dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; | |
7506dc79 | 2104 | pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", |
fdcdaf6c | 2105 | dev->vendor, dev->device); |
e1d3a908 | 2106 | } |
88d1dce3 OD |
2107 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); |
2108 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
2109 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
2110 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
2111 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
2112 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
2113 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
2114 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
2115 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); | |
2116 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
2117 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
2118 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
2119 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
2120 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
2121 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
2122 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
e1d3a908 | 2123 | |
426b3b8d SA |
2124 | /* |
2125 | * On some chipsets we can disable the generation of legacy INTx boot | |
2126 | * interrupts. | |
2127 | */ | |
2128 | ||
2129 | /* | |
82e1719c | 2130 | * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no |
426b3b8d | 2131 | * 300641-004US, section 5.7.3. |
b88bf6c3 SK |
2132 | * |
2133 | * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. | |
2134 | * Core IO on Xeon E5 v2, see Intel order no 329188-003. | |
2135 | * Core IO on Xeon E7 v2, see Intel order no 329595-002. | |
2136 | * Core IO on Xeon E5 v3, see Intel order no 330784-003. | |
2137 | * Core IO on Xeon E7 v3, see Intel order no 332315-001US. | |
2138 | * Core IO on Xeon E5 v4, see Intel order no 333810-002US. | |
2139 | * Core IO on Xeon E7 v4, see Intel order no 332315-001US. | |
2140 | * Core IO on Xeon D-1500, see Intel order no 332051-001. | |
2141 | * Core IO on Xeon Scalable, see Intel order no 610950. | |
426b3b8d | 2142 | */ |
b88bf6c3 | 2143 | #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ |
426b3b8d SA |
2144 | #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) |
2145 | ||
b88bf6c3 SK |
2146 | #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ |
2147 | #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) | |
2148 | ||
426b3b8d SA |
2149 | static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) |
2150 | { | |
2151 | u16 pci_config_word; | |
b88bf6c3 | 2152 | u32 pci_config_dword; |
426b3b8d SA |
2153 | |
2154 | if (noioapicquirk) | |
2155 | return; | |
2156 | ||
b88bf6c3 SK |
2157 | switch (dev->device) { |
2158 | case PCI_DEVICE_ID_INTEL_ESB_10: | |
2159 | pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, | |
2160 | &pci_config_word); | |
2161 | pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; | |
2162 | pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, | |
2163 | pci_config_word); | |
2164 | break; | |
2165 | case 0x3c28: /* Xeon E5 1600/2600/4600 */ | |
2166 | case 0x0e28: /* Xeon E5/E7 V2 */ | |
2167 | case 0x2f28: /* Xeon E5/E7 V3,V4 */ | |
2168 | case 0x6f28: /* Xeon D-1500 */ | |
2169 | case 0x2034: /* Xeon Scalable Family */ | |
2170 | pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, | |
2171 | &pci_config_dword); | |
2172 | pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; | |
2173 | pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, | |
2174 | pci_config_dword); | |
2175 | break; | |
2176 | default: | |
2177 | return; | |
2178 | } | |
7506dc79 | 2179 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
fdcdaf6c | 2180 | dev->vendor, dev->device); |
426b3b8d | 2181 | } |
b88bf6c3 SK |
2182 | /* |
2183 | * Device 29 Func 5 Device IDs of IO-APIC | |
2184 | * containing ABAR—APIC1 Alternate Base Address Register | |
2185 | */ | |
2186 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, | |
2187 | quirk_disable_intel_boot_interrupt); | |
2188 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, | |
2189 | quirk_disable_intel_boot_interrupt); | |
2190 | ||
2191 | /* | |
2192 | * Device 5 Func 0 Device IDs of Core IO modules/hubs | |
2193 | * containing Coherent Interface Protocol Interrupt Control | |
2194 | * | |
2195 | * Device IDs obtained from volume 2 datasheets of commented | |
2196 | * families above. | |
2197 | */ | |
2198 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, | |
2199 | quirk_disable_intel_boot_interrupt); | |
2200 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, | |
2201 | quirk_disable_intel_boot_interrupt); | |
2202 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, | |
2203 | quirk_disable_intel_boot_interrupt); | |
2204 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, | |
2205 | quirk_disable_intel_boot_interrupt); | |
2206 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, | |
2207 | quirk_disable_intel_boot_interrupt); | |
2208 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, | |
2209 | quirk_disable_intel_boot_interrupt); | |
2210 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, | |
2211 | quirk_disable_intel_boot_interrupt); | |
2212 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, | |
2213 | quirk_disable_intel_boot_interrupt); | |
2214 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, | |
2215 | quirk_disable_intel_boot_interrupt); | |
2216 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, | |
2217 | quirk_disable_intel_boot_interrupt); | |
77251188 | 2218 | |
82e1719c | 2219 | /* Disable boot interrupts on HT-1000 */ |
77251188 OD |
2220 | #define BC_HT1000_FEATURE_REG 0x64 |
2221 | #define BC_HT1000_PIC_REGS_ENABLE (1<<0) | |
2222 | #define BC_HT1000_MAP_IDX 0xC00 | |
2223 | #define BC_HT1000_MAP_DATA 0xC01 | |
2224 | ||
2225 | static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) | |
2226 | { | |
2227 | u32 pci_config_dword; | |
2228 | u8 irq; | |
2229 | ||
2230 | if (noioapicquirk) | |
2231 | return; | |
2232 | ||
2233 | pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); | |
2234 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | | |
2235 | BC_HT1000_PIC_REGS_ENABLE); | |
2236 | ||
2237 | for (irq = 0x10; irq < 0x10 + 32; irq++) { | |
2238 | outb(irq, BC_HT1000_MAP_IDX); | |
2239 | outb(0x00, BC_HT1000_MAP_DATA); | |
2240 | } | |
2241 | ||
2242 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); | |
2243 | ||
7506dc79 | 2244 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
fdcdaf6c | 2245 | dev->vendor, dev->device); |
77251188 | 2246 | } |
f7625980 BH |
2247 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
2248 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); | |
542622da | 2249 | |
82e1719c BH |
2250 | /* Disable boot interrupts on AMD and ATI chipsets */ |
2251 | ||
542622da OD |
2252 | /* |
2253 | * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 | |
2254 | * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode | |
2255 | * (due to an erratum). | |
2256 | */ | |
2257 | #define AMD_813X_MISC 0x40 | |
2258 | #define AMD_813X_NOIOAMODE (1<<0) | |
4fd8bdc5 | 2259 | #define AMD_813X_REV_B1 0x12 |
bbe19443 | 2260 | #define AMD_813X_REV_B2 0x13 |
542622da OD |
2261 | |
2262 | static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) | |
2263 | { | |
2264 | u32 pci_config_dword; | |
2265 | ||
2266 | if (noioapicquirk) | |
2267 | return; | |
4fd8bdc5 SA |
2268 | if ((dev->revision == AMD_813X_REV_B1) || |
2269 | (dev->revision == AMD_813X_REV_B2)) | |
bbe19443 | 2270 | return; |
542622da OD |
2271 | |
2272 | pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); | |
2273 | pci_config_dword &= ~AMD_813X_NOIOAMODE; | |
2274 | pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); | |
2275 | ||
7506dc79 | 2276 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
fdcdaf6c | 2277 | dev->vendor, dev->device); |
542622da | 2278 | } |
4fd8bdc5 SA |
2279 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
2280 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
2281 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
2282 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
542622da OD |
2283 | |
2284 | #define AMD_8111_PCI_IRQ_ROUTING 0x56 | |
2285 | ||
2286 | static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) | |
2287 | { | |
2288 | u16 pci_config_word; | |
2289 | ||
2290 | if (noioapicquirk) | |
2291 | return; | |
2292 | ||
2293 | pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); | |
2294 | if (!pci_config_word) { | |
7506dc79 | 2295 | pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", |
227f0647 | 2296 | dev->vendor, dev->device); |
542622da OD |
2297 | return; |
2298 | } | |
2299 | pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); | |
7506dc79 | 2300 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
fdcdaf6c | 2301 | dev->vendor, dev->device); |
542622da | 2302 | } |
f7625980 BH |
2303 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
2304 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); | |
426b3b8d SA |
2305 | #endif /* CONFIG_X86_IO_APIC */ |
2306 | ||
33dced2e SS |
2307 | /* |
2308 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size | |
2309 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. | |
2310 | * Re-allocate the region if needed... | |
2311 | */ | |
15856ad5 | 2312 | static void quirk_tc86c001_ide(struct pci_dev *dev) |
33dced2e SS |
2313 | { |
2314 | struct resource *r = &dev->resource[0]; | |
2315 | ||
2316 | if (r->start & 0x8) { | |
bd064f0a | 2317 | r->flags |= IORESOURCE_UNSET; |
33dced2e SS |
2318 | r->start = 0; |
2319 | r->end = 0xf; | |
2320 | } | |
2321 | } | |
2322 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, | |
2323 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, | |
2324 | quirk_tc86c001_ide); | |
2325 | ||
21c5fd97 | 2326 | /* |
82e1719c | 2327 | * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the |
21c5fd97 IA |
2328 | * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) |
2329 | * being read correctly if bit 7 of the base address is set. | |
2330 | * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). | |
2331 | * Re-allocate the regions to a 256-byte boundary if necessary. | |
2332 | */ | |
193c0d68 | 2333 | static void quirk_plx_pci9050(struct pci_dev *dev) |
21c5fd97 IA |
2334 | { |
2335 | unsigned int bar; | |
2336 | ||
2337 | /* Fixed in revision 2 (PCI 9052). */ | |
2338 | if (dev->revision >= 2) | |
2339 | return; | |
2340 | for (bar = 0; bar <= 1; bar++) | |
2341 | if (pci_resource_len(dev, bar) == 0x80 && | |
2342 | (pci_resource_start(dev, bar) & 0x80)) { | |
2343 | struct resource *r = &dev->resource[bar]; | |
7506dc79 | 2344 | pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", |
21c5fd97 | 2345 | bar); |
bd064f0a | 2346 | r->flags |= IORESOURCE_UNSET; |
21c5fd97 IA |
2347 | r->start = 0; |
2348 | r->end = 0xff; | |
2349 | } | |
2350 | } | |
2351 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
2352 | quirk_plx_pci9050); | |
2794bb28 IA |
2353 | /* |
2354 | * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) | |
2355 | * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, | |
2356 | * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, | |
2357 | * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. | |
2358 | * | |
2359 | * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" | |
2360 | * driver. | |
2361 | */ | |
2362 | DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); | |
2363 | DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); | |
21c5fd97 | 2364 | |
15856ad5 | 2365 | static void quirk_netmos(struct pci_dev *dev) |
1da177e4 LT |
2366 | { |
2367 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; | |
2368 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
2369 | ||
2370 | /* | |
2371 | * These Netmos parts are multiport serial devices with optional | |
2372 | * parallel ports. Even when parallel ports are present, they | |
2373 | * are identified as class SERIAL, which means the serial driver | |
2374 | * will claim them. To prevent this, mark them as class OTHER. | |
2375 | * These combo devices should be claimed by parport_serial. | |
2376 | * | |
2377 | * The subdevice ID is of the form 0x00PS, where <P> is the number | |
2378 | * of parallel ports and <S> is the number of serial ports. | |
2379 | */ | |
2380 | switch (dev->device) { | |
4c9c1686 JS |
2381 | case PCI_DEVICE_ID_NETMOS_9835: |
2382 | /* Well, this rule doesn't hold for the following 9835 device */ | |
2383 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && | |
2384 | dev->subsystem_device == 0x0299) | |
2385 | return; | |
df561f66 | 2386 | fallthrough; |
1da177e4 LT |
2387 | case PCI_DEVICE_ID_NETMOS_9735: |
2388 | case PCI_DEVICE_ID_NETMOS_9745: | |
1da177e4 LT |
2389 | case PCI_DEVICE_ID_NETMOS_9845: |
2390 | case PCI_DEVICE_ID_NETMOS_9855: | |
08803efe | 2391 | if (num_parallel) { |
7506dc79 | 2392 | pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", |
1da177e4 LT |
2393 | dev->device, num_parallel, num_serial); |
2394 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | | |
2395 | (dev->class & 0xff); | |
2396 | } | |
2397 | } | |
2398 | } | |
08803efe YL |
2399 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, |
2400 | PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); | |
1da177e4 | 2401 | |
15856ad5 | 2402 | static void quirk_e100_interrupt(struct pci_dev *dev) |
16a74744 | 2403 | { |
e64aeccb | 2404 | u16 command, pmcsr; |
16a74744 BH |
2405 | u8 __iomem *csr; |
2406 | u8 cmd_hi; | |
2407 | ||
2408 | switch (dev->device) { | |
2409 | /* PCI IDs taken from drivers/net/e100.c */ | |
2410 | case 0x1029: | |
2411 | case 0x1030 ... 0x1034: | |
2412 | case 0x1038 ... 0x103E: | |
2413 | case 0x1050 ... 0x1057: | |
2414 | case 0x1059: | |
2415 | case 0x1064 ... 0x106B: | |
2416 | case 0x1091 ... 0x1095: | |
2417 | case 0x1209: | |
2418 | case 0x1229: | |
2419 | case 0x2449: | |
2420 | case 0x2459: | |
2421 | case 0x245D: | |
2422 | case 0x27DC: | |
2423 | break; | |
2424 | default: | |
2425 | return; | |
2426 | } | |
2427 | ||
2428 | /* | |
2429 | * Some firmware hands off the e100 with interrupts enabled, | |
2430 | * which can cause a flood of interrupts if packets are | |
2431 | * received before the driver attaches to the device. So | |
2432 | * disable all e100 interrupts here. The driver will | |
2433 | * re-enable them when it's ready. | |
2434 | */ | |
2435 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
16a74744 | 2436 | |
1bef7dc0 | 2437 | if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
16a74744 BH |
2438 | return; |
2439 | ||
e64aeccb IK |
2440 | /* |
2441 | * Check that the device is in the D0 power state. If it's not, | |
2442 | * there is no point to look any further. | |
2443 | */ | |
728cdb75 YW |
2444 | if (dev->pm_cap) { |
2445 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
e64aeccb IK |
2446 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) |
2447 | return; | |
2448 | } | |
2449 | ||
1bef7dc0 BH |
2450 | /* Convert from PCI bus to resource space. */ |
2451 | csr = ioremap(pci_resource_start(dev, 0), 8); | |
16a74744 | 2452 | if (!csr) { |
7506dc79 | 2453 | pci_warn(dev, "Can't map e100 registers\n"); |
16a74744 BH |
2454 | return; |
2455 | } | |
2456 | ||
2457 | cmd_hi = readb(csr + 3); | |
2458 | if (cmd_hi == 0) { | |
7506dc79 | 2459 | pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); |
16a74744 BH |
2460 | writeb(1, csr + 3); |
2461 | } | |
2462 | ||
2463 | iounmap(csr); | |
2464 | } | |
4c5b28e2 YL |
2465 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
2466 | PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); | |
a5312e28 | 2467 | |
649426ef AD |
2468 | /* |
2469 | * The 82575 and 82598 may experience data corruption issues when transitioning | |
96291d56 | 2470 | * out of L0S. To prevent this we need to disable L0S on the PCIe link. |
649426ef | 2471 | */ |
15856ad5 | 2472 | static void quirk_disable_aspm_l0s(struct pci_dev *dev) |
649426ef | 2473 | { |
7506dc79 | 2474 | pci_info(dev, "Disabling L0s\n"); |
649426ef AD |
2475 | pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); |
2476 | } | |
2477 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); | |
2478 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); | |
2479 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); | |
2480 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); | |
2481 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); | |
2482 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); | |
2483 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); | |
2484 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); | |
2485 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); | |
2486 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); | |
2487 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); | |
2488 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); | |
2489 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); | |
2490 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); | |
2491 | ||
b361663c RH |
2492 | static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) |
2493 | { | |
2494 | pci_info(dev, "Disabling ASPM L0s/L1\n"); | |
2495 | pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); | |
2496 | } | |
2497 | ||
2498 | /* | |
2499 | * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the | |
2500 | * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; | |
2501 | * disable both L0s and L1 for now to be safe. | |
2502 | */ | |
2503 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); | |
2504 | ||
4ec73791 SM |
2505 | /* |
2506 | * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain | |
2507 | * Link bit cleared after starting the link retrain process to allow this | |
2508 | * process to finish. | |
2509 | * | |
2510 | * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the | |
2511 | * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. | |
2512 | */ | |
2513 | static void quirk_enable_clear_retrain_link(struct pci_dev *dev) | |
2514 | { | |
2515 | dev->clear_retrain_link = 1; | |
2516 | pci_info(dev, "Enable PCIe Retrain Link quirk\n"); | |
2517 | } | |
07a8d698 MR |
2518 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); |
2519 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); | |
2520 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); | |
4ec73791 | 2521 | |
15856ad5 | 2522 | static void fixup_rev1_53c810(struct pci_dev *dev) |
a5312e28 | 2523 | { |
e6323e3c BH |
2524 | u32 class = dev->class; |
2525 | ||
2526 | /* | |
2527 | * rev 1 ncr53c810 chips don't set the class at all which means | |
a5312e28 IK |
2528 | * they don't get their resources remapped. Fix that here. |
2529 | */ | |
e6323e3c BH |
2530 | if (class) |
2531 | return; | |
a5312e28 | 2532 | |
e6323e3c | 2533 | dev->class = PCI_CLASS_STORAGE_SCSI << 8; |
7506dc79 | 2534 | pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", |
e6323e3c | 2535 | class, dev->class); |
a5312e28 IK |
2536 | } |
2537 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); | |
2538 | ||
9d265124 | 2539 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
15856ad5 | 2540 | static void quirk_p64h2_1k_io(struct pci_dev *dev) |
9d265124 DY |
2541 | { |
2542 | u16 en1k; | |
9d265124 DY |
2543 | |
2544 | pci_read_config_word(dev, 0x40, &en1k); | |
2545 | ||
2546 | if (en1k & 0x200) { | |
7506dc79 | 2547 | pci_info(dev, "Enable I/O Space to 1KB granularity\n"); |
2b28ae19 | 2548 | dev->io_window_1k = 1; |
9d265124 DY |
2549 | } |
2550 | } | |
82e1719c | 2551 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); |
9d265124 | 2552 | |
82e1719c BH |
2553 | /* |
2554 | * Under some circumstances, AER is not linked with extended capabilities. | |
cf34a8e0 BG |
2555 | * Force it to be linked by setting the corresponding control bit in the |
2556 | * config space. | |
2557 | */ | |
1597cacb | 2558 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
cf34a8e0 BG |
2559 | { |
2560 | uint8_t b; | |
82e1719c | 2561 | |
cf34a8e0 BG |
2562 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { |
2563 | if (!(b & 0x20)) { | |
2564 | pci_write_config_byte(dev, 0xf41, b | 0x20); | |
7506dc79 | 2565 | pci_info(dev, "Linking AER extended capability\n"); |
cf34a8e0 BG |
2566 | } |
2567 | } | |
2568 | } | |
2569 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
2570 | quirk_nvidia_ck804_pcie_aer_ext_cap); | |
e1a2a51e | 2571 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
1597cacb | 2572 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
cf34a8e0 | 2573 | |
15856ad5 | 2574 | static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) |
53a9bf42 TY |
2575 | { |
2576 | /* | |
2577 | * Disable PCI Bus Parking and PCI Master read caching on CX700 | |
2578 | * which causes unspecified timing errors with a VT6212L on the PCI | |
ca846392 TY |
2579 | * bus leading to USB2.0 packet loss. |
2580 | * | |
2581 | * This quirk is only enabled if a second (on the external PCI bus) | |
2582 | * VT6212L is found -- the CX700 core itself also contains a USB | |
2583 | * host controller with the same PCI ID as the VT6212L. | |
53a9bf42 TY |
2584 | */ |
2585 | ||
ca846392 TY |
2586 | /* Count VT6212L instances */ |
2587 | struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, | |
2588 | PCI_DEVICE_ID_VIA_8235_USB_2, NULL); | |
53a9bf42 | 2589 | uint8_t b; |
ca846392 | 2590 | |
82e1719c BH |
2591 | /* |
2592 | * p should contain the first (internal) VT6212L -- see if we have | |
2593 | * an external one by searching again. | |
2594 | */ | |
ca846392 TY |
2595 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); |
2596 | if (!p) | |
2597 | return; | |
2598 | pci_dev_put(p); | |
2599 | ||
53a9bf42 TY |
2600 | if (pci_read_config_byte(dev, 0x76, &b) == 0) { |
2601 | if (b & 0x40) { | |
2602 | /* Turn off PCI Bus Parking */ | |
2603 | pci_write_config_byte(dev, 0x76, b ^ 0x40); | |
2604 | ||
7506dc79 | 2605 | pci_info(dev, "Disabling VIA CX700 PCI parking\n"); |
bc043274 TY |
2606 | } |
2607 | } | |
2608 | ||
2609 | if (pci_read_config_byte(dev, 0x72, &b) == 0) { | |
2610 | if (b != 0) { | |
53a9bf42 TY |
2611 | /* Turn off PCI Master read caching */ |
2612 | pci_write_config_byte(dev, 0x72, 0x0); | |
bc043274 TY |
2613 | |
2614 | /* Set PCI Master Bus time-out to "1x16 PCLK" */ | |
53a9bf42 | 2615 | pci_write_config_byte(dev, 0x75, 0x1); |
bc043274 TY |
2616 | |
2617 | /* Disable "Read FIFO Timer" */ | |
53a9bf42 TY |
2618 | pci_write_config_byte(dev, 0x77, 0x0); |
2619 | ||
7506dc79 | 2620 | pci_info(dev, "Disabling VIA CX700 PCI caching\n"); |
53a9bf42 TY |
2621 | } |
2622 | } | |
2623 | } | |
ca846392 | 2624 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); |
53a9bf42 | 2625 | |
25e742b2 | 2626 | static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) |
0b471506 MC |
2627 | { |
2628 | u32 rev; | |
2629 | ||
2630 | pci_read_config_dword(dev, 0xf4, &rev); | |
2631 | ||
2632 | /* Only CAP the MRRS if the device is a 5719 A0 */ | |
2633 | if (rev == 0x05719000) { | |
2634 | int readrq = pcie_get_readrq(dev); | |
2635 | if (readrq > 2048) | |
2636 | pcie_set_readrq(dev, 2048); | |
2637 | } | |
2638 | } | |
0b471506 MC |
2639 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, |
2640 | PCI_DEVICE_ID_TIGON3_5719, | |
2641 | quirk_brcm_5719_limit_mrrs); | |
2642 | ||
82e1719c BH |
2643 | /* |
2644 | * Originally in EDAC sources for i82875P: Intel tells BIOS developers to | |
2645 | * hide device 6 which configures the overflow device access containing the | |
2646 | * DRBs - this is where we expose device 6. | |
26c56dc0 MM |
2647 | * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm |
2648 | */ | |
15856ad5 | 2649 | static void quirk_unhide_mch_dev6(struct pci_dev *dev) |
26c56dc0 MM |
2650 | { |
2651 | u8 reg; | |
2652 | ||
2653 | if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { | |
7506dc79 | 2654 | pci_info(dev, "Enabling MCH 'Overflow' Device\n"); |
26c56dc0 MM |
2655 | pci_write_config_byte(dev, 0xF4, reg | 0x02); |
2656 | } | |
2657 | } | |
26c56dc0 MM |
2658 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, |
2659 | quirk_unhide_mch_dev6); | |
2660 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, | |
2661 | quirk_unhide_mch_dev6); | |
2662 | ||
3f79e107 | 2663 | #ifdef CONFIG_PCI_MSI |
82e1719c BH |
2664 | /* |
2665 | * Some chipsets do not support MSI. We cannot easily rely on setting | |
2666 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some | |
2667 | * other buses controlled by the chipset even if Linux is not aware of it. | |
2668 | * Instead of setting the flag on all buses in the machine, simply disable | |
2669 | * MSI globally. | |
3f79e107 | 2670 | */ |
15856ad5 | 2671 | static void quirk_disable_all_msi(struct pci_dev *dev) |
3f79e107 | 2672 | { |
88187dfa | 2673 | pci_no_msi(); |
7506dc79 | 2674 | pci_warn(dev, "MSI quirk detected; MSI disabled\n"); |
3f79e107 | 2675 | } |
ebdf7d39 TH |
2676 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); |
2677 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); | |
2678 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); | |
66d715c9 | 2679 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); |
184b812f | 2680 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
162dedd3 | 2681 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); |
549e1561 | 2682 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); |
10b4ad1a | 2683 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); |
778f7c19 | 2684 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); |
3f79e107 BG |
2685 | |
2686 | /* Disable MSI on chipsets that are known to not support it */ | |
15856ad5 | 2687 | static void quirk_disable_msi(struct pci_dev *dev) |
3f79e107 BG |
2688 | { |
2689 | if (dev->subordinate) { | |
7506dc79 | 2690 | pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); |
3f79e107 BG |
2691 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2692 | } | |
2693 | } | |
2694 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); | |
134b3450 | 2695 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); |
9313ff45 | 2696 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); |
6397c75c | 2697 | |
aff61369 CL |
2698 | /* |
2699 | * The APC bridge device in AMD 780 family northbridges has some random | |
2700 | * OEM subsystem ID in its vendor ID register (erratum 18), so instead | |
2701 | * we use the possible vendor/device IDs of the host bridge for the | |
2702 | * declared quirk, and search for the APC bridge by slot number. | |
2703 | */ | |
15856ad5 | 2704 | static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) |
aff61369 CL |
2705 | { |
2706 | struct pci_dev *apc_bridge; | |
2707 | ||
2708 | apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); | |
2709 | if (apc_bridge) { | |
2710 | if (apc_bridge->device == 0x9602) | |
2711 | quirk_disable_msi(apc_bridge); | |
2712 | pci_dev_put(apc_bridge); | |
2713 | } | |
2714 | } | |
2715 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); | |
2716 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); | |
2717 | ||
82e1719c BH |
2718 | /* |
2719 | * Go through the list of HyperTransport capabilities and return 1 if a HT | |
2720 | * MSI capability is found and enabled. | |
2721 | */ | |
25e742b2 | 2722 | static int msi_ht_cap_enabled(struct pci_dev *dev) |
6397c75c | 2723 | { |
fff905f3 | 2724 | int pos, ttl = PCI_FIND_CAP_TTL; |
7a380507 ME |
2725 | |
2726 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2727 | while (pos && ttl--) { | |
2728 | u8 flags; | |
2729 | ||
2730 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
3c78bc61 | 2731 | &flags) == 0) { |
7506dc79 | 2732 | pci_info(dev, "Found %s HT MSI Mapping\n", |
7a380507 | 2733 | flags & HT_MSI_FLAGS_ENABLE ? |
f0fda801 | 2734 | "enabled" : "disabled"); |
7a380507 | 2735 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; |
6397c75c | 2736 | } |
7a380507 ME |
2737 | |
2738 | pos = pci_find_next_ht_capability(dev, pos, | |
2739 | HT_CAPTYPE_MSI_MAPPING); | |
6397c75c BG |
2740 | } |
2741 | return 0; | |
2742 | } | |
2743 | ||
82e1719c | 2744 | /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ |
25e742b2 | 2745 | static void quirk_msi_ht_cap(struct pci_dev *dev) |
6397c75c | 2746 | { |
557853f4 MZ |
2747 | if (!msi_ht_cap_enabled(dev)) |
2748 | quirk_disable_msi(dev); | |
6397c75c BG |
2749 | } |
2750 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, | |
2751 | quirk_msi_ht_cap); | |
6bae1d96 | 2752 | |
82e1719c BH |
2753 | /* |
2754 | * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported | |
2755 | * if the MSI capability is set in any of these mappings. | |
6397c75c | 2756 | */ |
25e742b2 | 2757 | static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) |
6397c75c BG |
2758 | { |
2759 | struct pci_dev *pdev; | |
2760 | ||
82e1719c BH |
2761 | /* |
2762 | * Check HT MSI cap on this chipset and the root one. A single one | |
2763 | * having MSI is enough to be sure that MSI is supported. | |
6397c75c | 2764 | */ |
11f242f0 | 2765 | pdev = pci_get_slot(dev->bus, 0); |
9ac0ce85 JJ |
2766 | if (!pdev) |
2767 | return; | |
557853f4 MZ |
2768 | if (!msi_ht_cap_enabled(pdev)) |
2769 | quirk_msi_ht_cap(dev); | |
11f242f0 | 2770 | pci_dev_put(pdev); |
6397c75c BG |
2771 | } |
2772 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
2773 | quirk_nvidia_ck804_msi_ht_cap); | |
ba698ad4 | 2774 | |
415b6d0e | 2775 | /* Force enable MSI mapping capability on HT bridges */ |
25e742b2 | 2776 | static void ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e7 | 2777 | { |
fff905f3 | 2778 | int pos, ttl = PCI_FIND_CAP_TTL; |
9dc625e7 PC |
2779 | |
2780 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2781 | while (pos && ttl--) { | |
2782 | u8 flags; | |
2783 | ||
2784 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2785 | &flags) == 0) { | |
7506dc79 | 2786 | pci_info(dev, "Enabling HT MSI Mapping\n"); |
9dc625e7 PC |
2787 | |
2788 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2789 | flags | HT_MSI_FLAGS_ENABLE); | |
2790 | } | |
2791 | pos = pci_find_next_ht_capability(dev, pos, | |
2792 | HT_CAPTYPE_MSI_MAPPING); | |
2793 | } | |
2794 | } | |
415b6d0e BH |
2795 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, |
2796 | PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, | |
2797 | ht_enable_msi_mapping); | |
e0ae4f55 YL |
2798 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, |
2799 | ht_enable_msi_mapping); | |
2800 | ||
82e1719c BH |
2801 | /* |
2802 | * The P5N32-SLI motherboards from Asus have a problem with MSI | |
2803 | * for the MCP55 NIC. It is not yet determined whether the MSI problem | |
2804 | * also affects other devices. As for now, turn off MSI for this device. | |
75e07fc3 | 2805 | */ |
15856ad5 | 2806 | static void nvenet_msi_disable(struct pci_dev *dev) |
75e07fc3 | 2807 | { |
9251bac9 JD |
2808 | const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); |
2809 | ||
2810 | if (board_name && | |
2811 | (strstr(board_name, "P5N32-SLI PREMIUM") || | |
2812 | strstr(board_name, "P5N32-E SLI"))) { | |
7506dc79 | 2813 | pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); |
75e07fc3 AP |
2814 | dev->no_msi = 1; |
2815 | } | |
2816 | } | |
2817 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, | |
2818 | PCI_DEVICE_ID_NVIDIA_NVENET_15, | |
2819 | nvenet_msi_disable); | |
2820 | ||
8c7e96d3 | 2821 | /* |
bf32b8f9 VS |
2822 | * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device |
2823 | * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI | |
2824 | * interrupts for PME and AER events; instead only INTx interrupts are | |
2825 | * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts | |
b2105b9f | 2826 | * for other events, since PCIe specification doesn't support using a mix of |
8c7e96d3 VS |
2827 | * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port |
2828 | * service drivers registering their respective ISRs for MSIs. | |
2829 | */ | |
2830 | static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) | |
2831 | { | |
2832 | dev->no_msi = 1; | |
2833 | } | |
2834 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, | |
2835 | PCI_CLASS_BRIDGE_PCI, 8, | |
2836 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2837 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, | |
2838 | PCI_CLASS_BRIDGE_PCI, 8, | |
2839 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2840 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, | |
2841 | PCI_CLASS_BRIDGE_PCI, 8, | |
2842 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2843 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, | |
2844 | PCI_CLASS_BRIDGE_PCI, 8, | |
2845 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2846 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, | |
2847 | PCI_CLASS_BRIDGE_PCI, 8, | |
2848 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2849 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, | |
2850 | PCI_CLASS_BRIDGE_PCI, 8, | |
2851 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2852 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, | |
2853 | PCI_CLASS_BRIDGE_PCI, 8, | |
2854 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2855 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, | |
2856 | PCI_CLASS_BRIDGE_PCI, 8, | |
2857 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2858 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, | |
2859 | PCI_CLASS_BRIDGE_PCI, 8, | |
2860 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2861 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, | |
2862 | PCI_CLASS_BRIDGE_PCI, 8, | |
2863 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2864 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, | |
2865 | PCI_CLASS_BRIDGE_PCI, 8, | |
2866 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2867 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, | |
2868 | PCI_CLASS_BRIDGE_PCI, 8, | |
2869 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2870 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, | |
2871 | PCI_CLASS_BRIDGE_PCI, 8, | |
2872 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
bf32b8f9 VS |
2873 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, |
2874 | PCI_CLASS_BRIDGE_PCI, 8, | |
2875 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2876 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, | |
2877 | PCI_CLASS_BRIDGE_PCI, 8, | |
2878 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
2879 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, | |
2880 | PCI_CLASS_BRIDGE_PCI, 8, | |
2881 | pci_quirk_nvidia_tegra_disable_rp_msi); | |
8c7e96d3 | 2882 | |
66db60ea | 2883 | /* |
f7625980 BH |
2884 | * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing |
2885 | * config register. This register controls the routing of legacy | |
2886 | * interrupts from devices that route through the MCP55. If this register | |
2887 | * is misprogrammed, interrupts are only sent to the BSP, unlike | |
2888 | * conventional systems where the IRQ is broadcast to all online CPUs. Not | |
2889 | * having this register set properly prevents kdump from booting up | |
2890 | * properly, so let's make sure that we have it set correctly. | |
2891 | * Note that this is an undocumented register. | |
66db60ea | 2892 | */ |
15856ad5 | 2893 | static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) |
66db60ea NH |
2894 | { |
2895 | u32 cfg; | |
2896 | ||
49c2fa08 NH |
2897 | if (!pci_find_capability(dev, PCI_CAP_ID_HT)) |
2898 | return; | |
2899 | ||
66db60ea NH |
2900 | pci_read_config_dword(dev, 0x74, &cfg); |
2901 | ||
2902 | if (cfg & ((1 << 2) | (1 << 15))) { | |
25da8dba | 2903 | pr_info("Rewriting IRQ routing register on MCP55\n"); |
66db60ea NH |
2904 | cfg &= ~((1 << 2) | (1 << 15)); |
2905 | pci_write_config_dword(dev, 0x74, cfg); | |
2906 | } | |
2907 | } | |
66db60ea NH |
2908 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, |
2909 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, | |
2910 | nvbridge_check_legacy_irq_routing); | |
66db60ea NH |
2911 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, |
2912 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, | |
2913 | nvbridge_check_legacy_irq_routing); | |
2914 | ||
25e742b2 | 2915 | static int ht_check_msi_mapping(struct pci_dev *dev) |
de745306 | 2916 | { |
fff905f3 | 2917 | int pos, ttl = PCI_FIND_CAP_TTL; |
de745306 YL |
2918 | int found = 0; |
2919 | ||
82e1719c | 2920 | /* Check if there is HT MSI cap or enabled on this device */ |
de745306 YL |
2921 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
2922 | while (pos && ttl--) { | |
2923 | u8 flags; | |
2924 | ||
2925 | if (found < 1) | |
2926 | found = 1; | |
2927 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2928 | &flags) == 0) { | |
2929 | if (flags & HT_MSI_FLAGS_ENABLE) { | |
2930 | if (found < 2) { | |
2931 | found = 2; | |
2932 | break; | |
2933 | } | |
2934 | } | |
2935 | } | |
2936 | pos = pci_find_next_ht_capability(dev, pos, | |
2937 | HT_CAPTYPE_MSI_MAPPING); | |
2938 | } | |
2939 | ||
2940 | return found; | |
2941 | } | |
2942 | ||
25e742b2 | 2943 | static int host_bridge_with_leaf(struct pci_dev *host_bridge) |
de745306 YL |
2944 | { |
2945 | struct pci_dev *dev; | |
2946 | int pos; | |
2947 | int i, dev_no; | |
2948 | int found = 0; | |
2949 | ||
2950 | dev_no = host_bridge->devfn >> 3; | |
2951 | for (i = dev_no + 1; i < 0x20; i++) { | |
2952 | dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); | |
2953 | if (!dev) | |
2954 | continue; | |
2955 | ||
82e1719c | 2956 | /* found next host bridge? */ |
de745306 YL |
2957 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); |
2958 | if (pos != 0) { | |
2959 | pci_dev_put(dev); | |
2960 | break; | |
2961 | } | |
2962 | ||
2963 | if (ht_check_msi_mapping(dev)) { | |
2964 | found = 1; | |
2965 | pci_dev_put(dev); | |
2966 | break; | |
2967 | } | |
2968 | pci_dev_put(dev); | |
2969 | } | |
2970 | ||
2971 | return found; | |
2972 | } | |
2973 | ||
eeafda70 YL |
2974 | #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ |
2975 | #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ | |
2976 | ||
25e742b2 | 2977 | static int is_end_of_ht_chain(struct pci_dev *dev) |
eeafda70 YL |
2978 | { |
2979 | int pos, ctrl_off; | |
2980 | int end = 0; | |
2981 | u16 flags, ctrl; | |
2982 | ||
2983 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); | |
2984 | ||
2985 | if (!pos) | |
2986 | goto out; | |
2987 | ||
2988 | pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); | |
2989 | ||
2990 | ctrl_off = ((flags >> 10) & 1) ? | |
2991 | PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; | |
2992 | pci_read_config_word(dev, pos + ctrl_off, &ctrl); | |
2993 | ||
2994 | if (ctrl & (1 << 6)) | |
2995 | end = 1; | |
2996 | ||
2997 | out: | |
2998 | return end; | |
2999 | } | |
3000 | ||
25e742b2 | 3001 | static void nv_ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e7 PC |
3002 | { |
3003 | struct pci_dev *host_bridge; | |
1dec6b05 YL |
3004 | int pos; |
3005 | int i, dev_no; | |
3006 | int found = 0; | |
3007 | ||
3008 | dev_no = dev->devfn >> 3; | |
3009 | for (i = dev_no; i >= 0; i--) { | |
3010 | host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); | |
3011 | if (!host_bridge) | |
3012 | continue; | |
3013 | ||
3014 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
3015 | if (pos != 0) { | |
3016 | found = 1; | |
3017 | break; | |
3018 | } | |
3019 | pci_dev_put(host_bridge); | |
3020 | } | |
3021 | ||
3022 | if (!found) | |
3023 | return; | |
3024 | ||
eeafda70 YL |
3025 | /* don't enable end_device/host_bridge with leaf directly here */ |
3026 | if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && | |
3027 | host_bridge_with_leaf(host_bridge)) | |
de745306 YL |
3028 | goto out; |
3029 | ||
1dec6b05 YL |
3030 | /* root did that ! */ |
3031 | if (msi_ht_cap_enabled(host_bridge)) | |
3032 | goto out; | |
3033 | ||
3034 | ht_enable_msi_mapping(dev); | |
3035 | ||
3036 | out: | |
3037 | pci_dev_put(host_bridge); | |
3038 | } | |
3039 | ||
25e742b2 | 3040 | static void ht_disable_msi_mapping(struct pci_dev *dev) |
1dec6b05 | 3041 | { |
fff905f3 | 3042 | int pos, ttl = PCI_FIND_CAP_TTL; |
1dec6b05 YL |
3043 | |
3044 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
3045 | while (pos && ttl--) { | |
3046 | u8 flags; | |
3047 | ||
3048 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
3049 | &flags) == 0) { | |
7506dc79 | 3050 | pci_info(dev, "Disabling HT MSI Mapping\n"); |
1dec6b05 YL |
3051 | |
3052 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
3053 | flags & ~HT_MSI_FLAGS_ENABLE); | |
3054 | } | |
3055 | pos = pci_find_next_ht_capability(dev, pos, | |
3056 | HT_CAPTYPE_MSI_MAPPING); | |
3057 | } | |
3058 | } | |
3059 | ||
25e742b2 | 3060 | static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) |
1dec6b05 YL |
3061 | { |
3062 | struct pci_dev *host_bridge; | |
3063 | int pos; | |
3064 | int found; | |
3065 | ||
3d2a5318 RW |
3066 | if (!pci_msi_enabled()) |
3067 | return; | |
3068 | ||
1dec6b05 YL |
3069 | /* check if there is HT MSI cap or enabled on this device */ |
3070 | found = ht_check_msi_mapping(dev); | |
3071 | ||
3072 | /* no HT MSI CAP */ | |
3073 | if (found == 0) | |
3074 | return; | |
9dc625e7 PC |
3075 | |
3076 | /* | |
3077 | * HT MSI mapping should be disabled on devices that are below | |
86b4ad7d | 3078 | * a non-HyperTransport host bridge. Locate the host bridge. |
9dc625e7 | 3079 | */ |
39c94652 SK |
3080 | host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, |
3081 | PCI_DEVFN(0, 0)); | |
9dc625e7 | 3082 | if (host_bridge == NULL) { |
7506dc79 | 3083 | pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); |
9dc625e7 PC |
3084 | return; |
3085 | } | |
3086 | ||
3087 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
3088 | if (pos != 0) { | |
3089 | /* Host bridge is to HT */ | |
1dec6b05 YL |
3090 | if (found == 1) { |
3091 | /* it is not enabled, try to enable it */ | |
de745306 YL |
3092 | if (all) |
3093 | ht_enable_msi_mapping(dev); | |
3094 | else | |
3095 | nv_ht_enable_msi_mapping(dev); | |
1dec6b05 | 3096 | } |
dff3aef7 | 3097 | goto out; |
9dc625e7 PC |
3098 | } |
3099 | ||
1dec6b05 YL |
3100 | /* HT MSI is not enabled */ |
3101 | if (found == 1) | |
dff3aef7 | 3102 | goto out; |
9dc625e7 | 3103 | |
1dec6b05 YL |
3104 | /* Host bridge is not to HT, disable HT MSI mapping on this device */ |
3105 | ht_disable_msi_mapping(dev); | |
dff3aef7 MS |
3106 | |
3107 | out: | |
3108 | pci_dev_put(host_bridge); | |
9dc625e7 | 3109 | } |
de745306 | 3110 | |
25e742b2 | 3111 | static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) |
de745306 YL |
3112 | { |
3113 | return __nv_msi_ht_cap_quirk(dev, 1); | |
3114 | } | |
82e1719c BH |
3115 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
3116 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); | |
de745306 | 3117 | |
25e742b2 | 3118 | static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) |
de745306 YL |
3119 | { |
3120 | return __nv_msi_ht_cap_quirk(dev, 0); | |
3121 | } | |
de745306 | 3122 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
6dab62ee | 3123 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
de745306 | 3124 | |
15856ad5 | 3125 | static void quirk_msi_intx_disable_bug(struct pci_dev *dev) |
ba698ad4 DM |
3126 | { |
3127 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
3128 | } | |
82e1719c | 3129 | |
15856ad5 | 3130 | static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) |
4600c9d7 SH |
3131 | { |
3132 | struct pci_dev *p; | |
3133 | ||
82e1719c BH |
3134 | /* |
3135 | * SB700 MSI issue will be fixed at HW level from revision A21; | |
4600c9d7 SH |
3136 | * we need check PCI REVISION ID of SMBus controller to get SB700 |
3137 | * revision. | |
3138 | */ | |
3139 | p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
3140 | NULL); | |
3141 | if (!p) | |
3142 | return; | |
3143 | ||
3144 | if ((p->revision < 0x3B) && (p->revision >= 0x30)) | |
3145 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
3146 | pci_dev_put(p); | |
3147 | } | |
82e1719c | 3148 | |
70588818 XH |
3149 | static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) |
3150 | { | |
3151 | /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ | |
3152 | if (dev->revision < 0x18) { | |
7506dc79 | 3153 | pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); |
70588818 XH |
3154 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; |
3155 | } | |
3156 | } | |
ba698ad4 DM |
3157 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
3158 | PCI_DEVICE_ID_TIGON3_5780, | |
3159 | quirk_msi_intx_disable_bug); | |
3160 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
3161 | PCI_DEVICE_ID_TIGON3_5780S, | |
3162 | quirk_msi_intx_disable_bug); | |
3163 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
3164 | PCI_DEVICE_ID_TIGON3_5714, | |
3165 | quirk_msi_intx_disable_bug); | |
3166 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
3167 | PCI_DEVICE_ID_TIGON3_5714S, | |
3168 | quirk_msi_intx_disable_bug); | |
3169 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
3170 | PCI_DEVICE_ID_TIGON3_5715, | |
3171 | quirk_msi_intx_disable_bug); | |
3172 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
3173 | PCI_DEVICE_ID_TIGON3_5715S, | |
3174 | quirk_msi_intx_disable_bug); | |
3175 | ||
bc38b411 | 3176 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
4600c9d7 | 3177 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 3178 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, |
4600c9d7 | 3179 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 3180 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, |
4600c9d7 | 3181 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 3182 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, |
4600c9d7 | 3183 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 3184 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, |
4600c9d7 | 3185 | quirk_msi_intx_disable_ati_bug); |
bc38b411 DM |
3186 | |
3187 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, | |
3188 | quirk_msi_intx_disable_bug); | |
3189 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, | |
3190 | quirk_msi_intx_disable_bug); | |
3191 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, | |
3192 | quirk_msi_intx_disable_bug); | |
3193 | ||
7cb6a291 HX |
3194 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, |
3195 | quirk_msi_intx_disable_bug); | |
3196 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, | |
3197 | quirk_msi_intx_disable_bug); | |
3198 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, | |
3199 | quirk_msi_intx_disable_bug); | |
3200 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, | |
3201 | quirk_msi_intx_disable_bug); | |
3202 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, | |
3203 | quirk_msi_intx_disable_bug); | |
3204 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, | |
3205 | quirk_msi_intx_disable_bug); | |
70588818 XH |
3206 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, |
3207 | quirk_msi_intx_disable_qca_bug); | |
3208 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, | |
3209 | quirk_msi_intx_disable_qca_bug); | |
3210 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, | |
3211 | quirk_msi_intx_disable_qca_bug); | |
3212 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, | |
3213 | quirk_msi_intx_disable_qca_bug); | |
3214 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, | |
3215 | quirk_msi_intx_disable_qca_bug); | |
738cb37b JC |
3216 | |
3217 | /* | |
3218 | * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it | |
3219 | * should be disabled on platforms where the device (mistakenly) advertises it. | |
3220 | * | |
3221 | * Notice that this quirk also disables MSI (which may work, but hasn't been | |
3222 | * tested), since currently there is no standard way to disable only MSI-X. | |
3223 | * | |
3224 | * The 0031 device id is reused for other non Root Port device types, | |
3225 | * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. | |
3226 | */ | |
3227 | static void quirk_al_msi_disable(struct pci_dev *dev) | |
3228 | { | |
3229 | dev->no_msi = 1; | |
3230 | pci_warn(dev, "Disabling MSI/MSI-X\n"); | |
3231 | } | |
3232 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, | |
3233 | PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); | |
3f79e107 | 3234 | #endif /* CONFIG_PCI_MSI */ |
3d137310 | 3235 | |
82e1719c BH |
3236 | /* |
3237 | * Allow manual resource allocation for PCI hotplug bridges via | |
3238 | * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI | |
3239 | * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to | |
3240 | * allocate resources when hotplug device is inserted and PCI bus is | |
3241 | * rescanned. | |
3322340a | 3242 | */ |
15856ad5 | 3243 | static void quirk_hotplug_bridge(struct pci_dev *dev) |
3322340a FR |
3244 | { |
3245 | dev->is_hotplug_bridge = 1; | |
3246 | } | |
3322340a FR |
3247 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); |
3248 | ||
03cd8f7e | 3249 | /* |
82e1719c BH |
3250 | * This is a quirk for the Ricoh MMC controller found as a part of some |
3251 | * multifunction chips. | |
3252 | * | |
25985edc | 3253 | * This is very similar and based on the ricoh_mmc driver written by |
03cd8f7e ML |
3254 | * Philip Langdale. Thank you for these magic sequences. |
3255 | * | |
82e1719c BH |
3256 | * These chips implement the four main memory card controllers (SD, MMC, |
3257 | * MS, xD) and one or both of CardBus or FireWire. | |
03cd8f7e | 3258 | * |
82e1719c BH |
3259 | * It happens that they implement SD and MMC support as separate |
3260 | * controllers (and PCI functions). The Linux SDHCI driver supports MMC | |
3261 | * cards but the chip detects MMC cards in hardware and directs them to the | |
3262 | * MMC controller - so the SDHCI driver never sees them. | |
03cd8f7e | 3263 | * |
82e1719c BH |
3264 | * To get around this, we must disable the useless MMC controller. At that |
3265 | * point, the SDHCI controller will start seeing them. It seems to be the | |
3266 | * case that the relevant PCI registers to deactivate the MMC controller | |
3267 | * live on PCI function 0, which might be the CardBus controller or the | |
3268 | * FireWire controller, depending on the particular chip in question | |
03cd8f7e ML |
3269 | * |
3270 | * This has to be done early, because as soon as we disable the MMC controller | |
82e1719c BH |
3271 | * other PCI functions shift up one level, e.g. function #2 becomes function |
3272 | * #1, and this will confuse the PCI core. | |
03cd8f7e | 3273 | */ |
03cd8f7e ML |
3274 | #ifdef CONFIG_MMC_RICOH_MMC |
3275 | static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) | |
3276 | { | |
03cd8f7e ML |
3277 | u8 write_enable; |
3278 | u8 write_target; | |
3279 | u8 disable; | |
3280 | ||
82e1719c BH |
3281 | /* |
3282 | * Disable via CardBus interface | |
3283 | * | |
3284 | * This must be done via function #0 | |
3285 | */ | |
03cd8f7e ML |
3286 | if (PCI_FUNC(dev->devfn)) |
3287 | return; | |
3288 | ||
3289 | pci_read_config_byte(dev, 0xB7, &disable); | |
3290 | if (disable & 0x02) | |
3291 | return; | |
3292 | ||
3293 | pci_read_config_byte(dev, 0x8E, &write_enable); | |
3294 | pci_write_config_byte(dev, 0x8E, 0xAA); | |
3295 | pci_read_config_byte(dev, 0x8D, &write_target); | |
3296 | pci_write_config_byte(dev, 0x8D, 0xB7); | |
3297 | pci_write_config_byte(dev, 0xB7, disable | 0x02); | |
3298 | pci_write_config_byte(dev, 0x8E, write_enable); | |
3299 | pci_write_config_byte(dev, 0x8D, write_target); | |
3300 | ||
82e1719c | 3301 | pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); |
7506dc79 | 3302 | pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); |
03cd8f7e ML |
3303 | } |
3304 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); | |
3305 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); | |
3306 | ||
3307 | static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) | |
3308 | { | |
03cd8f7e ML |
3309 | u8 write_enable; |
3310 | u8 disable; | |
3311 | ||
82e1719c BH |
3312 | /* |
3313 | * Disable via FireWire interface | |
3314 | * | |
3315 | * This must be done via function #0 | |
3316 | */ | |
03cd8f7e ML |
3317 | if (PCI_FUNC(dev->devfn)) |
3318 | return; | |
15bed0f2 | 3319 | /* |
812089e0 | 3320 | * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize |
82e1719c BH |
3321 | * certain types of SD/MMC cards. Lowering the SD base clock |
3322 | * frequency from 200Mhz to 50Mhz fixes this issue. | |
15bed0f2 MI |
3323 | * |
3324 | * 0x150 - SD2.0 mode enable for changing base clock | |
3325 | * frequency to 50Mhz | |
3326 | * 0xe1 - Base clock frequency | |
3327 | * 0x32 - 50Mhz new clock frequency | |
3328 | * 0xf9 - Key register for 0x150 | |
3329 | * 0xfc - key register for 0xe1 | |
3330 | */ | |
812089e0 AL |
3331 | if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || |
3332 | dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { | |
15bed0f2 MI |
3333 | pci_write_config_byte(dev, 0xf9, 0xfc); |
3334 | pci_write_config_byte(dev, 0x150, 0x10); | |
3335 | pci_write_config_byte(dev, 0xf9, 0x00); | |
3336 | pci_write_config_byte(dev, 0xfc, 0x01); | |
3337 | pci_write_config_byte(dev, 0xe1, 0x32); | |
3338 | pci_write_config_byte(dev, 0xfc, 0x00); | |
3339 | ||
7506dc79 | 3340 | pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); |
15bed0f2 | 3341 | } |
3e309cdf JB |
3342 | |
3343 | pci_read_config_byte(dev, 0xCB, &disable); | |
3344 | ||
3345 | if (disable & 0x02) | |
3346 | return; | |
3347 | ||
3348 | pci_read_config_byte(dev, 0xCA, &write_enable); | |
3349 | pci_write_config_byte(dev, 0xCA, 0x57); | |
3350 | pci_write_config_byte(dev, 0xCB, disable | 0x02); | |
3351 | pci_write_config_byte(dev, 0xCA, write_enable); | |
3352 | ||
82e1719c | 3353 | pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); |
7506dc79 | 3354 | pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); |
3e309cdf | 3355 | |
03cd8f7e ML |
3356 | } |
3357 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); | |
3358 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); | |
812089e0 AL |
3359 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); |
3360 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); | |
be98ca65 MI |
3361 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); |
3362 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); | |
03cd8f7e ML |
3363 | #endif /*CONFIG_MMC_RICOH_MMC*/ |
3364 | ||
d3f13810 | 3365 | #ifdef CONFIG_DMAR_TABLE |
254e4200 SS |
3366 | #define VTUNCERRMSK_REG 0x1ac |
3367 | #define VTD_MSK_SPEC_ERRORS (1 << 31) | |
3368 | /* | |
82e1719c BH |
3369 | * This is a quirk for masking VT-d spec-defined errors to platform error |
3370 | * handling logic. Without this, platforms using Intel 7500, 5500 chipsets | |
254e4200 | 3371 | * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based |
82e1719c | 3372 | * on the RAS config settings of the platform) when a VT-d fault happens. |
254e4200 SS |
3373 | * The resulting SMI caused the system to hang. |
3374 | * | |
82e1719c | 3375 | * VT-d spec-related errors are already handled by the VT-d OS code, so no |
254e4200 SS |
3376 | * need to report the same error through other channels. |
3377 | */ | |
3378 | static void vtd_mask_spec_errors(struct pci_dev *dev) | |
3379 | { | |
3380 | u32 word; | |
3381 | ||
3382 | pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); | |
3383 | pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); | |
3384 | } | |
3385 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); | |
3386 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); | |
3387 | #endif | |
03cd8f7e | 3388 | |
15856ad5 | 3389 | static void fixup_ti816x_class(struct pci_dev *dev) |
63c44080 | 3390 | { |
d1541dc9 BH |
3391 | u32 class = dev->class; |
3392 | ||
63c44080 | 3393 | /* TI 816x devices do not have class code set when in PCIe boot mode */ |
d1541dc9 | 3394 | dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; |
7506dc79 | 3395 | pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", |
d1541dc9 | 3396 | class, dev->class); |
63c44080 | 3397 | } |
40c96236 | 3398 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, |
2b4aed1d | 3399 | PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); |
63c44080 | 3400 | |
82e1719c BH |
3401 | /* |
3402 | * Some PCIe devices do not work reliably with the claimed maximum | |
a94d072b BH |
3403 | * payload size supported. |
3404 | */ | |
15856ad5 | 3405 | static void fixup_mpss_256(struct pci_dev *dev) |
a94d072b BH |
3406 | { |
3407 | dev->pcie_mpss = 1; /* 256 bytes */ | |
3408 | } | |
b8da302e MB |
3409 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, |
3410 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); | |
3411 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, | |
3412 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); | |
3413 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, | |
3414 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); | |
b12d93e9 | 3415 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); |
a94d072b | 3416 | |
82e1719c BH |
3417 | /* |
3418 | * Intel 5000 and 5100 Memory controllers have an erratum with read completion | |
d387a8d6 | 3419 | * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. |
82e1719c | 3420 | * Since there is no way of knowing what the PCIe MPS on each fabric will be |
d387a8d6 JM |
3421 | * until all of the devices are discovered and buses walked, read completion |
3422 | * coalescing must be disabled. Unfortunately, it cannot be re-enabled because | |
3423 | * it is possible to hotplug a device with MPS of 256B. | |
3424 | */ | |
15856ad5 | 3425 | static void quirk_intel_mc_errata(struct pci_dev *dev) |
d387a8d6 JM |
3426 | { |
3427 | int err; | |
3428 | u16 rcc; | |
3429 | ||
27d868b5 KB |
3430 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF || |
3431 | pcie_bus_config == PCIE_BUS_DEFAULT) | |
d387a8d6 JM |
3432 | return; |
3433 | ||
82e1719c BH |
3434 | /* |
3435 | * Intel erratum specifies bits to change but does not say what | |
3436 | * they are. Keeping them magical until such time as the registers | |
3437 | * and values can be explained. | |
d387a8d6 JM |
3438 | */ |
3439 | err = pci_read_config_word(dev, 0x48, &rcc); | |
3440 | if (err) { | |
7506dc79 | 3441 | pci_err(dev, "Error attempting to read the read completion coalescing register\n"); |
d387a8d6 JM |
3442 | return; |
3443 | } | |
3444 | ||
3445 | if (!(rcc & (1 << 10))) | |
3446 | return; | |
3447 | ||
3448 | rcc &= ~(1 << 10); | |
3449 | ||
3450 | err = pci_write_config_word(dev, 0x48, rcc); | |
3451 | if (err) { | |
7506dc79 | 3452 | pci_err(dev, "Error attempting to write the read completion coalescing register\n"); |
d387a8d6 JM |
3453 | return; |
3454 | } | |
3455 | ||
82e1719c | 3456 | pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); |
d387a8d6 JM |
3457 | } |
3458 | /* Intel 5000 series memory controllers and ports 2-7 */ | |
3459 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); | |
3460 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); | |
3461 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); | |
3462 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); | |
3463 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); | |
3464 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); | |
3465 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); | |
3466 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); | |
3467 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); | |
3468 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); | |
3469 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); | |
3470 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); | |
3471 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); | |
3472 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); | |
3473 | /* Intel 5100 series memory controllers and ports 2-7 */ | |
3474 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); | |
3475 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); | |
3476 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); | |
3477 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); | |
3478 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); | |
3479 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); | |
3480 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); | |
3481 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); | |
3482 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); | |
3483 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); | |
3484 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); | |
3485 | ||
12b03188 | 3486 | /* |
82e1719c BH |
3487 | * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. |
3488 | * To work around this, query the size it should be configured to by the | |
3489 | * device and modify the resource end to correspond to this new size. | |
12b03188 JM |
3490 | */ |
3491 | static void quirk_intel_ntb(struct pci_dev *dev) | |
3492 | { | |
3493 | int rc; | |
3494 | u8 val; | |
3495 | ||
3496 | rc = pci_read_config_byte(dev, 0x00D0, &val); | |
3497 | if (rc) | |
3498 | return; | |
3499 | ||
3500 | dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; | |
3501 | ||
3502 | rc = pci_read_config_byte(dev, 0x00D1, &val); | |
3503 | if (rc) | |
3504 | return; | |
3505 | ||
3506 | dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; | |
3507 | } | |
3508 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); | |
3509 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); | |
3510 | ||
f67fd55f | 3511 | /* |
82e1719c BH |
3512 | * Some BIOS implementations leave the Intel GPU interrupts enabled, even |
3513 | * though no one is handling them (e.g., if the i915 driver is never | |
3514 | * loaded). Additionally the interrupt destination is not set up properly | |
f67fd55f TJ |
3515 | * and the interrupt ends up -somewhere-. |
3516 | * | |
82e1719c BH |
3517 | * These spurious interrupts are "sticky" and the kernel disables the |
3518 | * (shared) interrupt line after 100,000+ generated interrupts. | |
f67fd55f | 3519 | * |
82e1719c BH |
3520 | * Fix it by disabling the still enabled interrupts. This resolves crashes |
3521 | * often seen on monitor unplug. | |
f67fd55f TJ |
3522 | */ |
3523 | #define I915_DEIER_REG 0x4400c | |
15856ad5 | 3524 | static void disable_igfx_irq(struct pci_dev *dev) |
f67fd55f TJ |
3525 | { |
3526 | void __iomem *regs = pci_iomap(dev, 0, 0); | |
3527 | if (regs == NULL) { | |
7506dc79 | 3528 | pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); |
f67fd55f TJ |
3529 | return; |
3530 | } | |
3531 | ||
3532 | /* Check if any interrupt line is still enabled */ | |
3533 | if (readl(regs + I915_DEIER_REG) != 0) { | |
7506dc79 | 3534 | pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); |
f67fd55f TJ |
3535 | |
3536 | writel(0, regs + I915_DEIER_REG); | |
3537 | } | |
3538 | ||
3539 | pci_iounmap(dev, regs); | |
3540 | } | |
d0c9606b BM |
3541 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); |
3542 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); | |
3543 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); | |
f67fd55f | 3544 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); |
d0c9606b | 3545 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); |
f67fd55f | 3546 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); |
7c82126a | 3547 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); |
f67fd55f | 3548 | |
b8cac70a TB |
3549 | /* |
3550 | * PCI devices which are on Intel chips can skip the 10ms delay | |
3551 | * before entering D3 mode. | |
3552 | */ | |
3789af9a KW |
3553 | static void quirk_remove_d3hot_delay(struct pci_dev *dev) |
3554 | { | |
3555 | dev->d3hot_delay = 0; | |
3556 | } | |
3557 | /* C600 Series devices do not need 10ms d3hot_delay */ | |
3558 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); | |
3559 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); | |
3560 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); | |
3561 | /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ | |
3562 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); | |
3563 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); | |
3564 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); | |
3565 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); | |
3566 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); | |
3567 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); | |
3568 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); | |
3569 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); | |
3570 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); | |
3571 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); | |
3572 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); | |
3573 | /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ | |
3574 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); | |
3575 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); | |
3576 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); | |
3577 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); | |
3578 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); | |
3579 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); | |
3580 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); | |
3581 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); | |
3582 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); | |
d76d2fe0 | 3583 | |
fbebb9fd | 3584 | /* |
d76d2fe0 | 3585 | * Some devices may pass our check in pci_intx_mask_supported() if |
fbebb9fd BH |
3586 | * PCI_COMMAND_INTX_DISABLE works though they actually do not properly |
3587 | * support this feature. | |
3588 | */ | |
15856ad5 | 3589 | static void quirk_broken_intx_masking(struct pci_dev *dev) |
fbebb9fd BH |
3590 | { |
3591 | dev->broken_intx_masking = 1; | |
3592 | } | |
b88214ce NO |
3593 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, |
3594 | quirk_broken_intx_masking); | |
3595 | DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ | |
3596 | quirk_broken_intx_masking); | |
7c1efb68 BH |
3597 | DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ |
3598 | quirk_broken_intx_masking); | |
d76d2fe0 | 3599 | |
3cb30b73 AW |
3600 | /* |
3601 | * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) | |
3602 | * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC | |
3603 | * | |
3604 | * RTL8110SC - Fails under PCI device assignment using DisINTx masking. | |
3605 | */ | |
b88214ce NO |
3606 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, |
3607 | quirk_broken_intx_masking); | |
fbebb9fd | 3608 | |
8bcf4525 AW |
3609 | /* |
3610 | * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, | |
3611 | * DisINTx can be set but the interrupt status bit is non-functional. | |
3612 | */ | |
82e1719c BH |
3613 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); |
3614 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); | |
3615 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); | |
3616 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); | |
3617 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); | |
3618 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); | |
3619 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); | |
3620 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); | |
3621 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); | |
3622 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); | |
3623 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); | |
3624 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); | |
3625 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); | |
3626 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); | |
3627 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); | |
3628 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); | |
8bcf4525 | 3629 | |
d76d2fe0 NO |
3630 | static u16 mellanox_broken_intx_devs[] = { |
3631 | PCI_DEVICE_ID_MELLANOX_HERMON_SDR, | |
3632 | PCI_DEVICE_ID_MELLANOX_HERMON_DDR, | |
3633 | PCI_DEVICE_ID_MELLANOX_HERMON_QDR, | |
3634 | PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, | |
3635 | PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, | |
3636 | PCI_DEVICE_ID_MELLANOX_HERMON_EN, | |
3637 | PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, | |
3638 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, | |
3639 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, | |
3640 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, | |
3641 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, | |
3642 | PCI_DEVICE_ID_MELLANOX_CONNECTX2, | |
3643 | PCI_DEVICE_ID_MELLANOX_CONNECTX3, | |
3644 | PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, | |
d76d2fe0 NO |
3645 | }; |
3646 | ||
1600f625 NO |
3647 | #define CONNECTX_4_CURR_MAX_MINOR 99 |
3648 | #define CONNECTX_4_INTX_SUPPORT_MINOR 14 | |
3649 | ||
3650 | /* | |
3651 | * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. | |
3652 | * If so, don't mark it as broken. | |
3653 | * FW minor > 99 means older FW version format and no INTx masking support. | |
3654 | * FW minor < 14 means new FW version format and no INTx masking support. | |
3655 | */ | |
d76d2fe0 NO |
3656 | static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) |
3657 | { | |
1600f625 NO |
3658 | __be32 __iomem *fw_ver; |
3659 | u16 fw_major; | |
3660 | u16 fw_minor; | |
3661 | u16 fw_subminor; | |
3662 | u32 fw_maj_min; | |
3663 | u32 fw_sub_min; | |
d76d2fe0 NO |
3664 | int i; |
3665 | ||
3666 | for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { | |
3667 | if (pdev->device == mellanox_broken_intx_devs[i]) { | |
3668 | pdev->broken_intx_masking = 1; | |
3669 | return; | |
3670 | } | |
3671 | } | |
1600f625 | 3672 | |
82e1719c BH |
3673 | /* |
3674 | * Getting here means Connect-IB cards and up. Connect-IB has no INTx | |
1600f625 NO |
3675 | * support so shouldn't be checked further |
3676 | */ | |
3677 | if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) | |
3678 | return; | |
3679 | ||
3680 | if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && | |
3681 | pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) | |
3682 | return; | |
3683 | ||
3684 | /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ | |
3685 | if (pci_enable_device_mem(pdev)) { | |
7506dc79 | 3686 | pci_warn(pdev, "Can't enable device memory\n"); |
1600f625 NO |
3687 | return; |
3688 | } | |
3689 | ||
3690 | fw_ver = ioremap(pci_resource_start(pdev, 0), 4); | |
3691 | if (!fw_ver) { | |
7506dc79 | 3692 | pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); |
1600f625 NO |
3693 | goto out; |
3694 | } | |
3695 | ||
3696 | /* Reading from resource space should be 32b aligned */ | |
3697 | fw_maj_min = ioread32be(fw_ver); | |
3698 | fw_sub_min = ioread32be(fw_ver + 1); | |
3699 | fw_major = fw_maj_min & 0xffff; | |
3700 | fw_minor = fw_maj_min >> 16; | |
3701 | fw_subminor = fw_sub_min & 0xffff; | |
3702 | if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || | |
3703 | fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { | |
7506dc79 | 3704 | pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", |
1600f625 NO |
3705 | fw_major, fw_minor, fw_subminor, pdev->device == |
3706 | PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); | |
3707 | pdev->broken_intx_masking = 1; | |
3708 | } | |
3709 | ||
3710 | iounmap(fw_ver); | |
3711 | ||
3712 | out: | |
3713 | pci_disable_device(pdev); | |
d76d2fe0 NO |
3714 | } |
3715 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, | |
3716 | mellanox_check_broken_intx_masking); | |
8bcf4525 | 3717 | |
c3e59ee4 AW |
3718 | static void quirk_no_bus_reset(struct pci_dev *dev) |
3719 | { | |
3720 | dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; | |
3721 | } | |
3722 | ||
4c207e71 SD |
3723 | /* |
3724 | * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be | |
3725 | * prevented for those affected devices. | |
3726 | */ | |
3727 | static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) | |
3728 | { | |
d5af729d | 3729 | if ((dev->device & 0xffc0) == 0x2340 || dev->device == 0x1eb8) |
4c207e71 SD |
3730 | quirk_no_bus_reset(dev); |
3731 | } | |
3732 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, | |
3733 | quirk_nvidia_no_bus_reset); | |
3734 | ||
c3e59ee4 | 3735 | /* |
9ac0108c CB |
3736 | * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. |
3737 | * The device will throw a Link Down error on AER-capable systems and | |
3738 | * regardless of AER, config space of the device is never accessible again | |
3739 | * and typically causes the system to hang or reset when access is attempted. | |
16bbbc87 | 3740 | * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ |
c3e59ee4 AW |
3741 | */ |
3742 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); | |
9ac0108c CB |
3743 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); |
3744 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); | |
8e2e0317 | 3745 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); |
6afb7e26 | 3746 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); |
e3f4bd34 | 3747 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); |
c3e59ee4 | 3748 | |
82215510 DD |
3749 | /* |
3750 | * Root port on some Cavium CN8xxx chips do not successfully complete a bus | |
3751 | * reset when used with certain child devices. After the reset, config | |
3752 | * accesses to the child may fail. | |
3753 | */ | |
3754 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); | |
3755 | ||
b5cf198e AJ |
3756 | /* |
3757 | * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS | |
3758 | * automatically disables LTSSM when Secondary Bus Reset is received and | |
3759 | * the device stops working. Prevent bus reset for these devices. With | |
3760 | * this change, the device can be assigned to VMs with VFIO, but it will | |
3761 | * leak state between VMs. Reference | |
3762 | * https://e2e.ti.com/support/processors/f/791/t/954382 | |
3763 | */ | |
3764 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); | |
3765 | ||
d84f3174 AW |
3766 | static void quirk_no_pm_reset(struct pci_dev *dev) |
3767 | { | |
3768 | /* | |
3769 | * We can't do a bus reset on root bus devices, but an ineffective | |
3770 | * PM reset may be better than nothing. | |
3771 | */ | |
3772 | if (!pci_is_root_bus(dev->bus)) | |
3773 | dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; | |
3774 | } | |
3775 | ||
3776 | /* | |
3777 | * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition | |
3778 | * causes a reset (i.e., they advertise NoSoftRst-). This transition seems | |
3779 | * to have no effect on the device: it retains the framebuffer contents and | |
3780 | * monitor sync. Advertising this support makes other layers, like VFIO, | |
3781 | * assume pci_reset_function() is viable for this device. Mark it as | |
3782 | * unavailable to skip it when testing reset methods. | |
3783 | */ | |
3784 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, | |
3785 | PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); | |
3786 | ||
19bf4d4f LW |
3787 | /* |
3788 | * Thunderbolt controllers with broken MSI hotplug signaling: | |
3789 | * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part | |
3790 | * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). | |
3791 | */ | |
3792 | static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) | |
3793 | { | |
3794 | if (pdev->is_hotplug_bridge && | |
3795 | (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || | |
3796 | pdev->revision <= 1)) | |
3797 | pdev->no_msi = 1; | |
3798 | } | |
3799 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, | |
3800 | quirk_thunderbolt_hotplug_msi); | |
3801 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, | |
3802 | quirk_thunderbolt_hotplug_msi); | |
3803 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, | |
3804 | quirk_thunderbolt_hotplug_msi); | |
3805 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, | |
3806 | quirk_thunderbolt_hotplug_msi); | |
3807 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, | |
3808 | quirk_thunderbolt_hotplug_msi); | |
3809 | ||
1df5172c AN |
3810 | #ifdef CONFIG_ACPI |
3811 | /* | |
3812 | * Apple: Shutdown Cactus Ridge Thunderbolt controller. | |
3813 | * | |
3814 | * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be | |
3815 | * shutdown before suspend. Otherwise the native host interface (NHI) will not | |
3816 | * be present after resume if a device was plugged in before suspend. | |
3817 | * | |
82e1719c BH |
3818 | * The Thunderbolt controller consists of a PCIe switch with downstream |
3819 | * bridges leading to the NHI and to the tunnel PCI bridges. | |
1df5172c AN |
3820 | * |
3821 | * This quirk cuts power to the whole chip. Therefore we have to apply it | |
3822 | * during suspend_noirq of the upstream bridge. | |
3823 | * | |
3824 | * Power is automagically restored before resume. No action is needed. | |
3825 | */ | |
3826 | static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) | |
3827 | { | |
3828 | acpi_handle bridge, SXIO, SXFP, SXLV; | |
3829 | ||
630b3aff | 3830 | if (!x86_apple_machine) |
1df5172c AN |
3831 | return; |
3832 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) | |
3833 | return; | |
4694ae37 KK |
3834 | |
3835 | /* | |
3836 | * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. | |
3837 | * We don't know how to turn it back on again, but firmware does, | |
3838 | * so we can only use SXIO/SXFP/SXLF if we're suspending via | |
3839 | * firmware. | |
3840 | */ | |
3841 | if (!pm_suspend_via_firmware()) | |
3842 | return; | |
3843 | ||
1df5172c AN |
3844 | bridge = ACPI_HANDLE(&dev->dev); |
3845 | if (!bridge) | |
3846 | return; | |
82e1719c | 3847 | |
1df5172c AN |
3848 | /* |
3849 | * SXIO and SXLV are present only on machines requiring this quirk. | |
82e1719c BH |
3850 | * Thunderbolt bridges in external devices might have the same |
3851 | * device ID as those on the host, but they will not have the | |
3852 | * associated ACPI methods. This implicitly checks that we are at | |
3853 | * the right bridge. | |
1df5172c AN |
3854 | */ |
3855 | if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) | |
3856 | || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) | |
3857 | || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) | |
3858 | return; | |
82e1719c | 3859 | pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); |
1df5172c AN |
3860 | |
3861 | /* magic sequence */ | |
3862 | acpi_execute_simple_method(SXIO, NULL, 1); | |
3863 | acpi_execute_simple_method(SXFP, NULL, 0); | |
3864 | msleep(300); | |
3865 | acpi_execute_simple_method(SXLV, NULL, 0); | |
3866 | acpi_execute_simple_method(SXIO, NULL, 0); | |
3867 | acpi_execute_simple_method(SXLV, NULL, 0); | |
3868 | } | |
1d111406 LW |
3869 | DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, |
3870 | PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, | |
1df5172c | 3871 | quirk_apple_poweroff_thunderbolt); |
1df5172c AN |
3872 | #endif |
3873 | ||
b9c3b266 | 3874 | /* |
4091fb95 | 3875 | * Following are device-specific reset methods which can be used to |
b9c3b266 DC |
3876 | * reset a single function if other methods (e.g. FLR, PM D0->D3) are |
3877 | * not available. | |
3878 | */ | |
9bdc81ce | 3879 | static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) |
c763e7b5 | 3880 | { |
76b57c67 BH |
3881 | /* |
3882 | * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf | |
3883 | * | |
3884 | * The 82599 supports FLR on VFs, but FLR support is reported only | |
3885 | * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). | |
c8d8096a CH |
3886 | * Thus we must call pcie_flr() directly without first checking if it is |
3887 | * supported. | |
76b57c67 | 3888 | */ |
c8d8096a CH |
3889 | if (!probe) |
3890 | pcie_flr(dev); | |
c763e7b5 DC |
3891 | return 0; |
3892 | } | |
3893 | ||
aba72ddc VS |
3894 | #define SOUTH_CHICKEN2 0xc2004 |
3895 | #define PCH_PP_STATUS 0xc7200 | |
3896 | #define PCH_PP_CONTROL 0xc7204 | |
df558de1 XH |
3897 | #define MSG_CTL 0x45010 |
3898 | #define NSDE_PWR_STATE 0xd0100 | |
3899 | #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ | |
3900 | ||
9bdc81ce | 3901 | static int reset_ivb_igd(struct pci_dev *dev, bool probe) |
df558de1 XH |
3902 | { |
3903 | void __iomem *mmio_base; | |
3904 | unsigned long timeout; | |
3905 | u32 val; | |
3906 | ||
3907 | if (probe) | |
3908 | return 0; | |
3909 | ||
3910 | mmio_base = pci_iomap(dev, 0, 0); | |
3911 | if (!mmio_base) | |
3912 | return -ENOMEM; | |
3913 | ||
3914 | iowrite32(0x00000002, mmio_base + MSG_CTL); | |
3915 | ||
3916 | /* | |
3917 | * Clobbering SOUTH_CHICKEN2 register is fine only if the next | |
3918 | * driver loaded sets the right bits. However, this's a reset and | |
3919 | * the bits have been set by i915 previously, so we clobber | |
3920 | * SOUTH_CHICKEN2 register directly here. | |
3921 | */ | |
3922 | iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); | |
3923 | ||
3924 | val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; | |
3925 | iowrite32(val, mmio_base + PCH_PP_CONTROL); | |
3926 | ||
3927 | timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); | |
3928 | do { | |
3929 | val = ioread32(mmio_base + PCH_PP_STATUS); | |
3930 | if ((val & 0xb0000000) == 0) | |
3931 | goto reset_complete; | |
3932 | msleep(10); | |
3933 | } while (time_before(jiffies, timeout)); | |
7506dc79 | 3934 | pci_warn(dev, "timeout during reset\n"); |
df558de1 XH |
3935 | |
3936 | reset_complete: | |
3937 | iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); | |
3938 | ||
3939 | pci_iounmap(dev, mmio_base); | |
3940 | return 0; | |
3941 | } | |
3942 | ||
82e1719c | 3943 | /* Device-specific reset method for Chelsio T4-based adapters */ |
9bdc81ce | 3944 | static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) |
2c6217e0 CL |
3945 | { |
3946 | u16 old_command; | |
3947 | u16 msix_flags; | |
3948 | ||
3949 | /* | |
3950 | * If this isn't a Chelsio T4-based device, return -ENOTTY indicating | |
3951 | * that we have no device-specific reset method. | |
3952 | */ | |
3953 | if ((dev->device & 0xf000) != 0x4000) | |
3954 | return -ENOTTY; | |
3955 | ||
3956 | /* | |
3957 | * If this is the "probe" phase, return 0 indicating that we can | |
3958 | * reset this device. | |
3959 | */ | |
3960 | if (probe) | |
3961 | return 0; | |
3962 | ||
3963 | /* | |
3964 | * T4 can wedge if there are DMAs in flight within the chip and Bus | |
3965 | * Master has been disabled. We need to have it on till the Function | |
3966 | * Level Reset completes. (BUS_MASTER is disabled in | |
3967 | * pci_reset_function()). | |
3968 | */ | |
3969 | pci_read_config_word(dev, PCI_COMMAND, &old_command); | |
3970 | pci_write_config_word(dev, PCI_COMMAND, | |
3971 | old_command | PCI_COMMAND_MASTER); | |
3972 | ||
3973 | /* | |
3974 | * Perform the actual device function reset, saving and restoring | |
3975 | * configuration information around the reset. | |
3976 | */ | |
3977 | pci_save_state(dev); | |
3978 | ||
3979 | /* | |
3980 | * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts | |
3981 | * are disabled when an MSI-X interrupt message needs to be delivered. | |
3982 | * So we briefly re-enable MSI-X interrupts for the duration of the | |
3983 | * FLR. The pci_restore_state() below will restore the original | |
3984 | * MSI-X state. | |
3985 | */ | |
3986 | pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); | |
3987 | if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) | |
3988 | pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, | |
3989 | msix_flags | | |
3990 | PCI_MSIX_FLAGS_ENABLE | | |
3991 | PCI_MSIX_FLAGS_MASKALL); | |
3992 | ||
48f52d1a | 3993 | pcie_flr(dev); |
2c6217e0 CL |
3994 | |
3995 | /* | |
3996 | * Restore the configuration information (BAR values, etc.) including | |
3997 | * the original PCI Configuration Space Command word, and return | |
3998 | * success. | |
3999 | */ | |
4000 | pci_restore_state(dev); | |
4001 | pci_write_config_word(dev, PCI_COMMAND, old_command); | |
4002 | return 0; | |
4003 | } | |
4004 | ||
c763e7b5 | 4005 | #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed |
df558de1 XH |
4006 | #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 |
4007 | #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 | |
c763e7b5 | 4008 | |
ffb08634 AW |
4009 | /* |
4010 | * The Samsung SM961/PM961 controller can sometimes enter a fatal state after | |
4011 | * FLR where config space reads from the device return -1. We seem to be | |
4012 | * able to avoid this condition if we disable the NVMe controller prior to | |
4013 | * FLR. This quirk is generic for any NVMe class device requiring similar | |
4014 | * assistance to quiesce the device prior to FLR. | |
4015 | * | |
4016 | * NVMe specification: https://nvmexpress.org/resources/specifications/ | |
4017 | * Revision 1.0e: | |
4018 | * Chapter 2: Required and optional PCI config registers | |
4019 | * Chapter 3: NVMe control registers | |
4020 | * Chapter 7.3: Reset behavior | |
4021 | */ | |
9bdc81ce | 4022 | static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) |
ffb08634 AW |
4023 | { |
4024 | void __iomem *bar; | |
4025 | u16 cmd; | |
4026 | u32 cfg; | |
4027 | ||
4028 | if (dev->class != PCI_CLASS_STORAGE_EXPRESS || | |
9bdc81ce | 4029 | pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) |
ffb08634 AW |
4030 | return -ENOTTY; |
4031 | ||
4032 | if (probe) | |
4033 | return 0; | |
4034 | ||
4035 | bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); | |
4036 | if (!bar) | |
4037 | return -ENOTTY; | |
4038 | ||
4039 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4040 | pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); | |
4041 | ||
4042 | cfg = readl(bar + NVME_REG_CC); | |
4043 | ||
4044 | /* Disable controller if enabled */ | |
4045 | if (cfg & NVME_CC_ENABLE) { | |
4046 | u32 cap = readl(bar + NVME_REG_CAP); | |
4047 | unsigned long timeout; | |
4048 | ||
4049 | /* | |
4050 | * Per nvme_disable_ctrl() skip shutdown notification as it | |
4051 | * could complete commands to the admin queue. We only intend | |
4052 | * to quiesce the device before reset. | |
4053 | */ | |
4054 | cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); | |
4055 | ||
4056 | writel(cfg, bar + NVME_REG_CC); | |
4057 | ||
4058 | /* | |
4059 | * Some controllers require an additional delay here, see | |
4060 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet | |
4061 | * supported by this quirk. | |
4062 | */ | |
4063 | ||
4064 | /* Cap register provides max timeout in 500ms increments */ | |
4065 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
4066 | ||
4067 | for (;;) { | |
4068 | u32 status = readl(bar + NVME_REG_CSTS); | |
4069 | ||
4070 | /* Ready status becomes zero on disable complete */ | |
4071 | if (!(status & NVME_CSTS_RDY)) | |
4072 | break; | |
4073 | ||
4074 | msleep(100); | |
4075 | ||
4076 | if (time_after(jiffies, timeout)) { | |
4077 | pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); | |
4078 | break; | |
4079 | } | |
4080 | } | |
4081 | } | |
4082 | ||
4083 | pci_iounmap(dev, bar); | |
4084 | ||
4085 | pcie_flr(dev); | |
4086 | ||
4087 | return 0; | |
4088 | } | |
4089 | ||
51ba0945 | 4090 | /* |
0ac448e0 MP |
4091 | * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will |
4092 | * timeout waiting for ready status to change after NVMe enable if the driver | |
4093 | * starts interacting with the device too soon after FLR. A 250ms delay after | |
4094 | * FLR has heuristically proven to produce reliably working results for device | |
4095 | * assignment cases. | |
51ba0945 | 4096 | */ |
9bdc81ce | 4097 | static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) |
51ba0945 | 4098 | { |
51ba0945 | 4099 | if (probe) |
9bdc81ce | 4100 | return pcie_reset_flr(dev, PCI_RESET_PROBE); |
51ba0945 | 4101 | |
9bdc81ce | 4102 | pcie_reset_flr(dev, PCI_RESET_DO_RESET); |
51ba0945 AW |
4103 | |
4104 | msleep(250); | |
4105 | ||
4106 | return 0; | |
4107 | } | |
4108 | ||
ce00322c C |
4109 | #define PCI_DEVICE_ID_HINIC_VF 0x375E |
4110 | #define HINIC_VF_FLR_TYPE 0x1000 | |
4111 | #define HINIC_VF_FLR_CAP_BIT (1UL << 30) | |
4112 | #define HINIC_VF_OP 0xE80 | |
4113 | #define HINIC_VF_FLR_PROC_BIT (1UL << 18) | |
4114 | #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ | |
4115 | ||
4116 | /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ | |
9bdc81ce | 4117 | static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) |
ce00322c C |
4118 | { |
4119 | unsigned long timeout; | |
4120 | void __iomem *bar; | |
4121 | u32 val; | |
4122 | ||
4123 | if (probe) | |
4124 | return 0; | |
4125 | ||
4126 | bar = pci_iomap(pdev, 0, 0); | |
4127 | if (!bar) | |
4128 | return -ENOTTY; | |
4129 | ||
4130 | /* Get and check firmware capabilities */ | |
4131 | val = ioread32be(bar + HINIC_VF_FLR_TYPE); | |
4132 | if (!(val & HINIC_VF_FLR_CAP_BIT)) { | |
4133 | pci_iounmap(pdev, bar); | |
4134 | return -ENOTTY; | |
4135 | } | |
4136 | ||
4137 | /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ | |
4138 | val = ioread32be(bar + HINIC_VF_OP); | |
4139 | val = val | HINIC_VF_FLR_PROC_BIT; | |
4140 | iowrite32be(val, bar + HINIC_VF_OP); | |
4141 | ||
4142 | pcie_flr(pdev); | |
4143 | ||
4144 | /* | |
4145 | * The device must recapture its Bus and Device Numbers after FLR | |
4146 | * in order generate Completions. Issue a config write to let the | |
4147 | * device capture this information. | |
4148 | */ | |
4149 | pci_write_config_word(pdev, PCI_VENDOR_ID, 0); | |
4150 | ||
4151 | /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ | |
4152 | timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); | |
4153 | do { | |
4154 | val = ioread32be(bar + HINIC_VF_OP); | |
4155 | if (!(val & HINIC_VF_FLR_PROC_BIT)) | |
4156 | goto reset_complete; | |
4157 | msleep(20); | |
4158 | } while (time_before(jiffies, timeout)); | |
4159 | ||
4160 | val = ioread32be(bar + HINIC_VF_OP); | |
4161 | if (!(val & HINIC_VF_FLR_PROC_BIT)) | |
4162 | goto reset_complete; | |
4163 | ||
4164 | pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); | |
4165 | ||
4166 | reset_complete: | |
4167 | pci_iounmap(pdev, bar); | |
4168 | ||
4169 | return 0; | |
4170 | } | |
4171 | ||
5b889bf2 | 4172 | static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { |
c763e7b5 DC |
4173 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, |
4174 | reset_intel_82599_sfp_virtfn }, | |
df558de1 XH |
4175 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, |
4176 | reset_ivb_igd }, | |
4177 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, | |
4178 | reset_ivb_igd }, | |
ffb08634 | 4179 | { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, |
51ba0945 | 4180 | { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, |
0349a070 | 4181 | { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, |
0ac448e0 | 4182 | { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, |
2c6217e0 CL |
4183 | { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, |
4184 | reset_chelsio_generic_dev }, | |
ce00322c C |
4185 | { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, |
4186 | reset_hinic_vf_dev }, | |
b9c3b266 DC |
4187 | { 0 } |
4188 | }; | |
5b889bf2 | 4189 | |
df558de1 XH |
4190 | /* |
4191 | * These device-specific reset methods are here rather than in a driver | |
4192 | * because when a host assigns a device to a guest VM, the host may need | |
4193 | * to reset the device but probably doesn't have a driver for it. | |
4194 | */ | |
9bdc81ce | 4195 | int pci_dev_specific_reset(struct pci_dev *dev, bool probe) |
5b889bf2 | 4196 | { |
df9d1e8a | 4197 | const struct pci_dev_reset_methods *i; |
5b889bf2 RW |
4198 | |
4199 | for (i = pci_dev_reset_methods; i->reset; i++) { | |
4200 | if ((i->vendor == dev->vendor || | |
4201 | i->vendor == (u16)PCI_ANY_ID) && | |
4202 | (i->device == dev->device || | |
4203 | i->device == (u16)PCI_ANY_ID)) | |
4204 | return i->reset(dev, probe); | |
4205 | } | |
4206 | ||
4207 | return -ENOTTY; | |
4208 | } | |
12ea6cad | 4209 | |
ec637fb2 AW |
4210 | static void quirk_dma_func0_alias(struct pci_dev *dev) |
4211 | { | |
f0af9593 | 4212 | if (PCI_FUNC(dev->devfn) != 0) |
09298542 | 4213 | pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); |
ec637fb2 AW |
4214 | } |
4215 | ||
4216 | /* | |
4217 | * https://bugzilla.redhat.com/show_bug.cgi?id=605888 | |
4218 | * | |
4219 | * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. | |
4220 | */ | |
4221 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); | |
4222 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); | |
4223 | ||
cc346a47 AW |
4224 | static void quirk_dma_func1_alias(struct pci_dev *dev) |
4225 | { | |
f0af9593 | 4226 | if (PCI_FUNC(dev->devfn) != 1) |
09298542 | 4227 | pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); |
cc346a47 AW |
4228 | } |
4229 | ||
4230 | /* | |
4231 | * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some | |
4232 | * SKUs function 1 is present and is a legacy IDE controller, in other | |
4233 | * SKUs this function is not present, making this a ghost requester. | |
4234 | * https://bugzilla.kernel.org/show_bug.cgi?id=42679 | |
4235 | */ | |
247de694 SA |
4236 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, |
4237 | quirk_dma_func1_alias); | |
cc346a47 AW |
4238 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, |
4239 | quirk_dma_func1_alias); | |
e4453758 YL |
4240 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ |
4241 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, | |
4242 | quirk_dma_func1_alias); | |
aa008206 AW |
4243 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, |
4244 | quirk_dma_func1_alias); | |
cc346a47 AW |
4245 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ |
4246 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, | |
4247 | quirk_dma_func1_alias); | |
9cde402a AP |
4248 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, |
4249 | quirk_dma_func1_alias); | |
cc346a47 AW |
4250 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ |
4251 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, | |
4252 | quirk_dma_func1_alias); | |
4253 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ | |
4254 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, | |
4255 | quirk_dma_func1_alias); | |
00456b35 AS |
4256 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ |
4257 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, | |
4258 | quirk_dma_func1_alias); | |
7695e73f BH |
4259 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ |
4260 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, | |
4261 | quirk_dma_func1_alias); | |
cc346a47 AW |
4262 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ |
4263 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, | |
4264 | quirk_dma_func1_alias); | |
05998379 BH |
4265 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ |
4266 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, | |
4267 | quirk_dma_func1_alias); | |
832e4e1f TVC |
4268 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ |
4269 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, | |
4270 | quirk_dma_func1_alias); | |
cc346a47 AW |
4271 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ |
4272 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, | |
4273 | quirk_dma_func1_alias); | |
88d34171 RM |
4274 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, |
4275 | quirk_dma_func1_alias); | |
c2e0fb96 JC |
4276 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, |
4277 | quirk_dma_func1_alias); | |
1903be82 HG |
4278 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, |
4279 | quirk_dma_func1_alias); | |
cc346a47 AW |
4280 | /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ |
4281 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, | |
4282 | PCI_DEVICE_ID_JMICRON_JMB388_ESD, | |
4283 | quirk_dma_func1_alias); | |
8b9b963e TS |
4284 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ |
4285 | DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ | |
4286 | 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ | |
4287 | quirk_dma_func1_alias); | |
cc346a47 | 4288 | |
d3d2ab43 AW |
4289 | /* |
4290 | * Some devices DMA with the wrong devfn, not just the wrong function. | |
4291 | * quirk_fixed_dma_alias() uses this table to create fixed aliases, where | |
4292 | * the alias is "fixed" and independent of the device devfn. | |
4293 | * | |
4294 | * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O | |
4295 | * processor. To software, this appears as a PCIe-to-PCI/X bridge with a | |
4296 | * single device on the secondary bus. In reality, the single exposed | |
4297 | * device at 0e.0 is the Address Translation Unit (ATU) of the controller | |
4298 | * that provides a bridge to the internal bus of the I/O processor. The | |
4299 | * controller supports private devices, which can be hidden from PCI config | |
4300 | * space. In the case of the Adaptec 3405, a private device at 01.0 | |
4301 | * appears to be the DMA engine, which therefore needs to become a DMA | |
4302 | * alias for the device. | |
4303 | */ | |
4304 | static const struct pci_device_id fixed_dma_alias_tbl[] = { | |
4305 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, | |
4306 | PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ | |
4307 | .driver_data = PCI_DEVFN(1, 0) }, | |
db83f87b AW |
4308 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, |
4309 | PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ | |
4310 | .driver_data = PCI_DEVFN(1, 0) }, | |
d3d2ab43 AW |
4311 | { 0 } |
4312 | }; | |
4313 | ||
4314 | static void quirk_fixed_dma_alias(struct pci_dev *dev) | |
4315 | { | |
4316 | const struct pci_device_id *id; | |
4317 | ||
4318 | id = pci_match_id(fixed_dma_alias_tbl, dev); | |
48c83080 | 4319 | if (id) |
09298542 | 4320 | pci_add_dma_alias(dev, id->driver_data, 1); |
d3d2ab43 | 4321 | } |
d3d2ab43 AW |
4322 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); |
4323 | ||
ebdb51eb AW |
4324 | /* |
4325 | * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in | |
4326 | * using the wrong DMA alias for the device. Some of these devices can be | |
4327 | * used as either forward or reverse bridges, so we need to test whether the | |
4328 | * device is operating in the correct mode. We could probably apply this | |
4329 | * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test | |
4330 | * is for a non-root, non-PCIe bridge where the upstream device is PCIe and | |
4331 | * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. | |
4332 | */ | |
4333 | static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) | |
4334 | { | |
4335 | if (!pci_is_root_bus(pdev->bus) && | |
4336 | pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
4337 | !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && | |
4338 | pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) | |
4339 | pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; | |
4340 | } | |
4341 | /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ | |
4342 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, | |
4343 | quirk_use_pcie_bridge_dma_alias); | |
4344 | /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ | |
4345 | DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); | |
98ca50db AW |
4346 | /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ |
4347 | DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); | |
fce5d57e JW |
4348 | /* ITE 8893 has the same problem as the 8892 */ |
4349 | DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); | |
8ab4abbe AW |
4350 | /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ |
4351 | DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); | |
ebdb51eb | 4352 | |
b1a928cd JL |
4353 | /* |
4354 | * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to | |
4355 | * be added as aliases to the DMA device in order to allow buffer access | |
4356 | * when IOMMU is enabled. Following devfns have to match RIT-LUT table | |
4357 | * programmed in the EEPROM. | |
4358 | */ | |
4359 | static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) | |
4360 | { | |
09298542 JS |
4361 | pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); |
4362 | pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); | |
4363 | pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); | |
b1a928cd JL |
4364 | } |
4365 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); | |
4366 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); | |
4367 | ||
56b4cd4b SP |
4368 | /* |
4369 | * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices | |
4370 | * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). | |
4371 | * | |
4372 | * Similarly to MIC x200, we need to add DMA aliases to allow buffer access | |
4373 | * when IOMMU is enabled. These aliases allow computational unit access to | |
4374 | * host memory. These aliases mark the whole VCA device as one IOMMU | |
4375 | * group. | |
4376 | * | |
4377 | * All possible slot numbers (0x20) are used, since we are unable to tell | |
4378 | * what slot is used on other side. This quirk is intended for both host | |
4379 | * and computational unit sides. The VCA devices have up to five functions | |
4380 | * (four for DMA channels and one additional). | |
4381 | */ | |
4382 | static void quirk_pex_vca_alias(struct pci_dev *pdev) | |
4383 | { | |
4384 | const unsigned int num_pci_slots = 0x20; | |
4385 | unsigned int slot; | |
4386 | ||
09298542 JS |
4387 | for (slot = 0; slot < num_pci_slots; slot++) |
4388 | pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); | |
56b4cd4b SP |
4389 | } |
4390 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); | |
4391 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); | |
4392 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); | |
4393 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); | |
4394 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); | |
4395 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); | |
4396 | ||
45a23293 J |
4397 | /* |
4398 | * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are | |
4399 | * associated not at the root bus, but at a bridge below. This quirk avoids | |
4400 | * generating invalid DMA aliases. | |
4401 | */ | |
4402 | static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) | |
4403 | { | |
4404 | pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; | |
4405 | } | |
4406 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, | |
4407 | quirk_bridge_cavm_thrx2_pcie_root); | |
4408 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, | |
4409 | quirk_bridge_cavm_thrx2_pcie_root); | |
4410 | ||
3657cebd KHC |
4411 | /* |
4412 | * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) | |
4413 | * class code. Fix it. | |
4414 | */ | |
4415 | static void quirk_tw686x_class(struct pci_dev *pdev) | |
4416 | { | |
4417 | u32 class = pdev->class; | |
4418 | ||
4419 | /* Use "Multimedia controller" class */ | |
4420 | pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; | |
7506dc79 | 4421 | pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", |
3657cebd KHC |
4422 | class, pdev->class); |
4423 | } | |
2b4aed1d | 4424 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd | 4425 | quirk_tw686x_class); |
2b4aed1d | 4426 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd | 4427 | quirk_tw686x_class); |
2b4aed1d | 4428 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd | 4429 | quirk_tw686x_class); |
2b4aed1d | 4430 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd KHC |
4431 | quirk_tw686x_class); |
4432 | ||
a99b646a | 4433 | /* |
4434 | * Some devices have problems with Transaction Layer Packets with the Relaxed | |
4435 | * Ordering Attribute set. Such devices should mark themselves and other | |
82e1719c | 4436 | * device drivers should check before sending TLPs with RO set. |
a99b646a | 4437 | */ |
4438 | static void quirk_relaxedordering_disable(struct pci_dev *dev) | |
4439 | { | |
4440 | dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; | |
7506dc79 | 4441 | pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); |
a99b646a | 4442 | } |
4443 | ||
87e09cde | 4444 | /* |
4445 | * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root | |
82e1719c | 4446 | * Complex have a Flow Control Credit issue which can cause performance |
87e09cde | 4447 | * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. |
4448 | */ | |
4449 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, | |
4450 | quirk_relaxedordering_disable); | |
4451 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, | |
4452 | quirk_relaxedordering_disable); | |
4453 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, | |
4454 | quirk_relaxedordering_disable); | |
4455 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, | |
4456 | quirk_relaxedordering_disable); | |
4457 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, | |
4458 | quirk_relaxedordering_disable); | |
4459 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, | |
4460 | quirk_relaxedordering_disable); | |
4461 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, | |
4462 | quirk_relaxedordering_disable); | |
4463 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, | |
4464 | quirk_relaxedordering_disable); | |
4465 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, | |
4466 | quirk_relaxedordering_disable); | |
4467 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, | |
4468 | quirk_relaxedordering_disable); | |
4469 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, | |
4470 | quirk_relaxedordering_disable); | |
4471 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, | |
4472 | quirk_relaxedordering_disable); | |
4473 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, | |
4474 | quirk_relaxedordering_disable); | |
4475 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, | |
4476 | quirk_relaxedordering_disable); | |
4477 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, | |
4478 | quirk_relaxedordering_disable); | |
4479 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, | |
4480 | quirk_relaxedordering_disable); | |
4481 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, | |
4482 | quirk_relaxedordering_disable); | |
4483 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, | |
4484 | quirk_relaxedordering_disable); | |
4485 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, | |
4486 | quirk_relaxedordering_disable); | |
4487 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, | |
4488 | quirk_relaxedordering_disable); | |
4489 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, | |
4490 | quirk_relaxedordering_disable); | |
4491 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, | |
4492 | quirk_relaxedordering_disable); | |
4493 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, | |
4494 | quirk_relaxedordering_disable); | |
4495 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, | |
4496 | quirk_relaxedordering_disable); | |
4497 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, | |
4498 | quirk_relaxedordering_disable); | |
4499 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, | |
4500 | quirk_relaxedordering_disable); | |
4501 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, | |
4502 | quirk_relaxedordering_disable); | |
4503 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, | |
4504 | quirk_relaxedordering_disable); | |
4505 | ||
077fa19c | 4506 | /* |
82e1719c | 4507 | * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex |
077fa19c | 4508 | * where Upstream Transaction Layer Packets with the Relaxed Ordering |
4509 | * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering | |
4510 | * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules | |
4511 | * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 | |
4512 | * November 10, 2010). As a result, on this platform we can't use Relaxed | |
4513 | * Ordering for Upstream TLPs. | |
4514 | */ | |
4515 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, | |
4516 | quirk_relaxedordering_disable); | |
4517 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, | |
4518 | quirk_relaxedordering_disable); | |
4519 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, | |
4520 | quirk_relaxedordering_disable); | |
4521 | ||
c56d4450 HS |
4522 | /* |
4523 | * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same | |
4524 | * values for the Attribute as were supplied in the header of the | |
4525 | * corresponding Request, except as explicitly allowed when IDO is used." | |
4526 | * | |
4527 | * If a non-compliant device generates a completion with a different | |
4528 | * attribute than the request, the receiver may accept it (which itself | |
4529 | * seems non-compliant based on sec 2.3.2), or it may handle it as a | |
4530 | * Malformed TLP or an Unexpected Completion, which will probably lead to a | |
4531 | * device access timeout. | |
4532 | * | |
4533 | * If the non-compliant device generates completions with zero attributes | |
4534 | * (instead of copying the attributes from the request), we can work around | |
4535 | * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in | |
4536 | * upstream devices so they always generate requests with zero attributes. | |
4537 | * | |
4538 | * This affects other devices under the same Root Port, but since these | |
4539 | * attributes are performance hints, there should be no functional problem. | |
4540 | * | |
4541 | * Note that Configuration Space accesses are never supposed to have TLP | |
4542 | * Attributes, so we're safe waiting till after any Configuration Space | |
4543 | * accesses to do the Root Port fixup. | |
4544 | */ | |
4545 | static void quirk_disable_root_port_attributes(struct pci_dev *pdev) | |
4546 | { | |
6ae72bfa | 4547 | struct pci_dev *root_port = pcie_find_root_port(pdev); |
c56d4450 HS |
4548 | |
4549 | if (!root_port) { | |
7506dc79 | 4550 | pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); |
c56d4450 HS |
4551 | return; |
4552 | } | |
4553 | ||
7506dc79 | 4554 | pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", |
c56d4450 HS |
4555 | dev_name(&pdev->dev)); |
4556 | pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, | |
4557 | PCI_EXP_DEVCTL_RELAX_EN | | |
4558 | PCI_EXP_DEVCTL_NOSNOOP_EN, 0); | |
4559 | } | |
4560 | ||
4561 | /* | |
4562 | * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the | |
4563 | * Completion it generates. | |
4564 | */ | |
4565 | static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) | |
4566 | { | |
4567 | /* | |
4568 | * This mask/compare operation selects for Physical Function 4 on a | |
4569 | * T5. We only need to fix up the Root Port once for any of the | |
4570 | * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely | |
82e1719c | 4571 | * 0x54xx so we use that one. |
c56d4450 HS |
4572 | */ |
4573 | if ((pdev->device & 0xff00) == 0x5400) | |
4574 | quirk_disable_root_port_attributes(pdev); | |
4575 | } | |
4576 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, | |
4577 | quirk_chelsio_T5_disable_root_port_attributes); | |
4578 | ||
7cf2cba4 BH |
4579 | /* |
4580 | * pci_acs_ctrl_enabled - compare desired ACS controls with those provided | |
4581 | * by a device | |
4582 | * @acs_ctrl_req: Bitmask of desired ACS controls | |
4583 | * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by | |
4584 | * the hardware design | |
4585 | * | |
4586 | * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included | |
4587 | * in @acs_ctrl_ena, i.e., the device provides all the access controls the | |
4588 | * caller desires. Return 0 otherwise. | |
4589 | */ | |
4590 | static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) | |
4591 | { | |
4592 | if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) | |
4593 | return 1; | |
4594 | return 0; | |
4595 | } | |
4596 | ||
15b100df AW |
4597 | /* |
4598 | * AMD has indicated that the devices below do not support peer-to-peer | |
4599 | * in any system where they are found in the southbridge with an AMD | |
4600 | * IOMMU in the system. Multifunction devices that do not support | |
4601 | * peer-to-peer between functions can claim to support a subset of ACS. | |
4602 | * Such devices effectively enable request redirect (RR) and completion | |
4603 | * redirect (CR) since all transactions are redirected to the upstream | |
4604 | * root complex. | |
4605 | * | |
16bbbc87 BH |
4606 | * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ |
4607 | * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ | |
4608 | * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ | |
15b100df AW |
4609 | * |
4610 | * 1002:4385 SBx00 SMBus Controller | |
4611 | * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller | |
4612 | * 1002:4383 SBx00 Azalia (Intel HDA) | |
4613 | * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller | |
4614 | * 1002:4384 SBx00 PCI to PCI Bridge | |
4615 | * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller | |
3587e625 MR |
4616 | * |
4617 | * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 | |
4618 | * | |
4619 | * 1022:780f [AMD] FCH PCI Bridge | |
4620 | * 1022:7809 [AMD] FCH USB OHCI Controller | |
15b100df AW |
4621 | */ |
4622 | static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) | |
4623 | { | |
4624 | #ifdef CONFIG_ACPI | |
4625 | struct acpi_table_header *header = NULL; | |
4626 | acpi_status status; | |
4627 | ||
4628 | /* Targeting multifunction devices on the SB (appears on root bus) */ | |
4629 | if (!dev->multifunction || !pci_is_root_bus(dev->bus)) | |
4630 | return -ENODEV; | |
4631 | ||
4632 | /* The IVRS table describes the AMD IOMMU */ | |
4633 | status = acpi_get_table("IVRS", 0, &header); | |
4634 | if (ACPI_FAILURE(status)) | |
4635 | return -ENODEV; | |
4636 | ||
090688fa HG |
4637 | acpi_put_table(header); |
4638 | ||
15b100df AW |
4639 | /* Filter out flags not applicable to multifunction */ |
4640 | acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); | |
4641 | ||
7cf2cba4 | 4642 | return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); |
15b100df AW |
4643 | #else |
4644 | return -ENODEV; | |
4645 | #endif | |
4646 | } | |
4647 | ||
f2ddaf8d VL |
4648 | static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) |
4649 | { | |
f338bb9f GC |
4650 | if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) |
4651 | return false; | |
4652 | ||
4653 | switch (dev->device) { | |
f2ddaf8d | 4654 | /* |
f338bb9f GC |
4655 | * Effectively selects all downstream ports for whole ThunderX1 |
4656 | * (which represents 8 SoCs). | |
f2ddaf8d | 4657 | */ |
f338bb9f GC |
4658 | case 0xa000 ... 0xa7ff: /* ThunderX1 */ |
4659 | case 0xaf84: /* ThunderX2 */ | |
4660 | case 0xb884: /* ThunderX3 */ | |
4661 | return true; | |
4662 | default: | |
4663 | return false; | |
4664 | } | |
f2ddaf8d VL |
4665 | } |
4666 | ||
b404bcfb MJ |
4667 | static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) |
4668 | { | |
c8de8ed2 BH |
4669 | if (!pci_quirk_cavium_acs_match(dev)) |
4670 | return -ENOTTY; | |
4671 | ||
b404bcfb | 4672 | /* |
c8de8ed2 | 4673 | * Cavium Root Ports don't advertise an ACS capability. However, |
7f342678 | 4674 | * the RTL internally implements similar protection as if ACS had |
c8de8ed2 | 4675 | * Source Validation, Request Redirection, Completion Redirection, |
7f342678 VL |
4676 | * and Upstream Forwarding features enabled. Assert that the |
4677 | * hardware implements and enables equivalent ACS functionality for | |
4678 | * these flags. | |
b404bcfb | 4679 | */ |
7cf2cba4 BH |
4680 | return pci_acs_ctrl_enabled(acs_flags, |
4681 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
b404bcfb MJ |
4682 | } |
4683 | ||
a0418aa2 FK |
4684 | static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) |
4685 | { | |
4686 | /* | |
82e1719c | 4687 | * X-Gene Root Ports matching this quirk do not allow peer-to-peer |
a0418aa2 FK |
4688 | * transactions with others, allowing masking out these bits as if they |
4689 | * were unimplemented in the ACS capability. | |
4690 | */ | |
7cf2cba4 BH |
4691 | return pci_acs_ctrl_enabled(acs_flags, |
4692 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
a0418aa2 FK |
4693 | } |
4694 | ||
299bd044 RP |
4695 | /* |
4696 | * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. | |
4697 | * But the implementation could block peer-to-peer transactions between them | |
4698 | * and provide ACS-like functionality. | |
4699 | */ | |
4700 | static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) | |
4701 | { | |
4702 | if (!pci_is_pcie(dev) || | |
4703 | ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && | |
4704 | (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) | |
4705 | return -ENOTTY; | |
4706 | ||
4707 | switch (dev->device) { | |
4708 | case 0x0710 ... 0x071e: | |
4709 | case 0x0721: | |
4710 | case 0x0723 ... 0x0732: | |
4711 | return pci_acs_ctrl_enabled(acs_flags, | |
4712 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
4713 | } | |
4714 | ||
4715 | return false; | |
4716 | } | |
4717 | ||
d99321b6 | 4718 | /* |
c8de8ed2 | 4719 | * Many Intel PCH Root Ports do provide ACS-like features to disable peer |
d99321b6 AW |
4720 | * transactions and validate bus numbers in requests, but do not provide an |
4721 | * actual PCIe ACS capability. This is the list of device IDs known to fall | |
4722 | * into that category as provided by Intel in Red Hat bugzilla 1037684. | |
4723 | */ | |
4724 | static const u16 pci_quirk_intel_pch_acs_ids[] = { | |
4725 | /* Ibexpeak PCH */ | |
4726 | 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, | |
4727 | 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, | |
4728 | /* Cougarpoint PCH */ | |
4729 | 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, | |
4730 | 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, | |
4731 | /* Pantherpoint PCH */ | |
4732 | 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, | |
4733 | 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, | |
4734 | /* Lynxpoint-H PCH */ | |
4735 | 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, | |
4736 | 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, | |
4737 | /* Lynxpoint-LP PCH */ | |
4738 | 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, | |
4739 | 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, | |
4740 | /* Wildcat PCH */ | |
4741 | 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, | |
4742 | 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, | |
1a30fd0d AW |
4743 | /* Patsburg (X79) PCH */ |
4744 | 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, | |
78e88358 AW |
4745 | /* Wellsburg (X99) PCH */ |
4746 | 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, | |
4747 | 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, | |
dca230d1 AW |
4748 | /* Lynx Point (9 series) PCH */ |
4749 | 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, | |
d99321b6 AW |
4750 | }; |
4751 | ||
4752 | static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) | |
4753 | { | |
4754 | int i; | |
4755 | ||
4756 | /* Filter out a few obvious non-matches first */ | |
4757 | if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) | |
4758 | return false; | |
4759 | ||
4760 | for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) | |
4761 | if (pci_quirk_intel_pch_acs_ids[i] == dev->device) | |
4762 | return true; | |
4763 | ||
4764 | return false; | |
4765 | } | |
4766 | ||
d99321b6 AW |
4767 | static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) |
4768 | { | |
d99321b6 AW |
4769 | if (!pci_quirk_intel_pch_acs_match(dev)) |
4770 | return -ENOTTY; | |
4771 | ||
c8de8ed2 | 4772 | if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) |
7cf2cba4 BH |
4773 | return pci_acs_ctrl_enabled(acs_flags, |
4774 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
c8de8ed2 | 4775 | |
7cf2cba4 | 4776 | return pci_acs_ctrl_enabled(acs_flags, 0); |
d99321b6 AW |
4777 | } |
4778 | ||
33be632b | 4779 | /* |
c8de8ed2 | 4780 | * These QCOM Root Ports do provide ACS-like features to disable peer |
33be632b SK |
4781 | * transactions and validate bus numbers in requests, but do not provide an |
4782 | * actual PCIe ACS capability. Hardware supports source validation but it | |
4783 | * will report the issue as Completer Abort instead of ACS Violation. | |
c8de8ed2 BH |
4784 | * Hardware doesn't support peer-to-peer and each Root Port is a Root |
4785 | * Complex with unique segment numbers. It is not possible for one Root | |
4786 | * Port to pass traffic to another Root Port. All PCIe transactions are | |
4787 | * terminated inside the Root Port. | |
33be632b SK |
4788 | */ |
4789 | static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) | |
4790 | { | |
7cf2cba4 BH |
4791 | return pci_acs_ctrl_enabled(acs_flags, |
4792 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
33be632b SK |
4793 | } |
4794 | ||
d08c8b85 WK |
4795 | /* |
4796 | * Each of these NXP Root Ports is in a Root Complex with a unique segment | |
4797 | * number and does provide isolation features to disable peer transactions | |
4798 | * and validate bus numbers in requests, but does not provide an ACS | |
4799 | * capability. | |
4800 | */ | |
4801 | static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) | |
4802 | { | |
4803 | return pci_acs_ctrl_enabled(acs_flags, | |
4804 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
4805 | } | |
4806 | ||
76e67e9e AS |
4807 | static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) |
4808 | { | |
4809 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) | |
4810 | return -ENOTTY; | |
4811 | ||
4812 | /* | |
4813 | * Amazon's Annapurna Labs root ports don't include an ACS capability, | |
4814 | * but do include ACS-like functionality. The hardware doesn't support | |
4815 | * peer-to-peer transactions via the root port and each has a unique | |
4816 | * segment number. | |
4817 | * | |
4818 | * Additionally, the root ports cannot send traffic to each other. | |
4819 | */ | |
4820 | acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
4821 | ||
4822 | return acs_flags ? 0 : 1; | |
4823 | } | |
4824 | ||
1bf2bf22 AW |
4825 | /* |
4826 | * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in | |
4827 | * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, | |
4828 | * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and | |
4829 | * control registers whereas the PCIe spec packs them into words (Rev 3.0, | |
4830 | * 7.16 ACS Extended Capability). The bit definitions are correct, but the | |
4831 | * control register is at offset 8 instead of 6 and we should probably use | |
4832 | * dword accesses to them. This applies to the following PCI Device IDs, as | |
4833 | * found in volume 1 of the datasheet[2]: | |
4834 | * | |
4835 | * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} | |
4836 | * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} | |
4837 | * | |
4838 | * N.B. This doesn't fix what lspci shows. | |
4839 | * | |
7184f5b4 AW |
4840 | * The 100 series chipset specification update includes this as errata #23[3]. |
4841 | * | |
4842 | * The 200 series chipset (Union Point) has the same bug according to the | |
4843 | * specification update (Intel 200 Series Chipset Family Platform Controller | |
4844 | * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, | |
4845 | * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this | |
4846 | * chipset include: | |
4847 | * | |
4848 | * 0xa290-0xa29f PCI Express Root port #{0-16} | |
4849 | * 0xa2e7-0xa2ee PCI Express Root port #{17-24} | |
4850 | * | |
e8440f4b AW |
4851 | * Mobile chipsets are also affected, 7th & 8th Generation |
4852 | * Specification update confirms ACS errata 22, status no fix: (7th Generation | |
4853 | * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel | |
4854 | * Processor Family I/O for U Quad Core Platforms Specification Update, | |
4855 | * August 2017, Revision 002, Document#: 334660-002)[6] | |
4856 | * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O | |
4857 | * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U | |
4858 | * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] | |
4859 | * | |
4860 | * 0x9d10-0x9d1b PCI Express Root port #{1-12} | |
4861 | * | |
7ecd4a81 AK |
4862 | * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html |
4863 | * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html | |
4864 | * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html | |
4865 | * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html | |
4866 | * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html | |
e8440f4b AW |
4867 | * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html |
4868 | * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html | |
1bf2bf22 AW |
4869 | */ |
4870 | static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) | |
4871 | { | |
7184f5b4 AW |
4872 | if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) |
4873 | return false; | |
4874 | ||
4875 | switch (dev->device) { | |
4876 | case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ | |
4877 | case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ | |
e8440f4b | 4878 | case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ |
7184f5b4 AW |
4879 | return true; |
4880 | } | |
4881 | ||
4882 | return false; | |
1bf2bf22 AW |
4883 | } |
4884 | ||
4885 | #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) | |
4886 | ||
4887 | static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) | |
4888 | { | |
4889 | int pos; | |
4890 | u32 cap, ctrl; | |
4891 | ||
4892 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) | |
4893 | return -ENOTTY; | |
4894 | ||
52fbf5bd | 4895 | pos = dev->acs_cap; |
1bf2bf22 AW |
4896 | if (!pos) |
4897 | return -ENOTTY; | |
4898 | ||
4899 | /* see pci_acs_flags_enabled() */ | |
4900 | pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); | |
4901 | acs_flags &= (cap | PCI_ACS_EC); | |
4902 | ||
4903 | pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); | |
4904 | ||
7cf2cba4 | 4905 | return pci_acs_ctrl_enabled(acs_flags, ctrl); |
1bf2bf22 AW |
4906 | } |
4907 | ||
100ebb2c | 4908 | static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) |
89b51cb5 AW |
4909 | { |
4910 | /* | |
4911 | * SV, TB, and UF are not relevant to multifunction endpoints. | |
4912 | * | |
100ebb2c AW |
4913 | * Multifunction devices are only required to implement RR, CR, and DT |
4914 | * in their ACS capability if they support peer-to-peer transactions. | |
4915 | * Devices matching this quirk have been verified by the vendor to not | |
4916 | * perform peer-to-peer with other functions, allowing us to mask out | |
4917 | * these bits as if they were unimplemented in the ACS capability. | |
89b51cb5 | 4918 | */ |
7cf2cba4 BH |
4919 | return pci_acs_ctrl_enabled(acs_flags, |
4920 | PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | | |
4921 | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); | |
89b51cb5 AW |
4922 | } |
4923 | ||
3247bd10 AR |
4924 | static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) |
4925 | { | |
4926 | /* | |
4927 | * Intel RCiEP's are required to allow p2p only on translated | |
4928 | * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, | |
4929 | * "Root-Complex Peer to Peer Considerations". | |
4930 | */ | |
4931 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) | |
4932 | return -ENOTTY; | |
4933 | ||
4934 | return pci_acs_ctrl_enabled(acs_flags, | |
4935 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
4936 | } | |
4937 | ||
46b2c32d AR |
4938 | static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) |
4939 | { | |
4940 | /* | |
4941 | * iProc PAXB Root Ports don't advertise an ACS capability, but | |
4942 | * they do not allow peer-to-peer transactions between Root Ports. | |
4943 | * Allow each Root Port to be in a separate IOMMU group by masking | |
4944 | * SV/RR/CR/UF bits. | |
4945 | */ | |
7cf2cba4 BH |
4946 | return pci_acs_ctrl_enabled(acs_flags, |
4947 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
46b2c32d AR |
4948 | } |
4949 | ||
a2b9b123 ML |
4950 | /* |
4951 | * Wangxun 10G/1G NICs have no ACS capability, and on multi-function | |
4952 | * devices, peer-to-peer transactions are not be used between the functions. | |
4953 | * So add an ACS quirk for below devices to isolate functions. | |
4954 | * SFxxx 1G NICs(em). | |
4955 | * RP1000/RP2000 10G NICs(sp). | |
4956 | */ | |
4957 | static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) | |
4958 | { | |
4959 | switch (dev->device) { | |
4960 | case 0x0100 ... 0x010F: | |
4961 | case 0x1001: | |
4962 | case 0x2001: | |
4963 | return pci_acs_ctrl_enabled(acs_flags, | |
4964 | PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
4965 | } | |
4966 | ||
4967 | return false; | |
4968 | } | |
4969 | ||
ad805758 AW |
4970 | static const struct pci_dev_acs_enabled { |
4971 | u16 vendor; | |
4972 | u16 device; | |
4973 | int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); | |
4974 | } pci_dev_acs_enabled[] = { | |
15b100df AW |
4975 | { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, |
4976 | { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, | |
4977 | { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, | |
4978 | { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, | |
4979 | { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, | |
4980 | { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, | |
3587e625 MR |
4981 | { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, |
4982 | { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, | |
100ebb2c AW |
4983 | { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, |
4984 | { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, | |
9fad4012 | 4985 | { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, |
100ebb2c AW |
4986 | { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, |
4987 | { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, | |
4988 | { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, | |
4989 | { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, | |
4990 | { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, | |
4991 | { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, | |
4992 | { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, | |
4993 | { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, | |
4994 | { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, | |
4995 | { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, | |
4996 | { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, | |
4997 | { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, | |
4998 | { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, | |
4999 | { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, | |
5000 | { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, | |
5001 | { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, | |
5002 | { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, | |
5003 | { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, | |
5004 | { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, | |
5005 | { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, | |
d748804f AW |
5006 | /* 82580 */ |
5007 | { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, | |
5008 | { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, | |
5009 | { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, | |
5010 | { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, | |
5011 | { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, | |
5012 | { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, | |
5013 | { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, | |
5014 | /* 82576 */ | |
5015 | { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, | |
5016 | { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, | |
5017 | { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, | |
5018 | { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, | |
5019 | { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, | |
5020 | { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, | |
5021 | { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, | |
5022 | { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, | |
5023 | /* 82575 */ | |
5024 | { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, | |
5025 | { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, | |
5026 | { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, | |
5027 | /* I350 */ | |
5028 | { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, | |
5029 | { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, | |
5030 | { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, | |
5031 | { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, | |
5032 | /* 82571 (Quads omitted due to non-ACS switch) */ | |
5033 | { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, | |
5034 | { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, | |
5035 | { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, | |
5036 | { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, | |
95e16587 AW |
5037 | /* I219 */ |
5038 | { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, | |
5039 | { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, | |
3247bd10 | 5040 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, |
33be632b | 5041 | /* QCOM QDF2xxx root ports */ |
333c8c12 BH |
5042 | { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, |
5043 | { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, | |
01926f6b SY |
5044 | /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ |
5045 | { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, | |
d748804f | 5046 | /* Intel PCH root ports */ |
d99321b6 | 5047 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, |
1bf2bf22 | 5048 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, |
6a3763d1 VV |
5049 | { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ |
5050 | { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ | |
b404bcfb MJ |
5051 | /* Cavium ThunderX */ |
5052 | { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, | |
32837d8a GC |
5053 | /* Cavium multi-function devices */ |
5054 | { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, | |
5055 | { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, | |
5056 | { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, | |
a0418aa2 FK |
5057 | /* APM X-Gene */ |
5058 | { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, | |
4ef76ad0 FK |
5059 | /* Ampere Computing */ |
5060 | { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, | |
5061 | { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, | |
5062 | { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, | |
5063 | { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, | |
5064 | { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, | |
5065 | { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, | |
5066 | { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, | |
5067 | { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, | |
db2f77e2 SB |
5068 | /* Broadcom multi-function device */ |
5069 | { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, | |
afd306a6 PC |
5070 | { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, |
5071 | { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, | |
5072 | { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, | |
46b2c32d | 5073 | { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, |
76e67e9e AS |
5074 | /* Amazon Annapurna Labs */ |
5075 | { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, | |
0325837c RP |
5076 | /* Zhaoxin multi-function devices */ |
5077 | { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, | |
5078 | { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, | |
5079 | { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, | |
d08c8b85 WK |
5080 | /* NXP root ports, xx=16, 12, or 08 cores */ |
5081 | /* LX2xx0A : without security features + CAN-FD */ | |
5082 | { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, | |
5083 | { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, | |
5084 | { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, | |
5085 | /* LX2xx0C : security features + CAN-FD */ | |
5086 | { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, | |
5087 | { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, | |
5088 | { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, | |
5089 | /* LX2xx0E : security features + CAN */ | |
5090 | { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, | |
5091 | { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, | |
5092 | { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, | |
5093 | /* LX2xx0N : without security features + CAN */ | |
5094 | { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, | |
5095 | { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, | |
5096 | { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, | |
5097 | /* LX2xx2A : without security features + CAN-FD */ | |
5098 | { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, | |
5099 | { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, | |
5100 | { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, | |
5101 | /* LX2xx2C : security features + CAN-FD */ | |
5102 | { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, | |
5103 | { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, | |
5104 | { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, | |
5105 | /* LX2xx2E : security features + CAN */ | |
5106 | { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, | |
5107 | { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, | |
5108 | { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, | |
5109 | /* LX2xx2N : without security features + CAN */ | |
5110 | { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, | |
5111 | { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, | |
5112 | { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, | |
299bd044 RP |
5113 | /* Zhaoxin Root/Downstream Ports */ |
5114 | { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, | |
a2b9b123 ML |
5115 | /* Wangxun nics */ |
5116 | { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, | |
ad805758 AW |
5117 | { 0 } |
5118 | }; | |
5119 | ||
7cf2cba4 BH |
5120 | /* |
5121 | * pci_dev_specific_acs_enabled - check whether device provides ACS controls | |
5122 | * @dev: PCI device | |
5123 | * @acs_flags: Bitmask of desired ACS controls | |
5124 | * | |
5125 | * Returns: | |
5126 | * -ENOTTY: No quirk applies to this device; we can't tell whether the | |
5127 | * device provides the desired controls | |
5128 | * 0: Device does not provide all the desired controls | |
5129 | * >0: Device provides all the controls in @acs_flags | |
5130 | */ | |
ad805758 AW |
5131 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) |
5132 | { | |
5133 | const struct pci_dev_acs_enabled *i; | |
5134 | int ret; | |
5135 | ||
5136 | /* | |
5137 | * Allow devices that do not expose standard PCIe ACS capabilities | |
5138 | * or control to indicate their support here. Multi-function express | |
5139 | * devices which do not allow internal peer-to-peer between functions, | |
5140 | * but do not implement PCIe ACS may wish to return true here. | |
5141 | */ | |
5142 | for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { | |
5143 | if ((i->vendor == dev->vendor || | |
5144 | i->vendor == (u16)PCI_ANY_ID) && | |
5145 | (i->device == dev->device || | |
5146 | i->device == (u16)PCI_ANY_ID)) { | |
5147 | ret = i->acs_enabled(dev, acs_flags); | |
5148 | if (ret >= 0) | |
5149 | return ret; | |
5150 | } | |
5151 | } | |
5152 | ||
5153 | return -ENOTTY; | |
5154 | } | |
2c744244 | 5155 | |
d99321b6 AW |
5156 | /* Config space offset of Root Complex Base Address register */ |
5157 | #define INTEL_LPC_RCBA_REG 0xf0 | |
5158 | /* 31:14 RCBA address */ | |
5159 | #define INTEL_LPC_RCBA_MASK 0xffffc000 | |
5160 | /* RCBA Enable */ | |
5161 | #define INTEL_LPC_RCBA_ENABLE (1 << 0) | |
5162 | ||
5163 | /* Backbone Scratch Pad Register */ | |
5164 | #define INTEL_BSPR_REG 0x1104 | |
5165 | /* Backbone Peer Non-Posted Disable */ | |
5166 | #define INTEL_BSPR_REG_BPNPD (1 << 8) | |
5167 | /* Backbone Peer Posted Disable */ | |
5168 | #define INTEL_BSPR_REG_BPPD (1 << 9) | |
5169 | ||
5170 | /* Upstream Peer Decode Configuration Register */ | |
d8558ac8 | 5171 | #define INTEL_UPDCR_REG 0x1014 |
d99321b6 AW |
5172 | /* 5:0 Peer Decode Enable bits */ |
5173 | #define INTEL_UPDCR_REG_MASK 0x3f | |
5174 | ||
5175 | static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) | |
5176 | { | |
5177 | u32 rcba, bspr, updcr; | |
5178 | void __iomem *rcba_mem; | |
5179 | ||
5180 | /* | |
5181 | * Read the RCBA register from the LPC (D31:F0). PCH root ports | |
5182 | * are D28:F* and therefore get probed before LPC, thus we can't | |
82e1719c | 5183 | * use pci_get_slot()/pci_read_config_dword() here. |
d99321b6 AW |
5184 | */ |
5185 | pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), | |
5186 | INTEL_LPC_RCBA_REG, &rcba); | |
5187 | if (!(rcba & INTEL_LPC_RCBA_ENABLE)) | |
5188 | return -EINVAL; | |
5189 | ||
4bdc0d67 | 5190 | rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, |
d99321b6 AW |
5191 | PAGE_ALIGN(INTEL_UPDCR_REG)); |
5192 | if (!rcba_mem) | |
5193 | return -ENOMEM; | |
5194 | ||
5195 | /* | |
5196 | * The BSPR can disallow peer cycles, but it's set by soft strap and | |
5197 | * therefore read-only. If both posted and non-posted peer cycles are | |
5198 | * disallowed, we're ok. If either are allowed, then we need to use | |
5199 | * the UPDCR to disable peer decodes for each port. This provides the | |
5200 | * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | |
5201 | */ | |
5202 | bspr = readl(rcba_mem + INTEL_BSPR_REG); | |
5203 | bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; | |
5204 | if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { | |
5205 | updcr = readl(rcba_mem + INTEL_UPDCR_REG); | |
5206 | if (updcr & INTEL_UPDCR_REG_MASK) { | |
7506dc79 | 5207 | pci_info(dev, "Disabling UPDCR peer decodes\n"); |
d99321b6 AW |
5208 | updcr &= ~INTEL_UPDCR_REG_MASK; |
5209 | writel(updcr, rcba_mem + INTEL_UPDCR_REG); | |
5210 | } | |
5211 | } | |
5212 | ||
5213 | iounmap(rcba_mem); | |
5214 | return 0; | |
5215 | } | |
5216 | ||
5217 | /* Miscellaneous Port Configuration register */ | |
5218 | #define INTEL_MPC_REG 0xd8 | |
5219 | /* MPC: Invalid Receive Bus Number Check Enable */ | |
5220 | #define INTEL_MPC_REG_IRBNCE (1 << 26) | |
5221 | ||
5222 | static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) | |
5223 | { | |
5224 | u32 mpc; | |
5225 | ||
5226 | /* | |
5227 | * When enabled, the IRBNCE bit of the MPC register enables the | |
5228 | * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which | |
5229 | * ensures that requester IDs fall within the bus number range | |
5230 | * of the bridge. Enable if not already. | |
5231 | */ | |
5232 | pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); | |
5233 | if (!(mpc & INTEL_MPC_REG_IRBNCE)) { | |
7506dc79 | 5234 | pci_info(dev, "Enabling MPC IRBNCE\n"); |
d99321b6 AW |
5235 | mpc |= INTEL_MPC_REG_IRBNCE; |
5236 | pci_write_config_word(dev, INTEL_MPC_REG, mpc); | |
5237 | } | |
5238 | } | |
5239 | ||
76fc8e85 RJ |
5240 | /* |
5241 | * Currently this quirk does the equivalent of | |
5242 | * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | |
5243 | * | |
5244 | * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, | |
5245 | * if dev->external_facing || dev->untrusted | |
5246 | */ | |
d99321b6 AW |
5247 | static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) |
5248 | { | |
5249 | if (!pci_quirk_intel_pch_acs_match(dev)) | |
5250 | return -ENOTTY; | |
5251 | ||
5252 | if (pci_quirk_enable_intel_lpc_acs(dev)) { | |
7506dc79 | 5253 | pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); |
d99321b6 AW |
5254 | return 0; |
5255 | } | |
5256 | ||
5257 | pci_quirk_enable_intel_rp_mpc_acs(dev); | |
5258 | ||
5259 | dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; | |
5260 | ||
7506dc79 | 5261 | pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); |
d99321b6 AW |
5262 | |
5263 | return 0; | |
5264 | } | |
5265 | ||
1bf2bf22 AW |
5266 | static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) |
5267 | { | |
5268 | int pos; | |
5269 | u32 cap, ctrl; | |
5270 | ||
5271 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) | |
5272 | return -ENOTTY; | |
5273 | ||
52fbf5bd | 5274 | pos = dev->acs_cap; |
1bf2bf22 AW |
5275 | if (!pos) |
5276 | return -ENOTTY; | |
5277 | ||
5278 | pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); | |
5279 | pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); | |
5280 | ||
5281 | ctrl |= (cap & PCI_ACS_SV); | |
5282 | ctrl |= (cap & PCI_ACS_RR); | |
5283 | ctrl |= (cap & PCI_ACS_CR); | |
5284 | ctrl |= (cap & PCI_ACS_UF); | |
5285 | ||
7cae7849 | 5286 | if (pci_ats_disabled() || dev->external_facing || dev->untrusted) |
76fc8e85 RJ |
5287 | ctrl |= (cap & PCI_ACS_TB); |
5288 | ||
1bf2bf22 AW |
5289 | pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); |
5290 | ||
7506dc79 | 5291 | pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); |
1bf2bf22 AW |
5292 | |
5293 | return 0; | |
5294 | } | |
5295 | ||
10dbc9fe LG |
5296 | static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) |
5297 | { | |
5298 | int pos; | |
5299 | u32 cap, ctrl; | |
5300 | ||
5301 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) | |
5302 | return -ENOTTY; | |
5303 | ||
52fbf5bd | 5304 | pos = dev->acs_cap; |
10dbc9fe LG |
5305 | if (!pos) |
5306 | return -ENOTTY; | |
5307 | ||
5308 | pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); | |
5309 | pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); | |
5310 | ||
5311 | ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); | |
5312 | ||
5313 | pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); | |
5314 | ||
5315 | pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); | |
5316 | ||
5317 | return 0; | |
5318 | } | |
5319 | ||
73c47dde | 5320 | static const struct pci_dev_acs_ops { |
2c744244 AW |
5321 | u16 vendor; |
5322 | u16 device; | |
5323 | int (*enable_acs)(struct pci_dev *dev); | |
73c47dde LG |
5324 | int (*disable_acs_redir)(struct pci_dev *dev); |
5325 | } pci_dev_acs_ops[] = { | |
5326 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, | |
5327 | .enable_acs = pci_quirk_enable_intel_pch_acs, | |
5328 | }, | |
5329 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, | |
5330 | .enable_acs = pci_quirk_enable_intel_spt_pch_acs, | |
10dbc9fe | 5331 | .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, |
73c47dde | 5332 | }, |
2c744244 AW |
5333 | }; |
5334 | ||
c1d61c9b | 5335 | int pci_dev_specific_enable_acs(struct pci_dev *dev) |
2c744244 | 5336 | { |
73c47dde | 5337 | const struct pci_dev_acs_ops *p; |
3b269185 | 5338 | int i, ret; |
2c744244 | 5339 | |
73c47dde LG |
5340 | for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { |
5341 | p = &pci_dev_acs_ops[i]; | |
3b269185 LG |
5342 | if ((p->vendor == dev->vendor || |
5343 | p->vendor == (u16)PCI_ANY_ID) && | |
5344 | (p->device == dev->device || | |
73c47dde LG |
5345 | p->device == (u16)PCI_ANY_ID) && |
5346 | p->enable_acs) { | |
3b269185 | 5347 | ret = p->enable_acs(dev); |
2c744244 | 5348 | if (ret >= 0) |
73c47dde LG |
5349 | return ret; |
5350 | } | |
5351 | } | |
2c744244 | 5352 | |
73c47dde LG |
5353 | return -ENOTTY; |
5354 | } | |
5355 | ||
5356 | int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) | |
5357 | { | |
5358 | const struct pci_dev_acs_ops *p; | |
5359 | int i, ret; | |
5360 | ||
5361 | for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { | |
5362 | p = &pci_dev_acs_ops[i]; | |
5363 | if ((p->vendor == dev->vendor || | |
5364 | p->vendor == (u16)PCI_ANY_ID) && | |
5365 | (p->device == dev->device || | |
5366 | p->device == (u16)PCI_ANY_ID) && | |
5367 | p->disable_acs_redir) { | |
5368 | ret = p->disable_acs_redir(dev); | |
2c744244 | 5369 | if (ret >= 0) |
c1d61c9b | 5370 | return ret; |
2c744244 AW |
5371 | } |
5372 | } | |
c1d61c9b AW |
5373 | |
5374 | return -ENOTTY; | |
2c744244 | 5375 | } |
3388a614 TS |
5376 | |
5377 | /* | |
82e1719c | 5378 | * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with |
3388a614 TS |
5379 | * QuickAssist Technology (QAT) is prematurely terminated in hardware. The |
5380 | * Next Capability pointer in the MSI Capability Structure should point to | |
5381 | * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating | |
5382 | * the list. | |
5383 | */ | |
5384 | static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) | |
5385 | { | |
5386 | int pos, i = 0; | |
5387 | u8 next_cap; | |
5388 | u16 reg16, *cap; | |
5389 | struct pci_cap_saved_state *state; | |
5390 | ||
5391 | /* Bail if the hardware bug is fixed */ | |
5392 | if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) | |
5393 | return; | |
5394 | ||
5395 | /* Bail if MSI Capability Structure is not found for some reason */ | |
5396 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); | |
5397 | if (!pos) | |
5398 | return; | |
5399 | ||
5400 | /* | |
5401 | * Bail if Next Capability pointer in the MSI Capability Structure | |
5402 | * is not the expected incorrect 0x00. | |
5403 | */ | |
5404 | pci_read_config_byte(pdev, pos + 1, &next_cap); | |
5405 | if (next_cap) | |
5406 | return; | |
5407 | ||
5408 | /* | |
5409 | * PCIe Capability Structure is expected to be at 0x50 and should | |
5410 | * terminate the list (Next Capability pointer is 0x00). Verify | |
5411 | * Capability Id and Next Capability pointer is as expected. | |
5412 | * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() | |
5413 | * to correctly set kernel data structures which have already been | |
5414 | * set incorrectly due to the hardware bug. | |
5415 | */ | |
5416 | pos = 0x50; | |
5417 | pci_read_config_word(pdev, pos, ®16); | |
5418 | if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { | |
5419 | u32 status; | |
5420 | #ifndef PCI_EXP_SAVE_REGS | |
5421 | #define PCI_EXP_SAVE_REGS 7 | |
5422 | #endif | |
5423 | int size = PCI_EXP_SAVE_REGS * sizeof(u16); | |
5424 | ||
5425 | pdev->pcie_cap = pos; | |
5426 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
5427 | pdev->pcie_flags_reg = reg16; | |
5428 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); | |
5429 | pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; | |
5430 | ||
5431 | pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; | |
5432 | if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != | |
5433 | PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) | |
5434 | pdev->cfg_size = PCI_CFG_SPACE_SIZE; | |
5435 | ||
5436 | if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) | |
5437 | return; | |
5438 | ||
82e1719c | 5439 | /* Save PCIe cap */ |
3388a614 TS |
5440 | state = kzalloc(sizeof(*state) + size, GFP_KERNEL); |
5441 | if (!state) | |
5442 | return; | |
5443 | ||
5444 | state->cap.cap_nr = PCI_CAP_ID_EXP; | |
5445 | state->cap.cap_extended = 0; | |
5446 | state->cap.size = size; | |
5447 | cap = (u16 *)&state->cap.data[0]; | |
5448 | pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); | |
5449 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); | |
5450 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); | |
5451 | pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); | |
5452 | pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); | |
5453 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); | |
5454 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); | |
5455 | hlist_add_head(&state->next, &pdev->saved_cap_space); | |
5456 | } | |
5457 | } | |
5458 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); | |
443b40ba | 5459 | |
0d14f06c MS |
5460 | /* |
5461 | * FLR may cause the following to devices to hang: | |
5462 | * | |
5463 | * AMD Starship/Matisse HD Audio Controller 0x1487 | |
5727043c | 5464 | * AMD Starship USB 3.0 Host Controller 0x148c |
0d14f06c MS |
5465 | * AMD Matisse USB 3.0 Host Controller 0x149c |
5466 | * Intel 82579LM Gigabit Ethernet Controller 0x1502 | |
5467 | * Intel 82579V Gigabit Ethernet Controller 0x1503 | |
5468 | * | |
5469 | */ | |
5470 | static void quirk_no_flr(struct pci_dev *dev) | |
f65fd1aa SN |
5471 | { |
5472 | dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; | |
5473 | } | |
0d14f06c | 5474 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); |
5727043c | 5475 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); |
0d14f06c | 5476 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); |
63ba51db | 5477 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); |
0d14f06c MS |
5478 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); |
5479 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); | |
62ce94a7 | 5480 | |
d089d69c AK |
5481 | /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ |
5482 | static void quirk_no_flr_snet(struct pci_dev *dev) | |
5483 | { | |
5484 | if (dev->revision == 0x1) | |
5485 | quirk_no_flr(dev); | |
5486 | } | |
5487 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); | |
5488 | ||
62ce94a7 SK |
5489 | static void quirk_no_ext_tags(struct pci_dev *pdev) |
5490 | { | |
5491 | struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); | |
5492 | ||
5493 | if (!bridge) | |
5494 | return; | |
5495 | ||
5496 | bridge->no_ext_tags = 1; | |
7506dc79 | 5497 | pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); |
62ce94a7 SK |
5498 | |
5499 | pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); | |
5500 | } | |
1b30dfd3 | 5501 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); |
62ce94a7 | 5502 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); |
1b30dfd3 | 5503 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); |
62ce94a7 SK |
5504 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); |
5505 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); | |
1b30dfd3 SK |
5506 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); |
5507 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); | |
cf2d8041 | 5508 | |
9b44b0b0 JR |
5509 | #ifdef CONFIG_PCI_ATS |
5510 | /* | |
5e89cd30 AD |
5511 | * Some devices require additional driver setup to enable ATS. Don't use |
5512 | * ATS for those devices as ATS will be enabled before the driver has had a | |
5513 | * chance to load and configure the device. | |
9b44b0b0 | 5514 | */ |
5e89cd30 | 5515 | static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) |
9b44b0b0 | 5516 | { |
a2da5d8c AD |
5517 | if (pdev->device == 0x15d8) { |
5518 | if (pdev->revision == 0xcf && | |
5519 | pdev->subsystem_vendor == 0xea50 && | |
5520 | (pdev->subsystem_device == 0xce19 || | |
5521 | pdev->subsystem_device == 0xcc10 || | |
5522 | pdev->subsystem_device == 0xcc08)) | |
5523 | goto no_ats; | |
5524 | else | |
5525 | return; | |
5526 | } | |
5527 | ||
5528 | no_ats: | |
5e89cd30 | 5529 | pci_info(pdev, "disabling ATS\n"); |
9b44b0b0 JR |
5530 | pdev->ats_cap = 0; |
5531 | } | |
5532 | ||
5533 | /* AMD Stoney platform GPU */ | |
5e89cd30 AD |
5534 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); |
5535 | /* AMD Iceland dGPU */ | |
5536 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); | |
45beb31d | 5537 | /* AMD Navi10 dGPU */ |
3f1271b5 | 5538 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); |
45beb31d | 5539 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); |
3f1271b5 AD |
5540 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); |
5541 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); | |
5542 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); | |
5543 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); | |
5544 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); | |
5545 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); | |
5e89cd30 AD |
5546 | /* AMD Navi14 dGPU */ |
5547 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); | |
e8946a53 | 5548 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); |
3f1271b5 AD |
5549 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); |
5550 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); | |
a2da5d8c AD |
5551 | /* AMD Raven platform iGPU */ |
5552 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); | |
9b44b0b0 | 5553 | #endif /* CONFIG_PCI_ATS */ |
06dc4ee5 HZ |
5554 | |
5555 | /* Freescale PCIe doesn't support MSI in RC mode */ | |
5556 | static void quirk_fsl_no_msi(struct pci_dev *pdev) | |
5557 | { | |
5558 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) | |
5559 | pdev->no_msi = 1; | |
5560 | } | |
5561 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); | |
07f4f97d LW |
5562 | |
5563 | /* | |
a17beb1a AS |
5564 | * Although not allowed by the spec, some multi-function devices have |
5565 | * dependencies of one function (consumer) on another (supplier). For the | |
5566 | * consumer to work in D0, the supplier must also be in D0. Create a | |
5567 | * device link from the consumer to the supplier to enforce this | |
5568 | * dependency. Runtime PM is allowed by default on the consumer to prevent | |
5569 | * it from permanently keeping the supplier awake. | |
07f4f97d | 5570 | */ |
a17beb1a AS |
5571 | static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, |
5572 | unsigned int supplier, unsigned int class, | |
5573 | unsigned int class_shift) | |
07f4f97d | 5574 | { |
a17beb1a | 5575 | struct pci_dev *supplier_pdev; |
07f4f97d | 5576 | |
a17beb1a | 5577 | if (PCI_FUNC(pdev->devfn) != consumer) |
07f4f97d LW |
5578 | return; |
5579 | ||
a17beb1a AS |
5580 | supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), |
5581 | pdev->bus->number, | |
5582 | PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); | |
5583 | if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { | |
5584 | pci_dev_put(supplier_pdev); | |
07f4f97d LW |
5585 | return; |
5586 | } | |
5587 | ||
a17beb1a AS |
5588 | if (device_link_add(&pdev->dev, &supplier_pdev->dev, |
5589 | DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) | |
5590 | pci_info(pdev, "D0 power state depends on %s\n", | |
5591 | pci_name(supplier_pdev)); | |
5592 | else | |
5593 | pci_err(pdev, "Cannot enforce power dependency on %s\n", | |
5594 | pci_name(supplier_pdev)); | |
5595 | ||
5596 | pm_runtime_allow(&pdev->dev); | |
5597 | pci_dev_put(supplier_pdev); | |
5598 | } | |
07f4f97d | 5599 | |
a17beb1a AS |
5600 | /* |
5601 | * Create device link for GPUs with integrated HDA controller for streaming | |
5602 | * audio to attached displays. | |
5603 | */ | |
5604 | static void quirk_gpu_hda(struct pci_dev *hda) | |
5605 | { | |
5606 | pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); | |
07f4f97d LW |
5607 | } |
5608 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, | |
5609 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); | |
5610 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, | |
5611 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); | |
5612 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, | |
5613 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); | |
aa667c64 | 5614 | |
6d2e369f | 5615 | /* |
60b78ed0 | 5616 | * Create device link for GPUs with integrated USB xHCI Host |
6d2e369f AS |
5617 | * controller to VGA. |
5618 | */ | |
5619 | static void quirk_gpu_usb(struct pci_dev *usb) | |
5620 | { | |
5621 | pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); | |
5622 | } | |
5623 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, | |
5624 | PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); | |
60b78ed0 EQ |
5625 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, |
5626 | PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); | |
6d2e369f AS |
5627 | |
5628 | /* | |
60b78ed0 | 5629 | * Create device link for GPUs with integrated Type-C UCSI controller |
6d2e369f AS |
5630 | * to VGA. Currently there is no class code defined for UCSI device over PCI |
5631 | * so using UNKNOWN class for now and it will be updated when UCSI | |
5632 | * over PCI gets a class code. | |
5633 | */ | |
5634 | #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 | |
5635 | static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) | |
5636 | { | |
5637 | pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); | |
5638 | } | |
5639 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, | |
5640 | PCI_CLASS_SERIAL_UNKNOWN, 8, | |
5641 | quirk_gpu_usb_typec_ucsi); | |
60b78ed0 EQ |
5642 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, |
5643 | PCI_CLASS_SERIAL_UNKNOWN, 8, | |
5644 | quirk_gpu_usb_typec_ucsi); | |
6d2e369f | 5645 | |
b516ea58 LW |
5646 | /* |
5647 | * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it | |
5648 | * disabled. https://devtalk.nvidia.com/default/topic/1024022 | |
5649 | */ | |
5650 | static void quirk_nvidia_hda(struct pci_dev *gpu) | |
5651 | { | |
5652 | u8 hdr_type; | |
5653 | u32 val; | |
5654 | ||
5655 | /* There was no integrated HDA controller before MCP89 */ | |
5656 | if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) | |
5657 | return; | |
5658 | ||
5659 | /* Bit 25 at offset 0x488 enables the HDA controller */ | |
5660 | pci_read_config_dword(gpu, 0x488, &val); | |
5661 | if (val & BIT(25)) | |
5662 | return; | |
5663 | ||
5664 | pci_info(gpu, "Enabling HDA controller\n"); | |
5665 | pci_write_config_dword(gpu, 0x488, val | BIT(25)); | |
5666 | ||
5667 | /* The GPU becomes a multi-function device when the HDA is enabled */ | |
5668 | pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); | |
5669 | gpu->multifunction = !!(hdr_type & 0x80); | |
5670 | } | |
5671 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, | |
5672 | PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); | |
5673 | DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, | |
5674 | PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); | |
5675 | ||
aa667c64 JP |
5676 | /* |
5677 | * Some IDT switches incorrectly flag an ACS Source Validation error on | |
5678 | * completions for config read requests even though PCIe r4.0, sec | |
5679 | * 6.12.1.1, says that completions are never affected by ACS Source | |
5680 | * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: | |
5681 | * | |
5682 | * Item #36 - Downstream port applies ACS Source Validation to Completions | |
5683 | * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that | |
5684 | * completions are never affected by ACS Source Validation. However, | |
5685 | * completions received by a downstream port of the PCIe switch from a | |
5686 | * device that has not yet captured a PCIe bus number are incorrectly | |
5687 | * dropped by ACS Source Validation by the switch downstream port. | |
5688 | * | |
5689 | * The workaround suggested by IDT is to issue a config write to the | |
5690 | * downstream device before issuing the first config read. This allows the | |
5691 | * downstream device to capture its bus and device numbers (see PCIe r4.0, | |
5692 | * sec 2.2.9), thus avoiding the ACS error on the completion. | |
5693 | * | |
5694 | * However, we don't know when the device is ready to accept the config | |
5695 | * write, so we do config reads until we receive a non-Config Request Retry | |
5696 | * Status, then do the config write. | |
5697 | * | |
5698 | * To avoid hitting the erratum when doing the config reads, we disable ACS | |
5699 | * SV around this process. | |
5700 | */ | |
5701 | int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) | |
5702 | { | |
5703 | int pos; | |
5704 | u16 ctrl = 0; | |
5705 | bool found; | |
5706 | struct pci_dev *bridge = bus->self; | |
5707 | ||
52fbf5bd | 5708 | pos = bridge->acs_cap; |
aa667c64 JP |
5709 | |
5710 | /* Disable ACS SV before initial config reads */ | |
5711 | if (pos) { | |
5712 | pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); | |
5713 | if (ctrl & PCI_ACS_SV) | |
5714 | pci_write_config_word(bridge, pos + PCI_ACS_CTRL, | |
5715 | ctrl & ~PCI_ACS_SV); | |
5716 | } | |
5717 | ||
5718 | found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); | |
5719 | ||
5720 | /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ | |
5721 | if (found) | |
5722 | pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); | |
5723 | ||
5724 | /* Re-enable ACS_SV if it was previously enabled */ | |
5725 | if (ctrl & PCI_ACS_SV) | |
5726 | pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); | |
5727 | ||
5728 | return found; | |
5729 | } | |
e7aaf90f | 5730 | |
ad281ecf DM |
5731 | /* |
5732 | * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between | |
5733 | * NT endpoints via the internal switch fabric. These IDs replace the | |
86b4ad7d | 5734 | * originating Requester ID TLPs which access host memory on peer NTB |
ad281ecf DM |
5735 | * ports. Therefore, all proxy IDs must be aliased to the NTB device |
5736 | * to permit access when the IOMMU is turned on. | |
5737 | */ | |
5738 | static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) | |
5739 | { | |
5740 | void __iomem *mmio; | |
5741 | struct ntb_info_regs __iomem *mmio_ntb; | |
5742 | struct ntb_ctrl_regs __iomem *mmio_ctrl; | |
ad281ecf DM |
5743 | u64 partition_map; |
5744 | u8 partition; | |
5745 | int pp; | |
5746 | ||
5747 | if (pci_enable_device(pdev)) { | |
5748 | pci_err(pdev, "Cannot enable Switchtec device\n"); | |
5749 | return; | |
5750 | } | |
5751 | ||
5752 | mmio = pci_iomap(pdev, 0, 0); | |
5753 | if (mmio == NULL) { | |
5754 | pci_disable_device(pdev); | |
5755 | pci_err(pdev, "Cannot iomap Switchtec device\n"); | |
5756 | return; | |
5757 | } | |
5758 | ||
5759 | pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); | |
5760 | ||
5761 | mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; | |
5762 | mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; | |
ad281ecf DM |
5763 | |
5764 | partition = ioread8(&mmio_ntb->partition_id); | |
5765 | ||
5766 | partition_map = ioread32(&mmio_ntb->ep_map); | |
5767 | partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; | |
5768 | partition_map &= ~(1ULL << partition); | |
5769 | ||
5770 | for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { | |
5771 | struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; | |
5772 | u32 table_sz = 0; | |
5773 | int te; | |
5774 | ||
5775 | if (!(partition_map & (1ULL << pp))) | |
5776 | continue; | |
5777 | ||
5778 | pci_dbg(pdev, "Processing partition %d\n", pp); | |
5779 | ||
5780 | mmio_peer_ctrl = &mmio_ctrl[pp]; | |
5781 | ||
5782 | table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); | |
5783 | if (!table_sz) { | |
5784 | pci_warn(pdev, "Partition %d table_sz 0\n", pp); | |
5785 | continue; | |
5786 | } | |
5787 | ||
5788 | if (table_sz > 512) { | |
5789 | pci_warn(pdev, | |
5790 | "Invalid Switchtec partition %d table_sz %d\n", | |
5791 | pp, table_sz); | |
5792 | continue; | |
5793 | } | |
5794 | ||
5795 | for (te = 0; te < table_sz; te++) { | |
5796 | u32 rid_entry; | |
5797 | u8 devfn; | |
5798 | ||
5799 | rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); | |
5800 | devfn = (rid_entry >> 1) & 0xFF; | |
5801 | pci_dbg(pdev, | |
5802 | "Aliasing Partition %d Proxy ID %02x.%d\n", | |
5803 | pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
09298542 | 5804 | pci_add_dma_alias(pdev, devfn, 1); |
ad281ecf DM |
5805 | } |
5806 | } | |
5807 | ||
5808 | pci_iounmap(pdev, mmio); | |
5809 | pci_disable_device(pdev); | |
5810 | } | |
01d5d7fa | 5811 | #define SWITCHTEC_QUIRK(vid) \ |
742bbe1e LG |
5812 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ |
5813 | PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) | |
01d5d7fa LG |
5814 | |
5815 | SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ | |
5816 | SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ | |
5817 | SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ | |
5818 | SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ | |
5819 | SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ | |
5820 | SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ | |
5821 | SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ | |
5822 | SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ | |
5823 | SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ | |
5824 | SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ | |
5825 | SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ | |
5826 | SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ | |
5827 | SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ | |
5828 | SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ | |
5829 | SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ | |
5830 | SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ | |
5831 | SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ | |
5832 | SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ | |
5833 | SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ | |
5834 | SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ | |
5835 | SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ | |
5836 | SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ | |
5837 | SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ | |
5838 | SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ | |
5839 | SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ | |
5840 | SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ | |
5841 | SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ | |
5842 | SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ | |
5843 | SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ | |
5844 | SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ | |
7a30ebb9 KC |
5845 | SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ |
5846 | SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ | |
5847 | SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ | |
5848 | SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ | |
5849 | SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ | |
5850 | SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ | |
5851 | SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ | |
5852 | SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ | |
5853 | SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ | |
5854 | SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ | |
5855 | SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ | |
5856 | SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ | |
5857 | SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ | |
5858 | SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ | |
5859 | SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ | |
5860 | SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ | |
5861 | SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ | |
5862 | SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ | |
bb17b158 KC |
5863 | SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ |
5864 | SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ | |
5865 | SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ | |
5866 | SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ | |
5867 | SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ | |
5868 | SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ | |
5869 | SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ | |
5870 | SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ | |
5871 | SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ | |
0fb53e64 KC |
5872 | SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ |
5873 | SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ | |
5874 | SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ | |
5875 | SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ | |
5876 | SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ | |
5877 | SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ | |
5878 | SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ | |
5879 | SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ | |
5880 | SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ | |
5881 | SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ | |
5882 | SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ | |
5883 | SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ | |
5884 | SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ | |
5885 | SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ | |
5886 | SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ | |
5887 | SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ | |
5888 | SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ | |
5889 | SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ | |
5890 | SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ | |
5891 | SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ | |
5892 | SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ | |
5893 | SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ | |
5894 | SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ | |
5895 | SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ | |
5896 | SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ | |
5897 | SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ | |
5898 | SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ | |
5899 | SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ | |
5900 | SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ | |
5901 | SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ | |
5902 | SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ | |
5903 | SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ | |
5904 | SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ | |
5905 | SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ | |
5906 | SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ | |
5907 | SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ | |
e0547c81 | 5908 | |
7b90dfc4 JS |
5909 | /* |
5910 | * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. | |
5911 | * These IDs are used to forward responses to the originator on the other | |
5912 | * side of the NTB. Alias all possible IDs to the NTB to permit access when | |
5913 | * the IOMMU is turned on. | |
5914 | */ | |
5915 | static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) | |
5916 | { | |
5917 | pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); | |
5918 | /* PLX NTB may use all 256 devfns */ | |
5919 | pci_add_dma_alias(pdev, 0, 256); | |
5920 | } | |
5921 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); | |
5922 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); | |
e0547c81 LP |
5923 | |
5924 | /* | |
5925 | * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does | |
5926 | * not always reset the secondary Nvidia GPU between reboots if the system | |
5927 | * is configured to use Hybrid Graphics mode. This results in the GPU | |
5928 | * being left in whatever state it was in during the *previous* boot, which | |
5929 | * causes spurious interrupts from the GPU, which in turn causes us to | |
5930 | * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, | |
5931 | * this also completely breaks nouveau. | |
5932 | * | |
5933 | * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a | |
5934 | * clean state and fixes all these issues. | |
5935 | * | |
5936 | * When the machine is configured in Dedicated display mode, the issue | |
5937 | * doesn't occur. Fortunately the GPU advertises NoReset+ when in this | |
5938 | * mode, so we can detect that and avoid resetting it. | |
5939 | */ | |
5940 | static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) | |
5941 | { | |
5942 | void __iomem *map; | |
5943 | int ret; | |
5944 | ||
5945 | if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || | |
5946 | pdev->subsystem_device != 0x222e || | |
4ec36dfe | 5947 | !pci_reset_supported(pdev)) |
e0547c81 LP |
5948 | return; |
5949 | ||
5950 | if (pci_enable_device_mem(pdev)) | |
5951 | return; | |
5952 | ||
5953 | /* | |
5954 | * Based on nvkm_device_ctor() in | |
5955 | * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | |
5956 | */ | |
5957 | map = pci_iomap(pdev, 0, 0x23000); | |
5958 | if (!map) { | |
5959 | pci_err(pdev, "Can't map MMIO space\n"); | |
5960 | goto out_disable; | |
5961 | } | |
5962 | ||
5963 | /* | |
5964 | * Make sure the GPU looks like it's been POSTed before resetting | |
5965 | * it. | |
5966 | */ | |
5967 | if (ioread32(map + 0x2240c) & 0x2) { | |
5968 | pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); | |
ad54567a | 5969 | ret = pci_reset_bus(pdev); |
e0547c81 LP |
5970 | if (ret < 0) |
5971 | pci_err(pdev, "Failed to reset GPU: %d\n", ret); | |
5972 | } | |
5973 | ||
5974 | iounmap(map); | |
5975 | out_disable: | |
5976 | pci_disable_device(pdev); | |
5977 | } | |
5978 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, | |
5979 | PCI_CLASS_DISPLAY_VGA, 8, | |
5980 | quirk_reset_lenovo_thinkpad_p50_nvgpu); | |
2880325b KHF |
5981 | |
5982 | /* | |
5983 | * Device [1b21:2142] | |
5984 | * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. | |
5985 | */ | |
5986 | static void pci_fixup_no_d0_pme(struct pci_dev *dev) | |
5987 | { | |
5988 | pci_info(dev, "PME# does not work under D0, disabling it\n"); | |
5989 | dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); | |
5990 | } | |
5991 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); | |
0a8f4102 | 5992 | |
68f5fc4e | 5993 | /* |
f83c3794 AS |
5994 | * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] |
5995 | * | |
68f5fc4e KHF |
5996 | * These devices advertise PME# support in all power states but don't |
5997 | * reliably assert it. | |
f83c3794 AS |
5998 | * |
5999 | * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) | |
6000 | * says "The MSI Function is not implemented on this device" in chapters | |
6001 | * 7.3.27, 7.3.29-7.3.31. | |
68f5fc4e | 6002 | */ |
f83c3794 | 6003 | static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) |
68f5fc4e | 6004 | { |
f83c3794 AS |
6005 | #ifdef CONFIG_PCI_MSI |
6006 | pci_info(dev, "MSI is not implemented on this device, disabling it\n"); | |
6007 | dev->no_msi = 1; | |
6008 | #endif | |
68f5fc4e KHF |
6009 | pci_info(dev, "PME# is unreliable, disabling it\n"); |
6010 | dev->pme_support = 0; | |
6011 | } | |
f83c3794 AS |
6012 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); |
6013 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); | |
3925c3bb | 6014 | |
0a8f4102 BH |
6015 | static void apex_pci_fixup_class(struct pci_dev *pdev) |
6016 | { | |
6017 | pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; | |
6018 | } | |
6019 | DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, | |
6020 | PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); | |
acd61ffb NR |
6021 | |
6022 | /* | |
6023 | * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - | |
6024 | * ACS P2P Request Redirect is not functional | |
6025 | * | |
6026 | * When ACS P2P Request Redirect is enabled and bandwidth is not balanced | |
6027 | * between upstream and downstream ports, packets are queued in an internal | |
6028 | * buffer until CPLD packet. The workaround is to use the switch in store and | |
6029 | * forward mode. | |
6030 | */ | |
6031 | #define PI7C9X2Gxxx_MODE_REG 0x74 | |
6032 | #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) | |
6033 | static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) | |
6034 | { | |
6035 | struct pci_dev *upstream; | |
6036 | u16 val; | |
6037 | ||
6038 | /* Downstream ports only */ | |
6039 | if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) | |
6040 | return; | |
6041 | ||
6042 | /* Check for ACS P2P Request Redirect use */ | |
6043 | if (!pdev->acs_cap) | |
6044 | return; | |
6045 | pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); | |
6046 | if (!(val & PCI_ACS_RR)) | |
6047 | return; | |
6048 | ||
6049 | upstream = pci_upstream_bridge(pdev); | |
6050 | if (!upstream) | |
6051 | return; | |
6052 | ||
6053 | pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); | |
6054 | if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { | |
6055 | pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); | |
6056 | pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | | |
6057 | PI7C9X2Gxxx_STORE_FORWARD_MODE); | |
6058 | } | |
6059 | } | |
6060 | /* | |
6061 | * Apply fixup on enable and on resume, in order to apply the fix up whenever | |
6062 | * ACS configuration changes or switch mode is reset | |
6063 | */ | |
6064 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, | |
6065 | pci_fixup_pericom_acs_store_forward); | |
6066 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, | |
6067 | pci_fixup_pericom_acs_store_forward); | |
6068 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, | |
6069 | pci_fixup_pericom_acs_store_forward); | |
6070 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, | |
6071 | pci_fixup_pericom_acs_store_forward); | |
6072 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, | |
6073 | pci_fixup_pericom_acs_store_forward); | |
6074 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, | |
6075 | pci_fixup_pericom_acs_store_forward); | |
f21082fb MZ |
6076 | |
6077 | static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) | |
6078 | { | |
6079 | pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; | |
6080 | } | |
6081 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); | |
500b55b0 BH |
6082 | |
6083 | static void rom_bar_overlap_defect(struct pci_dev *dev) | |
6084 | { | |
6085 | pci_info(dev, "working around ROM BAR overlap defect\n"); | |
6086 | dev->rom_bar_overlap = 1; | |
6087 | } | |
6088 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); | |
6089 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); | |
6090 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); | |
6091 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); | |
03038d84 MW |
6092 | |
6093 | #ifdef CONFIG_PCIEASPM | |
6094 | /* | |
6095 | * Several Intel DG2 graphics devices advertise that they can only tolerate | |
6096 | * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 | |
6097 | * from being enabled. But in fact these devices can tolerate unlimited | |
6098 | * latency. Override their Device Capabilities value to allow ASPM L1 to | |
6099 | * be enabled. | |
6100 | */ | |
6101 | static void aspm_l1_acceptable_latency(struct pci_dev *dev) | |
6102 | { | |
6103 | u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); | |
6104 | ||
6105 | if (l1_lat < 7) { | |
6106 | dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); | |
6107 | pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", | |
6108 | l1_lat); | |
6109 | } | |
6110 | } | |
6111 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); | |
6112 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); | |
6113 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); | |
6114 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); | |
6115 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); | |
6116 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); | |
6117 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); | |
6118 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); | |
6119 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); | |
6120 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); | |
6121 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); | |
6122 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); | |
6123 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); | |
6124 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); | |
6125 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); | |
6126 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); | |
6127 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); | |
6128 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); | |
6129 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); | |
6130 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); | |
6131 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); | |
6132 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); | |
6133 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); | |
6134 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); | |
6135 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); | |
6136 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); | |
6137 | #endif | |
5459c0b7 MW |
6138 | |
6139 | #ifdef CONFIG_PCIE_DPC | |
6140 | /* | |
3b880349 MW |
6141 | * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears |
6142 | * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root | |
6143 | * Ports. | |
5459c0b7 MW |
6144 | */ |
6145 | static void dpc_log_size(struct pci_dev *dev) | |
6146 | { | |
6147 | u16 dpc, val; | |
6148 | ||
6149 | dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); | |
6150 | if (!dpc) | |
6151 | return; | |
6152 | ||
6153 | pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); | |
6154 | if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) | |
6155 | return; | |
6156 | ||
6157 | if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) { | |
6158 | pci_info(dev, "Overriding RP PIO Log Size to 4\n"); | |
6159 | dev->dpc_rp_log_size = 4; | |
6160 | } | |
6161 | } | |
6162 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); | |
6163 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); | |
6164 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); | |
6165 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); | |
3b880349 MW |
6166 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); |
6167 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); | |
6168 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); | |
6169 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); | |
5459c0b7 MW |
6170 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); |
6171 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); | |
6172 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); | |
6173 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); | |
6174 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); | |
6175 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); | |
6176 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); | |
6177 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); | |
6178 | #endif | |
ae9813db LH |
6179 | |
6180 | /* | |
6181 | * For a PCI device with multiple downstream devices, its driver may use | |
6182 | * a flattened device tree to describe the downstream devices. | |
6183 | * To overlay the flattened device tree, the PCI device and all its ancestor | |
6184 | * devices need to have device tree nodes on system base device tree. Thus, | |
6185 | * before driver probing, it might need to add a device tree node as the final | |
6186 | * fixup. | |
6187 | */ | |
6188 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); | |
6189 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); | |
26409dd0 | 6190 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); |