Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e BH |
3 | * This file contains work-arounds for many known PCI hardware bugs. |
4 | * Devices present only on certain architectures (host bridges et cetera) | |
5 | * should be handled in arch-specific code. | |
1da177e4 | 6 | * |
df62ab5e | 7 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. |
1da177e4 | 8 | * |
df62ab5e | 9 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> |
1da177e4 | 10 | * |
df62ab5e BH |
11 | * Init/reset quirks for USB host controllers should be in the USB quirks |
12 | * file, where their drivers can use them. | |
1da177e4 LT |
13 | */ |
14 | ||
1da177e4 LT |
15 | #include <linux/types.h> |
16 | #include <linux/kernel.h> | |
363c75db | 17 | #include <linux/export.h> |
1da177e4 LT |
18 | #include <linux/pci.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/delay.h> | |
25be5e6c | 21 | #include <linux/acpi.h> |
75e07fc3 | 22 | #include <linux/dmi.h> |
649426ef | 23 | #include <linux/pci-aspm.h> |
32a9a682 | 24 | #include <linux/ioport.h> |
3209874a AV |
25 | #include <linux/sched.h> |
26 | #include <linux/ktime.h> | |
9fe373f9 | 27 | #include <linux/mm.h> |
ffb08634 | 28 | #include <linux/nvme.h> |
630b3aff | 29 | #include <linux/platform_data/x86/apple.h> |
07f4f97d | 30 | #include <linux/pm_runtime.h> |
ad281ecf | 31 | #include <linux/switchtec.h> |
93177a74 | 32 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 33 | #include "pci.h" |
1da177e4 | 34 | |
78047350 BH |
35 | static ktime_t fixup_debug_start(struct pci_dev *dev, |
36 | void (*fn)(struct pci_dev *dev)) | |
37 | { | |
38 | if (initcall_debug) | |
d75f773c | 39 | pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); |
78047350 BH |
40 | |
41 | return ktime_get(); | |
42 | } | |
43 | ||
44 | static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, | |
45 | void (*fn)(struct pci_dev *dev)) | |
46 | { | |
47 | ktime_t delta, rettime; | |
48 | unsigned long long duration; | |
49 | ||
50 | rettime = ktime_get(); | |
51 | delta = ktime_sub(rettime, calltime); | |
52 | duration = (unsigned long long) ktime_to_ns(delta) >> 10; | |
53 | if (initcall_debug || duration > 10000) | |
d75f773c | 54 | pci_info(dev, "%pS took %lld usecs\n", fn, duration); |
78047350 BH |
55 | } |
56 | ||
57 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, | |
58 | struct pci_fixup *end) | |
59 | { | |
60 | ktime_t calltime; | |
61 | ||
62 | for (; f < end; f++) | |
63 | if ((f->class == (u32) (dev->class >> f->class_shift) || | |
64 | f->class == (u32) PCI_ANY_ID) && | |
65 | (f->vendor == dev->vendor || | |
66 | f->vendor == (u16) PCI_ANY_ID) && | |
67 | (f->device == dev->device || | |
68 | f->device == (u16) PCI_ANY_ID)) { | |
c9d8b55f AB |
69 | void (*hook)(struct pci_dev *dev); |
70 | #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS | |
71 | hook = offset_to_ptr(&f->hook_offset); | |
72 | #else | |
73 | hook = f->hook; | |
74 | #endif | |
75 | calltime = fixup_debug_start(dev, hook); | |
76 | hook(dev); | |
77 | fixup_debug_report(dev, calltime, hook); | |
78047350 BH |
78 | } |
79 | } | |
80 | ||
81 | extern struct pci_fixup __start_pci_fixups_early[]; | |
82 | extern struct pci_fixup __end_pci_fixups_early[]; | |
83 | extern struct pci_fixup __start_pci_fixups_header[]; | |
84 | extern struct pci_fixup __end_pci_fixups_header[]; | |
85 | extern struct pci_fixup __start_pci_fixups_final[]; | |
86 | extern struct pci_fixup __end_pci_fixups_final[]; | |
87 | extern struct pci_fixup __start_pci_fixups_enable[]; | |
88 | extern struct pci_fixup __end_pci_fixups_enable[]; | |
89 | extern struct pci_fixup __start_pci_fixups_resume[]; | |
90 | extern struct pci_fixup __end_pci_fixups_resume[]; | |
91 | extern struct pci_fixup __start_pci_fixups_resume_early[]; | |
92 | extern struct pci_fixup __end_pci_fixups_resume_early[]; | |
93 | extern struct pci_fixup __start_pci_fixups_suspend[]; | |
94 | extern struct pci_fixup __end_pci_fixups_suspend[]; | |
95 | extern struct pci_fixup __start_pci_fixups_suspend_late[]; | |
96 | extern struct pci_fixup __end_pci_fixups_suspend_late[]; | |
97 | ||
98 | static bool pci_apply_fixup_final_quirks; | |
99 | ||
100 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) | |
101 | { | |
102 | struct pci_fixup *start, *end; | |
103 | ||
104 | switch (pass) { | |
105 | case pci_fixup_early: | |
106 | start = __start_pci_fixups_early; | |
107 | end = __end_pci_fixups_early; | |
108 | break; | |
109 | ||
110 | case pci_fixup_header: | |
111 | start = __start_pci_fixups_header; | |
112 | end = __end_pci_fixups_header; | |
113 | break; | |
114 | ||
115 | case pci_fixup_final: | |
116 | if (!pci_apply_fixup_final_quirks) | |
117 | return; | |
118 | start = __start_pci_fixups_final; | |
119 | end = __end_pci_fixups_final; | |
120 | break; | |
121 | ||
122 | case pci_fixup_enable: | |
123 | start = __start_pci_fixups_enable; | |
124 | end = __end_pci_fixups_enable; | |
125 | break; | |
126 | ||
127 | case pci_fixup_resume: | |
128 | start = __start_pci_fixups_resume; | |
129 | end = __end_pci_fixups_resume; | |
130 | break; | |
131 | ||
132 | case pci_fixup_resume_early: | |
133 | start = __start_pci_fixups_resume_early; | |
134 | end = __end_pci_fixups_resume_early; | |
135 | break; | |
136 | ||
137 | case pci_fixup_suspend: | |
138 | start = __start_pci_fixups_suspend; | |
139 | end = __end_pci_fixups_suspend; | |
140 | break; | |
141 | ||
142 | case pci_fixup_suspend_late: | |
143 | start = __start_pci_fixups_suspend_late; | |
144 | end = __end_pci_fixups_suspend_late; | |
145 | break; | |
146 | ||
147 | default: | |
148 | /* stupid compiler warning, you would think with an enum... */ | |
149 | return; | |
150 | } | |
151 | pci_do_fixups(dev, start, end); | |
152 | } | |
153 | EXPORT_SYMBOL(pci_fixup_device); | |
154 | ||
155 | static int __init pci_apply_final_quirks(void) | |
156 | { | |
157 | struct pci_dev *dev = NULL; | |
158 | u8 cls = 0; | |
159 | u8 tmp; | |
160 | ||
161 | if (pci_cache_line_size) | |
34c6b710 | 162 | pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); |
78047350 BH |
163 | |
164 | pci_apply_fixup_final_quirks = true; | |
165 | for_each_pci_dev(dev) { | |
166 | pci_fixup_device(pci_fixup_final, dev); | |
167 | /* | |
168 | * If arch hasn't set it explicitly yet, use the CLS | |
169 | * value shared by all PCI devices. If there's a | |
170 | * mismatch, fall back to the default value. | |
171 | */ | |
172 | if (!pci_cache_line_size) { | |
173 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); | |
174 | if (!cls) | |
175 | cls = tmp; | |
176 | if (!tmp || cls == tmp) | |
177 | continue; | |
178 | ||
34c6b710 MK |
179 | pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", |
180 | cls << 2, tmp << 2, | |
181 | pci_dfl_cache_line_size << 2); | |
78047350 BH |
182 | pci_cache_line_size = pci_dfl_cache_line_size; |
183 | } | |
184 | } | |
185 | ||
186 | if (!pci_cache_line_size) { | |
34c6b710 MK |
187 | pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, |
188 | pci_dfl_cache_line_size << 2); | |
78047350 BH |
189 | pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; |
190 | } | |
191 | ||
192 | return 0; | |
193 | } | |
194 | fs_initcall_sync(pci_apply_final_quirks); | |
195 | ||
253d2e54 JP |
196 | /* |
197 | * Decoding should be disabled for a PCI device during BAR sizing to avoid | |
198 | * conflict. But doing so may cause problems on host bridge and perhaps other | |
199 | * key system devices. For devices that need to have mmio decoding always-on, | |
200 | * we need to set the dev->mmio_always_on bit. | |
201 | */ | |
15856ad5 | 202 | static void quirk_mmio_always_on(struct pci_dev *dev) |
253d2e54 | 203 | { |
52d21b5e | 204 | dev->mmio_always_on = 1; |
253d2e54 | 205 | } |
52d21b5e YL |
206 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, |
207 | PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); | |
253d2e54 | 208 | |
82e1719c BH |
209 | /* |
210 | * The Mellanox Tavor device gives false positive parity errors. Mark this | |
211 | * device with a broken_parity_status to allow PCI scanning code to "skip" | |
212 | * this now blacklisted device. | |
bd8481e1 | 213 | */ |
15856ad5 | 214 | static void quirk_mellanox_tavor(struct pci_dev *dev) |
bd8481e1 DT |
215 | { |
216 | dev->broken_parity_status = 1; /* This device gives false positives */ | |
217 | } | |
3c78bc61 RD |
218 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); |
219 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); | |
bd8481e1 | 220 | |
82e1719c BH |
221 | /* |
222 | * Deal with broken BIOSes that neglect to enable passive release, | |
223 | * which can cause problems in combination with the 82441FX/PPro MTRRs | |
224 | */ | |
1597cacb | 225 | static void quirk_passive_release(struct pci_dev *dev) |
1da177e4 LT |
226 | { |
227 | struct pci_dev *d = NULL; | |
228 | unsigned char dlc; | |
229 | ||
82e1719c BH |
230 | /* |
231 | * We have to make sure a particular bit is set in the PIIX3 | |
232 | * ISA bridge, so we have to go out and find it. | |
233 | */ | |
1da177e4 LT |
234 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { |
235 | pci_read_config_byte(d, 0x82, &dlc); | |
236 | if (!(dlc & 1<<1)) { | |
7506dc79 | 237 | pci_info(d, "PIIX3: Enabling Passive Release\n"); |
1da177e4 LT |
238 | dlc |= 1<<1; |
239 | pci_write_config_byte(d, 0x82, dlc); | |
240 | } | |
241 | } | |
242 | } | |
652c538e AM |
243 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
244 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); | |
1da177e4 | 245 | |
82e1719c BH |
246 | /* |
247 | * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a | |
248 | * workaround but VIA don't answer queries. If you happen to have good | |
249 | * contacts at VIA ask them for me please -- Alan | |
250 | * | |
251 | * This appears to be BIOS not version dependent. So presumably there is a | |
252 | * chipset level fix. | |
253 | */ | |
15856ad5 | 254 | static void quirk_isa_dma_hangs(struct pci_dev *dev) |
1da177e4 LT |
255 | { |
256 | if (!isa_dma_bridge_buggy) { | |
3c78bc61 | 257 | isa_dma_bridge_buggy = 1; |
7506dc79 | 258 | pci_info(dev, "Activating ISA DMA hang workarounds\n"); |
1da177e4 LT |
259 | } |
260 | } | |
82e1719c BH |
261 | /* |
262 | * It's not totally clear which chipsets are the problematic ones. We know | |
263 | * 82C586 and 82C596 variants are affected. | |
264 | */ | |
652c538e AM |
265 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); |
266 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); | |
267 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); | |
f7625980 | 268 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); |
652c538e AM |
269 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); |
270 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); | |
271 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); | |
1da177e4 | 272 | |
4731fdcf LB |
273 | /* |
274 | * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear | |
275 | * for some HT machines to use C4 w/o hanging. | |
276 | */ | |
15856ad5 | 277 | static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) |
4731fdcf LB |
278 | { |
279 | u32 pmbase; | |
280 | u16 pm1a; | |
281 | ||
282 | pci_read_config_dword(dev, 0x40, &pmbase); | |
283 | pmbase = pmbase & 0xff80; | |
284 | pm1a = inw(pmbase); | |
285 | ||
286 | if (pm1a & 0x10) { | |
7506dc79 | 287 | pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); |
4731fdcf LB |
288 | outw(0x10, pmbase); |
289 | } | |
290 | } | |
291 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); | |
292 | ||
82e1719c | 293 | /* Chipsets where PCI->PCI transfers vanish or hang */ |
15856ad5 | 294 | static void quirk_nopcipci(struct pci_dev *dev) |
1da177e4 | 295 | { |
3c78bc61 | 296 | if ((pci_pci_problems & PCIPCI_FAIL) == 0) { |
7506dc79 | 297 | pci_info(dev, "Disabling direct PCI/PCI transfers\n"); |
1da177e4 LT |
298 | pci_pci_problems |= PCIPCI_FAIL; |
299 | } | |
300 | } | |
652c538e AM |
301 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); |
302 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); | |
236561e5 | 303 | |
15856ad5 | 304 | static void quirk_nopciamd(struct pci_dev *dev) |
236561e5 AC |
305 | { |
306 | u8 rev; | |
307 | pci_read_config_byte(dev, 0x08, &rev); | |
308 | if (rev == 0x13) { | |
309 | /* Erratum 24 */ | |
7506dc79 | 310 | pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); |
236561e5 AC |
311 | pci_pci_problems |= PCIAGP_FAIL; |
312 | } | |
313 | } | |
652c538e | 314 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); |
1da177e4 | 315 | |
82e1719c | 316 | /* Triton requires workarounds to be used by the drivers */ |
15856ad5 | 317 | static void quirk_triton(struct pci_dev *dev) |
1da177e4 | 318 | { |
3c78bc61 | 319 | if ((pci_pci_problems&PCIPCI_TRITON) == 0) { |
7506dc79 | 320 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
321 | pci_pci_problems |= PCIPCI_TRITON; |
322 | } | |
323 | } | |
f7625980 BH |
324 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); |
325 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); | |
326 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); | |
327 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); | |
1da177e4 LT |
328 | |
329 | /* | |
82e1719c BH |
330 | * VIA Apollo KT133 needs PCI latency patch |
331 | * Made according to a Windows driver-based patch by George E. Breese; | |
332 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm | |
333 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on | |
334 | * which Mr Breese based his work. | |
1da177e4 | 335 | * |
82e1719c BH |
336 | * Updated based on further information from the site and also on |
337 | * information provided by VIA | |
1da177e4 | 338 | */ |
1597cacb | 339 | static void quirk_vialatency(struct pci_dev *dev) |
1da177e4 LT |
340 | { |
341 | struct pci_dev *p; | |
1da177e4 | 342 | u8 busarb; |
f7625980 | 343 | |
82e1719c BH |
344 | /* |
345 | * Ok, we have a potential problem chipset here. Now see if we have | |
346 | * a buggy southbridge. | |
347 | */ | |
1da177e4 | 348 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); |
3c78bc61 | 349 | if (p != NULL) { |
82e1719c BH |
350 | |
351 | /* | |
352 | * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; | |
353 | * thanks Dan Hollis. | |
354 | * Check for buggy part revisions | |
355 | */ | |
2b1afa87 | 356 | if (p->revision < 0x40 || p->revision > 0x42) |
1da177e4 LT |
357 | goto exit; |
358 | } else { | |
359 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); | |
3c78bc61 | 360 | if (p == NULL) /* No problem parts */ |
1da177e4 | 361 | goto exit; |
82e1719c | 362 | |
1da177e4 | 363 | /* Check for buggy part revisions */ |
2b1afa87 | 364 | if (p->revision < 0x10 || p->revision > 0x12) |
1da177e4 LT |
365 | goto exit; |
366 | } | |
f7625980 | 367 | |
1da177e4 | 368 | /* |
82e1719c BH |
369 | * Ok we have the problem. Now set the PCI master grant to occur |
370 | * every master grant. The apparent bug is that under high PCI load | |
371 | * (quite common in Linux of course) you can get data loss when the | |
372 | * CPU is held off the bus for 3 bus master requests. This happens | |
373 | * to include the IDE controllers.... | |
1da177e4 | 374 | * |
82e1719c BH |
375 | * VIA only apply this fix when an SB Live! is present but under |
376 | * both Linux and Windows this isn't enough, and we have seen | |
377 | * corruption without SB Live! but with things like 3 UDMA IDE | |
378 | * controllers. So we ignore that bit of the VIA recommendation.. | |
1da177e4 | 379 | */ |
1da177e4 | 380 | pci_read_config_byte(dev, 0x76, &busarb); |
82e1719c BH |
381 | |
382 | /* | |
383 | * Set bit 4 and bit 5 of byte 76 to 0x01 | |
384 | * "Master priority rotation on every PCI master grant" | |
385 | */ | |
1da177e4 LT |
386 | busarb &= ~(1<<5); |
387 | busarb |= (1<<4); | |
388 | pci_write_config_byte(dev, 0x76, busarb); | |
7506dc79 | 389 | pci_info(dev, "Applying VIA southbridge workaround\n"); |
1da177e4 LT |
390 | exit: |
391 | pci_dev_put(p); | |
392 | } | |
652c538e AM |
393 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
394 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
395 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1597cacb | 396 | /* Must restore this on a resume from RAM */ |
652c538e AM |
397 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
398 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
399 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1da177e4 | 400 | |
82e1719c | 401 | /* VIA Apollo VP3 needs ETBF on BT848/878 */ |
15856ad5 | 402 | static void quirk_viaetbf(struct pci_dev *dev) |
1da177e4 | 403 | { |
3c78bc61 | 404 | if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { |
7506dc79 | 405 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
406 | pci_pci_problems |= PCIPCI_VIAETBF; |
407 | } | |
408 | } | |
652c538e | 409 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); |
1da177e4 | 410 | |
15856ad5 | 411 | static void quirk_vsfx(struct pci_dev *dev) |
1da177e4 | 412 | { |
3c78bc61 | 413 | if ((pci_pci_problems&PCIPCI_VSFX) == 0) { |
7506dc79 | 414 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
415 | pci_pci_problems |= PCIPCI_VSFX; |
416 | } | |
417 | } | |
652c538e | 418 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); |
1da177e4 LT |
419 | |
420 | /* | |
82e1719c BH |
421 | * ALi Magik requires workarounds to be used by the drivers that DMA to AGP |
422 | * space. Latency must be set to 0xA and Triton workaround applied too. | |
423 | * [Info kindly provided by ALi] | |
f7625980 | 424 | */ |
15856ad5 | 425 | static void quirk_alimagik(struct pci_dev *dev) |
1da177e4 | 426 | { |
3c78bc61 | 427 | if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { |
7506dc79 | 428 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
429 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
430 | } | |
431 | } | |
f7625980 BH |
432 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); |
433 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); | |
1da177e4 | 434 | |
82e1719c | 435 | /* Natoma has some interesting boundary conditions with Zoran stuff at least */ |
15856ad5 | 436 | static void quirk_natoma(struct pci_dev *dev) |
1da177e4 | 437 | { |
3c78bc61 | 438 | if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { |
7506dc79 | 439 | pci_info(dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
440 | pci_pci_problems |= PCIPCI_NATOMA; |
441 | } | |
442 | } | |
f7625980 BH |
443 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); |
444 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); | |
445 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); | |
446 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); | |
447 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); | |
448 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); | |
1da177e4 LT |
449 | |
450 | /* | |
82e1719c BH |
451 | * This chip can cause PCI parity errors if config register 0xA0 is read |
452 | * while DMAs are occurring. | |
1da177e4 | 453 | */ |
15856ad5 | 454 | static void quirk_citrine(struct pci_dev *dev) |
1da177e4 LT |
455 | { |
456 | dev->cfg_size = 0xA0; | |
457 | } | |
652c538e | 458 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); |
1da177e4 | 459 | |
9f33a2ae JM |
460 | /* |
461 | * This chip can cause bus lockups if config addresses above 0x600 | |
462 | * are read or written. | |
463 | */ | |
464 | static void quirk_nfp6000(struct pci_dev *dev) | |
465 | { | |
466 | dev->cfg_size = 0x600; | |
467 | } | |
c2e771b0 | 468 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); |
9f33a2ae | 469 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); |
2538fb89 | 470 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); |
9f33a2ae JM |
471 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); |
472 | ||
9fe373f9 DL |
473 | /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ |
474 | static void quirk_extend_bar_to_page(struct pci_dev *dev) | |
475 | { | |
476 | int i; | |
477 | ||
2f686f1d | 478 | for (i = 0; i <= PCI_STD_RESOURCE_END; i++) { |
9fe373f9 DL |
479 | struct resource *r = &dev->resource[i]; |
480 | ||
481 | if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { | |
482 | r->end = PAGE_SIZE - 1; | |
483 | r->start = 0; | |
484 | r->flags |= IORESOURCE_UNSET; | |
7506dc79 | 485 | pci_info(dev, "expanded BAR %d to page size: %pR\n", |
9fe373f9 DL |
486 | i, r); |
487 | } | |
488 | } | |
489 | } | |
490 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); | |
491 | ||
1da177e4 | 492 | /* |
82e1719c BH |
493 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. |
494 | * If it's needed, re-allocate the region. | |
1da177e4 | 495 | */ |
15856ad5 | 496 | static void quirk_s3_64M(struct pci_dev *dev) |
1da177e4 LT |
497 | { |
498 | struct resource *r = &dev->resource[0]; | |
499 | ||
500 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { | |
bd064f0a | 501 | r->flags |= IORESOURCE_UNSET; |
1da177e4 LT |
502 | r->start = 0; |
503 | r->end = 0x3ffffff; | |
504 | } | |
505 | } | |
652c538e AM |
506 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); |
507 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); | |
1da177e4 | 508 | |
06cf35f9 MS |
509 | static void quirk_io(struct pci_dev *dev, int pos, unsigned size, |
510 | const char *name) | |
511 | { | |
512 | u32 region; | |
513 | struct pci_bus_region bus_region; | |
514 | struct resource *res = dev->resource + pos; | |
515 | ||
516 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); | |
517 | ||
518 | if (!region) | |
519 | return; | |
520 | ||
521 | res->name = pci_name(dev); | |
522 | res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; | |
523 | res->flags |= | |
524 | (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); | |
525 | region &= ~(size - 1); | |
526 | ||
527 | /* Convert from PCI bus to resource space */ | |
528 | bus_region.start = region; | |
529 | bus_region.end = region + size - 1; | |
530 | pcibios_bus_to_resource(dev->bus, res, &bus_region); | |
531 | ||
7506dc79 | 532 | pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", |
06cf35f9 MS |
533 | name, PCI_BASE_ADDRESS_0 + (pos << 2), res); |
534 | } | |
535 | ||
73d2eaac AS |
536 | /* |
537 | * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS | |
538 | * ver. 1.33 20070103) don't set the correct ISA PCI region header info. | |
539 | * BAR0 should be 8 bytes; instead, it may be set to something like 8k | |
540 | * (which conflicts w/ BAR1's memory range). | |
06cf35f9 MS |
541 | * |
542 | * CS553x's ISA PCI BARs may also be read-only (ref: | |
543 | * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). | |
73d2eaac | 544 | */ |
15856ad5 | 545 | static void quirk_cs5536_vsa(struct pci_dev *dev) |
73d2eaac | 546 | { |
06cf35f9 MS |
547 | static char *name = "CS5536 ISA bridge"; |
548 | ||
73d2eaac | 549 | if (pci_resource_len(dev, 0) != 8) { |
06cf35f9 MS |
550 | quirk_io(dev, 0, 8, name); /* SMB */ |
551 | quirk_io(dev, 1, 256, name); /* GPIO */ | |
552 | quirk_io(dev, 2, 64, name); /* MFGPT */ | |
7506dc79 | 553 | pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", |
06cf35f9 | 554 | name); |
73d2eaac AS |
555 | } |
556 | } | |
557 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); | |
558 | ||
65195c76 YL |
559 | static void quirk_io_region(struct pci_dev *dev, int port, |
560 | unsigned size, int nr, const char *name) | |
561 | { | |
562 | u16 region; | |
563 | struct pci_bus_region bus_region; | |
564 | struct resource *res = dev->resource + nr; | |
565 | ||
566 | pci_read_config_word(dev, port, ®ion); | |
567 | region &= ~(size - 1); | |
568 | ||
569 | if (!region) | |
570 | return; | |
571 | ||
572 | res->name = pci_name(dev); | |
573 | res->flags = IORESOURCE_IO; | |
574 | ||
575 | /* Convert from PCI bus to resource space */ | |
576 | bus_region.start = region; | |
577 | bus_region.end = region + size - 1; | |
fc279850 | 578 | pcibios_bus_to_resource(dev->bus, res, &bus_region); |
65195c76 YL |
579 | |
580 | if (!pci_claim_resource(dev, nr)) | |
7506dc79 | 581 | pci_info(dev, "quirk: %pR claimed by %s\n", res, name); |
65195c76 | 582 | } |
1da177e4 LT |
583 | |
584 | /* | |
82e1719c BH |
585 | * ATI Northbridge setups MCE the processor if you even read somewhere |
586 | * between 0x3b0->0x3bb or read 0x3d3 | |
1da177e4 | 587 | */ |
15856ad5 | 588 | static void quirk_ati_exploding_mce(struct pci_dev *dev) |
1da177e4 | 589 | { |
7506dc79 | 590 | pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); |
1da177e4 LT |
591 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
592 | request_region(0x3b0, 0x0C, "RadeonIGP"); | |
593 | request_region(0x3d3, 0x01, "RadeonIGP"); | |
594 | } | |
652c538e | 595 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); |
1da177e4 | 596 | |
be6646bf HR |
597 | /* |
598 | * In the AMD NL platform, this device ([1022:7912]) has a class code of | |
599 | * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will | |
600 | * claim it. | |
82e1719c | 601 | * |
be6646bf HR |
602 | * But the dwc3 driver is a more specific driver for this device, and we'd |
603 | * prefer to use it instead of xhci. To prevent xhci from claiming the | |
604 | * device, change the class code to 0x0c03fe, which the PCI r3.0 spec | |
605 | * defines as "USB device (not host controller)". The dwc3 driver can then | |
606 | * claim it based on its Vendor and Device ID. | |
607 | */ | |
608 | static void quirk_amd_nl_class(struct pci_dev *pdev) | |
609 | { | |
cd76d10b BH |
610 | u32 class = pdev->class; |
611 | ||
612 | /* Use "USB Device (not host controller)" class */ | |
7b78f48a | 613 | pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; |
7506dc79 | 614 | pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", |
cd76d10b | 615 | class, pdev->class); |
be6646bf HR |
616 | } |
617 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, | |
618 | quirk_amd_nl_class); | |
619 | ||
03e67425 TN |
620 | /* |
621 | * Synopsys USB 3.x host HAPS platform has a class code of | |
622 | * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these | |
623 | * devices should use dwc3-haps driver. Change these devices' class code to | |
624 | * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming | |
625 | * them. | |
626 | */ | |
627 | static void quirk_synopsys_haps(struct pci_dev *pdev) | |
628 | { | |
629 | u32 class = pdev->class; | |
630 | ||
631 | switch (pdev->device) { | |
632 | case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: | |
633 | case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: | |
634 | case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: | |
635 | pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; | |
636 | pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", | |
637 | class, pdev->class); | |
638 | break; | |
639 | } | |
640 | } | |
f57a98e1 TN |
641 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, |
642 | PCI_CLASS_SERIAL_USB_XHCI, 0, | |
643 | quirk_synopsys_haps); | |
03e67425 | 644 | |
1da177e4 | 645 | /* |
82e1719c BH |
646 | * Let's make the southbridge information explicit instead of having to |
647 | * worry about people probing the ACPI areas, for example.. (Yes, it | |
648 | * happens, and if you read the wrong ACPI register it will put the machine | |
649 | * to sleep with no way of waking it up again. Bummer). | |
1da177e4 LT |
650 | * |
651 | * ALI M7101: Two IO regions pointed to by words at | |
652 | * 0xE0 (64 bytes of ACPI registers) | |
653 | * 0xE2 (32 bytes of SMB registers) | |
654 | */ | |
15856ad5 | 655 | static void quirk_ali7101_acpi(struct pci_dev *dev) |
1da177e4 | 656 | { |
65195c76 YL |
657 | quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
658 | quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); | |
1da177e4 | 659 | } |
652c538e | 660 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); |
1da177e4 | 661 | |
6693e74a LT |
662 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
663 | { | |
664 | u32 devres; | |
665 | u32 mask, size, base; | |
666 | ||
667 | pci_read_config_dword(dev, port, &devres); | |
668 | if ((devres & enable) != enable) | |
669 | return; | |
670 | mask = (devres >> 16) & 15; | |
671 | base = devres & 0xffff; | |
672 | size = 16; | |
673 | for (;;) { | |
674 | unsigned bit = size >> 1; | |
675 | if ((bit & mask) == bit) | |
676 | break; | |
677 | size = bit; | |
678 | } | |
679 | /* | |
680 | * For now we only print it out. Eventually we'll want to | |
681 | * reserve it (at least if it's in the 0x1000+ range), but | |
f7625980 | 682 | * let's get enough confirmation reports first. |
6693e74a LT |
683 | */ |
684 | base &= -size; | |
7506dc79 | 685 | pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); |
6693e74a LT |
686 | } |
687 | ||
688 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) | |
689 | { | |
690 | u32 devres; | |
691 | u32 mask, size, base; | |
692 | ||
693 | pci_read_config_dword(dev, port, &devres); | |
694 | if ((devres & enable) != enable) | |
695 | return; | |
696 | base = devres & 0xffff0000; | |
697 | mask = (devres & 0x3f) << 16; | |
698 | size = 128 << 16; | |
699 | for (;;) { | |
700 | unsigned bit = size >> 1; | |
701 | if ((bit & mask) == bit) | |
702 | break; | |
703 | size = bit; | |
704 | } | |
82e1719c | 705 | |
6693e74a LT |
706 | /* |
707 | * For now we only print it out. Eventually we'll want to | |
f7625980 | 708 | * reserve it, but let's get enough confirmation reports first. |
6693e74a LT |
709 | */ |
710 | base &= -size; | |
7506dc79 | 711 | pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); |
6693e74a LT |
712 | } |
713 | ||
1da177e4 LT |
714 | /* |
715 | * PIIX4 ACPI: Two IO regions pointed to by longwords at | |
716 | * 0x40 (64 bytes of ACPI registers) | |
08db2a70 | 717 | * 0x90 (16 bytes of SMB registers) |
6693e74a | 718 | * and a few strange programmable PIIX4 device resources. |
1da177e4 | 719 | */ |
15856ad5 | 720 | static void quirk_piix4_acpi(struct pci_dev *dev) |
1da177e4 | 721 | { |
65195c76 | 722 | u32 res_a; |
1da177e4 | 723 | |
65195c76 YL |
724 | quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
725 | quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); | |
6693e74a LT |
726 | |
727 | /* Device resource A has enables for some of the other ones */ | |
728 | pci_read_config_dword(dev, 0x5c, &res_a); | |
729 | ||
730 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); | |
731 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); | |
732 | ||
733 | /* Device resource D is just bitfields for static resources */ | |
734 | ||
735 | /* Device 12 enabled? */ | |
736 | if (res_a & (1 << 29)) { | |
737 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); | |
738 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); | |
739 | } | |
740 | /* Device 13 enabled? */ | |
741 | if (res_a & (1 << 30)) { | |
742 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); | |
743 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); | |
744 | } | |
745 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); | |
746 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); | |
1da177e4 | 747 | } |
652c538e AM |
748 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); |
749 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); | |
1da177e4 | 750 | |
cdb97558 JS |
751 | #define ICH_PMBASE 0x40 |
752 | #define ICH_ACPI_CNTL 0x44 | |
753 | #define ICH4_ACPI_EN 0x10 | |
754 | #define ICH6_ACPI_EN 0x80 | |
755 | #define ICH4_GPIOBASE 0x58 | |
756 | #define ICH4_GPIO_CNTL 0x5c | |
757 | #define ICH4_GPIO_EN 0x10 | |
758 | #define ICH6_GPIOBASE 0x48 | |
759 | #define ICH6_GPIO_CNTL 0x4c | |
760 | #define ICH6_GPIO_EN 0x10 | |
761 | ||
1da177e4 LT |
762 | /* |
763 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at | |
764 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) | |
765 | * 0x58 (64 bytes of GPIO I/O space) | |
766 | */ | |
15856ad5 | 767 | static void quirk_ich4_lpc_acpi(struct pci_dev *dev) |
1da177e4 | 768 | { |
cdb97558 | 769 | u8 enable; |
1da177e4 | 770 | |
87e3dc38 JS |
771 | /* |
772 | * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict | |
773 | * with low legacy (and fixed) ports. We don't know the decoding | |
774 | * priority and can't tell whether the legacy device or the one created | |
775 | * here is really at that address. This happens on boards with broken | |
776 | * BIOSes. | |
82e1719c | 777 | */ |
cdb97558 | 778 | pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); |
65195c76 YL |
779 | if (enable & ICH4_ACPI_EN) |
780 | quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, | |
781 | "ICH4 ACPI/GPIO/TCO"); | |
1da177e4 | 782 | |
cdb97558 | 783 | pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); |
65195c76 YL |
784 | if (enable & ICH4_GPIO_EN) |
785 | quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, | |
786 | "ICH4 GPIO"); | |
1da177e4 | 787 | } |
652c538e AM |
788 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); |
789 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); | |
790 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); | |
791 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); | |
792 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); | |
793 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); | |
794 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); | |
795 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); | |
796 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); | |
797 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); | |
1da177e4 | 798 | |
15856ad5 | 799 | static void ich6_lpc_acpi_gpio(struct pci_dev *dev) |
2cea752f | 800 | { |
cdb97558 | 801 | u8 enable; |
2cea752f | 802 | |
cdb97558 | 803 | pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); |
65195c76 YL |
804 | if (enable & ICH6_ACPI_EN) |
805 | quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, | |
806 | "ICH6 ACPI/GPIO/TCO"); | |
2cea752f | 807 | |
cdb97558 | 808 | pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); |
65195c76 YL |
809 | if (enable & ICH6_GPIO_EN) |
810 | quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, | |
811 | "ICH6 GPIO"); | |
2cea752f | 812 | } |
894886e5 | 813 | |
82e1719c BH |
814 | static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, |
815 | const char *name, int dynsize) | |
894886e5 LT |
816 | { |
817 | u32 val; | |
818 | u32 size, base; | |
819 | ||
820 | pci_read_config_dword(dev, reg, &val); | |
821 | ||
822 | /* Enabled? */ | |
823 | if (!(val & 1)) | |
824 | return; | |
825 | base = val & 0xfffc; | |
826 | if (dynsize) { | |
827 | /* | |
828 | * This is not correct. It is 16, 32 or 64 bytes depending on | |
829 | * register D31:F0:ADh bits 5:4. | |
830 | * | |
831 | * But this gets us at least _part_ of it. | |
832 | */ | |
833 | size = 16; | |
834 | } else { | |
835 | size = 128; | |
836 | } | |
837 | base &= ~(size-1); | |
838 | ||
82e1719c BH |
839 | /* |
840 | * Just print it out for now. We should reserve it after more | |
841 | * debugging. | |
842 | */ | |
7506dc79 | 843 | pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); |
894886e5 LT |
844 | } |
845 | ||
15856ad5 | 846 | static void quirk_ich6_lpc(struct pci_dev *dev) |
894886e5 LT |
847 | { |
848 | /* Shared ACPI/GPIO decode with all ICH6+ */ | |
849 | ich6_lpc_acpi_gpio(dev); | |
850 | ||
851 | /* ICH6-specific generic IO decode */ | |
852 | ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); | |
853 | ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); | |
854 | } | |
855 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); | |
856 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); | |
857 | ||
82e1719c BH |
858 | static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, |
859 | const char *name) | |
894886e5 LT |
860 | { |
861 | u32 val; | |
862 | u32 mask, base; | |
863 | ||
864 | pci_read_config_dword(dev, reg, &val); | |
865 | ||
866 | /* Enabled? */ | |
867 | if (!(val & 1)) | |
868 | return; | |
869 | ||
82e1719c | 870 | /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ |
894886e5 LT |
871 | base = val & 0xfffc; |
872 | mask = (val >> 16) & 0xfc; | |
873 | mask |= 3; | |
874 | ||
82e1719c BH |
875 | /* |
876 | * Just print it out for now. We should reserve it after more | |
877 | * debugging. | |
878 | */ | |
7506dc79 | 879 | pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); |
894886e5 LT |
880 | } |
881 | ||
882 | /* ICH7-10 has the same common LPC generic IO decode registers */ | |
15856ad5 | 883 | static void quirk_ich7_lpc(struct pci_dev *dev) |
894886e5 | 884 | { |
5d9c0a79 | 885 | /* We share the common ACPI/GPIO decode with ICH6 */ |
894886e5 LT |
886 | ich6_lpc_acpi_gpio(dev); |
887 | ||
888 | /* And have 4 ICH7+ generic decodes */ | |
889 | ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); | |
890 | ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); | |
891 | ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); | |
892 | ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); | |
893 | } | |
894 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); | |
895 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); | |
896 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); | |
897 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); | |
898 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); | |
899 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); | |
900 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); | |
901 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); | |
902 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); | |
903 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); | |
904 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); | |
905 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); | |
906 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); | |
2cea752f | 907 | |
1da177e4 LT |
908 | /* |
909 | * VIA ACPI: One IO region pointed to by longword at | |
910 | * 0x48 or 0x20 (256 bytes of ACPI registers) | |
911 | */ | |
15856ad5 | 912 | static void quirk_vt82c586_acpi(struct pci_dev *dev) |
1da177e4 | 913 | { |
65195c76 YL |
914 | if (dev->revision & 0x10) |
915 | quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, | |
916 | "vt82c586 ACPI"); | |
1da177e4 | 917 | } |
652c538e | 918 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); |
1da177e4 LT |
919 | |
920 | /* | |
921 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at | |
922 | * 0x48 (256 bytes of ACPI registers) | |
923 | * 0x70 (128 bytes of hardware monitoring register) | |
924 | * 0x90 (16 bytes of SMB registers) | |
925 | */ | |
15856ad5 | 926 | static void quirk_vt82c686_acpi(struct pci_dev *dev) |
1da177e4 | 927 | { |
1da177e4 LT |
928 | quirk_vt82c586_acpi(dev); |
929 | ||
65195c76 YL |
930 | quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, |
931 | "vt82c686 HW-mon"); | |
1da177e4 | 932 | |
65195c76 | 933 | quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); |
1da177e4 | 934 | } |
652c538e | 935 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); |
1da177e4 | 936 | |
6d85f29b IK |
937 | /* |
938 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at | |
939 | * 0x88 (128 bytes of power management registers) | |
940 | * 0xd0 (16 bytes of SMB registers) | |
941 | */ | |
15856ad5 | 942 | static void quirk_vt8235_acpi(struct pci_dev *dev) |
6d85f29b | 943 | { |
65195c76 YL |
944 | quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
945 | quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); | |
6d85f29b IK |
946 | } |
947 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); | |
948 | ||
1f56f4a2 | 949 | /* |
82e1719c BH |
950 | * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast |
951 | * back-to-back: Disable fast back-to-back on the secondary bus segment | |
1f56f4a2 | 952 | */ |
15856ad5 | 953 | static void quirk_xio2000a(struct pci_dev *dev) |
1f56f4a2 GB |
954 | { |
955 | struct pci_dev *pdev; | |
956 | u16 command; | |
957 | ||
7506dc79 | 958 | pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); |
1f56f4a2 GB |
959 | list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { |
960 | pci_read_config_word(pdev, PCI_COMMAND, &command); | |
961 | if (command & PCI_COMMAND_FAST_BACK) | |
962 | pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); | |
963 | } | |
964 | } | |
965 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, | |
966 | quirk_xio2000a); | |
1da177e4 | 967 | |
f7625980 | 968 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
969 | |
970 | #include <asm/io_apic.h> | |
971 | ||
972 | /* | |
973 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip | |
974 | * devices to the external APIC. | |
975 | * | |
82e1719c BH |
976 | * TODO: When we have device-specific interrupt routers, this code will go |
977 | * away from quirks. | |
1da177e4 | 978 | */ |
1597cacb | 979 | static void quirk_via_ioapic(struct pci_dev *dev) |
1da177e4 LT |
980 | { |
981 | u8 tmp; | |
f7625980 | 982 | |
1da177e4 LT |
983 | if (nr_ioapics < 1) |
984 | tmp = 0; /* nothing routed to external APIC */ | |
985 | else | |
986 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ | |
f7625980 | 987 | |
7506dc79 | 988 | pci_info(dev, "%sbling VIA external APIC routing\n", |
1da177e4 LT |
989 | tmp == 0 ? "Disa" : "Ena"); |
990 | ||
991 | /* Offset 0x58: External APIC IRQ output control */ | |
3c78bc61 | 992 | pci_write_config_byte(dev, 0x58, tmp); |
1da177e4 | 993 | } |
652c538e | 994 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
e1a2a51e | 995 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
1da177e4 | 996 | |
a1740913 | 997 | /* |
f7625980 | 998 | * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. |
a1740913 KW |
999 | * This leads to doubled level interrupt rates. |
1000 | * Set this bit to get rid of cycle wastage. | |
1001 | * Otherwise uncritical. | |
1002 | */ | |
1597cacb | 1003 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
a1740913 KW |
1004 | { |
1005 | u8 misc_control2; | |
1006 | #define BYPASS_APIC_DEASSERT 8 | |
1007 | ||
1008 | pci_read_config_byte(dev, 0x5B, &misc_control2); | |
1009 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { | |
7506dc79 | 1010 | pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); |
a1740913 KW |
1011 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); |
1012 | } | |
1013 | } | |
1014 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); | |
e1a2a51e | 1015 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
a1740913 | 1016 | |
1da177e4 | 1017 | /* |
82e1719c | 1018 | * The AMD IO-APIC can hang the box when an APIC IRQ is masked. |
1da177e4 LT |
1019 | * We check all revs >= B0 (yet not in the pre production!) as the bug |
1020 | * is currently marked NoFix | |
1021 | * | |
1022 | * We have multiple reports of hangs with this chipset that went away with | |
236561e5 | 1023 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
82e1719c | 1024 | * of course. However the advice is demonstrably good even if so. |
1da177e4 | 1025 | */ |
15856ad5 | 1026 | static void quirk_amd_ioapic(struct pci_dev *dev) |
1da177e4 | 1027 | { |
44c10138 | 1028 | if (dev->revision >= 0x02) { |
7506dc79 FL |
1029 | pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
1030 | pci_warn(dev, " : booting with the \"noapic\" option\n"); | |
1da177e4 LT |
1031 | } |
1032 | } | |
652c538e | 1033 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); |
1da177e4 LT |
1034 | #endif /* CONFIG_X86_IO_APIC */ |
1035 | ||
0bec9057 | 1036 | #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) |
21b5b8ee AJ |
1037 | |
1038 | static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) | |
1039 | { | |
82e1719c | 1040 | /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ |
21b5b8ee AJ |
1041 | if (dev->subsystem_device == 0xa118) |
1042 | dev->sriov->link = dev->devfn; | |
1043 | } | |
1044 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); | |
1045 | #endif | |
1046 | ||
d556ad4b PO |
1047 | /* |
1048 | * Some settings of MMRBC can lead to data corruption so block changes. | |
1049 | * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide | |
1050 | */ | |
15856ad5 | 1051 | static void quirk_amd_8131_mmrbc(struct pci_dev *dev) |
d556ad4b | 1052 | { |
aa288d4d | 1053 | if (dev->subordinate && dev->revision <= 0x12) { |
7506dc79 | 1054 | pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", |
227f0647 | 1055 | dev->revision); |
d556ad4b PO |
1056 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; |
1057 | } | |
1058 | } | |
1059 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); | |
1da177e4 | 1060 | |
1da177e4 | 1061 | /* |
82e1719c BH |
1062 | * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up |
1063 | * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register | |
1064 | * at all. Therefore it seems like setting the pci_dev's IRQ to the value | |
1065 | * of the ACPI SCI interrupt is only done for convenience. | |
1da177e4 LT |
1066 | * -jgarzik |
1067 | */ | |
15856ad5 | 1068 | static void quirk_via_acpi(struct pci_dev *d) |
1da177e4 | 1069 | { |
1da177e4 | 1070 | u8 irq; |
82e1719c BH |
1071 | |
1072 | /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ | |
1da177e4 LT |
1073 | pci_read_config_byte(d, 0x42, &irq); |
1074 | irq &= 0xf; | |
1075 | if (irq && (irq != 2)) | |
1076 | d->irq = irq; | |
1077 | } | |
652c538e AM |
1078 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); |
1079 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); | |
1da177e4 | 1080 | |
82e1719c | 1081 | /* VIA bridges which have VLink */ |
c06bb5d4 JD |
1082 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
1083 | ||
1084 | static void quirk_via_bridge(struct pci_dev *dev) | |
1085 | { | |
1086 | /* See what bridge we have and find the device ranges */ | |
1087 | switch (dev->device) { | |
1088 | case PCI_DEVICE_ID_VIA_82C686: | |
82e1719c BH |
1089 | /* |
1090 | * The VT82C686 is special; it attaches to PCI and can have | |
1091 | * any device number. All its subdevices are functions of | |
1092 | * that single device. | |
1093 | */ | |
cb7468ef JD |
1094 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); |
1095 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); | |
c06bb5d4 JD |
1096 | break; |
1097 | case PCI_DEVICE_ID_VIA_8237: | |
1098 | case PCI_DEVICE_ID_VIA_8237A: | |
1099 | via_vlink_dev_lo = 15; | |
1100 | break; | |
1101 | case PCI_DEVICE_ID_VIA_8235: | |
1102 | via_vlink_dev_lo = 16; | |
1103 | break; | |
1104 | case PCI_DEVICE_ID_VIA_8231: | |
1105 | case PCI_DEVICE_ID_VIA_8233_0: | |
1106 | case PCI_DEVICE_ID_VIA_8233A: | |
1107 | case PCI_DEVICE_ID_VIA_8233C_0: | |
1108 | via_vlink_dev_lo = 17; | |
1109 | break; | |
1110 | } | |
1111 | } | |
1112 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); | |
1113 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); | |
1114 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); | |
1115 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); | |
1116 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); | |
1117 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); | |
1118 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); | |
1119 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); | |
09d6029f | 1120 | |
82e1719c BH |
1121 | /* |
1122 | * quirk_via_vlink - VIA VLink IRQ number update | |
1123 | * @dev: PCI device | |
1597cacb | 1124 | * |
82e1719c BH |
1125 | * If the device we are dealing with is on a PIC IRQ we need to ensure that |
1126 | * the IRQ line register which usually is not relevant for PCI cards, is | |
1127 | * actually written so that interrupts get sent to the right place. | |
1128 | * | |
1129 | * We only do this on systems where a VIA south bridge was detected, and | |
1130 | * only for VIA devices on the motherboard (see quirk_via_bridge above). | |
1597cacb | 1131 | */ |
1597cacb | 1132 | static void quirk_via_vlink(struct pci_dev *dev) |
25be5e6c LB |
1133 | { |
1134 | u8 irq, new_irq; | |
1135 | ||
c06bb5d4 JD |
1136 | /* Check if we have VLink at all */ |
1137 | if (via_vlink_dev_lo == -1) | |
09d6029f DD |
1138 | return; |
1139 | ||
1140 | new_irq = dev->irq; | |
1141 | ||
1142 | /* Don't quirk interrupts outside the legacy IRQ range */ | |
1143 | if (!new_irq || new_irq > 15) | |
1144 | return; | |
1145 | ||
1597cacb | 1146 | /* Internal device ? */ |
c06bb5d4 JD |
1147 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
1148 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) | |
1597cacb AC |
1149 | return; |
1150 | ||
82e1719c BH |
1151 | /* |
1152 | * This is an internal VLink device on a PIC interrupt. The BIOS | |
1153 | * ought to have set this but may not have, so we redo it. | |
1154 | */ | |
25be5e6c LB |
1155 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
1156 | if (new_irq != irq) { | |
7506dc79 | 1157 | pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", |
f0fda801 | 1158 | irq, new_irq); |
25be5e6c LB |
1159 | udelay(15); /* unknown if delay really needed */ |
1160 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); | |
1161 | } | |
1162 | } | |
1597cacb | 1163 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
25be5e6c | 1164 | |
1da177e4 | 1165 | /* |
82e1719c BH |
1166 | * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID |
1167 | * of VT82C597 for backward compatibility. We need to switch it off to be | |
1168 | * able to recognize the real type of the chip. | |
1da177e4 | 1169 | */ |
15856ad5 | 1170 | static void quirk_vt82c598_id(struct pci_dev *dev) |
1da177e4 LT |
1171 | { |
1172 | pci_write_config_byte(dev, 0xfc, 0); | |
1173 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); | |
1174 | } | |
652c538e | 1175 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); |
1da177e4 LT |
1176 | |
1177 | /* | |
82e1719c BH |
1178 | * CardBus controllers have a legacy base address that enables them to |
1179 | * respond as i82365 pcmcia controllers. We don't want them to do this | |
1180 | * even if the Linux CardBus driver is not loaded, because the Linux i82365 | |
1181 | * driver does not (and should not) handle CardBus. | |
1da177e4 | 1182 | */ |
1597cacb | 1183 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
1da177e4 | 1184 | { |
1da177e4 LT |
1185 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); |
1186 | } | |
ae9de56b YL |
1187 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, |
1188 | PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); | |
1189 | DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, | |
1190 | PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); | |
1da177e4 LT |
1191 | |
1192 | /* | |
82e1719c BH |
1193 | * Following the PCI ordering rules is optional on the AMD762. I'm not sure |
1194 | * what the designers were smoking but let's not inhale... | |
1da177e4 | 1195 | * |
82e1719c BH |
1196 | * To be fair to AMD, it follows the spec by default, it's BIOS people who |
1197 | * turn it off! | |
1da177e4 | 1198 | */ |
1597cacb | 1199 | static void quirk_amd_ordering(struct pci_dev *dev) |
1da177e4 LT |
1200 | { |
1201 | u32 pcic; | |
1202 | pci_read_config_dword(dev, 0x4C, &pcic); | |
3c78bc61 | 1203 | if ((pcic & 6) != 6) { |
1da177e4 | 1204 | pcic |= 6; |
7506dc79 | 1205 | pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); |
1da177e4 LT |
1206 | pci_write_config_dword(dev, 0x4C, pcic); |
1207 | pci_read_config_dword(dev, 0x84, &pcic); | |
3c78bc61 | 1208 | pcic |= (1 << 23); /* Required in this mode */ |
1da177e4 LT |
1209 | pci_write_config_dword(dev, 0x84, pcic); |
1210 | } | |
1211 | } | |
652c538e | 1212 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
e1a2a51e | 1213 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
1da177e4 LT |
1214 | |
1215 | /* | |
82e1719c | 1216 | * DreamWorks-provided workaround for Dunord I-3000 problem |
1da177e4 | 1217 | * |
82e1719c BH |
1218 | * This card decodes and responds to addresses not apparently assigned to |
1219 | * it. We force a larger allocation to ensure that nothing gets put too | |
1220 | * close to it. | |
1da177e4 | 1221 | */ |
15856ad5 | 1222 | static void quirk_dunord(struct pci_dev *dev) |
1da177e4 | 1223 | { |
3c78bc61 | 1224 | struct resource *r = &dev->resource[1]; |
bd064f0a BH |
1225 | |
1226 | r->flags |= IORESOURCE_UNSET; | |
1da177e4 LT |
1227 | r->start = 0; |
1228 | r->end = 0xffffff; | |
1229 | } | |
652c538e | 1230 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); |
1da177e4 LT |
1231 | |
1232 | /* | |
82e1719c BH |
1233 | * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive |
1234 | * decoding (transparent), and does indicate this in the ProgIf. | |
1235 | * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. | |
1da177e4 | 1236 | */ |
15856ad5 | 1237 | static void quirk_transparent_bridge(struct pci_dev *dev) |
1da177e4 LT |
1238 | { |
1239 | dev->transparent = 1; | |
1240 | } | |
652c538e AM |
1241 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); |
1242 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); | |
1da177e4 LT |
1243 | |
1244 | /* | |
82e1719c BH |
1245 | * Common misconfiguration of the MediaGX/Geode PCI master that will reduce |
1246 | * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets | |
1247 | * found at http://www.national.com/analog for info on what these bits do. | |
1248 | * <christer@weinigel.se> | |
1da177e4 | 1249 | */ |
1597cacb | 1250 | static void quirk_mediagx_master(struct pci_dev *dev) |
1da177e4 LT |
1251 | { |
1252 | u8 reg; | |
3c78bc61 | 1253 | |
1da177e4 LT |
1254 | pci_read_config_byte(dev, 0x41, ®); |
1255 | if (reg & 2) { | |
1256 | reg &= ~2; | |
7506dc79 | 1257 | pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", |
227f0647 | 1258 | reg); |
3c78bc61 | 1259 | pci_write_config_byte(dev, 0x41, reg); |
1da177e4 LT |
1260 | } |
1261 | } | |
652c538e AM |
1262 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
1263 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); | |
1da177e4 | 1264 | |
1da177e4 | 1265 | /* |
82e1719c BH |
1266 | * Ensure C0 rev restreaming is off. This is normally done by the BIOS but |
1267 | * in the odd case it is not the results are corruption hence the presence | |
1268 | * of a Linux check. | |
1da177e4 | 1269 | */ |
1597cacb | 1270 | static void quirk_disable_pxb(struct pci_dev *pdev) |
1da177e4 LT |
1271 | { |
1272 | u16 config; | |
f7625980 | 1273 | |
44c10138 | 1274 | if (pdev->revision != 0x04) /* Only C0 requires this */ |
1da177e4 LT |
1275 | return; |
1276 | pci_read_config_word(pdev, 0x40, &config); | |
1277 | if (config & (1<<6)) { | |
1278 | config &= ~(1<<6); | |
1279 | pci_write_config_word(pdev, 0x40, config); | |
7506dc79 | 1280 | pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); |
1da177e4 LT |
1281 | } |
1282 | } | |
652c538e | 1283 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
e1a2a51e | 1284 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
1da177e4 | 1285 | |
25e742b2 | 1286 | static void quirk_amd_ide_mode(struct pci_dev *pdev) |
ab17443a | 1287 | { |
5deab536 | 1288 | /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ |
05a7d22b | 1289 | u8 tmp; |
ab17443a | 1290 | |
05a7d22b CC |
1291 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); |
1292 | if (tmp == 0x01) { | |
ab17443a CH |
1293 | pci_read_config_byte(pdev, 0x40, &tmp); |
1294 | pci_write_config_byte(pdev, 0x40, tmp|1); | |
1295 | pci_write_config_byte(pdev, 0x9, 1); | |
1296 | pci_write_config_byte(pdev, 0xa, 6); | |
1297 | pci_write_config_byte(pdev, 0x40, tmp); | |
1298 | ||
c9f89475 | 1299 | pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
7506dc79 | 1300 | pci_info(pdev, "set SATA to AHCI mode\n"); |
ab17443a CH |
1301 | } |
1302 | } | |
05a7d22b | 1303 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1304 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
05a7d22b | 1305 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1306 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
5deab536 SH |
1307 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); |
1308 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); | |
fafe5c3d SH |
1309 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); |
1310 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); | |
ab17443a | 1311 | |
82e1719c | 1312 | /* Serverworks CSB5 IDE does not fully support native mode */ |
15856ad5 | 1313 | static void quirk_svwks_csb5ide(struct pci_dev *pdev) |
1da177e4 LT |
1314 | { |
1315 | u8 prog; | |
1316 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1317 | if (prog & 5) { | |
1318 | prog &= ~5; | |
1319 | pdev->class &= ~5; | |
1320 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
368c73d4 | 1321 | /* PCI layer will sort out resources */ |
1da177e4 LT |
1322 | } |
1323 | } | |
652c538e | 1324 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); |
1da177e4 | 1325 | |
82e1719c | 1326 | /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ |
15856ad5 | 1327 | static void quirk_ide_samemode(struct pci_dev *pdev) |
1da177e4 LT |
1328 | { |
1329 | u8 prog; | |
1330 | ||
1331 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1332 | ||
1333 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { | |
7506dc79 | 1334 | pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); |
1da177e4 LT |
1335 | prog &= ~5; |
1336 | pdev->class &= ~5; | |
1337 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
1da177e4 LT |
1338 | } |
1339 | } | |
368c73d4 | 1340 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
1da177e4 | 1341 | |
82e1719c | 1342 | /* Some ATA devices break if put into D3 */ |
15856ad5 | 1343 | static void quirk_no_ata_d3(struct pci_dev *pdev) |
979b1791 | 1344 | { |
faa738bb | 1345 | pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; |
979b1791 | 1346 | } |
faa738bb YL |
1347 | /* Quirk the legacy ATA devices only. The AHCI ones are ok */ |
1348 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, | |
1349 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
1350 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, | |
1351 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
7a661c6f | 1352 | /* ALi loses some register settings that we cannot then restore */ |
faa738bb YL |
1353 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, |
1354 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
7a661c6f AC |
1355 | /* VIA comes back fine but we need to keep it alive or ACPI GTM failures |
1356 | occur when mode detecting */ | |
faa738bb YL |
1357 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, |
1358 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
979b1791 | 1359 | |
82e1719c BH |
1360 | /* |
1361 | * This was originally an Alpha-specific thing, but it really fits here. | |
1da177e4 LT |
1362 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. |
1363 | */ | |
15856ad5 | 1364 | static void quirk_eisa_bridge(struct pci_dev *dev) |
1da177e4 LT |
1365 | { |
1366 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; | |
1367 | } | |
652c538e | 1368 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); |
1da177e4 LT |
1369 | |
1370 | /* | |
1371 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge | |
1372 | * is not activated. The myth is that Asus said that they do not want the | |
1373 | * users to be irritated by just another PCI Device in the Win98 device | |
f7625980 | 1374 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors |
1da177e4 LT |
1375 | * package 2.7.0 for details) |
1376 | * | |
f7625980 BH |
1377 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC |
1378 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it | |
d7698edc | 1379 | * becomes necessary to do this tweak in two steps -- the chosen trigger |
1380 | * is either the Host bridge (preferred) or on-board VGA controller. | |
9208ee82 JD |
1381 | * |
1382 | * Note that we used to unhide the SMBus that way on Toshiba laptops | |
1383 | * (Satellite A40 and Tecra M2) but then found that the thermal management | |
1384 | * was done by SMM code, which could cause unsynchronized concurrent | |
1385 | * accesses to the SMBus registers, with potentially bad effects. Thus you | |
1386 | * should be very careful when adding new entries: if SMM is accessing the | |
1387 | * Intel SMBus, this is a very good reason to leave it hidden. | |
a99acc83 JD |
1388 | * |
1389 | * Likewise, many recent laptops use ACPI for thermal management. If the | |
1390 | * ACPI DSDT code accesses the SMBus, then Linux should not access it | |
1391 | * natively, and keeping the SMBus hidden is the right thing to do. If you | |
1392 | * are about to add an entry in the table below, please first disassemble | |
1393 | * the DSDT and double-check that there is no code accessing the SMBus. | |
1da177e4 | 1394 | */ |
9d24a81e | 1395 | static int asus_hides_smbus; |
1da177e4 | 1396 | |
15856ad5 | 1397 | static void asus_hides_smbus_hostbridge(struct pci_dev *dev) |
1da177e4 LT |
1398 | { |
1399 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1400 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) | |
3c78bc61 | 1401 | switch (dev->subsystem_device) { |
a00db371 | 1402 | case 0x8025: /* P4B-LX */ |
1da177e4 LT |
1403 | case 0x8070: /* P4B */ |
1404 | case 0x8088: /* P4B533 */ | |
1405 | case 0x1626: /* L3C notebook */ | |
1406 | asus_hides_smbus = 1; | |
1407 | } | |
2f2d39d2 | 1408 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
3c78bc61 | 1409 | switch (dev->subsystem_device) { |
1da177e4 LT |
1410 | case 0x80b1: /* P4GE-V */ |
1411 | case 0x80b2: /* P4PE */ | |
1412 | case 0x8093: /* P4B533-V */ | |
1413 | asus_hides_smbus = 1; | |
1414 | } | |
2f2d39d2 | 1415 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
3c78bc61 | 1416 | switch (dev->subsystem_device) { |
1da177e4 LT |
1417 | case 0x8030: /* P4T533 */ |
1418 | asus_hides_smbus = 1; | |
1419 | } | |
2f2d39d2 | 1420 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
1da177e4 LT |
1421 | switch (dev->subsystem_device) { |
1422 | case 0x8070: /* P4G8X Deluxe */ | |
1423 | asus_hides_smbus = 1; | |
1424 | } | |
2f2d39d2 | 1425 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
321311af JD |
1426 | switch (dev->subsystem_device) { |
1427 | case 0x80c9: /* PU-DLS */ | |
1428 | asus_hides_smbus = 1; | |
1429 | } | |
2f2d39d2 | 1430 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
1da177e4 LT |
1431 | switch (dev->subsystem_device) { |
1432 | case 0x1751: /* M2N notebook */ | |
1433 | case 0x1821: /* M5N notebook */ | |
4096ed0f | 1434 | case 0x1897: /* A6L notebook */ |
1da177e4 LT |
1435 | asus_hides_smbus = 1; |
1436 | } | |
2f2d39d2 | 1437 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1da177e4 LT |
1438 | switch (dev->subsystem_device) { |
1439 | case 0x184b: /* W1N notebook */ | |
1440 | case 0x186a: /* M6Ne notebook */ | |
1441 | asus_hides_smbus = 1; | |
1442 | } | |
2f2d39d2 | 1443 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
2e45785c JD |
1444 | switch (dev->subsystem_device) { |
1445 | case 0x80f2: /* P4P800-X */ | |
1446 | asus_hides_smbus = 1; | |
1447 | } | |
2f2d39d2 | 1448 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
acc06632 M |
1449 | switch (dev->subsystem_device) { |
1450 | case 0x1882: /* M6V notebook */ | |
2d1e1c75 | 1451 | case 0x1977: /* A6VA notebook */ |
acc06632 M |
1452 | asus_hides_smbus = 1; |
1453 | } | |
1da177e4 LT |
1454 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
1455 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
3c78bc61 | 1456 | switch (dev->subsystem_device) { |
1da177e4 LT |
1457 | case 0x088C: /* HP Compaq nc8000 */ |
1458 | case 0x0890: /* HP Compaq nc6000 */ | |
1459 | asus_hides_smbus = 1; | |
1460 | } | |
2f2d39d2 | 1461 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1da177e4 LT |
1462 | switch (dev->subsystem_device) { |
1463 | case 0x12bc: /* HP D330L */ | |
e3b1bd57 | 1464 | case 0x12bd: /* HP D530 */ |
74c57428 | 1465 | case 0x006a: /* HP Compaq nx9500 */ |
1da177e4 LT |
1466 | asus_hides_smbus = 1; |
1467 | } | |
677cc644 JD |
1468 | else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) |
1469 | switch (dev->subsystem_device) { | |
1470 | case 0x12bf: /* HP xw4100 */ | |
1471 | asus_hides_smbus = 1; | |
1472 | } | |
3c78bc61 RD |
1473 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
1474 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1475 | switch (dev->subsystem_device) { | |
1476 | case 0xC00C: /* Samsung P35 notebook */ | |
1477 | asus_hides_smbus = 1; | |
1478 | } | |
c87f883e RIZ |
1479 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
1480 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
3c78bc61 | 1481 | switch (dev->subsystem_device) { |
c87f883e RIZ |
1482 | case 0x0058: /* Compaq Evo N620c */ |
1483 | asus_hides_smbus = 1; | |
1484 | } | |
d7698edc | 1485 | else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) |
3c78bc61 | 1486 | switch (dev->subsystem_device) { |
d7698edc | 1487 | case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ |
1488 | /* Motherboard doesn't have Host bridge | |
1489 | * subvendor/subdevice IDs, therefore checking | |
1490 | * its on-board VGA controller */ | |
1491 | asus_hides_smbus = 1; | |
1492 | } | |
8293b0f6 | 1493 | else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) |
3c78bc61 | 1494 | switch (dev->subsystem_device) { |
10260d9a JD |
1495 | case 0x00b8: /* Compaq Evo D510 CMT */ |
1496 | case 0x00b9: /* Compaq Evo D510 SFF */ | |
6b5096e4 | 1497 | case 0x00ba: /* Compaq Evo D510 USDT */ |
8293b0f6 DS |
1498 | /* Motherboard doesn't have Host bridge |
1499 | * subvendor/subdevice IDs and on-board VGA | |
1500 | * controller is disabled if an AGP card is | |
1501 | * inserted, therefore checking USB UHCI | |
1502 | * Controller #1 */ | |
10260d9a JD |
1503 | asus_hides_smbus = 1; |
1504 | } | |
27e46859 KH |
1505 | else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) |
1506 | switch (dev->subsystem_device) { | |
1507 | case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ | |
1508 | /* Motherboard doesn't have host bridge | |
1509 | * subvendor/subdevice IDs, therefore checking | |
1510 | * its on-board VGA controller */ | |
1511 | asus_hides_smbus = 1; | |
1512 | } | |
1da177e4 LT |
1513 | } |
1514 | } | |
652c538e AM |
1515 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); |
1516 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); | |
1517 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); | |
1518 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); | |
677cc644 | 1519 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); |
652c538e AM |
1520 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); |
1521 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); | |
1522 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); | |
1523 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); | |
1524 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); | |
1525 | ||
1526 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); | |
8293b0f6 | 1527 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); |
27e46859 | 1528 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); |
d7698edc | 1529 | |
1597cacb | 1530 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
1da177e4 LT |
1531 | { |
1532 | u16 val; | |
f7625980 | 1533 | |
1da177e4 LT |
1534 | if (likely(!asus_hides_smbus)) |
1535 | return; | |
1536 | ||
1537 | pci_read_config_word(dev, 0xF2, &val); | |
1538 | if (val & 0x8) { | |
1539 | pci_write_config_word(dev, 0xF2, val & (~0x8)); | |
1540 | pci_read_config_word(dev, 0xF2, &val); | |
1541 | if (val & 0x8) | |
7506dc79 | 1542 | pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", |
227f0647 | 1543 | val); |
1da177e4 | 1544 | else |
7506dc79 | 1545 | pci_info(dev, "Enabled i801 SMBus device\n"); |
1da177e4 LT |
1546 | } |
1547 | } | |
652c538e AM |
1548 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1549 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1550 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1551 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1552 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1553 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1554 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
e1a2a51e RW |
1555 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1556 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1557 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1558 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1559 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1560 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1561 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
1597cacb | 1562 | |
e1a2a51e RW |
1563 | /* It appears we just have one such device. If not, we have a warning */ |
1564 | static void __iomem *asus_rcba_base; | |
1565 | static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) | |
acc06632 | 1566 | { |
e1a2a51e | 1567 | u32 rcba; |
acc06632 M |
1568 | |
1569 | if (likely(!asus_hides_smbus)) | |
1570 | return; | |
e1a2a51e RW |
1571 | WARN_ON(asus_rcba_base); |
1572 | ||
acc06632 | 1573 | pci_read_config_dword(dev, 0xF0, &rcba); |
e1a2a51e RW |
1574 | /* use bits 31:14, 16 kB aligned */ |
1575 | asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); | |
1576 | if (asus_rcba_base == NULL) | |
1577 | return; | |
1578 | } | |
1579 | ||
1580 | static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) | |
1581 | { | |
1582 | u32 val; | |
1583 | ||
1584 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1585 | return; | |
82e1719c | 1586 | |
e1a2a51e RW |
1587 | /* read the Function Disable register, dword mode only */ |
1588 | val = readl(asus_rcba_base + 0x3418); | |
82e1719c BH |
1589 | |
1590 | /* enable the SMBus device */ | |
1591 | writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); | |
e1a2a51e RW |
1592 | } |
1593 | ||
1594 | static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) | |
1595 | { | |
1596 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1597 | return; | |
82e1719c | 1598 | |
e1a2a51e RW |
1599 | iounmap(asus_rcba_base); |
1600 | asus_rcba_base = NULL; | |
7506dc79 | 1601 | pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); |
acc06632 | 1602 | } |
e1a2a51e RW |
1603 | |
1604 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) | |
1605 | { | |
1606 | asus_hides_smbus_lpc_ich6_suspend(dev); | |
1607 | asus_hides_smbus_lpc_ich6_resume_early(dev); | |
1608 | asus_hides_smbus_lpc_ich6_resume(dev); | |
1609 | } | |
652c538e | 1610 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); |
e1a2a51e RW |
1611 | DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); |
1612 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); | |
1613 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); | |
ce007ea5 | 1614 | |
82e1719c | 1615 | /* SiS 96x south bridge: BIOS typically hides SMBus device... */ |
1597cacb | 1616 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
1da177e4 LT |
1617 | { |
1618 | u8 val = 0; | |
1da177e4 | 1619 | pci_read_config_byte(dev, 0x77, &val); |
2f5c33b3 | 1620 | if (val & 0x10) { |
7506dc79 | 1621 | pci_info(dev, "Enabling SiS 96x SMBus\n"); |
2f5c33b3 MH |
1622 | pci_write_config_byte(dev, 0x77, val & ~0x10); |
1623 | } | |
1da177e4 | 1624 | } |
652c538e AM |
1625 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1626 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1627 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1628 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
e1a2a51e RW |
1629 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1630 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1631 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1632 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
1da177e4 | 1633 | |
1da177e4 LT |
1634 | /* |
1635 | * ... This is further complicated by the fact that some SiS96x south | |
1636 | * bridges pretend to be 85C503/5513 instead. In that case see if we | |
1637 | * spotted a compatible north bridge to make sure. | |
82e1719c | 1638 | * (pci_find_device() doesn't work yet) |
1da177e4 LT |
1639 | * |
1640 | * We can also enable the sis96x bit in the discovery register.. | |
1641 | */ | |
1da177e4 LT |
1642 | #define SIS_DETECT_REGISTER 0x40 |
1643 | ||
1597cacb | 1644 | static void quirk_sis_503(struct pci_dev *dev) |
1da177e4 LT |
1645 | { |
1646 | u8 reg; | |
1647 | u16 devid; | |
1648 | ||
1649 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); | |
1650 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); | |
1651 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); | |
1652 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { | |
1653 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); | |
1654 | return; | |
1655 | } | |
1656 | ||
1da177e4 | 1657 | /* |
82e1719c BH |
1658 | * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case |
1659 | * it has already been processed. (Depends on link order, which is | |
1660 | * apparently not guaranteed) | |
1da177e4 LT |
1661 | */ |
1662 | dev->device = devid; | |
2f5c33b3 | 1663 | quirk_sis_96x_smbus(dev); |
1da177e4 | 1664 | } |
652c538e | 1665 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
e1a2a51e | 1666 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
1da177e4 | 1667 | |
e5548e96 BJD |
1668 | /* |
1669 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller | |
1670 | * and MC97 modem controller are disabled when a second PCI soundcard is | |
1671 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. | |
1672 | * -- bjd | |
1673 | */ | |
1597cacb | 1674 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
e5548e96 BJD |
1675 | { |
1676 | u8 val; | |
1677 | int asus_hides_ac97 = 0; | |
1678 | ||
1679 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1680 | if (dev->device == PCI_DEVICE_ID_VIA_8237) | |
1681 | asus_hides_ac97 = 1; | |
1682 | } | |
1683 | ||
1684 | if (!asus_hides_ac97) | |
1685 | return; | |
1686 | ||
1687 | pci_read_config_byte(dev, 0x50, &val); | |
1688 | if (val & 0xc0) { | |
1689 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); | |
1690 | pci_read_config_byte(dev, 0x50, &val); | |
1691 | if (val & 0xc0) | |
7506dc79 | 1692 | pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", |
227f0647 | 1693 | val); |
e5548e96 | 1694 | else |
7506dc79 | 1695 | pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); |
e5548e96 BJD |
1696 | } |
1697 | } | |
652c538e | 1698 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
e1a2a51e | 1699 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
1597cacb | 1700 | |
77967052 | 1701 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
15e0c694 AC |
1702 | |
1703 | /* | |
82e1719c BH |
1704 | * If we are using libata we can drive this chip properly but must do this |
1705 | * early on to make the additional device appear during the PCI scanning. | |
15e0c694 | 1706 | */ |
5ee2ae7f | 1707 | static void quirk_jmicron_ata(struct pci_dev *pdev) |
15e0c694 | 1708 | { |
e34bb370 | 1709 | u32 conf1, conf5, class; |
15e0c694 AC |
1710 | u8 hdr; |
1711 | ||
1712 | /* Only poke fn 0 */ | |
1713 | if (PCI_FUNC(pdev->devfn)) | |
1714 | return; | |
1715 | ||
5ee2ae7f TH |
1716 | pci_read_config_dword(pdev, 0x40, &conf1); |
1717 | pci_read_config_dword(pdev, 0x80, &conf5); | |
15e0c694 | 1718 | |
5ee2ae7f TH |
1719 | conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ |
1720 | conf5 &= ~(1 << 24); /* Clear bit 24 */ | |
1721 | ||
1722 | switch (pdev->device) { | |
4daedcfe TH |
1723 | case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ |
1724 | case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ | |
5b6ae5ba | 1725 | case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ |
5ee2ae7f TH |
1726 | /* The controller should be in single function ahci mode */ |
1727 | conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ | |
1728 | break; | |
1729 | ||
1730 | case PCI_DEVICE_ID_JMICRON_JMB365: | |
1731 | case PCI_DEVICE_ID_JMICRON_JMB366: | |
1732 | /* Redirect IDE second PATA port to the right spot */ | |
1733 | conf5 |= (1 << 24); | |
1734 | /* Fall through */ | |
1735 | case PCI_DEVICE_ID_JMICRON_JMB361: | |
1736 | case PCI_DEVICE_ID_JMICRON_JMB363: | |
5b6ae5ba | 1737 | case PCI_DEVICE_ID_JMICRON_JMB369: |
5ee2ae7f TH |
1738 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ |
1739 | /* Set the class codes correctly and then direct IDE 0 */ | |
3a9e3a51 | 1740 | conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
5ee2ae7f TH |
1741 | break; |
1742 | ||
1743 | case PCI_DEVICE_ID_JMICRON_JMB368: | |
1744 | /* The controller should be in single function IDE mode */ | |
1745 | conf1 |= 0x00C00000; /* Set 22, 23 */ | |
1746 | break; | |
15e0c694 | 1747 | } |
5ee2ae7f TH |
1748 | |
1749 | pci_write_config_dword(pdev, 0x40, conf1); | |
1750 | pci_write_config_dword(pdev, 0x80, conf5); | |
1751 | ||
1752 | /* Update pdev accordingly */ | |
1753 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); | |
1754 | pdev->hdr_type = hdr & 0x7f; | |
1755 | pdev->multifunction = !!(hdr & 0x80); | |
e34bb370 TH |
1756 | |
1757 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); | |
1758 | pdev->class = class >> 8; | |
15e0c694 | 1759 | } |
5ee2ae7f TH |
1760 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1761 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
4daedcfe | 1762 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
5ee2ae7f | 1763 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
5b6ae5ba | 1764 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
5ee2ae7f TH |
1765 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
1766 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1767 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
5b6ae5ba | 1768 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
e1a2a51e RW |
1769 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1770 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
4daedcfe | 1771 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
e1a2a51e | 1772 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
5b6ae5ba | 1773 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
e1a2a51e RW |
1774 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
1775 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1776 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
5b6ae5ba | 1777 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
15e0c694 AC |
1778 | |
1779 | #endif | |
1780 | ||
91f15fb3 ZR |
1781 | static void quirk_jmicron_async_suspend(struct pci_dev *dev) |
1782 | { | |
1783 | if (dev->multifunction) { | |
1784 | device_disable_async_suspend(&dev->dev); | |
7506dc79 | 1785 | pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); |
91f15fb3 ZR |
1786 | } |
1787 | } | |
1788 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); | |
1789 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); | |
1790 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); | |
1791 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); | |
1792 | ||
1da177e4 | 1793 | #ifdef CONFIG_X86_IO_APIC |
15856ad5 | 1794 | static void quirk_alder_ioapic(struct pci_dev *pdev) |
1da177e4 LT |
1795 | { |
1796 | int i; | |
1797 | ||
1798 | if ((pdev->class >> 8) != 0xff00) | |
1799 | return; | |
1800 | ||
82e1719c BH |
1801 | /* |
1802 | * The first BAR is the location of the IO-APIC... we must | |
1da177e4 | 1803 | * not touch this (and it's already covered by the fixmap), so |
82e1719c BH |
1804 | * forcibly insert it into the resource tree. |
1805 | */ | |
1da177e4 LT |
1806 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) |
1807 | insert_resource(&iomem_resource, &pdev->resource[0]); | |
1808 | ||
82e1719c BH |
1809 | /* |
1810 | * The next five BARs all seem to be rubbish, so just clean | |
1811 | * them out. | |
1812 | */ | |
3c78bc61 | 1813 | for (i = 1; i < 6; i++) |
1da177e4 | 1814 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); |
1da177e4 | 1815 | } |
652c538e | 1816 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); |
1da177e4 LT |
1817 | #endif |
1818 | ||
15856ad5 | 1819 | static void quirk_pcie_mch(struct pci_dev *pdev) |
1da177e4 | 1820 | { |
0ba379ec | 1821 | pdev->no_msi = 1; |
1da177e4 | 1822 | } |
652c538e AM |
1823 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); |
1824 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); | |
1825 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); | |
1da177e4 | 1826 | |
deb86999 | 1827 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); |
4602b88d KA |
1828 | |
1829 | /* | |
82e1719c BH |
1830 | * It's possible for the MSI to get corrupted if SHPC and ACPI are used |
1831 | * together on certain PXH-based systems. | |
4602b88d | 1832 | */ |
15856ad5 | 1833 | static void quirk_pcie_pxh(struct pci_dev *dev) |
4602b88d | 1834 | { |
4602b88d | 1835 | dev->no_msi = 1; |
7506dc79 | 1836 | pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); |
4602b88d KA |
1837 | } |
1838 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); | |
1839 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); | |
1840 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); | |
1841 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); | |
1842 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); | |
1843 | ||
ffadcc2f | 1844 | /* |
82e1719c BH |
1845 | * Some Intel PCI Express chipsets have trouble with downstream device |
1846 | * power management. | |
ffadcc2f | 1847 | */ |
3c78bc61 | 1848 | static void quirk_intel_pcie_pm(struct pci_dev *dev) |
ffadcc2f KCA |
1849 | { |
1850 | pci_pm_d3_delay = 120; | |
1851 | dev->no_d1d2 = 1; | |
1852 | } | |
ffadcc2f KCA |
1853 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); |
1854 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); | |
1855 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); | |
1856 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); | |
1857 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); | |
1858 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); | |
1859 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); | |
1860 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); | |
1861 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); | |
1862 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); | |
1863 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); | |
1864 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); | |
1865 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); | |
1866 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); | |
1867 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); | |
1868 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); | |
1869 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); | |
1870 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); | |
1871 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); | |
1872 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); | |
1873 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); | |
4602b88d | 1874 | |
5938628c BH |
1875 | static void quirk_radeon_pm(struct pci_dev *dev) |
1876 | { | |
1877 | if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && | |
1878 | dev->subsystem_device == 0x00e2) { | |
1879 | if (dev->d3_delay < 20) { | |
1880 | dev->d3_delay = 20; | |
7506dc79 | 1881 | pci_info(dev, "extending delay after power-on from D3 to %d msec\n", |
5938628c BH |
1882 | dev->d3_delay); |
1883 | } | |
1884 | } | |
1885 | } | |
1886 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); | |
1887 | ||
426b3b8d | 1888 | #ifdef CONFIG_X86_IO_APIC |
c4e649b0 SA |
1889 | static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) |
1890 | { | |
1891 | noioapicreroute = 1; | |
1892 | pr_info("%s detected: disable boot interrupt reroute\n", d->ident); | |
1893 | ||
1894 | return 0; | |
1895 | } | |
1896 | ||
6faadbbb | 1897 | static const struct dmi_system_id boot_interrupt_dmi_table[] = { |
c4e649b0 SA |
1898 | /* |
1899 | * Systems to exclude from boot interrupt reroute quirks | |
1900 | */ | |
1901 | { | |
1902 | .callback = dmi_disable_ioapicreroute, | |
1903 | .ident = "ASUSTek Computer INC. M2N-LR", | |
1904 | .matches = { | |
1905 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), | |
1906 | DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), | |
1907 | }, | |
1908 | }, | |
1909 | {} | |
1910 | }; | |
1911 | ||
e1d3a908 SA |
1912 | /* |
1913 | * Boot interrupts on some chipsets cannot be turned off. For these chipsets, | |
82e1719c | 1914 | * remap the original interrupt in the Linux kernel to the boot interrupt, so |
e1d3a908 SA |
1915 | * that a PCI device's interrupt handler is installed on the boot interrupt |
1916 | * line instead. | |
1917 | */ | |
1918 | static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) | |
1919 | { | |
c4e649b0 | 1920 | dmi_check_system(boot_interrupt_dmi_table); |
41b9eb26 | 1921 | if (noioapicquirk || noioapicreroute) |
e1d3a908 SA |
1922 | return; |
1923 | ||
1924 | dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; | |
7506dc79 | 1925 | pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", |
fdcdaf6c | 1926 | dev->vendor, dev->device); |
e1d3a908 | 1927 | } |
88d1dce3 OD |
1928 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); |
1929 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
1930 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
1931 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
1932 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
1933 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
1934 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
1935 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
1936 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); | |
1937 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
1938 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
1939 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
1940 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
1941 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
1942 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
1943 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
e1d3a908 | 1944 | |
426b3b8d SA |
1945 | /* |
1946 | * On some chipsets we can disable the generation of legacy INTx boot | |
1947 | * interrupts. | |
1948 | */ | |
1949 | ||
1950 | /* | |
82e1719c | 1951 | * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no |
426b3b8d SA |
1952 | * 300641-004US, section 5.7.3. |
1953 | */ | |
1954 | #define INTEL_6300_IOAPIC_ABAR 0x40 | |
1955 | #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) | |
1956 | ||
1957 | static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) | |
1958 | { | |
1959 | u16 pci_config_word; | |
1960 | ||
1961 | if (noioapicquirk) | |
1962 | return; | |
1963 | ||
1964 | pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); | |
1965 | pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; | |
1966 | pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); | |
1967 | ||
7506dc79 | 1968 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
fdcdaf6c | 1969 | dev->vendor, dev->device); |
426b3b8d | 1970 | } |
f7625980 BH |
1971 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); |
1972 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); | |
77251188 | 1973 | |
82e1719c | 1974 | /* Disable boot interrupts on HT-1000 */ |
77251188 OD |
1975 | #define BC_HT1000_FEATURE_REG 0x64 |
1976 | #define BC_HT1000_PIC_REGS_ENABLE (1<<0) | |
1977 | #define BC_HT1000_MAP_IDX 0xC00 | |
1978 | #define BC_HT1000_MAP_DATA 0xC01 | |
1979 | ||
1980 | static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) | |
1981 | { | |
1982 | u32 pci_config_dword; | |
1983 | u8 irq; | |
1984 | ||
1985 | if (noioapicquirk) | |
1986 | return; | |
1987 | ||
1988 | pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); | |
1989 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | | |
1990 | BC_HT1000_PIC_REGS_ENABLE); | |
1991 | ||
1992 | for (irq = 0x10; irq < 0x10 + 32; irq++) { | |
1993 | outb(irq, BC_HT1000_MAP_IDX); | |
1994 | outb(0x00, BC_HT1000_MAP_DATA); | |
1995 | } | |
1996 | ||
1997 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); | |
1998 | ||
7506dc79 | 1999 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
fdcdaf6c | 2000 | dev->vendor, dev->device); |
77251188 | 2001 | } |
f7625980 BH |
2002 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
2003 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); | |
542622da | 2004 | |
82e1719c BH |
2005 | /* Disable boot interrupts on AMD and ATI chipsets */ |
2006 | ||
542622da OD |
2007 | /* |
2008 | * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 | |
2009 | * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode | |
2010 | * (due to an erratum). | |
2011 | */ | |
2012 | #define AMD_813X_MISC 0x40 | |
2013 | #define AMD_813X_NOIOAMODE (1<<0) | |
4fd8bdc5 | 2014 | #define AMD_813X_REV_B1 0x12 |
bbe19443 | 2015 | #define AMD_813X_REV_B2 0x13 |
542622da OD |
2016 | |
2017 | static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) | |
2018 | { | |
2019 | u32 pci_config_dword; | |
2020 | ||
2021 | if (noioapicquirk) | |
2022 | return; | |
4fd8bdc5 SA |
2023 | if ((dev->revision == AMD_813X_REV_B1) || |
2024 | (dev->revision == AMD_813X_REV_B2)) | |
bbe19443 | 2025 | return; |
542622da OD |
2026 | |
2027 | pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); | |
2028 | pci_config_dword &= ~AMD_813X_NOIOAMODE; | |
2029 | pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); | |
2030 | ||
7506dc79 | 2031 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
fdcdaf6c | 2032 | dev->vendor, dev->device); |
542622da | 2033 | } |
4fd8bdc5 SA |
2034 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
2035 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
2036 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
2037 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
542622da OD |
2038 | |
2039 | #define AMD_8111_PCI_IRQ_ROUTING 0x56 | |
2040 | ||
2041 | static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) | |
2042 | { | |
2043 | u16 pci_config_word; | |
2044 | ||
2045 | if (noioapicquirk) | |
2046 | return; | |
2047 | ||
2048 | pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); | |
2049 | if (!pci_config_word) { | |
7506dc79 | 2050 | pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", |
227f0647 | 2051 | dev->vendor, dev->device); |
542622da OD |
2052 | return; |
2053 | } | |
2054 | pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); | |
7506dc79 | 2055 | pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", |
fdcdaf6c | 2056 | dev->vendor, dev->device); |
542622da | 2057 | } |
f7625980 BH |
2058 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
2059 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); | |
426b3b8d SA |
2060 | #endif /* CONFIG_X86_IO_APIC */ |
2061 | ||
33dced2e SS |
2062 | /* |
2063 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size | |
2064 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. | |
2065 | * Re-allocate the region if needed... | |
2066 | */ | |
15856ad5 | 2067 | static void quirk_tc86c001_ide(struct pci_dev *dev) |
33dced2e SS |
2068 | { |
2069 | struct resource *r = &dev->resource[0]; | |
2070 | ||
2071 | if (r->start & 0x8) { | |
bd064f0a | 2072 | r->flags |= IORESOURCE_UNSET; |
33dced2e SS |
2073 | r->start = 0; |
2074 | r->end = 0xf; | |
2075 | } | |
2076 | } | |
2077 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, | |
2078 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, | |
2079 | quirk_tc86c001_ide); | |
2080 | ||
21c5fd97 | 2081 | /* |
82e1719c | 2082 | * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the |
21c5fd97 IA |
2083 | * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) |
2084 | * being read correctly if bit 7 of the base address is set. | |
2085 | * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). | |
2086 | * Re-allocate the regions to a 256-byte boundary if necessary. | |
2087 | */ | |
193c0d68 | 2088 | static void quirk_plx_pci9050(struct pci_dev *dev) |
21c5fd97 IA |
2089 | { |
2090 | unsigned int bar; | |
2091 | ||
2092 | /* Fixed in revision 2 (PCI 9052). */ | |
2093 | if (dev->revision >= 2) | |
2094 | return; | |
2095 | for (bar = 0; bar <= 1; bar++) | |
2096 | if (pci_resource_len(dev, bar) == 0x80 && | |
2097 | (pci_resource_start(dev, bar) & 0x80)) { | |
2098 | struct resource *r = &dev->resource[bar]; | |
7506dc79 | 2099 | pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", |
21c5fd97 | 2100 | bar); |
bd064f0a | 2101 | r->flags |= IORESOURCE_UNSET; |
21c5fd97 IA |
2102 | r->start = 0; |
2103 | r->end = 0xff; | |
2104 | } | |
2105 | } | |
2106 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
2107 | quirk_plx_pci9050); | |
2794bb28 IA |
2108 | /* |
2109 | * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) | |
2110 | * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, | |
2111 | * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, | |
2112 | * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. | |
2113 | * | |
2114 | * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" | |
2115 | * driver. | |
2116 | */ | |
2117 | DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); | |
2118 | DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); | |
21c5fd97 | 2119 | |
15856ad5 | 2120 | static void quirk_netmos(struct pci_dev *dev) |
1da177e4 LT |
2121 | { |
2122 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; | |
2123 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
2124 | ||
2125 | /* | |
2126 | * These Netmos parts are multiport serial devices with optional | |
2127 | * parallel ports. Even when parallel ports are present, they | |
2128 | * are identified as class SERIAL, which means the serial driver | |
2129 | * will claim them. To prevent this, mark them as class OTHER. | |
2130 | * These combo devices should be claimed by parport_serial. | |
2131 | * | |
2132 | * The subdevice ID is of the form 0x00PS, where <P> is the number | |
2133 | * of parallel ports and <S> is the number of serial ports. | |
2134 | */ | |
2135 | switch (dev->device) { | |
4c9c1686 JS |
2136 | case PCI_DEVICE_ID_NETMOS_9835: |
2137 | /* Well, this rule doesn't hold for the following 9835 device */ | |
2138 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && | |
2139 | dev->subsystem_device == 0x0299) | |
2140 | return; | |
1d09d577 | 2141 | /* else, fall through */ |
1da177e4 LT |
2142 | case PCI_DEVICE_ID_NETMOS_9735: |
2143 | case PCI_DEVICE_ID_NETMOS_9745: | |
1da177e4 LT |
2144 | case PCI_DEVICE_ID_NETMOS_9845: |
2145 | case PCI_DEVICE_ID_NETMOS_9855: | |
08803efe | 2146 | if (num_parallel) { |
7506dc79 | 2147 | pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", |
1da177e4 LT |
2148 | dev->device, num_parallel, num_serial); |
2149 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | | |
2150 | (dev->class & 0xff); | |
2151 | } | |
2152 | } | |
2153 | } | |
08803efe YL |
2154 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, |
2155 | PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); | |
1da177e4 | 2156 | |
15856ad5 | 2157 | static void quirk_e100_interrupt(struct pci_dev *dev) |
16a74744 | 2158 | { |
e64aeccb | 2159 | u16 command, pmcsr; |
16a74744 BH |
2160 | u8 __iomem *csr; |
2161 | u8 cmd_hi; | |
2162 | ||
2163 | switch (dev->device) { | |
2164 | /* PCI IDs taken from drivers/net/e100.c */ | |
2165 | case 0x1029: | |
2166 | case 0x1030 ... 0x1034: | |
2167 | case 0x1038 ... 0x103E: | |
2168 | case 0x1050 ... 0x1057: | |
2169 | case 0x1059: | |
2170 | case 0x1064 ... 0x106B: | |
2171 | case 0x1091 ... 0x1095: | |
2172 | case 0x1209: | |
2173 | case 0x1229: | |
2174 | case 0x2449: | |
2175 | case 0x2459: | |
2176 | case 0x245D: | |
2177 | case 0x27DC: | |
2178 | break; | |
2179 | default: | |
2180 | return; | |
2181 | } | |
2182 | ||
2183 | /* | |
2184 | * Some firmware hands off the e100 with interrupts enabled, | |
2185 | * which can cause a flood of interrupts if packets are | |
2186 | * received before the driver attaches to the device. So | |
2187 | * disable all e100 interrupts here. The driver will | |
2188 | * re-enable them when it's ready. | |
2189 | */ | |
2190 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
16a74744 | 2191 | |
1bef7dc0 | 2192 | if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
16a74744 BH |
2193 | return; |
2194 | ||
e64aeccb IK |
2195 | /* |
2196 | * Check that the device is in the D0 power state. If it's not, | |
2197 | * there is no point to look any further. | |
2198 | */ | |
728cdb75 YW |
2199 | if (dev->pm_cap) { |
2200 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
e64aeccb IK |
2201 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) |
2202 | return; | |
2203 | } | |
2204 | ||
1bef7dc0 BH |
2205 | /* Convert from PCI bus to resource space. */ |
2206 | csr = ioremap(pci_resource_start(dev, 0), 8); | |
16a74744 | 2207 | if (!csr) { |
7506dc79 | 2208 | pci_warn(dev, "Can't map e100 registers\n"); |
16a74744 BH |
2209 | return; |
2210 | } | |
2211 | ||
2212 | cmd_hi = readb(csr + 3); | |
2213 | if (cmd_hi == 0) { | |
7506dc79 | 2214 | pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); |
16a74744 BH |
2215 | writeb(1, csr + 3); |
2216 | } | |
2217 | ||
2218 | iounmap(csr); | |
2219 | } | |
4c5b28e2 YL |
2220 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
2221 | PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); | |
a5312e28 | 2222 | |
649426ef AD |
2223 | /* |
2224 | * The 82575 and 82598 may experience data corruption issues when transitioning | |
96291d56 | 2225 | * out of L0S. To prevent this we need to disable L0S on the PCIe link. |
649426ef | 2226 | */ |
15856ad5 | 2227 | static void quirk_disable_aspm_l0s(struct pci_dev *dev) |
649426ef | 2228 | { |
7506dc79 | 2229 | pci_info(dev, "Disabling L0s\n"); |
649426ef AD |
2230 | pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); |
2231 | } | |
2232 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); | |
2233 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); | |
2234 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); | |
2235 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); | |
2236 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); | |
2237 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); | |
2238 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); | |
2239 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); | |
2240 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); | |
2241 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); | |
2242 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); | |
2243 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); | |
2244 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); | |
2245 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); | |
2246 | ||
4ec73791 SM |
2247 | /* |
2248 | * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain | |
2249 | * Link bit cleared after starting the link retrain process to allow this | |
2250 | * process to finish. | |
2251 | * | |
2252 | * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the | |
2253 | * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. | |
2254 | */ | |
2255 | static void quirk_enable_clear_retrain_link(struct pci_dev *dev) | |
2256 | { | |
2257 | dev->clear_retrain_link = 1; | |
2258 | pci_info(dev, "Enable PCIe Retrain Link quirk\n"); | |
2259 | } | |
2260 | DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link); | |
2261 | DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link); | |
2262 | DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link); | |
2263 | ||
15856ad5 | 2264 | static void fixup_rev1_53c810(struct pci_dev *dev) |
a5312e28 | 2265 | { |
e6323e3c BH |
2266 | u32 class = dev->class; |
2267 | ||
2268 | /* | |
2269 | * rev 1 ncr53c810 chips don't set the class at all which means | |
a5312e28 IK |
2270 | * they don't get their resources remapped. Fix that here. |
2271 | */ | |
e6323e3c BH |
2272 | if (class) |
2273 | return; | |
a5312e28 | 2274 | |
e6323e3c | 2275 | dev->class = PCI_CLASS_STORAGE_SCSI << 8; |
7506dc79 | 2276 | pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", |
e6323e3c | 2277 | class, dev->class); |
a5312e28 IK |
2278 | } |
2279 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); | |
2280 | ||
9d265124 | 2281 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
15856ad5 | 2282 | static void quirk_p64h2_1k_io(struct pci_dev *dev) |
9d265124 DY |
2283 | { |
2284 | u16 en1k; | |
9d265124 DY |
2285 | |
2286 | pci_read_config_word(dev, 0x40, &en1k); | |
2287 | ||
2288 | if (en1k & 0x200) { | |
7506dc79 | 2289 | pci_info(dev, "Enable I/O Space to 1KB granularity\n"); |
2b28ae19 | 2290 | dev->io_window_1k = 1; |
9d265124 DY |
2291 | } |
2292 | } | |
82e1719c | 2293 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); |
9d265124 | 2294 | |
82e1719c BH |
2295 | /* |
2296 | * Under some circumstances, AER is not linked with extended capabilities. | |
cf34a8e0 BG |
2297 | * Force it to be linked by setting the corresponding control bit in the |
2298 | * config space. | |
2299 | */ | |
1597cacb | 2300 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
cf34a8e0 BG |
2301 | { |
2302 | uint8_t b; | |
82e1719c | 2303 | |
cf34a8e0 BG |
2304 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { |
2305 | if (!(b & 0x20)) { | |
2306 | pci_write_config_byte(dev, 0xf41, b | 0x20); | |
7506dc79 | 2307 | pci_info(dev, "Linking AER extended capability\n"); |
cf34a8e0 BG |
2308 | } |
2309 | } | |
2310 | } | |
2311 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
2312 | quirk_nvidia_ck804_pcie_aer_ext_cap); | |
e1a2a51e | 2313 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
1597cacb | 2314 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
cf34a8e0 | 2315 | |
15856ad5 | 2316 | static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) |
53a9bf42 TY |
2317 | { |
2318 | /* | |
2319 | * Disable PCI Bus Parking and PCI Master read caching on CX700 | |
2320 | * which causes unspecified timing errors with a VT6212L on the PCI | |
ca846392 TY |
2321 | * bus leading to USB2.0 packet loss. |
2322 | * | |
2323 | * This quirk is only enabled if a second (on the external PCI bus) | |
2324 | * VT6212L is found -- the CX700 core itself also contains a USB | |
2325 | * host controller with the same PCI ID as the VT6212L. | |
53a9bf42 TY |
2326 | */ |
2327 | ||
ca846392 TY |
2328 | /* Count VT6212L instances */ |
2329 | struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, | |
2330 | PCI_DEVICE_ID_VIA_8235_USB_2, NULL); | |
53a9bf42 | 2331 | uint8_t b; |
ca846392 | 2332 | |
82e1719c BH |
2333 | /* |
2334 | * p should contain the first (internal) VT6212L -- see if we have | |
2335 | * an external one by searching again. | |
2336 | */ | |
ca846392 TY |
2337 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); |
2338 | if (!p) | |
2339 | return; | |
2340 | pci_dev_put(p); | |
2341 | ||
53a9bf42 TY |
2342 | if (pci_read_config_byte(dev, 0x76, &b) == 0) { |
2343 | if (b & 0x40) { | |
2344 | /* Turn off PCI Bus Parking */ | |
2345 | pci_write_config_byte(dev, 0x76, b ^ 0x40); | |
2346 | ||
7506dc79 | 2347 | pci_info(dev, "Disabling VIA CX700 PCI parking\n"); |
bc043274 TY |
2348 | } |
2349 | } | |
2350 | ||
2351 | if (pci_read_config_byte(dev, 0x72, &b) == 0) { | |
2352 | if (b != 0) { | |
53a9bf42 TY |
2353 | /* Turn off PCI Master read caching */ |
2354 | pci_write_config_byte(dev, 0x72, 0x0); | |
bc043274 TY |
2355 | |
2356 | /* Set PCI Master Bus time-out to "1x16 PCLK" */ | |
53a9bf42 | 2357 | pci_write_config_byte(dev, 0x75, 0x1); |
bc043274 TY |
2358 | |
2359 | /* Disable "Read FIFO Timer" */ | |
53a9bf42 TY |
2360 | pci_write_config_byte(dev, 0x77, 0x0); |
2361 | ||
7506dc79 | 2362 | pci_info(dev, "Disabling VIA CX700 PCI caching\n"); |
53a9bf42 TY |
2363 | } |
2364 | } | |
2365 | } | |
ca846392 | 2366 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); |
53a9bf42 | 2367 | |
25e742b2 | 2368 | static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) |
0b471506 MC |
2369 | { |
2370 | u32 rev; | |
2371 | ||
2372 | pci_read_config_dword(dev, 0xf4, &rev); | |
2373 | ||
2374 | /* Only CAP the MRRS if the device is a 5719 A0 */ | |
2375 | if (rev == 0x05719000) { | |
2376 | int readrq = pcie_get_readrq(dev); | |
2377 | if (readrq > 2048) | |
2378 | pcie_set_readrq(dev, 2048); | |
2379 | } | |
2380 | } | |
0b471506 MC |
2381 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, |
2382 | PCI_DEVICE_ID_TIGON3_5719, | |
2383 | quirk_brcm_5719_limit_mrrs); | |
2384 | ||
ce709f86 JM |
2385 | #ifdef CONFIG_PCIE_IPROC_PLATFORM |
2386 | static void quirk_paxc_bridge(struct pci_dev *pdev) | |
2387 | { | |
82e1719c BH |
2388 | /* |
2389 | * The PCI config space is shared with the PAXC root port and the first | |
ce709f86 JM |
2390 | * Ethernet device. So, we need to workaround this by telling the PCI |
2391 | * code that the bridge is not an Ethernet device. | |
2392 | */ | |
2393 | if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
2394 | pdev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
2395 | ||
82e1719c BH |
2396 | /* |
2397 | * MPSS is not being set properly (as it is currently 0). This is | |
ce709f86 JM |
2398 | * because that area of the PCI config space is hard coded to zero, and |
2399 | * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) | |
2400 | * so that the MPS can be set to the real max value. | |
2401 | */ | |
2402 | pdev->pcie_mpss = 2; | |
2403 | } | |
2404 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge); | |
2405 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); | |
b95e2cd0 RJ |
2406 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge); |
2407 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge); | |
2408 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge); | |
ce709f86 JM |
2409 | #endif |
2410 | ||
82e1719c BH |
2411 | /* |
2412 | * Originally in EDAC sources for i82875P: Intel tells BIOS developers to | |
2413 | * hide device 6 which configures the overflow device access containing the | |
2414 | * DRBs - this is where we expose device 6. | |
26c56dc0 MM |
2415 | * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm |
2416 | */ | |
15856ad5 | 2417 | static void quirk_unhide_mch_dev6(struct pci_dev *dev) |
26c56dc0 MM |
2418 | { |
2419 | u8 reg; | |
2420 | ||
2421 | if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { | |
7506dc79 | 2422 | pci_info(dev, "Enabling MCH 'Overflow' Device\n"); |
26c56dc0 MM |
2423 | pci_write_config_byte(dev, 0xF4, reg | 0x02); |
2424 | } | |
2425 | } | |
26c56dc0 MM |
2426 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, |
2427 | quirk_unhide_mch_dev6); | |
2428 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, | |
2429 | quirk_unhide_mch_dev6); | |
2430 | ||
3f79e107 | 2431 | #ifdef CONFIG_PCI_MSI |
82e1719c BH |
2432 | /* |
2433 | * Some chipsets do not support MSI. We cannot easily rely on setting | |
2434 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some | |
2435 | * other buses controlled by the chipset even if Linux is not aware of it. | |
2436 | * Instead of setting the flag on all buses in the machine, simply disable | |
2437 | * MSI globally. | |
3f79e107 | 2438 | */ |
15856ad5 | 2439 | static void quirk_disable_all_msi(struct pci_dev *dev) |
3f79e107 | 2440 | { |
88187dfa | 2441 | pci_no_msi(); |
7506dc79 | 2442 | pci_warn(dev, "MSI quirk detected; MSI disabled\n"); |
3f79e107 | 2443 | } |
ebdf7d39 TH |
2444 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); |
2445 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); | |
2446 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); | |
66d715c9 | 2447 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); |
184b812f | 2448 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
162dedd3 | 2449 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); |
549e1561 | 2450 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); |
10b4ad1a | 2451 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); |
3f79e107 BG |
2452 | |
2453 | /* Disable MSI on chipsets that are known to not support it */ | |
15856ad5 | 2454 | static void quirk_disable_msi(struct pci_dev *dev) |
3f79e107 BG |
2455 | { |
2456 | if (dev->subordinate) { | |
7506dc79 | 2457 | pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); |
3f79e107 BG |
2458 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2459 | } | |
2460 | } | |
2461 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); | |
134b3450 | 2462 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); |
9313ff45 | 2463 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); |
6397c75c | 2464 | |
aff61369 CL |
2465 | /* |
2466 | * The APC bridge device in AMD 780 family northbridges has some random | |
2467 | * OEM subsystem ID in its vendor ID register (erratum 18), so instead | |
2468 | * we use the possible vendor/device IDs of the host bridge for the | |
2469 | * declared quirk, and search for the APC bridge by slot number. | |
2470 | */ | |
15856ad5 | 2471 | static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) |
aff61369 CL |
2472 | { |
2473 | struct pci_dev *apc_bridge; | |
2474 | ||
2475 | apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); | |
2476 | if (apc_bridge) { | |
2477 | if (apc_bridge->device == 0x9602) | |
2478 | quirk_disable_msi(apc_bridge); | |
2479 | pci_dev_put(apc_bridge); | |
2480 | } | |
2481 | } | |
2482 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); | |
2483 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); | |
2484 | ||
82e1719c BH |
2485 | /* |
2486 | * Go through the list of HyperTransport capabilities and return 1 if a HT | |
2487 | * MSI capability is found and enabled. | |
2488 | */ | |
25e742b2 | 2489 | static int msi_ht_cap_enabled(struct pci_dev *dev) |
6397c75c | 2490 | { |
fff905f3 | 2491 | int pos, ttl = PCI_FIND_CAP_TTL; |
7a380507 ME |
2492 | |
2493 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2494 | while (pos && ttl--) { | |
2495 | u8 flags; | |
2496 | ||
2497 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
3c78bc61 | 2498 | &flags) == 0) { |
7506dc79 | 2499 | pci_info(dev, "Found %s HT MSI Mapping\n", |
7a380507 | 2500 | flags & HT_MSI_FLAGS_ENABLE ? |
f0fda801 | 2501 | "enabled" : "disabled"); |
7a380507 | 2502 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; |
6397c75c | 2503 | } |
7a380507 ME |
2504 | |
2505 | pos = pci_find_next_ht_capability(dev, pos, | |
2506 | HT_CAPTYPE_MSI_MAPPING); | |
6397c75c BG |
2507 | } |
2508 | return 0; | |
2509 | } | |
2510 | ||
82e1719c | 2511 | /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ |
25e742b2 | 2512 | static void quirk_msi_ht_cap(struct pci_dev *dev) |
6397c75c BG |
2513 | { |
2514 | if (dev->subordinate && !msi_ht_cap_enabled(dev)) { | |
7506dc79 | 2515 | pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); |
6397c75c BG |
2516 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2517 | } | |
2518 | } | |
2519 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, | |
2520 | quirk_msi_ht_cap); | |
6bae1d96 | 2521 | |
82e1719c BH |
2522 | /* |
2523 | * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported | |
2524 | * if the MSI capability is set in any of these mappings. | |
6397c75c | 2525 | */ |
25e742b2 | 2526 | static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) |
6397c75c BG |
2527 | { |
2528 | struct pci_dev *pdev; | |
2529 | ||
2530 | if (!dev->subordinate) | |
2531 | return; | |
2532 | ||
82e1719c BH |
2533 | /* |
2534 | * Check HT MSI cap on this chipset and the root one. A single one | |
2535 | * having MSI is enough to be sure that MSI is supported. | |
6397c75c | 2536 | */ |
11f242f0 | 2537 | pdev = pci_get_slot(dev->bus, 0); |
9ac0ce85 JJ |
2538 | if (!pdev) |
2539 | return; | |
0c875c28 | 2540 | if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
7506dc79 | 2541 | pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); |
6397c75c BG |
2542 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2543 | } | |
11f242f0 | 2544 | pci_dev_put(pdev); |
6397c75c BG |
2545 | } |
2546 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
2547 | quirk_nvidia_ck804_msi_ht_cap); | |
ba698ad4 | 2548 | |
415b6d0e | 2549 | /* Force enable MSI mapping capability on HT bridges */ |
25e742b2 | 2550 | static void ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e7 | 2551 | { |
fff905f3 | 2552 | int pos, ttl = PCI_FIND_CAP_TTL; |
9dc625e7 PC |
2553 | |
2554 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2555 | while (pos && ttl--) { | |
2556 | u8 flags; | |
2557 | ||
2558 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2559 | &flags) == 0) { | |
7506dc79 | 2560 | pci_info(dev, "Enabling HT MSI Mapping\n"); |
9dc625e7 PC |
2561 | |
2562 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2563 | flags | HT_MSI_FLAGS_ENABLE); | |
2564 | } | |
2565 | pos = pci_find_next_ht_capability(dev, pos, | |
2566 | HT_CAPTYPE_MSI_MAPPING); | |
2567 | } | |
2568 | } | |
415b6d0e BH |
2569 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, |
2570 | PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, | |
2571 | ht_enable_msi_mapping); | |
e0ae4f55 YL |
2572 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, |
2573 | ht_enable_msi_mapping); | |
2574 | ||
82e1719c BH |
2575 | /* |
2576 | * The P5N32-SLI motherboards from Asus have a problem with MSI | |
2577 | * for the MCP55 NIC. It is not yet determined whether the MSI problem | |
2578 | * also affects other devices. As for now, turn off MSI for this device. | |
75e07fc3 | 2579 | */ |
15856ad5 | 2580 | static void nvenet_msi_disable(struct pci_dev *dev) |
75e07fc3 | 2581 | { |
9251bac9 JD |
2582 | const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); |
2583 | ||
2584 | if (board_name && | |
2585 | (strstr(board_name, "P5N32-SLI PREMIUM") || | |
2586 | strstr(board_name, "P5N32-E SLI"))) { | |
7506dc79 | 2587 | pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); |
75e07fc3 AP |
2588 | dev->no_msi = 1; |
2589 | } | |
2590 | } | |
2591 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, | |
2592 | PCI_DEVICE_ID_NVIDIA_NVENET_15, | |
2593 | nvenet_msi_disable); | |
2594 | ||
66db60ea | 2595 | /* |
f7625980 BH |
2596 | * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing |
2597 | * config register. This register controls the routing of legacy | |
2598 | * interrupts from devices that route through the MCP55. If this register | |
2599 | * is misprogrammed, interrupts are only sent to the BSP, unlike | |
2600 | * conventional systems where the IRQ is broadcast to all online CPUs. Not | |
2601 | * having this register set properly prevents kdump from booting up | |
2602 | * properly, so let's make sure that we have it set correctly. | |
2603 | * Note that this is an undocumented register. | |
66db60ea | 2604 | */ |
15856ad5 | 2605 | static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) |
66db60ea NH |
2606 | { |
2607 | u32 cfg; | |
2608 | ||
49c2fa08 NH |
2609 | if (!pci_find_capability(dev, PCI_CAP_ID_HT)) |
2610 | return; | |
2611 | ||
66db60ea NH |
2612 | pci_read_config_dword(dev, 0x74, &cfg); |
2613 | ||
2614 | if (cfg & ((1 << 2) | (1 << 15))) { | |
25da8dba | 2615 | pr_info("Rewriting IRQ routing register on MCP55\n"); |
66db60ea NH |
2616 | cfg &= ~((1 << 2) | (1 << 15)); |
2617 | pci_write_config_dword(dev, 0x74, cfg); | |
2618 | } | |
2619 | } | |
66db60ea NH |
2620 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, |
2621 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, | |
2622 | nvbridge_check_legacy_irq_routing); | |
66db60ea NH |
2623 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, |
2624 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, | |
2625 | nvbridge_check_legacy_irq_routing); | |
2626 | ||
25e742b2 | 2627 | static int ht_check_msi_mapping(struct pci_dev *dev) |
de745306 | 2628 | { |
fff905f3 | 2629 | int pos, ttl = PCI_FIND_CAP_TTL; |
de745306 YL |
2630 | int found = 0; |
2631 | ||
82e1719c | 2632 | /* Check if there is HT MSI cap or enabled on this device */ |
de745306 YL |
2633 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); |
2634 | while (pos && ttl--) { | |
2635 | u8 flags; | |
2636 | ||
2637 | if (found < 1) | |
2638 | found = 1; | |
2639 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2640 | &flags) == 0) { | |
2641 | if (flags & HT_MSI_FLAGS_ENABLE) { | |
2642 | if (found < 2) { | |
2643 | found = 2; | |
2644 | break; | |
2645 | } | |
2646 | } | |
2647 | } | |
2648 | pos = pci_find_next_ht_capability(dev, pos, | |
2649 | HT_CAPTYPE_MSI_MAPPING); | |
2650 | } | |
2651 | ||
2652 | return found; | |
2653 | } | |
2654 | ||
25e742b2 | 2655 | static int host_bridge_with_leaf(struct pci_dev *host_bridge) |
de745306 YL |
2656 | { |
2657 | struct pci_dev *dev; | |
2658 | int pos; | |
2659 | int i, dev_no; | |
2660 | int found = 0; | |
2661 | ||
2662 | dev_no = host_bridge->devfn >> 3; | |
2663 | for (i = dev_no + 1; i < 0x20; i++) { | |
2664 | dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); | |
2665 | if (!dev) | |
2666 | continue; | |
2667 | ||
82e1719c | 2668 | /* found next host bridge? */ |
de745306 YL |
2669 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); |
2670 | if (pos != 0) { | |
2671 | pci_dev_put(dev); | |
2672 | break; | |
2673 | } | |
2674 | ||
2675 | if (ht_check_msi_mapping(dev)) { | |
2676 | found = 1; | |
2677 | pci_dev_put(dev); | |
2678 | break; | |
2679 | } | |
2680 | pci_dev_put(dev); | |
2681 | } | |
2682 | ||
2683 | return found; | |
2684 | } | |
2685 | ||
eeafda70 YL |
2686 | #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ |
2687 | #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ | |
2688 | ||
25e742b2 | 2689 | static int is_end_of_ht_chain(struct pci_dev *dev) |
eeafda70 YL |
2690 | { |
2691 | int pos, ctrl_off; | |
2692 | int end = 0; | |
2693 | u16 flags, ctrl; | |
2694 | ||
2695 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); | |
2696 | ||
2697 | if (!pos) | |
2698 | goto out; | |
2699 | ||
2700 | pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); | |
2701 | ||
2702 | ctrl_off = ((flags >> 10) & 1) ? | |
2703 | PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; | |
2704 | pci_read_config_word(dev, pos + ctrl_off, &ctrl); | |
2705 | ||
2706 | if (ctrl & (1 << 6)) | |
2707 | end = 1; | |
2708 | ||
2709 | out: | |
2710 | return end; | |
2711 | } | |
2712 | ||
25e742b2 | 2713 | static void nv_ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e7 PC |
2714 | { |
2715 | struct pci_dev *host_bridge; | |
1dec6b05 YL |
2716 | int pos; |
2717 | int i, dev_no; | |
2718 | int found = 0; | |
2719 | ||
2720 | dev_no = dev->devfn >> 3; | |
2721 | for (i = dev_no; i >= 0; i--) { | |
2722 | host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); | |
2723 | if (!host_bridge) | |
2724 | continue; | |
2725 | ||
2726 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
2727 | if (pos != 0) { | |
2728 | found = 1; | |
2729 | break; | |
2730 | } | |
2731 | pci_dev_put(host_bridge); | |
2732 | } | |
2733 | ||
2734 | if (!found) | |
2735 | return; | |
2736 | ||
eeafda70 YL |
2737 | /* don't enable end_device/host_bridge with leaf directly here */ |
2738 | if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && | |
2739 | host_bridge_with_leaf(host_bridge)) | |
de745306 YL |
2740 | goto out; |
2741 | ||
1dec6b05 YL |
2742 | /* root did that ! */ |
2743 | if (msi_ht_cap_enabled(host_bridge)) | |
2744 | goto out; | |
2745 | ||
2746 | ht_enable_msi_mapping(dev); | |
2747 | ||
2748 | out: | |
2749 | pci_dev_put(host_bridge); | |
2750 | } | |
2751 | ||
25e742b2 | 2752 | static void ht_disable_msi_mapping(struct pci_dev *dev) |
1dec6b05 | 2753 | { |
fff905f3 | 2754 | int pos, ttl = PCI_FIND_CAP_TTL; |
1dec6b05 YL |
2755 | |
2756 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2757 | while (pos && ttl--) { | |
2758 | u8 flags; | |
2759 | ||
2760 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2761 | &flags) == 0) { | |
7506dc79 | 2762 | pci_info(dev, "Disabling HT MSI Mapping\n"); |
1dec6b05 YL |
2763 | |
2764 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2765 | flags & ~HT_MSI_FLAGS_ENABLE); | |
2766 | } | |
2767 | pos = pci_find_next_ht_capability(dev, pos, | |
2768 | HT_CAPTYPE_MSI_MAPPING); | |
2769 | } | |
2770 | } | |
2771 | ||
25e742b2 | 2772 | static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) |
1dec6b05 YL |
2773 | { |
2774 | struct pci_dev *host_bridge; | |
2775 | int pos; | |
2776 | int found; | |
2777 | ||
3d2a5318 RW |
2778 | if (!pci_msi_enabled()) |
2779 | return; | |
2780 | ||
1dec6b05 YL |
2781 | /* check if there is HT MSI cap or enabled on this device */ |
2782 | found = ht_check_msi_mapping(dev); | |
2783 | ||
2784 | /* no HT MSI CAP */ | |
2785 | if (found == 0) | |
2786 | return; | |
9dc625e7 PC |
2787 | |
2788 | /* | |
2789 | * HT MSI mapping should be disabled on devices that are below | |
2790 | * a non-Hypertransport host bridge. Locate the host bridge... | |
2791 | */ | |
39c94652 SK |
2792 | host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, |
2793 | PCI_DEVFN(0, 0)); | |
9dc625e7 | 2794 | if (host_bridge == NULL) { |
7506dc79 | 2795 | pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); |
9dc625e7 PC |
2796 | return; |
2797 | } | |
2798 | ||
2799 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
2800 | if (pos != 0) { | |
2801 | /* Host bridge is to HT */ | |
1dec6b05 YL |
2802 | if (found == 1) { |
2803 | /* it is not enabled, try to enable it */ | |
de745306 YL |
2804 | if (all) |
2805 | ht_enable_msi_mapping(dev); | |
2806 | else | |
2807 | nv_ht_enable_msi_mapping(dev); | |
1dec6b05 | 2808 | } |
dff3aef7 | 2809 | goto out; |
9dc625e7 PC |
2810 | } |
2811 | ||
1dec6b05 YL |
2812 | /* HT MSI is not enabled */ |
2813 | if (found == 1) | |
dff3aef7 | 2814 | goto out; |
9dc625e7 | 2815 | |
1dec6b05 YL |
2816 | /* Host bridge is not to HT, disable HT MSI mapping on this device */ |
2817 | ht_disable_msi_mapping(dev); | |
dff3aef7 MS |
2818 | |
2819 | out: | |
2820 | pci_dev_put(host_bridge); | |
9dc625e7 | 2821 | } |
de745306 | 2822 | |
25e742b2 | 2823 | static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) |
de745306 YL |
2824 | { |
2825 | return __nv_msi_ht_cap_quirk(dev, 1); | |
2826 | } | |
82e1719c BH |
2827 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
2828 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); | |
de745306 | 2829 | |
25e742b2 | 2830 | static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) |
de745306 YL |
2831 | { |
2832 | return __nv_msi_ht_cap_quirk(dev, 0); | |
2833 | } | |
de745306 | 2834 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
6dab62ee | 2835 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
de745306 | 2836 | |
15856ad5 | 2837 | static void quirk_msi_intx_disable_bug(struct pci_dev *dev) |
ba698ad4 DM |
2838 | { |
2839 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2840 | } | |
82e1719c | 2841 | |
15856ad5 | 2842 | static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) |
4600c9d7 SH |
2843 | { |
2844 | struct pci_dev *p; | |
2845 | ||
82e1719c BH |
2846 | /* |
2847 | * SB700 MSI issue will be fixed at HW level from revision A21; | |
4600c9d7 SH |
2848 | * we need check PCI REVISION ID of SMBus controller to get SB700 |
2849 | * revision. | |
2850 | */ | |
2851 | p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
2852 | NULL); | |
2853 | if (!p) | |
2854 | return; | |
2855 | ||
2856 | if ((p->revision < 0x3B) && (p->revision >= 0x30)) | |
2857 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2858 | pci_dev_put(p); | |
2859 | } | |
82e1719c | 2860 | |
70588818 XH |
2861 | static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) |
2862 | { | |
2863 | /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ | |
2864 | if (dev->revision < 0x18) { | |
7506dc79 | 2865 | pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); |
70588818 XH |
2866 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; |
2867 | } | |
2868 | } | |
ba698ad4 DM |
2869 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
2870 | PCI_DEVICE_ID_TIGON3_5780, | |
2871 | quirk_msi_intx_disable_bug); | |
2872 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2873 | PCI_DEVICE_ID_TIGON3_5780S, | |
2874 | quirk_msi_intx_disable_bug); | |
2875 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2876 | PCI_DEVICE_ID_TIGON3_5714, | |
2877 | quirk_msi_intx_disable_bug); | |
2878 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2879 | PCI_DEVICE_ID_TIGON3_5714S, | |
2880 | quirk_msi_intx_disable_bug); | |
2881 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2882 | PCI_DEVICE_ID_TIGON3_5715, | |
2883 | quirk_msi_intx_disable_bug); | |
2884 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2885 | PCI_DEVICE_ID_TIGON3_5715S, | |
2886 | quirk_msi_intx_disable_bug); | |
2887 | ||
bc38b411 | 2888 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
4600c9d7 | 2889 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2890 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, |
4600c9d7 | 2891 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2892 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, |
4600c9d7 | 2893 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2894 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, |
4600c9d7 | 2895 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2896 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, |
4600c9d7 | 2897 | quirk_msi_intx_disable_ati_bug); |
bc38b411 DM |
2898 | |
2899 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, | |
2900 | quirk_msi_intx_disable_bug); | |
2901 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, | |
2902 | quirk_msi_intx_disable_bug); | |
2903 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, | |
2904 | quirk_msi_intx_disable_bug); | |
2905 | ||
7cb6a291 HX |
2906 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, |
2907 | quirk_msi_intx_disable_bug); | |
2908 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, | |
2909 | quirk_msi_intx_disable_bug); | |
2910 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, | |
2911 | quirk_msi_intx_disable_bug); | |
2912 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, | |
2913 | quirk_msi_intx_disable_bug); | |
2914 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, | |
2915 | quirk_msi_intx_disable_bug); | |
2916 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, | |
2917 | quirk_msi_intx_disable_bug); | |
70588818 XH |
2918 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, |
2919 | quirk_msi_intx_disable_qca_bug); | |
2920 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, | |
2921 | quirk_msi_intx_disable_qca_bug); | |
2922 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, | |
2923 | quirk_msi_intx_disable_qca_bug); | |
2924 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, | |
2925 | quirk_msi_intx_disable_qca_bug); | |
2926 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, | |
2927 | quirk_msi_intx_disable_qca_bug); | |
3f79e107 | 2928 | #endif /* CONFIG_PCI_MSI */ |
3d137310 | 2929 | |
82e1719c BH |
2930 | /* |
2931 | * Allow manual resource allocation for PCI hotplug bridges via | |
2932 | * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI | |
2933 | * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to | |
2934 | * allocate resources when hotplug device is inserted and PCI bus is | |
2935 | * rescanned. | |
3322340a | 2936 | */ |
15856ad5 | 2937 | static void quirk_hotplug_bridge(struct pci_dev *dev) |
3322340a FR |
2938 | { |
2939 | dev->is_hotplug_bridge = 1; | |
2940 | } | |
3322340a FR |
2941 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); |
2942 | ||
03cd8f7e | 2943 | /* |
82e1719c BH |
2944 | * This is a quirk for the Ricoh MMC controller found as a part of some |
2945 | * multifunction chips. | |
2946 | * | |
25985edc | 2947 | * This is very similar and based on the ricoh_mmc driver written by |
03cd8f7e ML |
2948 | * Philip Langdale. Thank you for these magic sequences. |
2949 | * | |
82e1719c BH |
2950 | * These chips implement the four main memory card controllers (SD, MMC, |
2951 | * MS, xD) and one or both of CardBus or FireWire. | |
03cd8f7e | 2952 | * |
82e1719c BH |
2953 | * It happens that they implement SD and MMC support as separate |
2954 | * controllers (and PCI functions). The Linux SDHCI driver supports MMC | |
2955 | * cards but the chip detects MMC cards in hardware and directs them to the | |
2956 | * MMC controller - so the SDHCI driver never sees them. | |
03cd8f7e | 2957 | * |
82e1719c BH |
2958 | * To get around this, we must disable the useless MMC controller. At that |
2959 | * point, the SDHCI controller will start seeing them. It seems to be the | |
2960 | * case that the relevant PCI registers to deactivate the MMC controller | |
2961 | * live on PCI function 0, which might be the CardBus controller or the | |
2962 | * FireWire controller, depending on the particular chip in question | |
03cd8f7e ML |
2963 | * |
2964 | * This has to be done early, because as soon as we disable the MMC controller | |
82e1719c BH |
2965 | * other PCI functions shift up one level, e.g. function #2 becomes function |
2966 | * #1, and this will confuse the PCI core. | |
03cd8f7e | 2967 | */ |
03cd8f7e ML |
2968 | #ifdef CONFIG_MMC_RICOH_MMC |
2969 | static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) | |
2970 | { | |
03cd8f7e ML |
2971 | u8 write_enable; |
2972 | u8 write_target; | |
2973 | u8 disable; | |
2974 | ||
82e1719c BH |
2975 | /* |
2976 | * Disable via CardBus interface | |
2977 | * | |
2978 | * This must be done via function #0 | |
2979 | */ | |
03cd8f7e ML |
2980 | if (PCI_FUNC(dev->devfn)) |
2981 | return; | |
2982 | ||
2983 | pci_read_config_byte(dev, 0xB7, &disable); | |
2984 | if (disable & 0x02) | |
2985 | return; | |
2986 | ||
2987 | pci_read_config_byte(dev, 0x8E, &write_enable); | |
2988 | pci_write_config_byte(dev, 0x8E, 0xAA); | |
2989 | pci_read_config_byte(dev, 0x8D, &write_target); | |
2990 | pci_write_config_byte(dev, 0x8D, 0xB7); | |
2991 | pci_write_config_byte(dev, 0xB7, disable | 0x02); | |
2992 | pci_write_config_byte(dev, 0x8E, write_enable); | |
2993 | pci_write_config_byte(dev, 0x8D, write_target); | |
2994 | ||
82e1719c | 2995 | pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); |
7506dc79 | 2996 | pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); |
03cd8f7e ML |
2997 | } |
2998 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); | |
2999 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); | |
3000 | ||
3001 | static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) | |
3002 | { | |
03cd8f7e ML |
3003 | u8 write_enable; |
3004 | u8 disable; | |
3005 | ||
82e1719c BH |
3006 | /* |
3007 | * Disable via FireWire interface | |
3008 | * | |
3009 | * This must be done via function #0 | |
3010 | */ | |
03cd8f7e ML |
3011 | if (PCI_FUNC(dev->devfn)) |
3012 | return; | |
15bed0f2 | 3013 | /* |
812089e0 | 3014 | * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize |
82e1719c BH |
3015 | * certain types of SD/MMC cards. Lowering the SD base clock |
3016 | * frequency from 200Mhz to 50Mhz fixes this issue. | |
15bed0f2 MI |
3017 | * |
3018 | * 0x150 - SD2.0 mode enable for changing base clock | |
3019 | * frequency to 50Mhz | |
3020 | * 0xe1 - Base clock frequency | |
3021 | * 0x32 - 50Mhz new clock frequency | |
3022 | * 0xf9 - Key register for 0x150 | |
3023 | * 0xfc - key register for 0xe1 | |
3024 | */ | |
812089e0 AL |
3025 | if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || |
3026 | dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { | |
15bed0f2 MI |
3027 | pci_write_config_byte(dev, 0xf9, 0xfc); |
3028 | pci_write_config_byte(dev, 0x150, 0x10); | |
3029 | pci_write_config_byte(dev, 0xf9, 0x00); | |
3030 | pci_write_config_byte(dev, 0xfc, 0x01); | |
3031 | pci_write_config_byte(dev, 0xe1, 0x32); | |
3032 | pci_write_config_byte(dev, 0xfc, 0x00); | |
3033 | ||
7506dc79 | 3034 | pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); |
15bed0f2 | 3035 | } |
3e309cdf JB |
3036 | |
3037 | pci_read_config_byte(dev, 0xCB, &disable); | |
3038 | ||
3039 | if (disable & 0x02) | |
3040 | return; | |
3041 | ||
3042 | pci_read_config_byte(dev, 0xCA, &write_enable); | |
3043 | pci_write_config_byte(dev, 0xCA, 0x57); | |
3044 | pci_write_config_byte(dev, 0xCB, disable | 0x02); | |
3045 | pci_write_config_byte(dev, 0xCA, write_enable); | |
3046 | ||
82e1719c | 3047 | pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); |
7506dc79 | 3048 | pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); |
3e309cdf | 3049 | |
03cd8f7e ML |
3050 | } |
3051 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); | |
3052 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); | |
812089e0 AL |
3053 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); |
3054 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); | |
be98ca65 MI |
3055 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); |
3056 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); | |
03cd8f7e ML |
3057 | #endif /*CONFIG_MMC_RICOH_MMC*/ |
3058 | ||
d3f13810 | 3059 | #ifdef CONFIG_DMAR_TABLE |
254e4200 SS |
3060 | #define VTUNCERRMSK_REG 0x1ac |
3061 | #define VTD_MSK_SPEC_ERRORS (1 << 31) | |
3062 | /* | |
82e1719c BH |
3063 | * This is a quirk for masking VT-d spec-defined errors to platform error |
3064 | * handling logic. Without this, platforms using Intel 7500, 5500 chipsets | |
254e4200 | 3065 | * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based |
82e1719c | 3066 | * on the RAS config settings of the platform) when a VT-d fault happens. |
254e4200 SS |
3067 | * The resulting SMI caused the system to hang. |
3068 | * | |
82e1719c | 3069 | * VT-d spec-related errors are already handled by the VT-d OS code, so no |
254e4200 SS |
3070 | * need to report the same error through other channels. |
3071 | */ | |
3072 | static void vtd_mask_spec_errors(struct pci_dev *dev) | |
3073 | { | |
3074 | u32 word; | |
3075 | ||
3076 | pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); | |
3077 | pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); | |
3078 | } | |
3079 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); | |
3080 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); | |
3081 | #endif | |
03cd8f7e | 3082 | |
15856ad5 | 3083 | static void fixup_ti816x_class(struct pci_dev *dev) |
63c44080 | 3084 | { |
d1541dc9 BH |
3085 | u32 class = dev->class; |
3086 | ||
63c44080 | 3087 | /* TI 816x devices do not have class code set when in PCIe boot mode */ |
d1541dc9 | 3088 | dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; |
7506dc79 | 3089 | pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", |
d1541dc9 | 3090 | class, dev->class); |
63c44080 | 3091 | } |
40c96236 | 3092 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, |
2b4aed1d | 3093 | PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); |
63c44080 | 3094 | |
82e1719c BH |
3095 | /* |
3096 | * Some PCIe devices do not work reliably with the claimed maximum | |
a94d072b BH |
3097 | * payload size supported. |
3098 | */ | |
15856ad5 | 3099 | static void fixup_mpss_256(struct pci_dev *dev) |
a94d072b BH |
3100 | { |
3101 | dev->pcie_mpss = 1; /* 256 bytes */ | |
3102 | } | |
3103 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, | |
3104 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); | |
3105 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, | |
3106 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); | |
3107 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, | |
3108 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); | |
3109 | ||
82e1719c BH |
3110 | /* |
3111 | * Intel 5000 and 5100 Memory controllers have an erratum with read completion | |
d387a8d6 | 3112 | * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. |
82e1719c | 3113 | * Since there is no way of knowing what the PCIe MPS on each fabric will be |
d387a8d6 JM |
3114 | * until all of the devices are discovered and buses walked, read completion |
3115 | * coalescing must be disabled. Unfortunately, it cannot be re-enabled because | |
3116 | * it is possible to hotplug a device with MPS of 256B. | |
3117 | */ | |
15856ad5 | 3118 | static void quirk_intel_mc_errata(struct pci_dev *dev) |
d387a8d6 JM |
3119 | { |
3120 | int err; | |
3121 | u16 rcc; | |
3122 | ||
27d868b5 KB |
3123 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF || |
3124 | pcie_bus_config == PCIE_BUS_DEFAULT) | |
d387a8d6 JM |
3125 | return; |
3126 | ||
82e1719c BH |
3127 | /* |
3128 | * Intel erratum specifies bits to change but does not say what | |
3129 | * they are. Keeping them magical until such time as the registers | |
3130 | * and values can be explained. | |
d387a8d6 JM |
3131 | */ |
3132 | err = pci_read_config_word(dev, 0x48, &rcc); | |
3133 | if (err) { | |
7506dc79 | 3134 | pci_err(dev, "Error attempting to read the read completion coalescing register\n"); |
d387a8d6 JM |
3135 | return; |
3136 | } | |
3137 | ||
3138 | if (!(rcc & (1 << 10))) | |
3139 | return; | |
3140 | ||
3141 | rcc &= ~(1 << 10); | |
3142 | ||
3143 | err = pci_write_config_word(dev, 0x48, rcc); | |
3144 | if (err) { | |
7506dc79 | 3145 | pci_err(dev, "Error attempting to write the read completion coalescing register\n"); |
d387a8d6 JM |
3146 | return; |
3147 | } | |
3148 | ||
82e1719c | 3149 | pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); |
d387a8d6 JM |
3150 | } |
3151 | /* Intel 5000 series memory controllers and ports 2-7 */ | |
3152 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); | |
3153 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); | |
3154 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); | |
3155 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); | |
3156 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); | |
3157 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); | |
3158 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); | |
3159 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); | |
3160 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); | |
3161 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); | |
3162 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); | |
3163 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); | |
3164 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); | |
3165 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); | |
3166 | /* Intel 5100 series memory controllers and ports 2-7 */ | |
3167 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); | |
3168 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); | |
3169 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); | |
3170 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); | |
3171 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); | |
3172 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); | |
3173 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); | |
3174 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); | |
3175 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); | |
3176 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); | |
3177 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); | |
3178 | ||
12b03188 | 3179 | /* |
82e1719c BH |
3180 | * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. |
3181 | * To work around this, query the size it should be configured to by the | |
3182 | * device and modify the resource end to correspond to this new size. | |
12b03188 JM |
3183 | */ |
3184 | static void quirk_intel_ntb(struct pci_dev *dev) | |
3185 | { | |
3186 | int rc; | |
3187 | u8 val; | |
3188 | ||
3189 | rc = pci_read_config_byte(dev, 0x00D0, &val); | |
3190 | if (rc) | |
3191 | return; | |
3192 | ||
3193 | dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; | |
3194 | ||
3195 | rc = pci_read_config_byte(dev, 0x00D1, &val); | |
3196 | if (rc) | |
3197 | return; | |
3198 | ||
3199 | dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; | |
3200 | } | |
3201 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); | |
3202 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); | |
3203 | ||
f67fd55f | 3204 | /* |
82e1719c BH |
3205 | * Some BIOS implementations leave the Intel GPU interrupts enabled, even |
3206 | * though no one is handling them (e.g., if the i915 driver is never | |
3207 | * loaded). Additionally the interrupt destination is not set up properly | |
f67fd55f TJ |
3208 | * and the interrupt ends up -somewhere-. |
3209 | * | |
82e1719c BH |
3210 | * These spurious interrupts are "sticky" and the kernel disables the |
3211 | * (shared) interrupt line after 100,000+ generated interrupts. | |
f67fd55f | 3212 | * |
82e1719c BH |
3213 | * Fix it by disabling the still enabled interrupts. This resolves crashes |
3214 | * often seen on monitor unplug. | |
f67fd55f TJ |
3215 | */ |
3216 | #define I915_DEIER_REG 0x4400c | |
15856ad5 | 3217 | static void disable_igfx_irq(struct pci_dev *dev) |
f67fd55f TJ |
3218 | { |
3219 | void __iomem *regs = pci_iomap(dev, 0, 0); | |
3220 | if (regs == NULL) { | |
7506dc79 | 3221 | pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); |
f67fd55f TJ |
3222 | return; |
3223 | } | |
3224 | ||
3225 | /* Check if any interrupt line is still enabled */ | |
3226 | if (readl(regs + I915_DEIER_REG) != 0) { | |
7506dc79 | 3227 | pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); |
f67fd55f TJ |
3228 | |
3229 | writel(0, regs + I915_DEIER_REG); | |
3230 | } | |
3231 | ||
3232 | pci_iounmap(dev, regs); | |
3233 | } | |
d0c9606b BM |
3234 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); |
3235 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); | |
3236 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); | |
f67fd55f | 3237 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); |
d0c9606b | 3238 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); |
f67fd55f | 3239 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); |
7c82126a | 3240 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); |
f67fd55f | 3241 | |
b8cac70a TB |
3242 | /* |
3243 | * PCI devices which are on Intel chips can skip the 10ms delay | |
3244 | * before entering D3 mode. | |
3245 | */ | |
3246 | static void quirk_remove_d3_delay(struct pci_dev *dev) | |
3247 | { | |
3248 | dev->d3_delay = 0; | |
3249 | } | |
cd3e2eb8 | 3250 | /* C600 Series devices do not need 10ms d3_delay */ |
b8cac70a | 3251 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); |
cd3e2eb8 | 3252 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); |
b8cac70a | 3253 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); |
cd3e2eb8 AS |
3254 | /* Lynxpoint-H PCH devices do not need 10ms d3_delay */ |
3255 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); | |
b8cac70a TB |
3256 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); |
3257 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); | |
cd3e2eb8 AS |
3258 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); |
3259 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); | |
b8cac70a | 3260 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); |
cd3e2eb8 AS |
3261 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); |
3262 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); | |
3263 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); | |
3264 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); | |
b8cac70a | 3265 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); |
4a118753 SK |
3266 | /* Intel Cherrytrail devices do not need 10ms d3_delay */ |
3267 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay); | |
cd3e2eb8 AS |
3268 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay); |
3269 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay); | |
4a118753 | 3270 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay); |
cd3e2eb8 AS |
3271 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay); |
3272 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay); | |
4a118753 SK |
3273 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay); |
3274 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay); | |
3275 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay); | |
d76d2fe0 | 3276 | |
fbebb9fd | 3277 | /* |
d76d2fe0 | 3278 | * Some devices may pass our check in pci_intx_mask_supported() if |
fbebb9fd BH |
3279 | * PCI_COMMAND_INTX_DISABLE works though they actually do not properly |
3280 | * support this feature. | |
3281 | */ | |
15856ad5 | 3282 | static void quirk_broken_intx_masking(struct pci_dev *dev) |
fbebb9fd BH |
3283 | { |
3284 | dev->broken_intx_masking = 1; | |
3285 | } | |
b88214ce NO |
3286 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, |
3287 | quirk_broken_intx_masking); | |
3288 | DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ | |
3289 | quirk_broken_intx_masking); | |
7c1efb68 BH |
3290 | DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ |
3291 | quirk_broken_intx_masking); | |
d76d2fe0 | 3292 | |
3cb30b73 AW |
3293 | /* |
3294 | * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) | |
3295 | * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC | |
3296 | * | |
3297 | * RTL8110SC - Fails under PCI device assignment using DisINTx masking. | |
3298 | */ | |
b88214ce NO |
3299 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, |
3300 | quirk_broken_intx_masking); | |
fbebb9fd | 3301 | |
8bcf4525 AW |
3302 | /* |
3303 | * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, | |
3304 | * DisINTx can be set but the interrupt status bit is non-functional. | |
3305 | */ | |
82e1719c BH |
3306 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); |
3307 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); | |
3308 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); | |
3309 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); | |
3310 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); | |
3311 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); | |
3312 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); | |
3313 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); | |
3314 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); | |
3315 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); | |
3316 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); | |
3317 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); | |
3318 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); | |
3319 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); | |
3320 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); | |
3321 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); | |
8bcf4525 | 3322 | |
d76d2fe0 NO |
3323 | static u16 mellanox_broken_intx_devs[] = { |
3324 | PCI_DEVICE_ID_MELLANOX_HERMON_SDR, | |
3325 | PCI_DEVICE_ID_MELLANOX_HERMON_DDR, | |
3326 | PCI_DEVICE_ID_MELLANOX_HERMON_QDR, | |
3327 | PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, | |
3328 | PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, | |
3329 | PCI_DEVICE_ID_MELLANOX_HERMON_EN, | |
3330 | PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, | |
3331 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, | |
3332 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, | |
3333 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, | |
3334 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, | |
3335 | PCI_DEVICE_ID_MELLANOX_CONNECTX2, | |
3336 | PCI_DEVICE_ID_MELLANOX_CONNECTX3, | |
3337 | PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, | |
d76d2fe0 NO |
3338 | }; |
3339 | ||
1600f625 NO |
3340 | #define CONNECTX_4_CURR_MAX_MINOR 99 |
3341 | #define CONNECTX_4_INTX_SUPPORT_MINOR 14 | |
3342 | ||
3343 | /* | |
3344 | * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. | |
3345 | * If so, don't mark it as broken. | |
3346 | * FW minor > 99 means older FW version format and no INTx masking support. | |
3347 | * FW minor < 14 means new FW version format and no INTx masking support. | |
3348 | */ | |
d76d2fe0 NO |
3349 | static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) |
3350 | { | |
1600f625 NO |
3351 | __be32 __iomem *fw_ver; |
3352 | u16 fw_major; | |
3353 | u16 fw_minor; | |
3354 | u16 fw_subminor; | |
3355 | u32 fw_maj_min; | |
3356 | u32 fw_sub_min; | |
d76d2fe0 NO |
3357 | int i; |
3358 | ||
3359 | for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { | |
3360 | if (pdev->device == mellanox_broken_intx_devs[i]) { | |
3361 | pdev->broken_intx_masking = 1; | |
3362 | return; | |
3363 | } | |
3364 | } | |
1600f625 | 3365 | |
82e1719c BH |
3366 | /* |
3367 | * Getting here means Connect-IB cards and up. Connect-IB has no INTx | |
1600f625 NO |
3368 | * support so shouldn't be checked further |
3369 | */ | |
3370 | if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) | |
3371 | return; | |
3372 | ||
3373 | if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && | |
3374 | pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) | |
3375 | return; | |
3376 | ||
3377 | /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ | |
3378 | if (pci_enable_device_mem(pdev)) { | |
7506dc79 | 3379 | pci_warn(pdev, "Can't enable device memory\n"); |
1600f625 NO |
3380 | return; |
3381 | } | |
3382 | ||
3383 | fw_ver = ioremap(pci_resource_start(pdev, 0), 4); | |
3384 | if (!fw_ver) { | |
7506dc79 | 3385 | pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); |
1600f625 NO |
3386 | goto out; |
3387 | } | |
3388 | ||
3389 | /* Reading from resource space should be 32b aligned */ | |
3390 | fw_maj_min = ioread32be(fw_ver); | |
3391 | fw_sub_min = ioread32be(fw_ver + 1); | |
3392 | fw_major = fw_maj_min & 0xffff; | |
3393 | fw_minor = fw_maj_min >> 16; | |
3394 | fw_subminor = fw_sub_min & 0xffff; | |
3395 | if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || | |
3396 | fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { | |
7506dc79 | 3397 | pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", |
1600f625 NO |
3398 | fw_major, fw_minor, fw_subminor, pdev->device == |
3399 | PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); | |
3400 | pdev->broken_intx_masking = 1; | |
3401 | } | |
3402 | ||
3403 | iounmap(fw_ver); | |
3404 | ||
3405 | out: | |
3406 | pci_disable_device(pdev); | |
d76d2fe0 NO |
3407 | } |
3408 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, | |
3409 | mellanox_check_broken_intx_masking); | |
8bcf4525 | 3410 | |
c3e59ee4 AW |
3411 | static void quirk_no_bus_reset(struct pci_dev *dev) |
3412 | { | |
3413 | dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; | |
3414 | } | |
3415 | ||
3416 | /* | |
9ac0108c CB |
3417 | * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. |
3418 | * The device will throw a Link Down error on AER-capable systems and | |
3419 | * regardless of AER, config space of the device is never accessible again | |
3420 | * and typically causes the system to hang or reset when access is attempted. | |
c3e59ee4 AW |
3421 | * http://www.spinics.net/lists/linux-pci/msg34797.html |
3422 | */ | |
3423 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); | |
9ac0108c CB |
3424 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); |
3425 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); | |
8e2e0317 | 3426 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); |
6afb7e26 | 3427 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); |
c3e59ee4 | 3428 | |
82215510 DD |
3429 | /* |
3430 | * Root port on some Cavium CN8xxx chips do not successfully complete a bus | |
3431 | * reset when used with certain child devices. After the reset, config | |
3432 | * accesses to the child may fail. | |
3433 | */ | |
3434 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); | |
3435 | ||
d84f3174 AW |
3436 | static void quirk_no_pm_reset(struct pci_dev *dev) |
3437 | { | |
3438 | /* | |
3439 | * We can't do a bus reset on root bus devices, but an ineffective | |
3440 | * PM reset may be better than nothing. | |
3441 | */ | |
3442 | if (!pci_is_root_bus(dev->bus)) | |
3443 | dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; | |
3444 | } | |
3445 | ||
3446 | /* | |
3447 | * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition | |
3448 | * causes a reset (i.e., they advertise NoSoftRst-). This transition seems | |
3449 | * to have no effect on the device: it retains the framebuffer contents and | |
3450 | * monitor sync. Advertising this support makes other layers, like VFIO, | |
3451 | * assume pci_reset_function() is viable for this device. Mark it as | |
3452 | * unavailable to skip it when testing reset methods. | |
3453 | */ | |
3454 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, | |
3455 | PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); | |
3456 | ||
19bf4d4f LW |
3457 | /* |
3458 | * Thunderbolt controllers with broken MSI hotplug signaling: | |
3459 | * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part | |
3460 | * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). | |
3461 | */ | |
3462 | static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) | |
3463 | { | |
3464 | if (pdev->is_hotplug_bridge && | |
3465 | (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || | |
3466 | pdev->revision <= 1)) | |
3467 | pdev->no_msi = 1; | |
3468 | } | |
3469 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, | |
3470 | quirk_thunderbolt_hotplug_msi); | |
3471 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, | |
3472 | quirk_thunderbolt_hotplug_msi); | |
3473 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, | |
3474 | quirk_thunderbolt_hotplug_msi); | |
3475 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, | |
3476 | quirk_thunderbolt_hotplug_msi); | |
3477 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, | |
3478 | quirk_thunderbolt_hotplug_msi); | |
3479 | ||
1df5172c AN |
3480 | #ifdef CONFIG_ACPI |
3481 | /* | |
3482 | * Apple: Shutdown Cactus Ridge Thunderbolt controller. | |
3483 | * | |
3484 | * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be | |
3485 | * shutdown before suspend. Otherwise the native host interface (NHI) will not | |
3486 | * be present after resume if a device was plugged in before suspend. | |
3487 | * | |
82e1719c BH |
3488 | * The Thunderbolt controller consists of a PCIe switch with downstream |
3489 | * bridges leading to the NHI and to the tunnel PCI bridges. | |
1df5172c AN |
3490 | * |
3491 | * This quirk cuts power to the whole chip. Therefore we have to apply it | |
3492 | * during suspend_noirq of the upstream bridge. | |
3493 | * | |
3494 | * Power is automagically restored before resume. No action is needed. | |
3495 | */ | |
3496 | static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) | |
3497 | { | |
3498 | acpi_handle bridge, SXIO, SXFP, SXLV; | |
3499 | ||
630b3aff | 3500 | if (!x86_apple_machine) |
1df5172c AN |
3501 | return; |
3502 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) | |
3503 | return; | |
3504 | bridge = ACPI_HANDLE(&dev->dev); | |
3505 | if (!bridge) | |
3506 | return; | |
82e1719c | 3507 | |
1df5172c AN |
3508 | /* |
3509 | * SXIO and SXLV are present only on machines requiring this quirk. | |
82e1719c BH |
3510 | * Thunderbolt bridges in external devices might have the same |
3511 | * device ID as those on the host, but they will not have the | |
3512 | * associated ACPI methods. This implicitly checks that we are at | |
3513 | * the right bridge. | |
1df5172c AN |
3514 | */ |
3515 | if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) | |
3516 | || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) | |
3517 | || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) | |
3518 | return; | |
82e1719c | 3519 | pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); |
1df5172c AN |
3520 | |
3521 | /* magic sequence */ | |
3522 | acpi_execute_simple_method(SXIO, NULL, 1); | |
3523 | acpi_execute_simple_method(SXFP, NULL, 0); | |
3524 | msleep(300); | |
3525 | acpi_execute_simple_method(SXLV, NULL, 0); | |
3526 | acpi_execute_simple_method(SXIO, NULL, 0); | |
3527 | acpi_execute_simple_method(SXLV, NULL, 0); | |
3528 | } | |
1d111406 LW |
3529 | DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, |
3530 | PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, | |
1df5172c AN |
3531 | quirk_apple_poweroff_thunderbolt); |
3532 | ||
3533 | /* | |
82e1719c | 3534 | * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels |
1df5172c | 3535 | * |
82e1719c | 3536 | * During suspend the Thunderbolt controller is reset and all PCI |
1df5172c AN |
3537 | * tunnels are lost. The NHI driver will try to reestablish all tunnels |
3538 | * during resume. We have to manually wait for the NHI since there is | |
3539 | * no parent child relationship between the NHI and the tunneled | |
3540 | * bridges. | |
3541 | */ | |
3542 | static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) | |
3543 | { | |
3544 | struct pci_dev *sibling = NULL; | |
3545 | struct pci_dev *nhi = NULL; | |
3546 | ||
630b3aff | 3547 | if (!x86_apple_machine) |
1df5172c AN |
3548 | return; |
3549 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) | |
3550 | return; | |
82e1719c | 3551 | |
1df5172c | 3552 | /* |
82e1719c BH |
3553 | * Find the NHI and confirm that we are a bridge on the Thunderbolt |
3554 | * host controller and not on a Thunderbolt endpoint. | |
1df5172c AN |
3555 | */ |
3556 | sibling = pci_get_slot(dev->bus, 0x0); | |
3557 | if (sibling == dev) | |
3558 | goto out; /* we are the downstream bridge to the NHI */ | |
3559 | if (!sibling || !sibling->subordinate) | |
3560 | goto out; | |
3561 | nhi = pci_get_slot(sibling->subordinate, 0x0); | |
3562 | if (!nhi) | |
3563 | goto out; | |
3564 | if (nhi->vendor != PCI_VENDOR_ID_INTEL | |
19bf4d4f LW |
3565 | || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE && |
3566 | nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C && | |
82a6a81c | 3567 | nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI && |
1d111406 | 3568 | nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) |
25eb7e5c | 3569 | || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) |
1df5172c | 3570 | goto out; |
82e1719c | 3571 | pci_info(dev, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n"); |
1df5172c AN |
3572 | device_pm_wait_for_dev(&dev->dev, &nhi->dev); |
3573 | out: | |
3574 | pci_dev_put(nhi); | |
3575 | pci_dev_put(sibling); | |
3576 | } | |
19bf4d4f LW |
3577 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, |
3578 | PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, | |
1df5172c | 3579 | quirk_apple_wait_for_thunderbolt); |
1d111406 LW |
3580 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, |
3581 | PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, | |
1df5172c | 3582 | quirk_apple_wait_for_thunderbolt); |
82a6a81c XG |
3583 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, |
3584 | PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE, | |
3585 | quirk_apple_wait_for_thunderbolt); | |
1d111406 LW |
3586 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, |
3587 | PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE, | |
1df5172c AN |
3588 | quirk_apple_wait_for_thunderbolt); |
3589 | #endif | |
3590 | ||
b9c3b266 | 3591 | /* |
4091fb95 | 3592 | * Following are device-specific reset methods which can be used to |
b9c3b266 DC |
3593 | * reset a single function if other methods (e.g. FLR, PM D0->D3) are |
3594 | * not available. | |
3595 | */ | |
c763e7b5 DC |
3596 | static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) |
3597 | { | |
76b57c67 BH |
3598 | /* |
3599 | * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf | |
3600 | * | |
3601 | * The 82599 supports FLR on VFs, but FLR support is reported only | |
3602 | * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). | |
c8d8096a CH |
3603 | * Thus we must call pcie_flr() directly without first checking if it is |
3604 | * supported. | |
76b57c67 | 3605 | */ |
c8d8096a CH |
3606 | if (!probe) |
3607 | pcie_flr(dev); | |
c763e7b5 DC |
3608 | return 0; |
3609 | } | |
3610 | ||
aba72ddc VS |
3611 | #define SOUTH_CHICKEN2 0xc2004 |
3612 | #define PCH_PP_STATUS 0xc7200 | |
3613 | #define PCH_PP_CONTROL 0xc7204 | |
df558de1 XH |
3614 | #define MSG_CTL 0x45010 |
3615 | #define NSDE_PWR_STATE 0xd0100 | |
3616 | #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ | |
3617 | ||
3618 | static int reset_ivb_igd(struct pci_dev *dev, int probe) | |
3619 | { | |
3620 | void __iomem *mmio_base; | |
3621 | unsigned long timeout; | |
3622 | u32 val; | |
3623 | ||
3624 | if (probe) | |
3625 | return 0; | |
3626 | ||
3627 | mmio_base = pci_iomap(dev, 0, 0); | |
3628 | if (!mmio_base) | |
3629 | return -ENOMEM; | |
3630 | ||
3631 | iowrite32(0x00000002, mmio_base + MSG_CTL); | |
3632 | ||
3633 | /* | |
3634 | * Clobbering SOUTH_CHICKEN2 register is fine only if the next | |
3635 | * driver loaded sets the right bits. However, this's a reset and | |
3636 | * the bits have been set by i915 previously, so we clobber | |
3637 | * SOUTH_CHICKEN2 register directly here. | |
3638 | */ | |
3639 | iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); | |
3640 | ||
3641 | val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; | |
3642 | iowrite32(val, mmio_base + PCH_PP_CONTROL); | |
3643 | ||
3644 | timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); | |
3645 | do { | |
3646 | val = ioread32(mmio_base + PCH_PP_STATUS); | |
3647 | if ((val & 0xb0000000) == 0) | |
3648 | goto reset_complete; | |
3649 | msleep(10); | |
3650 | } while (time_before(jiffies, timeout)); | |
7506dc79 | 3651 | pci_warn(dev, "timeout during reset\n"); |
df558de1 XH |
3652 | |
3653 | reset_complete: | |
3654 | iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); | |
3655 | ||
3656 | pci_iounmap(dev, mmio_base); | |
3657 | return 0; | |
3658 | } | |
3659 | ||
82e1719c | 3660 | /* Device-specific reset method for Chelsio T4-based adapters */ |
2c6217e0 CL |
3661 | static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) |
3662 | { | |
3663 | u16 old_command; | |
3664 | u16 msix_flags; | |
3665 | ||
3666 | /* | |
3667 | * If this isn't a Chelsio T4-based device, return -ENOTTY indicating | |
3668 | * that we have no device-specific reset method. | |
3669 | */ | |
3670 | if ((dev->device & 0xf000) != 0x4000) | |
3671 | return -ENOTTY; | |
3672 | ||
3673 | /* | |
3674 | * If this is the "probe" phase, return 0 indicating that we can | |
3675 | * reset this device. | |
3676 | */ | |
3677 | if (probe) | |
3678 | return 0; | |
3679 | ||
3680 | /* | |
3681 | * T4 can wedge if there are DMAs in flight within the chip and Bus | |
3682 | * Master has been disabled. We need to have it on till the Function | |
3683 | * Level Reset completes. (BUS_MASTER is disabled in | |
3684 | * pci_reset_function()). | |
3685 | */ | |
3686 | pci_read_config_word(dev, PCI_COMMAND, &old_command); | |
3687 | pci_write_config_word(dev, PCI_COMMAND, | |
3688 | old_command | PCI_COMMAND_MASTER); | |
3689 | ||
3690 | /* | |
3691 | * Perform the actual device function reset, saving and restoring | |
3692 | * configuration information around the reset. | |
3693 | */ | |
3694 | pci_save_state(dev); | |
3695 | ||
3696 | /* | |
3697 | * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts | |
3698 | * are disabled when an MSI-X interrupt message needs to be delivered. | |
3699 | * So we briefly re-enable MSI-X interrupts for the duration of the | |
3700 | * FLR. The pci_restore_state() below will restore the original | |
3701 | * MSI-X state. | |
3702 | */ | |
3703 | pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); | |
3704 | if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) | |
3705 | pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, | |
3706 | msix_flags | | |
3707 | PCI_MSIX_FLAGS_ENABLE | | |
3708 | PCI_MSIX_FLAGS_MASKALL); | |
3709 | ||
48f52d1a | 3710 | pcie_flr(dev); |
2c6217e0 CL |
3711 | |
3712 | /* | |
3713 | * Restore the configuration information (BAR values, etc.) including | |
3714 | * the original PCI Configuration Space Command word, and return | |
3715 | * success. | |
3716 | */ | |
3717 | pci_restore_state(dev); | |
3718 | pci_write_config_word(dev, PCI_COMMAND, old_command); | |
3719 | return 0; | |
3720 | } | |
3721 | ||
c763e7b5 | 3722 | #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed |
df558de1 XH |
3723 | #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 |
3724 | #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 | |
c763e7b5 | 3725 | |
ffb08634 AW |
3726 | /* |
3727 | * The Samsung SM961/PM961 controller can sometimes enter a fatal state after | |
3728 | * FLR where config space reads from the device return -1. We seem to be | |
3729 | * able to avoid this condition if we disable the NVMe controller prior to | |
3730 | * FLR. This quirk is generic for any NVMe class device requiring similar | |
3731 | * assistance to quiesce the device prior to FLR. | |
3732 | * | |
3733 | * NVMe specification: https://nvmexpress.org/resources/specifications/ | |
3734 | * Revision 1.0e: | |
3735 | * Chapter 2: Required and optional PCI config registers | |
3736 | * Chapter 3: NVMe control registers | |
3737 | * Chapter 7.3: Reset behavior | |
3738 | */ | |
3739 | static int nvme_disable_and_flr(struct pci_dev *dev, int probe) | |
3740 | { | |
3741 | void __iomem *bar; | |
3742 | u16 cmd; | |
3743 | u32 cfg; | |
3744 | ||
3745 | if (dev->class != PCI_CLASS_STORAGE_EXPRESS || | |
3746 | !pcie_has_flr(dev) || !pci_resource_start(dev, 0)) | |
3747 | return -ENOTTY; | |
3748 | ||
3749 | if (probe) | |
3750 | return 0; | |
3751 | ||
3752 | bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); | |
3753 | if (!bar) | |
3754 | return -ENOTTY; | |
3755 | ||
3756 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3757 | pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); | |
3758 | ||
3759 | cfg = readl(bar + NVME_REG_CC); | |
3760 | ||
3761 | /* Disable controller if enabled */ | |
3762 | if (cfg & NVME_CC_ENABLE) { | |
3763 | u32 cap = readl(bar + NVME_REG_CAP); | |
3764 | unsigned long timeout; | |
3765 | ||
3766 | /* | |
3767 | * Per nvme_disable_ctrl() skip shutdown notification as it | |
3768 | * could complete commands to the admin queue. We only intend | |
3769 | * to quiesce the device before reset. | |
3770 | */ | |
3771 | cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); | |
3772 | ||
3773 | writel(cfg, bar + NVME_REG_CC); | |
3774 | ||
3775 | /* | |
3776 | * Some controllers require an additional delay here, see | |
3777 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet | |
3778 | * supported by this quirk. | |
3779 | */ | |
3780 | ||
3781 | /* Cap register provides max timeout in 500ms increments */ | |
3782 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
3783 | ||
3784 | for (;;) { | |
3785 | u32 status = readl(bar + NVME_REG_CSTS); | |
3786 | ||
3787 | /* Ready status becomes zero on disable complete */ | |
3788 | if (!(status & NVME_CSTS_RDY)) | |
3789 | break; | |
3790 | ||
3791 | msleep(100); | |
3792 | ||
3793 | if (time_after(jiffies, timeout)) { | |
3794 | pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); | |
3795 | break; | |
3796 | } | |
3797 | } | |
3798 | } | |
3799 | ||
3800 | pci_iounmap(dev, bar); | |
3801 | ||
3802 | pcie_flr(dev); | |
3803 | ||
3804 | return 0; | |
3805 | } | |
3806 | ||
51ba0945 AW |
3807 | /* |
3808 | * Intel DC P3700 NVMe controller will timeout waiting for ready status | |
3809 | * to change after NVMe enable if the driver starts interacting with the | |
3810 | * device too soon after FLR. A 250ms delay after FLR has heuristically | |
3811 | * proven to produce reliably working results for device assignment cases. | |
3812 | */ | |
3813 | static int delay_250ms_after_flr(struct pci_dev *dev, int probe) | |
3814 | { | |
3815 | if (!pcie_has_flr(dev)) | |
3816 | return -ENOTTY; | |
3817 | ||
3818 | if (probe) | |
3819 | return 0; | |
3820 | ||
3821 | pcie_flr(dev); | |
3822 | ||
3823 | msleep(250); | |
3824 | ||
3825 | return 0; | |
3826 | } | |
3827 | ||
5b889bf2 | 3828 | static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { |
c763e7b5 DC |
3829 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, |
3830 | reset_intel_82599_sfp_virtfn }, | |
df558de1 XH |
3831 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, |
3832 | reset_ivb_igd }, | |
3833 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, | |
3834 | reset_ivb_igd }, | |
ffb08634 | 3835 | { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, |
51ba0945 | 3836 | { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, |
2c6217e0 CL |
3837 | { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, |
3838 | reset_chelsio_generic_dev }, | |
b9c3b266 DC |
3839 | { 0 } |
3840 | }; | |
5b889bf2 | 3841 | |
df558de1 XH |
3842 | /* |
3843 | * These device-specific reset methods are here rather than in a driver | |
3844 | * because when a host assigns a device to a guest VM, the host may need | |
3845 | * to reset the device but probably doesn't have a driver for it. | |
3846 | */ | |
5b889bf2 RW |
3847 | int pci_dev_specific_reset(struct pci_dev *dev, int probe) |
3848 | { | |
df9d1e8a | 3849 | const struct pci_dev_reset_methods *i; |
5b889bf2 RW |
3850 | |
3851 | for (i = pci_dev_reset_methods; i->reset; i++) { | |
3852 | if ((i->vendor == dev->vendor || | |
3853 | i->vendor == (u16)PCI_ANY_ID) && | |
3854 | (i->device == dev->device || | |
3855 | i->device == (u16)PCI_ANY_ID)) | |
3856 | return i->reset(dev, probe); | |
3857 | } | |
3858 | ||
3859 | return -ENOTTY; | |
3860 | } | |
12ea6cad | 3861 | |
ec637fb2 AW |
3862 | static void quirk_dma_func0_alias(struct pci_dev *dev) |
3863 | { | |
f0af9593 BH |
3864 | if (PCI_FUNC(dev->devfn) != 0) |
3865 | pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
ec637fb2 AW |
3866 | } |
3867 | ||
3868 | /* | |
3869 | * https://bugzilla.redhat.com/show_bug.cgi?id=605888 | |
3870 | * | |
3871 | * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. | |
3872 | */ | |
3873 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); | |
3874 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); | |
3875 | ||
cc346a47 AW |
3876 | static void quirk_dma_func1_alias(struct pci_dev *dev) |
3877 | { | |
f0af9593 BH |
3878 | if (PCI_FUNC(dev->devfn) != 1) |
3879 | pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1)); | |
cc346a47 AW |
3880 | } |
3881 | ||
3882 | /* | |
3883 | * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some | |
3884 | * SKUs function 1 is present and is a legacy IDE controller, in other | |
3885 | * SKUs this function is not present, making this a ghost requester. | |
3886 | * https://bugzilla.kernel.org/show_bug.cgi?id=42679 | |
3887 | */ | |
247de694 SA |
3888 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, |
3889 | quirk_dma_func1_alias); | |
cc346a47 AW |
3890 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, |
3891 | quirk_dma_func1_alias); | |
aa008206 AW |
3892 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, |
3893 | quirk_dma_func1_alias); | |
cc346a47 AW |
3894 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ |
3895 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, | |
3896 | quirk_dma_func1_alias); | |
9cde402a AP |
3897 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, |
3898 | quirk_dma_func1_alias); | |
cc346a47 AW |
3899 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ |
3900 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, | |
3901 | quirk_dma_func1_alias); | |
3902 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ | |
3903 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, | |
3904 | quirk_dma_func1_alias); | |
00456b35 AS |
3905 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ |
3906 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, | |
3907 | quirk_dma_func1_alias); | |
7695e73f BH |
3908 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ |
3909 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, | |
3910 | quirk_dma_func1_alias); | |
cc346a47 AW |
3911 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ |
3912 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, | |
3913 | quirk_dma_func1_alias); | |
832e4e1f TVC |
3914 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ |
3915 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, | |
3916 | quirk_dma_func1_alias); | |
cc346a47 AW |
3917 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ |
3918 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, | |
3919 | quirk_dma_func1_alias); | |
c2e0fb96 JC |
3920 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, |
3921 | quirk_dma_func1_alias); | |
1903be82 HG |
3922 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, |
3923 | quirk_dma_func1_alias); | |
cc346a47 AW |
3924 | /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ |
3925 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, | |
3926 | PCI_DEVICE_ID_JMICRON_JMB388_ESD, | |
3927 | quirk_dma_func1_alias); | |
8b9b963e TS |
3928 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ |
3929 | DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ | |
3930 | 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ | |
3931 | quirk_dma_func1_alias); | |
cc346a47 | 3932 | |
d3d2ab43 AW |
3933 | /* |
3934 | * Some devices DMA with the wrong devfn, not just the wrong function. | |
3935 | * quirk_fixed_dma_alias() uses this table to create fixed aliases, where | |
3936 | * the alias is "fixed" and independent of the device devfn. | |
3937 | * | |
3938 | * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O | |
3939 | * processor. To software, this appears as a PCIe-to-PCI/X bridge with a | |
3940 | * single device on the secondary bus. In reality, the single exposed | |
3941 | * device at 0e.0 is the Address Translation Unit (ATU) of the controller | |
3942 | * that provides a bridge to the internal bus of the I/O processor. The | |
3943 | * controller supports private devices, which can be hidden from PCI config | |
3944 | * space. In the case of the Adaptec 3405, a private device at 01.0 | |
3945 | * appears to be the DMA engine, which therefore needs to become a DMA | |
3946 | * alias for the device. | |
3947 | */ | |
3948 | static const struct pci_device_id fixed_dma_alias_tbl[] = { | |
3949 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, | |
3950 | PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ | |
3951 | .driver_data = PCI_DEVFN(1, 0) }, | |
db83f87b AW |
3952 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, |
3953 | PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ | |
3954 | .driver_data = PCI_DEVFN(1, 0) }, | |
d3d2ab43 AW |
3955 | { 0 } |
3956 | }; | |
3957 | ||
3958 | static void quirk_fixed_dma_alias(struct pci_dev *dev) | |
3959 | { | |
3960 | const struct pci_device_id *id; | |
3961 | ||
3962 | id = pci_match_id(fixed_dma_alias_tbl, dev); | |
48c83080 | 3963 | if (id) |
f0af9593 | 3964 | pci_add_dma_alias(dev, id->driver_data); |
d3d2ab43 AW |
3965 | } |
3966 | ||
3967 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); | |
3968 | ||
ebdb51eb AW |
3969 | /* |
3970 | * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in | |
3971 | * using the wrong DMA alias for the device. Some of these devices can be | |
3972 | * used as either forward or reverse bridges, so we need to test whether the | |
3973 | * device is operating in the correct mode. We could probably apply this | |
3974 | * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test | |
3975 | * is for a non-root, non-PCIe bridge where the upstream device is PCIe and | |
3976 | * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. | |
3977 | */ | |
3978 | static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) | |
3979 | { | |
3980 | if (!pci_is_root_bus(pdev->bus) && | |
3981 | pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
3982 | !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && | |
3983 | pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) | |
3984 | pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; | |
3985 | } | |
3986 | /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ | |
3987 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, | |
3988 | quirk_use_pcie_bridge_dma_alias); | |
3989 | /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ | |
3990 | DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); | |
98ca50db AW |
3991 | /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ |
3992 | DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); | |
fce5d57e JW |
3993 | /* ITE 8893 has the same problem as the 8892 */ |
3994 | DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); | |
8ab4abbe AW |
3995 | /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ |
3996 | DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); | |
ebdb51eb | 3997 | |
b1a928cd JL |
3998 | /* |
3999 | * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to | |
4000 | * be added as aliases to the DMA device in order to allow buffer access | |
4001 | * when IOMMU is enabled. Following devfns have to match RIT-LUT table | |
4002 | * programmed in the EEPROM. | |
4003 | */ | |
4004 | static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) | |
4005 | { | |
4006 | pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0)); | |
4007 | pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0)); | |
4008 | pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3)); | |
4009 | } | |
4010 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); | |
4011 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); | |
4012 | ||
45a23293 J |
4013 | /* |
4014 | * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are | |
4015 | * associated not at the root bus, but at a bridge below. This quirk avoids | |
4016 | * generating invalid DMA aliases. | |
4017 | */ | |
4018 | static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) | |
4019 | { | |
4020 | pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; | |
4021 | } | |
4022 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, | |
4023 | quirk_bridge_cavm_thrx2_pcie_root); | |
4024 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, | |
4025 | quirk_bridge_cavm_thrx2_pcie_root); | |
4026 | ||
3657cebd KHC |
4027 | /* |
4028 | * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) | |
4029 | * class code. Fix it. | |
4030 | */ | |
4031 | static void quirk_tw686x_class(struct pci_dev *pdev) | |
4032 | { | |
4033 | u32 class = pdev->class; | |
4034 | ||
4035 | /* Use "Multimedia controller" class */ | |
4036 | pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; | |
7506dc79 | 4037 | pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", |
3657cebd KHC |
4038 | class, pdev->class); |
4039 | } | |
2b4aed1d | 4040 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd | 4041 | quirk_tw686x_class); |
2b4aed1d | 4042 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd | 4043 | quirk_tw686x_class); |
2b4aed1d | 4044 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd | 4045 | quirk_tw686x_class); |
2b4aed1d | 4046 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd KHC |
4047 | quirk_tw686x_class); |
4048 | ||
a99b646a | 4049 | /* |
4050 | * Some devices have problems with Transaction Layer Packets with the Relaxed | |
4051 | * Ordering Attribute set. Such devices should mark themselves and other | |
82e1719c | 4052 | * device drivers should check before sending TLPs with RO set. |
a99b646a | 4053 | */ |
4054 | static void quirk_relaxedordering_disable(struct pci_dev *dev) | |
4055 | { | |
4056 | dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; | |
7506dc79 | 4057 | pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); |
a99b646a | 4058 | } |
4059 | ||
87e09cde | 4060 | /* |
4061 | * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root | |
82e1719c | 4062 | * Complex have a Flow Control Credit issue which can cause performance |
87e09cde | 4063 | * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. |
4064 | */ | |
4065 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, | |
4066 | quirk_relaxedordering_disable); | |
4067 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, | |
4068 | quirk_relaxedordering_disable); | |
4069 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, | |
4070 | quirk_relaxedordering_disable); | |
4071 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, | |
4072 | quirk_relaxedordering_disable); | |
4073 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, | |
4074 | quirk_relaxedordering_disable); | |
4075 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, | |
4076 | quirk_relaxedordering_disable); | |
4077 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, | |
4078 | quirk_relaxedordering_disable); | |
4079 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, | |
4080 | quirk_relaxedordering_disable); | |
4081 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, | |
4082 | quirk_relaxedordering_disable); | |
4083 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, | |
4084 | quirk_relaxedordering_disable); | |
4085 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, | |
4086 | quirk_relaxedordering_disable); | |
4087 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, | |
4088 | quirk_relaxedordering_disable); | |
4089 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, | |
4090 | quirk_relaxedordering_disable); | |
4091 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, | |
4092 | quirk_relaxedordering_disable); | |
4093 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, | |
4094 | quirk_relaxedordering_disable); | |
4095 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, | |
4096 | quirk_relaxedordering_disable); | |
4097 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, | |
4098 | quirk_relaxedordering_disable); | |
4099 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, | |
4100 | quirk_relaxedordering_disable); | |
4101 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, | |
4102 | quirk_relaxedordering_disable); | |
4103 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, | |
4104 | quirk_relaxedordering_disable); | |
4105 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, | |
4106 | quirk_relaxedordering_disable); | |
4107 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, | |
4108 | quirk_relaxedordering_disable); | |
4109 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, | |
4110 | quirk_relaxedordering_disable); | |
4111 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, | |
4112 | quirk_relaxedordering_disable); | |
4113 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, | |
4114 | quirk_relaxedordering_disable); | |
4115 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, | |
4116 | quirk_relaxedordering_disable); | |
4117 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, | |
4118 | quirk_relaxedordering_disable); | |
4119 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, | |
4120 | quirk_relaxedordering_disable); | |
4121 | ||
077fa19c | 4122 | /* |
82e1719c | 4123 | * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex |
077fa19c | 4124 | * where Upstream Transaction Layer Packets with the Relaxed Ordering |
4125 | * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering | |
4126 | * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules | |
4127 | * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 | |
4128 | * November 10, 2010). As a result, on this platform we can't use Relaxed | |
4129 | * Ordering for Upstream TLPs. | |
4130 | */ | |
4131 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, | |
4132 | quirk_relaxedordering_disable); | |
4133 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, | |
4134 | quirk_relaxedordering_disable); | |
4135 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, | |
4136 | quirk_relaxedordering_disable); | |
4137 | ||
c56d4450 HS |
4138 | /* |
4139 | * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same | |
4140 | * values for the Attribute as were supplied in the header of the | |
4141 | * corresponding Request, except as explicitly allowed when IDO is used." | |
4142 | * | |
4143 | * If a non-compliant device generates a completion with a different | |
4144 | * attribute than the request, the receiver may accept it (which itself | |
4145 | * seems non-compliant based on sec 2.3.2), or it may handle it as a | |
4146 | * Malformed TLP or an Unexpected Completion, which will probably lead to a | |
4147 | * device access timeout. | |
4148 | * | |
4149 | * If the non-compliant device generates completions with zero attributes | |
4150 | * (instead of copying the attributes from the request), we can work around | |
4151 | * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in | |
4152 | * upstream devices so they always generate requests with zero attributes. | |
4153 | * | |
4154 | * This affects other devices under the same Root Port, but since these | |
4155 | * attributes are performance hints, there should be no functional problem. | |
4156 | * | |
4157 | * Note that Configuration Space accesses are never supposed to have TLP | |
4158 | * Attributes, so we're safe waiting till after any Configuration Space | |
4159 | * accesses to do the Root Port fixup. | |
4160 | */ | |
4161 | static void quirk_disable_root_port_attributes(struct pci_dev *pdev) | |
4162 | { | |
4163 | struct pci_dev *root_port = pci_find_pcie_root_port(pdev); | |
4164 | ||
4165 | if (!root_port) { | |
7506dc79 | 4166 | pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); |
c56d4450 HS |
4167 | return; |
4168 | } | |
4169 | ||
7506dc79 | 4170 | pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", |
c56d4450 HS |
4171 | dev_name(&pdev->dev)); |
4172 | pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, | |
4173 | PCI_EXP_DEVCTL_RELAX_EN | | |
4174 | PCI_EXP_DEVCTL_NOSNOOP_EN, 0); | |
4175 | } | |
4176 | ||
4177 | /* | |
4178 | * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the | |
4179 | * Completion it generates. | |
4180 | */ | |
4181 | static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) | |
4182 | { | |
4183 | /* | |
4184 | * This mask/compare operation selects for Physical Function 4 on a | |
4185 | * T5. We only need to fix up the Root Port once for any of the | |
4186 | * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely | |
82e1719c | 4187 | * 0x54xx so we use that one. |
c56d4450 HS |
4188 | */ |
4189 | if ((pdev->device & 0xff00) == 0x5400) | |
4190 | quirk_disable_root_port_attributes(pdev); | |
4191 | } | |
4192 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, | |
4193 | quirk_chelsio_T5_disable_root_port_attributes); | |
4194 | ||
15b100df AW |
4195 | /* |
4196 | * AMD has indicated that the devices below do not support peer-to-peer | |
4197 | * in any system where they are found in the southbridge with an AMD | |
4198 | * IOMMU in the system. Multifunction devices that do not support | |
4199 | * peer-to-peer between functions can claim to support a subset of ACS. | |
4200 | * Such devices effectively enable request redirect (RR) and completion | |
4201 | * redirect (CR) since all transactions are redirected to the upstream | |
4202 | * root complex. | |
4203 | * | |
4204 | * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 | |
4205 | * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 | |
4206 | * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 | |
4207 | * | |
4208 | * 1002:4385 SBx00 SMBus Controller | |
4209 | * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller | |
4210 | * 1002:4383 SBx00 Azalia (Intel HDA) | |
4211 | * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller | |
4212 | * 1002:4384 SBx00 PCI to PCI Bridge | |
4213 | * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller | |
3587e625 MR |
4214 | * |
4215 | * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 | |
4216 | * | |
4217 | * 1022:780f [AMD] FCH PCI Bridge | |
4218 | * 1022:7809 [AMD] FCH USB OHCI Controller | |
15b100df AW |
4219 | */ |
4220 | static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) | |
4221 | { | |
4222 | #ifdef CONFIG_ACPI | |
4223 | struct acpi_table_header *header = NULL; | |
4224 | acpi_status status; | |
4225 | ||
4226 | /* Targeting multifunction devices on the SB (appears on root bus) */ | |
4227 | if (!dev->multifunction || !pci_is_root_bus(dev->bus)) | |
4228 | return -ENODEV; | |
4229 | ||
4230 | /* The IVRS table describes the AMD IOMMU */ | |
4231 | status = acpi_get_table("IVRS", 0, &header); | |
4232 | if (ACPI_FAILURE(status)) | |
4233 | return -ENODEV; | |
4234 | ||
4235 | /* Filter out flags not applicable to multifunction */ | |
4236 | acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); | |
4237 | ||
4238 | return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; | |
4239 | #else | |
4240 | return -ENODEV; | |
4241 | #endif | |
4242 | } | |
4243 | ||
f2ddaf8d VL |
4244 | static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) |
4245 | { | |
4246 | /* | |
4247 | * Effectively selects all downstream ports for whole ThunderX 1 | |
4248 | * family by 0xf800 mask (which represents 8 SoCs), while the lower | |
4249 | * bits of device ID are used to indicate which subdevice is used | |
4250 | * within the SoC. | |
4251 | */ | |
4252 | return (pci_is_pcie(dev) && | |
4253 | (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) && | |
4254 | ((dev->device & 0xf800) == 0xa000)); | |
4255 | } | |
4256 | ||
b404bcfb MJ |
4257 | static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) |
4258 | { | |
4259 | /* | |
7f342678 VL |
4260 | * Cavium root ports don't advertise an ACS capability. However, |
4261 | * the RTL internally implements similar protection as if ACS had | |
4262 | * Request Redirection, Completion Redirection, Source Validation, | |
4263 | * and Upstream Forwarding features enabled. Assert that the | |
4264 | * hardware implements and enables equivalent ACS functionality for | |
4265 | * these flags. | |
b404bcfb | 4266 | */ |
7f342678 | 4267 | acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF); |
b404bcfb | 4268 | |
f2ddaf8d | 4269 | if (!pci_quirk_cavium_acs_match(dev)) |
b77d537d MJ |
4270 | return -ENOTTY; |
4271 | ||
b404bcfb MJ |
4272 | return acs_flags ? 0 : 1; |
4273 | } | |
4274 | ||
a0418aa2 FK |
4275 | static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) |
4276 | { | |
4277 | /* | |
82e1719c | 4278 | * X-Gene Root Ports matching this quirk do not allow peer-to-peer |
a0418aa2 FK |
4279 | * transactions with others, allowing masking out these bits as if they |
4280 | * were unimplemented in the ACS capability. | |
4281 | */ | |
4282 | acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
4283 | ||
4284 | return acs_flags ? 0 : 1; | |
4285 | } | |
4286 | ||
d99321b6 AW |
4287 | /* |
4288 | * Many Intel PCH root ports do provide ACS-like features to disable peer | |
4289 | * transactions and validate bus numbers in requests, but do not provide an | |
4290 | * actual PCIe ACS capability. This is the list of device IDs known to fall | |
4291 | * into that category as provided by Intel in Red Hat bugzilla 1037684. | |
4292 | */ | |
4293 | static const u16 pci_quirk_intel_pch_acs_ids[] = { | |
4294 | /* Ibexpeak PCH */ | |
4295 | 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, | |
4296 | 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, | |
4297 | /* Cougarpoint PCH */ | |
4298 | 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, | |
4299 | 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, | |
4300 | /* Pantherpoint PCH */ | |
4301 | 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, | |
4302 | 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, | |
4303 | /* Lynxpoint-H PCH */ | |
4304 | 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, | |
4305 | 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, | |
4306 | /* Lynxpoint-LP PCH */ | |
4307 | 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, | |
4308 | 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, | |
4309 | /* Wildcat PCH */ | |
4310 | 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, | |
4311 | 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, | |
1a30fd0d AW |
4312 | /* Patsburg (X79) PCH */ |
4313 | 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, | |
78e88358 AW |
4314 | /* Wellsburg (X99) PCH */ |
4315 | 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, | |
4316 | 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, | |
dca230d1 AW |
4317 | /* Lynx Point (9 series) PCH */ |
4318 | 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, | |
d99321b6 AW |
4319 | }; |
4320 | ||
4321 | static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) | |
4322 | { | |
4323 | int i; | |
4324 | ||
4325 | /* Filter out a few obvious non-matches first */ | |
4326 | if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) | |
4327 | return false; | |
4328 | ||
4329 | for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) | |
4330 | if (pci_quirk_intel_pch_acs_ids[i] == dev->device) | |
4331 | return true; | |
4332 | ||
4333 | return false; | |
4334 | } | |
4335 | ||
4336 | #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) | |
4337 | ||
4338 | static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) | |
4339 | { | |
4340 | u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? | |
4341 | INTEL_PCH_ACS_FLAGS : 0; | |
4342 | ||
4343 | if (!pci_quirk_intel_pch_acs_match(dev)) | |
4344 | return -ENOTTY; | |
4345 | ||
4346 | return acs_flags & ~flags ? 0 : 1; | |
4347 | } | |
4348 | ||
33be632b SK |
4349 | /* |
4350 | * These QCOM root ports do provide ACS-like features to disable peer | |
4351 | * transactions and validate bus numbers in requests, but do not provide an | |
4352 | * actual PCIe ACS capability. Hardware supports source validation but it | |
4353 | * will report the issue as Completer Abort instead of ACS Violation. | |
4354 | * Hardware doesn't support peer-to-peer and each root port is a root | |
4355 | * complex with unique segment numbers. It is not possible for one root | |
4356 | * port to pass traffic to another root port. All PCIe transactions are | |
4357 | * terminated inside the root port. | |
4358 | */ | |
4359 | static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) | |
4360 | { | |
4361 | u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); | |
4362 | int ret = acs_flags & ~flags ? 0 : 1; | |
4363 | ||
7506dc79 | 4364 | pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret); |
33be632b SK |
4365 | |
4366 | return ret; | |
4367 | } | |
4368 | ||
1bf2bf22 AW |
4369 | /* |
4370 | * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in | |
4371 | * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, | |
4372 | * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and | |
4373 | * control registers whereas the PCIe spec packs them into words (Rev 3.0, | |
4374 | * 7.16 ACS Extended Capability). The bit definitions are correct, but the | |
4375 | * control register is at offset 8 instead of 6 and we should probably use | |
4376 | * dword accesses to them. This applies to the following PCI Device IDs, as | |
4377 | * found in volume 1 of the datasheet[2]: | |
4378 | * | |
4379 | * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} | |
4380 | * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} | |
4381 | * | |
4382 | * N.B. This doesn't fix what lspci shows. | |
4383 | * | |
7184f5b4 AW |
4384 | * The 100 series chipset specification update includes this as errata #23[3]. |
4385 | * | |
4386 | * The 200 series chipset (Union Point) has the same bug according to the | |
4387 | * specification update (Intel 200 Series Chipset Family Platform Controller | |
4388 | * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, | |
4389 | * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this | |
4390 | * chipset include: | |
4391 | * | |
4392 | * 0xa290-0xa29f PCI Express Root port #{0-16} | |
4393 | * 0xa2e7-0xa2ee PCI Express Root port #{17-24} | |
4394 | * | |
e8440f4b AW |
4395 | * Mobile chipsets are also affected, 7th & 8th Generation |
4396 | * Specification update confirms ACS errata 22, status no fix: (7th Generation | |
4397 | * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel | |
4398 | * Processor Family I/O for U Quad Core Platforms Specification Update, | |
4399 | * August 2017, Revision 002, Document#: 334660-002)[6] | |
4400 | * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O | |
4401 | * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U | |
4402 | * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] | |
4403 | * | |
4404 | * 0x9d10-0x9d1b PCI Express Root port #{1-12} | |
4405 | * | |
1bf2bf22 AW |
4406 | * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html |
4407 | * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html | |
7184f5b4 AW |
4408 | * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html |
4409 | * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html | |
4410 | * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html | |
e8440f4b AW |
4411 | * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html |
4412 | * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html | |
1bf2bf22 AW |
4413 | */ |
4414 | static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) | |
4415 | { | |
7184f5b4 AW |
4416 | if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) |
4417 | return false; | |
4418 | ||
4419 | switch (dev->device) { | |
4420 | case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ | |
4421 | case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ | |
e8440f4b | 4422 | case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ |
7184f5b4 AW |
4423 | return true; |
4424 | } | |
4425 | ||
4426 | return false; | |
1bf2bf22 AW |
4427 | } |
4428 | ||
4429 | #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) | |
4430 | ||
4431 | static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) | |
4432 | { | |
4433 | int pos; | |
4434 | u32 cap, ctrl; | |
4435 | ||
4436 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) | |
4437 | return -ENOTTY; | |
4438 | ||
4439 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); | |
4440 | if (!pos) | |
4441 | return -ENOTTY; | |
4442 | ||
4443 | /* see pci_acs_flags_enabled() */ | |
4444 | pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); | |
4445 | acs_flags &= (cap | PCI_ACS_EC); | |
4446 | ||
4447 | pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); | |
4448 | ||
4449 | return acs_flags & ~ctrl ? 0 : 1; | |
4450 | } | |
4451 | ||
100ebb2c | 4452 | static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) |
89b51cb5 AW |
4453 | { |
4454 | /* | |
4455 | * SV, TB, and UF are not relevant to multifunction endpoints. | |
4456 | * | |
100ebb2c AW |
4457 | * Multifunction devices are only required to implement RR, CR, and DT |
4458 | * in their ACS capability if they support peer-to-peer transactions. | |
4459 | * Devices matching this quirk have been verified by the vendor to not | |
4460 | * perform peer-to-peer with other functions, allowing us to mask out | |
4461 | * these bits as if they were unimplemented in the ACS capability. | |
89b51cb5 AW |
4462 | */ |
4463 | acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | | |
4464 | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); | |
4465 | ||
4466 | return acs_flags ? 0 : 1; | |
4467 | } | |
4468 | ||
ad805758 AW |
4469 | static const struct pci_dev_acs_enabled { |
4470 | u16 vendor; | |
4471 | u16 device; | |
4472 | int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); | |
4473 | } pci_dev_acs_enabled[] = { | |
15b100df AW |
4474 | { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, |
4475 | { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, | |
4476 | { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, | |
4477 | { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, | |
4478 | { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, | |
4479 | { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, | |
3587e625 MR |
4480 | { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, |
4481 | { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, | |
100ebb2c AW |
4482 | { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, |
4483 | { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, | |
9fad4012 | 4484 | { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, |
100ebb2c AW |
4485 | { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, |
4486 | { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, | |
4487 | { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, | |
4488 | { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, | |
4489 | { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, | |
4490 | { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, | |
4491 | { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, | |
4492 | { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, | |
4493 | { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, | |
4494 | { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, | |
4495 | { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, | |
4496 | { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, | |
4497 | { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, | |
4498 | { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, | |
4499 | { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, | |
4500 | { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, | |
4501 | { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, | |
4502 | { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, | |
4503 | { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, | |
4504 | { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, | |
d748804f AW |
4505 | /* 82580 */ |
4506 | { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, | |
4507 | { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, | |
4508 | { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, | |
4509 | { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, | |
4510 | { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, | |
4511 | { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, | |
4512 | { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, | |
4513 | /* 82576 */ | |
4514 | { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, | |
4515 | { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, | |
4516 | { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, | |
4517 | { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, | |
4518 | { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, | |
4519 | { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, | |
4520 | { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, | |
4521 | { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, | |
4522 | /* 82575 */ | |
4523 | { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, | |
4524 | { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, | |
4525 | { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, | |
4526 | /* I350 */ | |
4527 | { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, | |
4528 | { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, | |
4529 | { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, | |
4530 | { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, | |
4531 | /* 82571 (Quads omitted due to non-ACS switch) */ | |
4532 | { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, | |
4533 | { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, | |
4534 | { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, | |
4535 | { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, | |
95e16587 AW |
4536 | /* I219 */ |
4537 | { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, | |
4538 | { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, | |
33be632b | 4539 | /* QCOM QDF2xxx root ports */ |
333c8c12 BH |
4540 | { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, |
4541 | { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, | |
01926f6b SY |
4542 | /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ |
4543 | { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, | |
d748804f | 4544 | /* Intel PCH root ports */ |
d99321b6 | 4545 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, |
1bf2bf22 | 4546 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, |
6a3763d1 VV |
4547 | { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ |
4548 | { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ | |
b404bcfb MJ |
4549 | /* Cavium ThunderX */ |
4550 | { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, | |
a0418aa2 FK |
4551 | /* APM X-Gene */ |
4552 | { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, | |
4ef76ad0 FK |
4553 | /* Ampere Computing */ |
4554 | { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, | |
4555 | { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, | |
4556 | { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, | |
4557 | { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, | |
4558 | { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, | |
4559 | { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, | |
4560 | { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, | |
4561 | { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, | |
ad805758 AW |
4562 | { 0 } |
4563 | }; | |
4564 | ||
4565 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) | |
4566 | { | |
4567 | const struct pci_dev_acs_enabled *i; | |
4568 | int ret; | |
4569 | ||
4570 | /* | |
4571 | * Allow devices that do not expose standard PCIe ACS capabilities | |
4572 | * or control to indicate their support here. Multi-function express | |
4573 | * devices which do not allow internal peer-to-peer between functions, | |
4574 | * but do not implement PCIe ACS may wish to return true here. | |
4575 | */ | |
4576 | for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { | |
4577 | if ((i->vendor == dev->vendor || | |
4578 | i->vendor == (u16)PCI_ANY_ID) && | |
4579 | (i->device == dev->device || | |
4580 | i->device == (u16)PCI_ANY_ID)) { | |
4581 | ret = i->acs_enabled(dev, acs_flags); | |
4582 | if (ret >= 0) | |
4583 | return ret; | |
4584 | } | |
4585 | } | |
4586 | ||
4587 | return -ENOTTY; | |
4588 | } | |
2c744244 | 4589 | |
d99321b6 AW |
4590 | /* Config space offset of Root Complex Base Address register */ |
4591 | #define INTEL_LPC_RCBA_REG 0xf0 | |
4592 | /* 31:14 RCBA address */ | |
4593 | #define INTEL_LPC_RCBA_MASK 0xffffc000 | |
4594 | /* RCBA Enable */ | |
4595 | #define INTEL_LPC_RCBA_ENABLE (1 << 0) | |
4596 | ||
4597 | /* Backbone Scratch Pad Register */ | |
4598 | #define INTEL_BSPR_REG 0x1104 | |
4599 | /* Backbone Peer Non-Posted Disable */ | |
4600 | #define INTEL_BSPR_REG_BPNPD (1 << 8) | |
4601 | /* Backbone Peer Posted Disable */ | |
4602 | #define INTEL_BSPR_REG_BPPD (1 << 9) | |
4603 | ||
4604 | /* Upstream Peer Decode Configuration Register */ | |
4605 | #define INTEL_UPDCR_REG 0x1114 | |
4606 | /* 5:0 Peer Decode Enable bits */ | |
4607 | #define INTEL_UPDCR_REG_MASK 0x3f | |
4608 | ||
4609 | static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) | |
4610 | { | |
4611 | u32 rcba, bspr, updcr; | |
4612 | void __iomem *rcba_mem; | |
4613 | ||
4614 | /* | |
4615 | * Read the RCBA register from the LPC (D31:F0). PCH root ports | |
4616 | * are D28:F* and therefore get probed before LPC, thus we can't | |
82e1719c | 4617 | * use pci_get_slot()/pci_read_config_dword() here. |
d99321b6 AW |
4618 | */ |
4619 | pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), | |
4620 | INTEL_LPC_RCBA_REG, &rcba); | |
4621 | if (!(rcba & INTEL_LPC_RCBA_ENABLE)) | |
4622 | return -EINVAL; | |
4623 | ||
4624 | rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, | |
4625 | PAGE_ALIGN(INTEL_UPDCR_REG)); | |
4626 | if (!rcba_mem) | |
4627 | return -ENOMEM; | |
4628 | ||
4629 | /* | |
4630 | * The BSPR can disallow peer cycles, but it's set by soft strap and | |
4631 | * therefore read-only. If both posted and non-posted peer cycles are | |
4632 | * disallowed, we're ok. If either are allowed, then we need to use | |
4633 | * the UPDCR to disable peer decodes for each port. This provides the | |
4634 | * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | |
4635 | */ | |
4636 | bspr = readl(rcba_mem + INTEL_BSPR_REG); | |
4637 | bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; | |
4638 | if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { | |
4639 | updcr = readl(rcba_mem + INTEL_UPDCR_REG); | |
4640 | if (updcr & INTEL_UPDCR_REG_MASK) { | |
7506dc79 | 4641 | pci_info(dev, "Disabling UPDCR peer decodes\n"); |
d99321b6 AW |
4642 | updcr &= ~INTEL_UPDCR_REG_MASK; |
4643 | writel(updcr, rcba_mem + INTEL_UPDCR_REG); | |
4644 | } | |
4645 | } | |
4646 | ||
4647 | iounmap(rcba_mem); | |
4648 | return 0; | |
4649 | } | |
4650 | ||
4651 | /* Miscellaneous Port Configuration register */ | |
4652 | #define INTEL_MPC_REG 0xd8 | |
4653 | /* MPC: Invalid Receive Bus Number Check Enable */ | |
4654 | #define INTEL_MPC_REG_IRBNCE (1 << 26) | |
4655 | ||
4656 | static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) | |
4657 | { | |
4658 | u32 mpc; | |
4659 | ||
4660 | /* | |
4661 | * When enabled, the IRBNCE bit of the MPC register enables the | |
4662 | * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which | |
4663 | * ensures that requester IDs fall within the bus number range | |
4664 | * of the bridge. Enable if not already. | |
4665 | */ | |
4666 | pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); | |
4667 | if (!(mpc & INTEL_MPC_REG_IRBNCE)) { | |
7506dc79 | 4668 | pci_info(dev, "Enabling MPC IRBNCE\n"); |
d99321b6 AW |
4669 | mpc |= INTEL_MPC_REG_IRBNCE; |
4670 | pci_write_config_word(dev, INTEL_MPC_REG, mpc); | |
4671 | } | |
4672 | } | |
4673 | ||
4674 | static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) | |
4675 | { | |
4676 | if (!pci_quirk_intel_pch_acs_match(dev)) | |
4677 | return -ENOTTY; | |
4678 | ||
4679 | if (pci_quirk_enable_intel_lpc_acs(dev)) { | |
7506dc79 | 4680 | pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); |
d99321b6 AW |
4681 | return 0; |
4682 | } | |
4683 | ||
4684 | pci_quirk_enable_intel_rp_mpc_acs(dev); | |
4685 | ||
4686 | dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; | |
4687 | ||
7506dc79 | 4688 | pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); |
d99321b6 AW |
4689 | |
4690 | return 0; | |
4691 | } | |
4692 | ||
1bf2bf22 AW |
4693 | static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) |
4694 | { | |
4695 | int pos; | |
4696 | u32 cap, ctrl; | |
4697 | ||
4698 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) | |
4699 | return -ENOTTY; | |
4700 | ||
4701 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); | |
4702 | if (!pos) | |
4703 | return -ENOTTY; | |
4704 | ||
4705 | pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); | |
4706 | pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); | |
4707 | ||
4708 | ctrl |= (cap & PCI_ACS_SV); | |
4709 | ctrl |= (cap & PCI_ACS_RR); | |
4710 | ctrl |= (cap & PCI_ACS_CR); | |
4711 | ctrl |= (cap & PCI_ACS_UF); | |
4712 | ||
4713 | pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); | |
4714 | ||
7506dc79 | 4715 | pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); |
1bf2bf22 AW |
4716 | |
4717 | return 0; | |
4718 | } | |
4719 | ||
10dbc9fe LG |
4720 | static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) |
4721 | { | |
4722 | int pos; | |
4723 | u32 cap, ctrl; | |
4724 | ||
4725 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) | |
4726 | return -ENOTTY; | |
4727 | ||
4728 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); | |
4729 | if (!pos) | |
4730 | return -ENOTTY; | |
4731 | ||
4732 | pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); | |
4733 | pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); | |
4734 | ||
4735 | ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); | |
4736 | ||
4737 | pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); | |
4738 | ||
4739 | pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); | |
4740 | ||
4741 | return 0; | |
4742 | } | |
4743 | ||
73c47dde | 4744 | static const struct pci_dev_acs_ops { |
2c744244 AW |
4745 | u16 vendor; |
4746 | u16 device; | |
4747 | int (*enable_acs)(struct pci_dev *dev); | |
73c47dde LG |
4748 | int (*disable_acs_redir)(struct pci_dev *dev); |
4749 | } pci_dev_acs_ops[] = { | |
4750 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, | |
4751 | .enable_acs = pci_quirk_enable_intel_pch_acs, | |
4752 | }, | |
4753 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, | |
4754 | .enable_acs = pci_quirk_enable_intel_spt_pch_acs, | |
10dbc9fe | 4755 | .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, |
73c47dde | 4756 | }, |
2c744244 AW |
4757 | }; |
4758 | ||
c1d61c9b | 4759 | int pci_dev_specific_enable_acs(struct pci_dev *dev) |
2c744244 | 4760 | { |
73c47dde | 4761 | const struct pci_dev_acs_ops *p; |
3b269185 | 4762 | int i, ret; |
2c744244 | 4763 | |
73c47dde LG |
4764 | for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { |
4765 | p = &pci_dev_acs_ops[i]; | |
3b269185 LG |
4766 | if ((p->vendor == dev->vendor || |
4767 | p->vendor == (u16)PCI_ANY_ID) && | |
4768 | (p->device == dev->device || | |
73c47dde LG |
4769 | p->device == (u16)PCI_ANY_ID) && |
4770 | p->enable_acs) { | |
3b269185 | 4771 | ret = p->enable_acs(dev); |
2c744244 | 4772 | if (ret >= 0) |
73c47dde LG |
4773 | return ret; |
4774 | } | |
4775 | } | |
2c744244 | 4776 | |
73c47dde LG |
4777 | return -ENOTTY; |
4778 | } | |
4779 | ||
4780 | int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) | |
4781 | { | |
4782 | const struct pci_dev_acs_ops *p; | |
4783 | int i, ret; | |
4784 | ||
4785 | for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { | |
4786 | p = &pci_dev_acs_ops[i]; | |
4787 | if ((p->vendor == dev->vendor || | |
4788 | p->vendor == (u16)PCI_ANY_ID) && | |
4789 | (p->device == dev->device || | |
4790 | p->device == (u16)PCI_ANY_ID) && | |
4791 | p->disable_acs_redir) { | |
4792 | ret = p->disable_acs_redir(dev); | |
2c744244 | 4793 | if (ret >= 0) |
c1d61c9b | 4794 | return ret; |
2c744244 AW |
4795 | } |
4796 | } | |
c1d61c9b AW |
4797 | |
4798 | return -ENOTTY; | |
2c744244 | 4799 | } |
3388a614 TS |
4800 | |
4801 | /* | |
82e1719c | 4802 | * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with |
3388a614 TS |
4803 | * QuickAssist Technology (QAT) is prematurely terminated in hardware. The |
4804 | * Next Capability pointer in the MSI Capability Structure should point to | |
4805 | * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating | |
4806 | * the list. | |
4807 | */ | |
4808 | static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) | |
4809 | { | |
4810 | int pos, i = 0; | |
4811 | u8 next_cap; | |
4812 | u16 reg16, *cap; | |
4813 | struct pci_cap_saved_state *state; | |
4814 | ||
4815 | /* Bail if the hardware bug is fixed */ | |
4816 | if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) | |
4817 | return; | |
4818 | ||
4819 | /* Bail if MSI Capability Structure is not found for some reason */ | |
4820 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); | |
4821 | if (!pos) | |
4822 | return; | |
4823 | ||
4824 | /* | |
4825 | * Bail if Next Capability pointer in the MSI Capability Structure | |
4826 | * is not the expected incorrect 0x00. | |
4827 | */ | |
4828 | pci_read_config_byte(pdev, pos + 1, &next_cap); | |
4829 | if (next_cap) | |
4830 | return; | |
4831 | ||
4832 | /* | |
4833 | * PCIe Capability Structure is expected to be at 0x50 and should | |
4834 | * terminate the list (Next Capability pointer is 0x00). Verify | |
4835 | * Capability Id and Next Capability pointer is as expected. | |
4836 | * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() | |
4837 | * to correctly set kernel data structures which have already been | |
4838 | * set incorrectly due to the hardware bug. | |
4839 | */ | |
4840 | pos = 0x50; | |
4841 | pci_read_config_word(pdev, pos, ®16); | |
4842 | if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { | |
4843 | u32 status; | |
4844 | #ifndef PCI_EXP_SAVE_REGS | |
4845 | #define PCI_EXP_SAVE_REGS 7 | |
4846 | #endif | |
4847 | int size = PCI_EXP_SAVE_REGS * sizeof(u16); | |
4848 | ||
4849 | pdev->pcie_cap = pos; | |
4850 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
4851 | pdev->pcie_flags_reg = reg16; | |
4852 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); | |
4853 | pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; | |
4854 | ||
4855 | pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; | |
4856 | if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != | |
4857 | PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) | |
4858 | pdev->cfg_size = PCI_CFG_SPACE_SIZE; | |
4859 | ||
4860 | if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) | |
4861 | return; | |
4862 | ||
82e1719c | 4863 | /* Save PCIe cap */ |
3388a614 TS |
4864 | state = kzalloc(sizeof(*state) + size, GFP_KERNEL); |
4865 | if (!state) | |
4866 | return; | |
4867 | ||
4868 | state->cap.cap_nr = PCI_CAP_ID_EXP; | |
4869 | state->cap.cap_extended = 0; | |
4870 | state->cap.size = size; | |
4871 | cap = (u16 *)&state->cap.data[0]; | |
4872 | pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); | |
4873 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); | |
4874 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); | |
4875 | pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); | |
4876 | pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); | |
4877 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); | |
4878 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); | |
4879 | hlist_add_head(&state->next, &pdev->saved_cap_space); | |
4880 | } | |
4881 | } | |
4882 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); | |
443b40ba | 4883 | |
82e1719c | 4884 | /* FLR may cause some 82579 devices to hang */ |
f65fd1aa SN |
4885 | static void quirk_intel_no_flr(struct pci_dev *dev) |
4886 | { | |
4887 | dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; | |
4888 | } | |
4889 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); | |
4890 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); | |
62ce94a7 SK |
4891 | |
4892 | static void quirk_no_ext_tags(struct pci_dev *pdev) | |
4893 | { | |
4894 | struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); | |
4895 | ||
4896 | if (!bridge) | |
4897 | return; | |
4898 | ||
4899 | bridge->no_ext_tags = 1; | |
7506dc79 | 4900 | pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); |
62ce94a7 SK |
4901 | |
4902 | pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); | |
4903 | } | |
1b30dfd3 | 4904 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); |
62ce94a7 | 4905 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); |
1b30dfd3 | 4906 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); |
62ce94a7 SK |
4907 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); |
4908 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); | |
1b30dfd3 SK |
4909 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); |
4910 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); | |
cf2d8041 | 4911 | |
9b44b0b0 JR |
4912 | #ifdef CONFIG_PCI_ATS |
4913 | /* | |
4914 | * Some devices have a broken ATS implementation causing IOMMU stalls. | |
4915 | * Don't use ATS for those devices. | |
4916 | */ | |
4917 | static void quirk_no_ats(struct pci_dev *pdev) | |
4918 | { | |
7506dc79 | 4919 | pci_info(pdev, "disabling ATS (broken on this device)\n"); |
9b44b0b0 JR |
4920 | pdev->ats_cap = 0; |
4921 | } | |
4922 | ||
4923 | /* AMD Stoney platform GPU */ | |
4924 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); | |
d28ca864 | 4925 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats); |
9b44b0b0 | 4926 | #endif /* CONFIG_PCI_ATS */ |
06dc4ee5 HZ |
4927 | |
4928 | /* Freescale PCIe doesn't support MSI in RC mode */ | |
4929 | static void quirk_fsl_no_msi(struct pci_dev *pdev) | |
4930 | { | |
4931 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) | |
4932 | pdev->no_msi = 1; | |
4933 | } | |
4934 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); | |
07f4f97d LW |
4935 | |
4936 | /* | |
4937 | * GPUs with integrated HDA controller for streaming audio to attached displays | |
4938 | * need a device link from the HDA controller (consumer) to the GPU (supplier) | |
4939 | * so that the GPU is powered up whenever the HDA controller is accessed. | |
4940 | * The GPU and HDA controller are functions 0 and 1 of the same PCI device. | |
4941 | * The device link stays in place until shutdown (or removal of the PCI device | |
4942 | * if it's hotplugged). Runtime PM is allowed by default on the HDA controller | |
4943 | * to prevent it from permanently keeping the GPU awake. | |
4944 | */ | |
4945 | static void quirk_gpu_hda(struct pci_dev *hda) | |
4946 | { | |
4947 | struct pci_dev *gpu; | |
4948 | ||
4949 | if (PCI_FUNC(hda->devfn) != 1) | |
4950 | return; | |
4951 | ||
4952 | gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus), | |
4953 | hda->bus->number, | |
4954 | PCI_DEVFN(PCI_SLOT(hda->devfn), 0)); | |
4955 | if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) { | |
4956 | pci_dev_put(gpu); | |
4957 | return; | |
4958 | } | |
4959 | ||
4960 | if (!device_link_add(&hda->dev, &gpu->dev, | |
4961 | DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) | |
4962 | pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu)); | |
4963 | ||
4964 | pm_runtime_allow(&hda->dev); | |
4965 | pci_dev_put(gpu); | |
4966 | } | |
4967 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, | |
4968 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); | |
4969 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, | |
4970 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); | |
4971 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, | |
4972 | PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); | |
aa667c64 JP |
4973 | |
4974 | /* | |
4975 | * Some IDT switches incorrectly flag an ACS Source Validation error on | |
4976 | * completions for config read requests even though PCIe r4.0, sec | |
4977 | * 6.12.1.1, says that completions are never affected by ACS Source | |
4978 | * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: | |
4979 | * | |
4980 | * Item #36 - Downstream port applies ACS Source Validation to Completions | |
4981 | * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that | |
4982 | * completions are never affected by ACS Source Validation. However, | |
4983 | * completions received by a downstream port of the PCIe switch from a | |
4984 | * device that has not yet captured a PCIe bus number are incorrectly | |
4985 | * dropped by ACS Source Validation by the switch downstream port. | |
4986 | * | |
4987 | * The workaround suggested by IDT is to issue a config write to the | |
4988 | * downstream device before issuing the first config read. This allows the | |
4989 | * downstream device to capture its bus and device numbers (see PCIe r4.0, | |
4990 | * sec 2.2.9), thus avoiding the ACS error on the completion. | |
4991 | * | |
4992 | * However, we don't know when the device is ready to accept the config | |
4993 | * write, so we do config reads until we receive a non-Config Request Retry | |
4994 | * Status, then do the config write. | |
4995 | * | |
4996 | * To avoid hitting the erratum when doing the config reads, we disable ACS | |
4997 | * SV around this process. | |
4998 | */ | |
4999 | int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) | |
5000 | { | |
5001 | int pos; | |
5002 | u16 ctrl = 0; | |
5003 | bool found; | |
5004 | struct pci_dev *bridge = bus->self; | |
5005 | ||
5006 | pos = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ACS); | |
5007 | ||
5008 | /* Disable ACS SV before initial config reads */ | |
5009 | if (pos) { | |
5010 | pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); | |
5011 | if (ctrl & PCI_ACS_SV) | |
5012 | pci_write_config_word(bridge, pos + PCI_ACS_CTRL, | |
5013 | ctrl & ~PCI_ACS_SV); | |
5014 | } | |
5015 | ||
5016 | found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); | |
5017 | ||
5018 | /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ | |
5019 | if (found) | |
5020 | pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); | |
5021 | ||
5022 | /* Re-enable ACS_SV if it was previously enabled */ | |
5023 | if (ctrl & PCI_ACS_SV) | |
5024 | pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); | |
5025 | ||
5026 | return found; | |
5027 | } | |
e7aaf90f | 5028 | |
ad281ecf DM |
5029 | /* |
5030 | * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between | |
5031 | * NT endpoints via the internal switch fabric. These IDs replace the | |
5032 | * originating requestor ID TLPs which access host memory on peer NTB | |
5033 | * ports. Therefore, all proxy IDs must be aliased to the NTB device | |
5034 | * to permit access when the IOMMU is turned on. | |
5035 | */ | |
5036 | static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) | |
5037 | { | |
5038 | void __iomem *mmio; | |
5039 | struct ntb_info_regs __iomem *mmio_ntb; | |
5040 | struct ntb_ctrl_regs __iomem *mmio_ctrl; | |
ad281ecf DM |
5041 | u64 partition_map; |
5042 | u8 partition; | |
5043 | int pp; | |
5044 | ||
5045 | if (pci_enable_device(pdev)) { | |
5046 | pci_err(pdev, "Cannot enable Switchtec device\n"); | |
5047 | return; | |
5048 | } | |
5049 | ||
5050 | mmio = pci_iomap(pdev, 0, 0); | |
5051 | if (mmio == NULL) { | |
5052 | pci_disable_device(pdev); | |
5053 | pci_err(pdev, "Cannot iomap Switchtec device\n"); | |
5054 | return; | |
5055 | } | |
5056 | ||
5057 | pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); | |
5058 | ||
5059 | mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; | |
5060 | mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; | |
ad281ecf DM |
5061 | |
5062 | partition = ioread8(&mmio_ntb->partition_id); | |
5063 | ||
5064 | partition_map = ioread32(&mmio_ntb->ep_map); | |
5065 | partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; | |
5066 | partition_map &= ~(1ULL << partition); | |
5067 | ||
5068 | for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { | |
5069 | struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; | |
5070 | u32 table_sz = 0; | |
5071 | int te; | |
5072 | ||
5073 | if (!(partition_map & (1ULL << pp))) | |
5074 | continue; | |
5075 | ||
5076 | pci_dbg(pdev, "Processing partition %d\n", pp); | |
5077 | ||
5078 | mmio_peer_ctrl = &mmio_ctrl[pp]; | |
5079 | ||
5080 | table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); | |
5081 | if (!table_sz) { | |
5082 | pci_warn(pdev, "Partition %d table_sz 0\n", pp); | |
5083 | continue; | |
5084 | } | |
5085 | ||
5086 | if (table_sz > 512) { | |
5087 | pci_warn(pdev, | |
5088 | "Invalid Switchtec partition %d table_sz %d\n", | |
5089 | pp, table_sz); | |
5090 | continue; | |
5091 | } | |
5092 | ||
5093 | for (te = 0; te < table_sz; te++) { | |
5094 | u32 rid_entry; | |
5095 | u8 devfn; | |
5096 | ||
5097 | rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); | |
5098 | devfn = (rid_entry >> 1) & 0xFF; | |
5099 | pci_dbg(pdev, | |
5100 | "Aliasing Partition %d Proxy ID %02x.%d\n", | |
5101 | pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
5102 | pci_add_dma_alias(pdev, devfn); | |
5103 | } | |
5104 | } | |
5105 | ||
5106 | pci_iounmap(pdev, mmio); | |
5107 | pci_disable_device(pdev); | |
5108 | } | |
01d5d7fa | 5109 | #define SWITCHTEC_QUIRK(vid) \ |
742bbe1e LG |
5110 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ |
5111 | PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) | |
01d5d7fa LG |
5112 | |
5113 | SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ | |
5114 | SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ | |
5115 | SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ | |
5116 | SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ | |
5117 | SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ | |
5118 | SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ | |
5119 | SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ | |
5120 | SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ | |
5121 | SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ | |
5122 | SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ | |
5123 | SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ | |
5124 | SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ | |
5125 | SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ | |
5126 | SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ | |
5127 | SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ | |
5128 | SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ | |
5129 | SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ | |
5130 | SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ | |
5131 | SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ | |
5132 | SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ | |
5133 | SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ | |
5134 | SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ | |
5135 | SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ | |
5136 | SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ | |
5137 | SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ | |
5138 | SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ | |
5139 | SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ | |
5140 | SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ | |
5141 | SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ | |
5142 | SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ | |
e0547c81 LP |
5143 | |
5144 | /* | |
5145 | * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does | |
5146 | * not always reset the secondary Nvidia GPU between reboots if the system | |
5147 | * is configured to use Hybrid Graphics mode. This results in the GPU | |
5148 | * being left in whatever state it was in during the *previous* boot, which | |
5149 | * causes spurious interrupts from the GPU, which in turn causes us to | |
5150 | * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, | |
5151 | * this also completely breaks nouveau. | |
5152 | * | |
5153 | * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a | |
5154 | * clean state and fixes all these issues. | |
5155 | * | |
5156 | * When the machine is configured in Dedicated display mode, the issue | |
5157 | * doesn't occur. Fortunately the GPU advertises NoReset+ when in this | |
5158 | * mode, so we can detect that and avoid resetting it. | |
5159 | */ | |
5160 | static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) | |
5161 | { | |
5162 | void __iomem *map; | |
5163 | int ret; | |
5164 | ||
5165 | if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || | |
5166 | pdev->subsystem_device != 0x222e || | |
5167 | !pdev->reset_fn) | |
5168 | return; | |
5169 | ||
5170 | if (pci_enable_device_mem(pdev)) | |
5171 | return; | |
5172 | ||
5173 | /* | |
5174 | * Based on nvkm_device_ctor() in | |
5175 | * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | |
5176 | */ | |
5177 | map = pci_iomap(pdev, 0, 0x23000); | |
5178 | if (!map) { | |
5179 | pci_err(pdev, "Can't map MMIO space\n"); | |
5180 | goto out_disable; | |
5181 | } | |
5182 | ||
5183 | /* | |
5184 | * Make sure the GPU looks like it's been POSTed before resetting | |
5185 | * it. | |
5186 | */ | |
5187 | if (ioread32(map + 0x2240c) & 0x2) { | |
5188 | pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); | |
5189 | ret = pci_reset_function(pdev); | |
5190 | if (ret < 0) | |
5191 | pci_err(pdev, "Failed to reset GPU: %d\n", ret); | |
5192 | } | |
5193 | ||
5194 | iounmap(map); | |
5195 | out_disable: | |
5196 | pci_disable_device(pdev); | |
5197 | } | |
5198 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, | |
5199 | PCI_CLASS_DISPLAY_VGA, 8, | |
5200 | quirk_reset_lenovo_thinkpad_p50_nvgpu); |