[linux-2.6-block.git] / drivers / pci / proc.c

/*
 *	Procfs interface for the PCI bus.
 *
 *	Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
 */

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/capability.h>
#include <asm/uaccess.h>
#include <asm/byteorder.h>
#include "pci.h"

static int proc_initialized;	/* = 0 */

static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	return fixed_size_llseek(file, off, whence, dev->cfg_size);
}

static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
				 size_t nbytes, loff_t *ppos)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	unsigned int pos = *ppos;
	unsigned int cnt, size;

	/*
	 * Normal users can read only the standardized portion of the
	 * configuration space as several chips lock up when trying to read
	 * undefined locations (think of Intel PIIX4 as a typical example).
	 */

	if (capable(CAP_SYS_ADMIN))
		size = dev->cfg_size;
	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
		size = 128;
	else
		size = 64;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_WRITE, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		unsigned int val;
		pci_user_read_config_dword(dev, pos, &val);
		__put_user(cpu_to_le32(val), (__le32 __user *) buf);
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	return nbytes;
}

static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
				  size_t nbytes, loff_t *ppos)
{
	struct inode *ino = file_inode(file);
	struct pci_dev *dev = PDE_DATA(ino);
	int pos = *ppos;
	int size = dev->cfg_size;
	int cnt;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_READ, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		__le32 val;
		__get_user(val, (__le32 __user *) buf);
		pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	i_size_write(ino, dev->cfg_size);
	return nbytes;
}

struct pci_filp_private {
	enum pci_mmap_state mmap_state;
	int write_combine;
};

static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
			       unsigned long arg)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
#ifdef HAVE_PCI_MMAP
	struct pci_filp_private *fpriv = file->private_data;
#endif /* HAVE_PCI_MMAP */
	int ret = 0;

	switch (cmd) {
	case PCIIOC_CONTROLLER:
		ret = pci_domain_nr(dev->bus);
		break;

#ifdef HAVE_PCI_MMAP
	case PCIIOC_MMAP_IS_IO:
		fpriv->mmap_state = pci_mmap_io;
		break;

	case PCIIOC_MMAP_IS_MEM:
		fpriv->mmap_state = pci_mmap_mem;
		break;

	case PCIIOC_WRITE_COMBINE:
		if (arg)
			fpriv->write_combine = 1;
		else
			fpriv->write_combine = 0;
		break;

#endif /* HAVE_PCI_MMAP */

	default:
		ret = -EINVAL;
		break;
	}

	return ret;
}

#ifdef HAVE_PCI_MMAP
static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	struct pci_filp_private *fpriv = file->private_data;
	int i, ret, write_combine;

	if (!capable(CAP_SYS_RAWIO))
		return -EPERM;

	/* Make sure the caller is mapping a real resource for this device */
	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
		if (pci_mmap_fits(dev, i, vma,  PCI_MMAP_PROCFS))
			break;
	}

	if (i >= PCI_ROM_RESOURCE)
		return -ENODEV;

	if (fpriv->mmap_state == pci_mmap_mem)
		write_combine = fpriv->write_combine;
	else
		write_combine = 0;
	ret = pci_mmap_page_range(dev, vma,
				  fpriv->mmap_state, write_combine);
	if (ret < 0)
		return ret;

	return 0;
}

static int proc_bus_pci_open(struct inode *inode, struct file *file)
{
	struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);

	if (!fpriv)
		return -ENOMEM;

	fpriv->mmap_state = pci_mmap_io;
	fpriv->write_combine = 0;

	file->private_data = fpriv;

	return 0;
}

static int proc_bus_pci_release(struct inode *inode, struct file *file)
{
	kfree(file->private_data);
	file->private_data = NULL;

	return 0;
}
#endif /* HAVE_PCI_MMAP */

static const struct file_operations proc_bus_pci_operations = {
	.owner		= THIS_MODULE,
	.llseek		= proc_bus_pci_lseek,
	.read		= proc_bus_pci_read,
	.write		= proc_bus_pci_write,
	.unlocked_ioctl	= proc_bus_pci_ioctl,
	.compat_ioctl	= proc_bus_pci_ioctl,
#ifdef HAVE_PCI_MMAP
	.open		= proc_bus_pci_open,
	.release	= proc_bus_pci_release,
	.mmap		= proc_bus_pci_mmap,
#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	.get_unmapped_area = get_pci_unmapped_area,
#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
#endif /* HAVE_PCI_MMAP */
};

/* iterator */
static void *pci_seq_start(struct seq_file *m, loff_t *pos)
{
	struct pci_dev *dev = NULL;
	loff_t n = *pos;

	for_each_pci_dev(dev) {
		if (!n--)
			break;
	}
	return dev;
}

static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
{
	struct pci_dev *dev = v;

	(*pos)++;
	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	return dev;
}

static void pci_seq_stop(struct seq_file *m, void *v)
{
	if (v) {
		struct pci_dev *dev = v;
		pci_dev_put(dev);
	}
}

static int show_device(struct seq_file *m, void *v)
{
	const struct pci_dev *dev = v;
	const struct pci_driver *drv;
	int i;

	if (dev == NULL)
		return 0;

	drv = pci_dev_driver(dev);
	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
			dev->bus->number,
			dev->devfn,
			dev->vendor,
			dev->device,
			dev->irq);

	/* only print standard and ROM resources to preserve compatibility */
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			(unsigned long long)(start |
			(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
	}
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			dev->resource[i].start < dev->resource[i].end ?
			(unsigned long long)(end - start) + 1 : 0);
	}
	seq_putc(m, '\t');
	if (drv)
		seq_printf(m, "%s", drv->name);
	seq_putc(m, '\n');
	return 0;
}

static const struct seq_operations proc_bus_pci_devices_op = {
	.start	= pci_seq_start,
	.next	= pci_seq_next,
	.stop	= pci_seq_stop,
	.show	= show_device
};

static struct proc_dir_entry *proc_bus_pci_dir;

int pci_proc_attach_device(struct pci_dev *dev)
{
	struct pci_bus *bus = dev->bus;
	struct proc_dir_entry *e;
	char name[16];

	if (!proc_initialized)
		return -EACCES;

	if (!bus->procdir) {
		if (pci_proc_domain(bus)) {
			sprintf(name, "%04x:%02x", pci_domain_nr(bus),
					bus->number);
		} else {
			sprintf(name, "%02x", bus->number);
		}
		bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
		if (!bus->procdir)
			return -ENOMEM;
	}

	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
			     &proc_bus_pci_operations, dev);
	if (!e)
		return -ENOMEM;
	proc_set_size(e, dev->cfg_size);
	dev->procent = e;

	return 0;
}

int pci_proc_detach_device(struct pci_dev *dev)
{
	proc_remove(dev->procent);
	dev->procent = NULL;
	return 0;
}

int pci_proc_detach_bus(struct pci_bus *bus)
{
	proc_remove(bus->procdir);
	return 0;
}

static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
{
	return seq_open(file, &proc_bus_pci_devices_op);
}

static const struct file_operations proc_bus_pci_dev_operations = {
	.owner		= THIS_MODULE,
	.open		= proc_bus_pci_dev_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= seq_release,
};

static int __init pci_proc_init(void)
{
	struct pci_dev *dev = NULL;
	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
	proc_create("devices", 0, proc_bus_pci_dir,
		    &proc_bus_pci_dev_operations);
	proc_initialized = 1;
	for_each_pci_dev(dev)
		pci_proc_attach_device(dev);

	return 0;
}
device_initcall(pci_proc_init);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Procfs interface for the PCI bus.
	3	*
	4	* Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#include <linux/init.h>
	8	#include <linux/pci.h>
5a0e3ad6	9	#include <linux/slab.h>
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/proc_fs.h>
	12	#include <linux/seq_file.h>
aa0ac365	13	#include <linux/capability.h>
1da177e4 LT	14	#include <asm/uaccess.h>
1da177e4 LT	15	#include <asm/byteorder.h>
bc56b9e0	16	#include "pci.h"
1da177e4 LT	17
	18	static int proc_initialized; /* = 0 */
	19
3c78bc61	20	static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
1da177e4	21	{
54de90d6 AV	22	struct pci_dev *dev = PDE_DATA(file_inode(file));
54de90d6 AV	23	return fixed_size_llseek(file, off, whence, dev->cfg_size);
1da177e4 LT	24	}
1da177e4 LT	25
3c78bc61 RD	26	static ssize_t proc_bus_pci_read(struct file file, char __user buf,
3c78bc61 RD	27	size_t nbytes, loff_t *ppos)
1da177e4	28	{
d9dda78b	29	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4 LT	30	unsigned int pos = *ppos;
	31	unsigned int cnt, size;
	32
	33	/*
	34	* Normal users can read only the standardized portion of the
	35	* configuration space as several chips lock up when trying to read
	36	* undefined locations (think of Intel PIIX4 as a typical example).
	37	*/
	38
	39	if (capable(CAP_SYS_ADMIN))
d9dda78b	40	size = dev->cfg_size;
1da177e4 LT	41	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
	42	size = 128;
	43	else
	44	size = 64;
	45
	46	if (pos >= size)
	47	return 0;
	48	if (nbytes >= size)
	49	nbytes = size;
	50	if (pos + nbytes > size)
	51	nbytes = size - pos;
	52	cnt = nbytes;
	53
	54	if (!access_ok(VERIFY_WRITE, buf, cnt))
	55	return -EINVAL;
	56
b3c32c4f HY	57	pci_config_pm_runtime_get(dev);
b3c32c4f HY	58
1da177e4 LT	59	if ((pos & 1) && cnt) {
1da177e4 LT	60	unsigned char val;
e04b0ea2	61	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	62	__put_user(val, buf);
	63	buf++;
	64	pos++;
	65	cnt--;
	66	}
	67
	68	if ((pos & 3) && cnt > 2) {
	69	unsigned short val;
e04b0ea2	70	pci_user_read_config_word(dev, pos, &val);
f17a077e	71	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	72	buf += 2;
	73	pos += 2;
	74	cnt -= 2;
	75	}
	76
	77	while (cnt >= 4) {
	78	unsigned int val;
e04b0ea2	79	pci_user_read_config_dword(dev, pos, &val);
f17a077e	80	__put_user(cpu_to_le32(val), (__le32 __user *) buf);
1da177e4 LT	81	buf += 4;
	82	pos += 4;
	83	cnt -= 4;
	84	}
	85
	86	if (cnt >= 2) {
	87	unsigned short val;
e04b0ea2	88	pci_user_read_config_word(dev, pos, &val);
f17a077e	89	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	90	buf += 2;
	91	pos += 2;
	92	cnt -= 2;
	93	}
	94
	95	if (cnt) {
	96	unsigned char val;
e04b0ea2	97	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	98	__put_user(val, buf);
	99	buf++;
	100	pos++;
	101	cnt--;
	102	}
	103
b3c32c4f HY	104	pci_config_pm_runtime_put(dev);
b3c32c4f HY	105
1da177e4 LT	106	*ppos = pos;
	107	return nbytes;
	108	}
	109
3c78bc61 RD	110	static ssize_t proc_bus_pci_write(struct file file, const char __user buf,
3c78bc61 RD	111	size_t nbytes, loff_t *ppos)
1da177e4	112	{
496ad9aa	113	struct inode *ino = file_inode(file);
d9dda78b	114	struct pci_dev *dev = PDE_DATA(ino);
1da177e4	115	int pos = *ppos;
d9dda78b	116	int size = dev->cfg_size;
1da177e4 LT	117	int cnt;
	118
	119	if (pos >= size)
	120	return 0;
	121	if (nbytes >= size)
	122	nbytes = size;
	123	if (pos + nbytes > size)
	124	nbytes = size - pos;
	125	cnt = nbytes;
	126
	127	if (!access_ok(VERIFY_READ, buf, cnt))
	128	return -EINVAL;
	129
b3c32c4f HY	130	pci_config_pm_runtime_get(dev);
b3c32c4f HY	131
1da177e4 LT	132	if ((pos & 1) && cnt) {
	133	unsigned char val;
	134	__get_user(val, buf);
e04b0ea2	135	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	136	buf++;
	137	pos++;
	138	cnt--;
	139	}
	140
	141	if ((pos & 3) && cnt > 2) {
f17a077e HH	142	__le16 val;
f17a077e HH	143	__get_user(val, (__le16 __user *) buf);
e04b0ea2	144	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	145	buf += 2;
	146	pos += 2;
	147	cnt -= 2;
	148	}
	149
	150	while (cnt >= 4) {
f17a077e HH	151	__le32 val;
f17a077e HH	152	__get_user(val, (__le32 __user *) buf);
e04b0ea2	153	pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
1da177e4 LT	154	buf += 4;
	155	pos += 4;
	156	cnt -= 4;
	157	}
	158
	159	if (cnt >= 2) {
f17a077e HH	160	__le16 val;
f17a077e HH	161	__get_user(val, (__le16 __user *) buf);
e04b0ea2	162	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	163	buf += 2;
	164	pos += 2;
	165	cnt -= 2;
	166	}
	167
	168	if (cnt) {
	169	unsigned char val;
	170	__get_user(val, buf);
e04b0ea2	171	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	172	buf++;
	173	pos++;
	174	cnt--;
	175	}
	176
b3c32c4f HY	177	pci_config_pm_runtime_put(dev);
b3c32c4f HY	178
1da177e4	179	*ppos = pos;
d9dda78b	180	i_size_write(ino, dev->cfg_size);
1da177e4 LT	181	return nbytes;
	182	}
	183
	184	struct pci_filp_private {
	185	enum pci_mmap_state mmap_state;
	186	int write_combine;
	187	};
	188
add77184 MS	189	static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
add77184 MS	190	unsigned long arg)
1da177e4	191	{
d9dda78b	192	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4 LT	193	#ifdef HAVE_PCI_MMAP
	194	struct pci_filp_private *fpriv = file->private_data;
	195	#endif /* HAVE_PCI_MMAP */
	196	int ret = 0;
	197
	198	switch (cmd) {
	199	case PCIIOC_CONTROLLER:
	200	ret = pci_domain_nr(dev->bus);
	201	break;
	202
	203	#ifdef HAVE_PCI_MMAP
	204	case PCIIOC_MMAP_IS_IO:
	205	fpriv->mmap_state = pci_mmap_io;
	206	break;
	207
	208	case PCIIOC_MMAP_IS_MEM:
	209	fpriv->mmap_state = pci_mmap_mem;
	210	break;
	211
	212	case PCIIOC_WRITE_COMBINE:
	213	if (arg)
	214	fpriv->write_combine = 1;
	215	else
	216	fpriv->write_combine = 0;
	217	break;
	218
	219	#endif /* HAVE_PCI_MMAP */
	220
	221	default:
	222	ret = -EINVAL;
	223	break;
f7625980	224	}
1da177e4 LT	225
	226	return ret;
	227	}
	228
	229	#ifdef HAVE_PCI_MMAP
	230	static int proc_bus_pci_mmap(struct file file, struct vm_area_struct vma)
	231	{
d9dda78b	232	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4	233	struct pci_filp_private *fpriv = file->private_data;
3a92c319	234	int i, ret, write_combine;
1da177e4 LT	235
	236	if (!capable(CAP_SYS_RAWIO))
	237	return -EPERM;
	238
9eff02e2 JB	239	/* Make sure the caller is mapping a real resource for this device */
9eff02e2 JB	240	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
3b519e4e	241	if (pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
9eff02e2 JB	242	break;
	243	}
	244
	245	if (i >= PCI_ROM_RESOURCE)
	246	return -ENODEV;
	247
3a92c319 BH	248	if (fpriv->mmap_state == pci_mmap_mem)
	249	write_combine = fpriv->write_combine;
	250	else
	251	write_combine = 0;
1da177e4	252	ret = pci_mmap_page_range(dev, vma,
3a92c319	253	fpriv->mmap_state, write_combine);
1da177e4 LT	254	if (ret < 0)
	255	return ret;
	256
	257	return 0;
	258	}
	259
	260	static int proc_bus_pci_open(struct inode inode, struct file file)
	261	{
	262	struct pci_filp_private fpriv = kmalloc(sizeof(fpriv), GFP_KERNEL);
	263
	264	if (!fpriv)
	265	return -ENOMEM;
	266
	267	fpriv->mmap_state = pci_mmap_io;
	268	fpriv->write_combine = 0;
	269
	270	file->private_data = fpriv;
	271
	272	return 0;
	273	}
	274
	275	static int proc_bus_pci_release(struct inode inode, struct file file)
	276	{
	277	kfree(file->private_data);
	278	file->private_data = NULL;
	279
	280	return 0;
	281	}
	282	#endif /* HAVE_PCI_MMAP */
	283
d54b1fdb	284	static const struct file_operations proc_bus_pci_operations = {
c7705f34	285	.owner = THIS_MODULE,
1da177e4 LT	286	.llseek = proc_bus_pci_lseek,
	287	.read = proc_bus_pci_read,
	288	.write = proc_bus_pci_write,
add77184	289	.unlocked_ioctl = proc_bus_pci_ioctl,
991f7395	290	.compat_ioctl = proc_bus_pci_ioctl,
1da177e4 LT	291	#ifdef HAVE_PCI_MMAP
	292	.open = proc_bus_pci_open,
	293	.release = proc_bus_pci_release,
	294	.mmap = proc_bus_pci_mmap,
	295	#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	296	.get_unmapped_area = get_pci_unmapped_area,
	297	#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
	298	#endif /* HAVE_PCI_MMAP */
	299	};
	300
1da177e4 LT	301	/* iterator */
	302	static void pci_seq_start(struct seq_file m, loff_t *pos)
	303	{
	304	struct pci_dev *dev = NULL;
	305	loff_t n = *pos;
	306
	307	for_each_pci_dev(dev) {
	308	if (!n--)
	309	break;
	310	}
	311	return dev;
	312	}
	313
	314	static void pci_seq_next(struct seq_file m, void v, loff_t pos)
	315	{
	316	struct pci_dev *dev = v;
	317
	318	(*pos)++;
	319	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	320	return dev;
	321	}
	322
	323	static void pci_seq_stop(struct seq_file m, void v)
	324	{
	325	if (v) {
	326	struct pci_dev *dev = v;
	327	pci_dev_put(dev);
	328	}
	329	}
	330
	331	static int show_device(struct seq_file m, void v)
	332	{
	333	const struct pci_dev *dev = v;
	334	const struct pci_driver *drv;
	335	int i;
	336
	337	if (dev == NULL)
	338	return 0;
	339
	340	drv = pci_dev_driver(dev);
	341	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
	342	dev->bus->number,
	343	dev->devfn,
	344	dev->vendor,
	345	dev->device,
	346	dev->irq);
fde09c6d YZ	347
	348	/* only print standard and ROM resources to preserve compatibility */
	349	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	350	resource_size_t start, end;
2311b1f2	351	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3 GKH	352	seq_printf(m, "\t%16llx",
	353	(unsigned long long)(start \|
	354	(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
2311b1f2	355	}
fde09c6d	356	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	357	resource_size_t start, end;
2311b1f2	358	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3	359	seq_printf(m, "\t%16llx",
1da177e4	360	dev->resource[i].start < dev->resource[i].end ?
1396a8c3	361	(unsigned long long)(end - start) + 1 : 0);
2311b1f2	362	}
1da177e4 LT	363	seq_putc(m, '\t');
	364	if (drv)
	365	seq_printf(m, "%s", drv->name);
	366	seq_putc(m, '\n');
	367	return 0;
	368	}
	369
02d90fc3	370	static const struct seq_operations proc_bus_pci_devices_op = {
1da177e4 LT	371	.start = pci_seq_start,
	372	.next = pci_seq_next,
	373	.stop = pci_seq_stop,
	374	.show = show_device
	375	};
	376
	377	static struct proc_dir_entry *proc_bus_pci_dir;
	378
	379	int pci_proc_attach_device(struct pci_dev *dev)
	380	{
	381	struct pci_bus *bus = dev->bus;
	382	struct proc_dir_entry *e;
	383	char name[16];
	384
	385	if (!proc_initialized)
	386	return -EACCES;
	387
	388	if (!bus->procdir) {
	389	if (pci_proc_domain(bus)) {
	390	sprintf(name, "%04x:%02x", pci_domain_nr(bus),
	391	bus->number);
	392	} else {
	393	sprintf(name, "%02x", bus->number);
	394	}
	395	bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
	396	if (!bus->procdir)
	397	return -ENOMEM;
	398	}
	399
	400	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
c7705f34 DL	401	e = proc_create_data(name, S_IFREG \| S_IRUGO \| S_IWUSR, bus->procdir,
c7705f34 DL	402	&proc_bus_pci_operations, dev);
1da177e4 LT	403	if (!e)
1da177e4 LT	404	return -ENOMEM;
271a15ea	405	proc_set_size(e, dev->cfg_size);
1da177e4 LT	406	dev->procent = e;
	407
	408	return 0;
	409	}
	410
	411	int pci_proc_detach_device(struct pci_dev *dev)
	412	{
a8ca16ea DH	413	proc_remove(dev->procent);
a8ca16ea DH	414	dev->procent = NULL;
1da177e4 LT	415	return 0;
	416	}
	417
3c78bc61	418	int pci_proc_detach_bus(struct pci_bus *bus)
1da177e4	419	{
a8ca16ea	420	proc_remove(bus->procdir);
1da177e4 LT	421	return 0;
	422	}
	423
1da177e4 LT	424	static int proc_bus_pci_dev_open(struct inode inode, struct file file)
	425	{
	426	return seq_open(file, &proc_bus_pci_devices_op);
	427	}
3c78bc61	428
d54b1fdb	429	static const struct file_operations proc_bus_pci_dev_operations = {
c7705f34	430	.owner = THIS_MODULE,
1da177e4 LT	431	.open = proc_bus_pci_dev_open,
	432	.read = seq_read,
	433	.llseek = seq_lseek,
	434	.release = seq_release,
	435	};
	436
	437	static int __init pci_proc_init(void)
	438	{
1da177e4	439	struct pci_dev *dev = NULL;
9c37066d	440	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
c7705f34 DL	441	proc_create("devices", 0, proc_bus_pci_dir,
c7705f34 DL	442	&proc_bus_pci_dev_operations);
1da177e4	443	proc_initialized = 1;
4e344b1c	444	for_each_pci_dev(dev)
1da177e4	445	pci_proc_attach_device(dev);
4e344b1c	446
1da177e4 LT	447	return 0;
1da177e4 LT	448	}
eaf61142	449	device_initcall(pci_proc_init);