[linux-2.6-block.git] / drivers / pci / proc.c

/*
 *	Procfs interface for the PCI bus.
 *
 *	Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
 */

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/capability.h>
#include <linux/uaccess.h>
#include <asm/byteorder.h>
#include "pci.h"

static int proc_initialized;	/* = 0 */

static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	return fixed_size_llseek(file, off, whence, dev->cfg_size);
}

static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
				 size_t nbytes, loff_t *ppos)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	unsigned int pos = *ppos;
	unsigned int cnt, size;

	/*
	 * Normal users can read only the standardized portion of the
	 * configuration space as several chips lock up when trying to read
	 * undefined locations (think of Intel PIIX4 as a typical example).
	 */

	if (capable(CAP_SYS_ADMIN))
		size = dev->cfg_size;
	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
		size = 128;
	else
		size = 64;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_WRITE, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		unsigned int val;
		pci_user_read_config_dword(dev, pos, &val);
		__put_user(cpu_to_le32(val), (__le32 __user *) buf);
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	return nbytes;
}

static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
				  size_t nbytes, loff_t *ppos)
{
	struct inode *ino = file_inode(file);
	struct pci_dev *dev = PDE_DATA(ino);
	int pos = *ppos;
	int size = dev->cfg_size;
	int cnt;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_READ, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		__le32 val;
		__get_user(val, (__le32 __user *) buf);
		pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	i_size_write(ino, dev->cfg_size);
	return nbytes;
}

struct pci_filp_private {
	enum pci_mmap_state mmap_state;
	int write_combine;
};

static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
			       unsigned long arg)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
#ifdef HAVE_PCI_MMAP
	struct pci_filp_private *fpriv = file->private_data;
#endif /* HAVE_PCI_MMAP */
	int ret = 0;

	switch (cmd) {
	case PCIIOC_CONTROLLER:
		ret = pci_domain_nr(dev->bus);
		break;

#ifdef HAVE_PCI_MMAP
	case PCIIOC_MMAP_IS_IO:
		if (!arch_can_pci_mmap_io())
			return -EINVAL;
		fpriv->mmap_state = pci_mmap_io;
		break;

	case PCIIOC_MMAP_IS_MEM:
		fpriv->mmap_state = pci_mmap_mem;
		break;

	case PCIIOC_WRITE_COMBINE:
		if (arch_can_pci_mmap_wc()) {
			if (arg)
				fpriv->write_combine = 1;
			else
				fpriv->write_combine = 0;
			break;
		}
		/* If arch decided it can't, fall through... */
#endif /* HAVE_PCI_MMAP */
	default:
		ret = -EINVAL;
		break;
	}

	return ret;
}

#ifdef HAVE_PCI_MMAP
static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	struct pci_filp_private *fpriv = file->private_data;
	int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;

	if (!capable(CAP_SYS_RAWIO))
		return -EPERM;

	if (fpriv->mmap_state == pci_mmap_io) {
		if (!arch_can_pci_mmap_io())
			return -EINVAL;
		res_bit = IORESOURCE_IO;
	}

	/* Make sure the caller is mapping a real resource for this device */
	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
		if (dev->resource[i].flags & res_bit &&
		    pci_mmap_fits(dev, i, vma,  PCI_MMAP_PROCFS))
			break;
	}

	if (i >= PCI_ROM_RESOURCE)
		return -ENODEV;

	if (fpriv->mmap_state == pci_mmap_mem &&
	    fpriv->write_combine) {
		if (dev->resource[i].flags & IORESOURCE_PREFETCH)
			write_combine = 1;
		else
			return -EINVAL;
	}
	ret = pci_mmap_page_range(dev, i, vma,
				  fpriv->mmap_state, write_combine);
	if (ret < 0)
		return ret;

	return 0;
}

static int proc_bus_pci_open(struct inode *inode, struct file *file)
{
	struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);

	if (!fpriv)
		return -ENOMEM;

	fpriv->mmap_state = pci_mmap_io;
	fpriv->write_combine = 0;

	file->private_data = fpriv;

	return 0;
}

static int proc_bus_pci_release(struct inode *inode, struct file *file)
{
	kfree(file->private_data);
	file->private_data = NULL;

	return 0;
}
#endif /* HAVE_PCI_MMAP */

static const struct file_operations proc_bus_pci_operations = {
	.owner		= THIS_MODULE,
	.llseek		= proc_bus_pci_lseek,
	.read		= proc_bus_pci_read,
	.write		= proc_bus_pci_write,
	.unlocked_ioctl	= proc_bus_pci_ioctl,
	.compat_ioctl	= proc_bus_pci_ioctl,
#ifdef HAVE_PCI_MMAP
	.open		= proc_bus_pci_open,
	.release	= proc_bus_pci_release,
	.mmap		= proc_bus_pci_mmap,
#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	.get_unmapped_area = get_pci_unmapped_area,
#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
#endif /* HAVE_PCI_MMAP */
};

/* iterator */
static void *pci_seq_start(struct seq_file *m, loff_t *pos)
{
	struct pci_dev *dev = NULL;
	loff_t n = *pos;

	for_each_pci_dev(dev) {
		if (!n--)
			break;
	}
	return dev;
}

static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
{
	struct pci_dev *dev = v;

	(*pos)++;
	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	return dev;
}

static void pci_seq_stop(struct seq_file *m, void *v)
{
	if (v) {
		struct pci_dev *dev = v;
		pci_dev_put(dev);
	}
}

static int show_device(struct seq_file *m, void *v)
{
	const struct pci_dev *dev = v;
	const struct pci_driver *drv;
	int i;

	if (dev == NULL)
		return 0;

	drv = pci_dev_driver(dev);
	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
			dev->bus->number,
			dev->devfn,
			dev->vendor,
			dev->device,
			dev->irq);

	/* only print standard and ROM resources to preserve compatibility */
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			(unsigned long long)(start |
			(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
	}
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			dev->resource[i].start < dev->resource[i].end ?
			(unsigned long long)(end - start) + 1 : 0);
	}
	seq_putc(m, '\t');
	if (drv)
		seq_printf(m, "%s", drv->name);
	seq_putc(m, '\n');
	return 0;
}

static const struct seq_operations proc_bus_pci_devices_op = {
	.start	= pci_seq_start,
	.next	= pci_seq_next,
	.stop	= pci_seq_stop,
	.show	= show_device
};

static struct proc_dir_entry *proc_bus_pci_dir;

int pci_proc_attach_device(struct pci_dev *dev)
{
	struct pci_bus *bus = dev->bus;
	struct proc_dir_entry *e;
	char name[16];

	if (!proc_initialized)
		return -EACCES;

	if (!bus->procdir) {
		if (pci_proc_domain(bus)) {
			sprintf(name, "%04x:%02x", pci_domain_nr(bus),
					bus->number);
		} else {
			sprintf(name, "%02x", bus->number);
		}
		bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
		if (!bus->procdir)
			return -ENOMEM;
	}

	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
			     &proc_bus_pci_operations, dev);
	if (!e)
		return -ENOMEM;
	proc_set_size(e, dev->cfg_size);
	dev->procent = e;

	return 0;
}

int pci_proc_detach_device(struct pci_dev *dev)
{
	proc_remove(dev->procent);
	dev->procent = NULL;
	return 0;
}

int pci_proc_detach_bus(struct pci_bus *bus)
{
	proc_remove(bus->procdir);
	return 0;
}

static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
{
	return seq_open(file, &proc_bus_pci_devices_op);
}

static const struct file_operations proc_bus_pci_dev_operations = {
	.owner		= THIS_MODULE,
	.open		= proc_bus_pci_dev_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= seq_release,
};

static int __init pci_proc_init(void)
{
	struct pci_dev *dev = NULL;
	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
	proc_create("devices", 0, proc_bus_pci_dir,
		    &proc_bus_pci_dev_operations);
	proc_initialized = 1;
	for_each_pci_dev(dev)
		pci_proc_attach_device(dev);

	return 0;
}
device_initcall(pci_proc_init);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Procfs interface for the PCI bus.
	3	*
	4	* Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#include <linux/init.h>
	8	#include <linux/pci.h>
5a0e3ad6	9	#include <linux/slab.h>
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/proc_fs.h>
	12	#include <linux/seq_file.h>
aa0ac365	13	#include <linux/capability.h>
7c0f6ba6	14	#include <linux/uaccess.h>
1da177e4	15	#include <asm/byteorder.h>
bc56b9e0	16	#include "pci.h"
1da177e4 LT	17
	18	static int proc_initialized; /* = 0 */
	19
3c78bc61	20	static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
1da177e4	21	{
54de90d6 AV	22	struct pci_dev *dev = PDE_DATA(file_inode(file));
54de90d6 AV	23	return fixed_size_llseek(file, off, whence, dev->cfg_size);
1da177e4 LT	24	}
1da177e4 LT	25
3c78bc61 RD	26	static ssize_t proc_bus_pci_read(struct file file, char __user buf,
3c78bc61 RD	27	size_t nbytes, loff_t *ppos)
1da177e4	28	{
d9dda78b	29	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4 LT	30	unsigned int pos = *ppos;
	31	unsigned int cnt, size;
	32
	33	/*
	34	* Normal users can read only the standardized portion of the
	35	* configuration space as several chips lock up when trying to read
	36	* undefined locations (think of Intel PIIX4 as a typical example).
	37	*/
	38
	39	if (capable(CAP_SYS_ADMIN))
d9dda78b	40	size = dev->cfg_size;
1da177e4 LT	41	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
	42	size = 128;
	43	else
	44	size = 64;
	45
	46	if (pos >= size)
	47	return 0;
	48	if (nbytes >= size)
	49	nbytes = size;
	50	if (pos + nbytes > size)
	51	nbytes = size - pos;
	52	cnt = nbytes;
	53
	54	if (!access_ok(VERIFY_WRITE, buf, cnt))
	55	return -EINVAL;
	56
b3c32c4f HY	57	pci_config_pm_runtime_get(dev);
b3c32c4f HY	58
1da177e4 LT	59	if ((pos & 1) && cnt) {
1da177e4 LT	60	unsigned char val;
e04b0ea2	61	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	62	__put_user(val, buf);
	63	buf++;
	64	pos++;
	65	cnt--;
	66	}
	67
	68	if ((pos & 3) && cnt > 2) {
	69	unsigned short val;
e04b0ea2	70	pci_user_read_config_word(dev, pos, &val);
f17a077e	71	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	72	buf += 2;
	73	pos += 2;
	74	cnt -= 2;
	75	}
	76
	77	while (cnt >= 4) {
	78	unsigned int val;
e04b0ea2	79	pci_user_read_config_dword(dev, pos, &val);
f17a077e	80	__put_user(cpu_to_le32(val), (__le32 __user *) buf);
1da177e4 LT	81	buf += 4;
	82	pos += 4;
	83	cnt -= 4;
	84	}
	85
	86	if (cnt >= 2) {
	87	unsigned short val;
e04b0ea2	88	pci_user_read_config_word(dev, pos, &val);
f17a077e	89	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	90	buf += 2;
	91	pos += 2;
	92	cnt -= 2;
	93	}
	94
	95	if (cnt) {
	96	unsigned char val;
e04b0ea2	97	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	98	__put_user(val, buf);
	99	buf++;
	100	pos++;
	101	cnt--;
	102	}
	103
b3c32c4f HY	104	pci_config_pm_runtime_put(dev);
b3c32c4f HY	105
1da177e4 LT	106	*ppos = pos;
	107	return nbytes;
	108	}
	109
3c78bc61 RD	110	static ssize_t proc_bus_pci_write(struct file file, const char __user buf,
3c78bc61 RD	111	size_t nbytes, loff_t *ppos)
1da177e4	112	{
496ad9aa	113	struct inode *ino = file_inode(file);
d9dda78b	114	struct pci_dev *dev = PDE_DATA(ino);
1da177e4	115	int pos = *ppos;
d9dda78b	116	int size = dev->cfg_size;
1da177e4 LT	117	int cnt;
	118
	119	if (pos >= size)
	120	return 0;
	121	if (nbytes >= size)
	122	nbytes = size;
	123	if (pos + nbytes > size)
	124	nbytes = size - pos;
	125	cnt = nbytes;
	126
	127	if (!access_ok(VERIFY_READ, buf, cnt))
	128	return -EINVAL;
	129
b3c32c4f HY	130	pci_config_pm_runtime_get(dev);
b3c32c4f HY	131
1da177e4 LT	132	if ((pos & 1) && cnt) {
	133	unsigned char val;
	134	__get_user(val, buf);
e04b0ea2	135	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	136	buf++;
	137	pos++;
	138	cnt--;
	139	}
	140
	141	if ((pos & 3) && cnt > 2) {
f17a077e HH	142	__le16 val;
f17a077e HH	143	__get_user(val, (__le16 __user *) buf);
e04b0ea2	144	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	145	buf += 2;
	146	pos += 2;
	147	cnt -= 2;
	148	}
	149
	150	while (cnt >= 4) {
f17a077e HH	151	__le32 val;
f17a077e HH	152	__get_user(val, (__le32 __user *) buf);
e04b0ea2	153	pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
1da177e4 LT	154	buf += 4;
	155	pos += 4;
	156	cnt -= 4;
	157	}
	158
	159	if (cnt >= 2) {
f17a077e HH	160	__le16 val;
f17a077e HH	161	__get_user(val, (__le16 __user *) buf);
e04b0ea2	162	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	163	buf += 2;
	164	pos += 2;
	165	cnt -= 2;
	166	}
	167
	168	if (cnt) {
	169	unsigned char val;
	170	__get_user(val, buf);
e04b0ea2	171	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	172	buf++;
	173	pos++;
	174	cnt--;
	175	}
	176
b3c32c4f HY	177	pci_config_pm_runtime_put(dev);
b3c32c4f HY	178
1da177e4	179	*ppos = pos;
d9dda78b	180	i_size_write(ino, dev->cfg_size);
1da177e4 LT	181	return nbytes;
	182	}
	183
	184	struct pci_filp_private {
	185	enum pci_mmap_state mmap_state;
	186	int write_combine;
	187	};
	188
add77184 MS	189	static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
add77184 MS	190	unsigned long arg)
1da177e4	191	{
d9dda78b	192	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4 LT	193	#ifdef HAVE_PCI_MMAP
	194	struct pci_filp_private *fpriv = file->private_data;
	195	#endif /* HAVE_PCI_MMAP */
	196	int ret = 0;
	197
	198	switch (cmd) {
	199	case PCIIOC_CONTROLLER:
	200	ret = pci_domain_nr(dev->bus);
	201	break;
	202
	203	#ifdef HAVE_PCI_MMAP
	204	case PCIIOC_MMAP_IS_IO:
e854d8b2 DW	205	if (!arch_can_pci_mmap_io())
e854d8b2 DW	206	return -EINVAL;
1da177e4 LT	207	fpriv->mmap_state = pci_mmap_io;
	208	break;
	209
	210	case PCIIOC_MMAP_IS_MEM:
	211	fpriv->mmap_state = pci_mmap_mem;
	212	break;
	213
	214	case PCIIOC_WRITE_COMBINE:
ae749c7a DW	215	if (arch_can_pci_mmap_wc()) {
	216	if (arg)
	217	fpriv->write_combine = 1;
	218	else
	219	fpriv->write_combine = 0;
	220	break;
	221	}
	222	/* If arch decided it can't, fall through... */
1da177e4	223	#endif /* HAVE_PCI_MMAP */
1da177e4 LT	224	default:
	225	ret = -EINVAL;
	226	break;
f7625980	227	}
1da177e4 LT	228
	229	return ret;
	230	}
	231
	232	#ifdef HAVE_PCI_MMAP
	233	static int proc_bus_pci_mmap(struct file file, struct vm_area_struct vma)
	234	{
d9dda78b	235	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4	236	struct pci_filp_private *fpriv = file->private_data;
e854d8b2	237	int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;
1da177e4 LT	238
	239	if (!capable(CAP_SYS_RAWIO))
	240	return -EPERM;
	241
e854d8b2 DW	242	if (fpriv->mmap_state == pci_mmap_io) {
	243	if (!arch_can_pci_mmap_io())
	244	return -EINVAL;
17caf567	245	res_bit = IORESOURCE_IO;
e854d8b2	246	}
17caf567	247
9eff02e2 JB	248	/* Make sure the caller is mapping a real resource for this device */
9eff02e2 JB	249	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
17caf567 DW	250	if (dev->resource[i].flags & res_bit &&
17caf567 DW	251	pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
9eff02e2 JB	252	break;
	253	}
	254
	255	if (i >= PCI_ROM_RESOURCE)
	256	return -ENODEV;
	257
cef4d023 DW	258	if (fpriv->mmap_state == pci_mmap_mem &&
	259	fpriv->write_combine) {
	260	if (dev->resource[i].flags & IORESOURCE_PREFETCH)
	261	write_combine = 1;
	262	else
	263	return -EINVAL;
	264	}
f66e2258	265	ret = pci_mmap_page_range(dev, i, vma,
3a92c319	266	fpriv->mmap_state, write_combine);
1da177e4 LT	267	if (ret < 0)
	268	return ret;
	269
	270	return 0;
	271	}
	272
	273	static int proc_bus_pci_open(struct inode inode, struct file file)
	274	{
	275	struct pci_filp_private fpriv = kmalloc(sizeof(fpriv), GFP_KERNEL);
	276
	277	if (!fpriv)
	278	return -ENOMEM;
	279
	280	fpriv->mmap_state = pci_mmap_io;
	281	fpriv->write_combine = 0;
	282
	283	file->private_data = fpriv;
	284
	285	return 0;
	286	}
	287
	288	static int proc_bus_pci_release(struct inode inode, struct file file)
	289	{
	290	kfree(file->private_data);
	291	file->private_data = NULL;
	292
	293	return 0;
	294	}
	295	#endif /* HAVE_PCI_MMAP */
	296
d54b1fdb	297	static const struct file_operations proc_bus_pci_operations = {
c7705f34	298	.owner = THIS_MODULE,
1da177e4 LT	299	.llseek = proc_bus_pci_lseek,
	300	.read = proc_bus_pci_read,
	301	.write = proc_bus_pci_write,
add77184	302	.unlocked_ioctl = proc_bus_pci_ioctl,
991f7395	303	.compat_ioctl = proc_bus_pci_ioctl,
1da177e4 LT	304	#ifdef HAVE_PCI_MMAP
	305	.open = proc_bus_pci_open,
	306	.release = proc_bus_pci_release,
	307	.mmap = proc_bus_pci_mmap,
	308	#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	309	.get_unmapped_area = get_pci_unmapped_area,
	310	#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
	311	#endif /* HAVE_PCI_MMAP */
	312	};
	313
1da177e4 LT	314	/* iterator */
	315	static void pci_seq_start(struct seq_file m, loff_t *pos)
	316	{
	317	struct pci_dev *dev = NULL;
	318	loff_t n = *pos;
	319
	320	for_each_pci_dev(dev) {
	321	if (!n--)
	322	break;
	323	}
	324	return dev;
	325	}
	326
	327	static void pci_seq_next(struct seq_file m, void v, loff_t pos)
	328	{
	329	struct pci_dev *dev = v;
	330
	331	(*pos)++;
	332	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	333	return dev;
	334	}
	335
	336	static void pci_seq_stop(struct seq_file m, void v)
	337	{
	338	if (v) {
	339	struct pci_dev *dev = v;
	340	pci_dev_put(dev);
	341	}
	342	}
	343
	344	static int show_device(struct seq_file m, void v)
	345	{
	346	const struct pci_dev *dev = v;
	347	const struct pci_driver *drv;
	348	int i;
	349
	350	if (dev == NULL)
	351	return 0;
	352
	353	drv = pci_dev_driver(dev);
	354	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
	355	dev->bus->number,
	356	dev->devfn,
	357	dev->vendor,
	358	dev->device,
	359	dev->irq);
fde09c6d YZ	360
	361	/* only print standard and ROM resources to preserve compatibility */
	362	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	363	resource_size_t start, end;
2311b1f2	364	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3 GKH	365	seq_printf(m, "\t%16llx",
	366	(unsigned long long)(start \|
	367	(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
2311b1f2	368	}
fde09c6d	369	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	370	resource_size_t start, end;
2311b1f2	371	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3	372	seq_printf(m, "\t%16llx",
1da177e4	373	dev->resource[i].start < dev->resource[i].end ?
1396a8c3	374	(unsigned long long)(end - start) + 1 : 0);
2311b1f2	375	}
1da177e4 LT	376	seq_putc(m, '\t');
	377	if (drv)
	378	seq_printf(m, "%s", drv->name);
	379	seq_putc(m, '\n');
	380	return 0;
	381	}
	382
02d90fc3	383	static const struct seq_operations proc_bus_pci_devices_op = {
1da177e4 LT	384	.start = pci_seq_start,
	385	.next = pci_seq_next,
	386	.stop = pci_seq_stop,
	387	.show = show_device
	388	};
	389
	390	static struct proc_dir_entry *proc_bus_pci_dir;
	391
	392	int pci_proc_attach_device(struct pci_dev *dev)
	393	{
	394	struct pci_bus *bus = dev->bus;
	395	struct proc_dir_entry *e;
	396	char name[16];
	397
	398	if (!proc_initialized)
	399	return -EACCES;
	400
	401	if (!bus->procdir) {
	402	if (pci_proc_domain(bus)) {
	403	sprintf(name, "%04x:%02x", pci_domain_nr(bus),
	404	bus->number);
	405	} else {
	406	sprintf(name, "%02x", bus->number);
	407	}
	408	bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
	409	if (!bus->procdir)
	410	return -ENOMEM;
	411	}
	412
	413	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
c7705f34 DL	414	e = proc_create_data(name, S_IFREG \| S_IRUGO \| S_IWUSR, bus->procdir,
c7705f34 DL	415	&proc_bus_pci_operations, dev);
1da177e4 LT	416	if (!e)
1da177e4 LT	417	return -ENOMEM;
271a15ea	418	proc_set_size(e, dev->cfg_size);
1da177e4 LT	419	dev->procent = e;
	420
	421	return 0;
	422	}
	423
	424	int pci_proc_detach_device(struct pci_dev *dev)
	425	{
a8ca16ea DH	426	proc_remove(dev->procent);
a8ca16ea DH	427	dev->procent = NULL;
1da177e4 LT	428	return 0;
	429	}
	430
3c78bc61	431	int pci_proc_detach_bus(struct pci_bus *bus)
1da177e4	432	{
a8ca16ea	433	proc_remove(bus->procdir);
1da177e4 LT	434	return 0;
	435	}
	436
1da177e4 LT	437	static int proc_bus_pci_dev_open(struct inode inode, struct file file)
	438	{
	439	return seq_open(file, &proc_bus_pci_devices_op);
	440	}
3c78bc61	441
d54b1fdb	442	static const struct file_operations proc_bus_pci_dev_operations = {
c7705f34	443	.owner = THIS_MODULE,
1da177e4 LT	444	.open = proc_bus_pci_dev_open,
	445	.read = seq_read,
	446	.llseek = seq_lseek,
	447	.release = seq_release,
	448	};
	449
	450	static int __init pci_proc_init(void)
	451	{
1da177e4	452	struct pci_dev *dev = NULL;
9c37066d	453	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
c7705f34 DL	454	proc_create("devices", 0, proc_bus_pci_dir,
c7705f34 DL	455	&proc_bus_pci_dev_operations);
1da177e4	456	proc_initialized = 1;
4e344b1c	457	for_each_pci_dev(dev)
1da177e4	458	pci_proc_attach_device(dev);
4e344b1c	459
1da177e4 LT	460	return 0;
1da177e4 LT	461	}
eaf61142	462	device_initcall(pci_proc_init);