Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
50230713 | 9 | #include <linux/of_device.h> |
de335bb4 | 10 | #include <linux/of_pci.h> |
589fcc23 | 11 | #include <linux/pci_hotplug.h> |
1da177e4 LT |
12 | #include <linux/slab.h> |
13 | #include <linux/module.h> | |
14 | #include <linux/cpumask.h> | |
7d715a6c | 15 | #include <linux/pci-aspm.h> |
b07461a8 | 16 | #include <linux/aer.h> |
29dbe1f0 | 17 | #include <linux/acpi.h> |
788858eb | 18 | #include <linux/irqdomain.h> |
d963f651 | 19 | #include <linux/pm_runtime.h> |
bc56b9e0 | 20 | #include "pci.h" |
1da177e4 LT |
21 | |
22 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
23 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 | 24 | |
0b950f0f | 25 | static struct resource busn_resource = { |
67cdc827 YL |
26 | .name = "PCI busn", |
27 | .start = 0, | |
28 | .end = 255, | |
29 | .flags = IORESOURCE_BUS, | |
30 | }; | |
31 | ||
1da177e4 LT |
32 | /* Ugh. Need to stop exporting this to modules. */ |
33 | LIST_HEAD(pci_root_buses); | |
34 | EXPORT_SYMBOL(pci_root_buses); | |
35 | ||
5cc62c20 YL |
36 | static LIST_HEAD(pci_domain_busn_res_list); |
37 | ||
38 | struct pci_domain_busn_res { | |
39 | struct list_head list; | |
40 | struct resource res; | |
41 | int domain_nr; | |
42 | }; | |
43 | ||
44 | static struct resource *get_pci_domain_busn_res(int domain_nr) | |
45 | { | |
46 | struct pci_domain_busn_res *r; | |
47 | ||
48 | list_for_each_entry(r, &pci_domain_busn_res_list, list) | |
49 | if (r->domain_nr == domain_nr) | |
50 | return &r->res; | |
51 | ||
52 | r = kzalloc(sizeof(*r), GFP_KERNEL); | |
53 | if (!r) | |
54 | return NULL; | |
55 | ||
56 | r->domain_nr = domain_nr; | |
57 | r->res.start = 0; | |
58 | r->res.end = 0xff; | |
59 | r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; | |
60 | ||
61 | list_add_tail(&r->list, &pci_domain_busn_res_list); | |
62 | ||
63 | return &r->res; | |
64 | } | |
65 | ||
70308923 GKH |
66 | static int find_anything(struct device *dev, void *data) |
67 | { | |
68 | return 1; | |
69 | } | |
1da177e4 | 70 | |
ed4aaadb ZY |
71 | /* |
72 | * Some device drivers need know if pci is initiated. | |
73 | * Basically, we think pci is not initiated when there | |
70308923 | 74 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
75 | */ |
76 | int no_pci_devices(void) | |
77 | { | |
70308923 GKH |
78 | struct device *dev; |
79 | int no_devices; | |
ed4aaadb | 80 | |
70308923 GKH |
81 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
82 | no_devices = (dev == NULL); | |
83 | put_device(dev); | |
84 | return no_devices; | |
85 | } | |
ed4aaadb ZY |
86 | EXPORT_SYMBOL(no_pci_devices); |
87 | ||
1da177e4 LT |
88 | /* |
89 | * PCI Bus Class | |
90 | */ | |
fd7d1ced | 91 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 92 | { |
fd7d1ced | 93 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 | 94 | |
ff0387c3 | 95 | put_device(pci_bus->bridge); |
2fe2abf8 | 96 | pci_bus_remove_resources(pci_bus); |
98d9f30c | 97 | pci_release_bus_of_node(pci_bus); |
1da177e4 LT |
98 | kfree(pci_bus); |
99 | } | |
100 | ||
101 | static struct class pcibus_class = { | |
102 | .name = "pci_bus", | |
fd7d1ced | 103 | .dev_release = &release_pcibus_dev, |
56039e65 | 104 | .dev_groups = pcibus_groups, |
1da177e4 LT |
105 | }; |
106 | ||
107 | static int __init pcibus_class_init(void) | |
108 | { | |
109 | return class_register(&pcibus_class); | |
110 | } | |
111 | postcore_initcall(pcibus_class_init); | |
112 | ||
6ac665c6 | 113 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 114 | { |
6ac665c6 | 115 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
116 | if (!size) |
117 | return 0; | |
118 | ||
119 | /* Get the lowest of them to find the decode size, and | |
120 | from that the extent. */ | |
121 | size = (size & ~(size-1)) - 1; | |
122 | ||
123 | /* base == maxbase can be valid only if the BAR has | |
124 | already been programmed with all 1s. */ | |
125 | if (base == maxbase && ((base | size) & mask) != mask) | |
126 | return 0; | |
127 | ||
128 | return size; | |
129 | } | |
130 | ||
28c6821a | 131 | static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) |
6ac665c6 | 132 | { |
8d6a6a47 | 133 | u32 mem_type; |
28c6821a | 134 | unsigned long flags; |
8d6a6a47 | 135 | |
6ac665c6 | 136 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
28c6821a BH |
137 | flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
138 | flags |= IORESOURCE_IO; | |
139 | return flags; | |
6ac665c6 | 140 | } |
07eddf3d | 141 | |
28c6821a BH |
142 | flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
143 | flags |= IORESOURCE_MEM; | |
144 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
145 | flags |= IORESOURCE_PREFETCH; | |
07eddf3d | 146 | |
8d6a6a47 BH |
147 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
148 | switch (mem_type) { | |
149 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
150 | break; | |
151 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
0ff9514b | 152 | /* 1M mem BAR treated as 32-bit BAR */ |
8d6a6a47 BH |
153 | break; |
154 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
28c6821a BH |
155 | flags |= IORESOURCE_MEM_64; |
156 | break; | |
8d6a6a47 | 157 | default: |
0ff9514b | 158 | /* mem unknown type treated as 32-bit BAR */ |
8d6a6a47 BH |
159 | break; |
160 | } | |
28c6821a | 161 | return flags; |
07eddf3d YL |
162 | } |
163 | ||
808e34e2 ZK |
164 | #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) |
165 | ||
0b400c7e YZ |
166 | /** |
167 | * pci_read_base - read a PCI BAR | |
168 | * @dev: the PCI device | |
169 | * @type: type of the BAR | |
170 | * @res: resource buffer to be filled in | |
171 | * @pos: BAR position in the config space | |
172 | * | |
173 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 174 | */ |
0b400c7e | 175 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
3c78bc61 | 176 | struct resource *res, unsigned int pos) |
07eddf3d | 177 | { |
dc5205ef | 178 | u32 l = 0, sz = 0, mask; |
23b13bc7 | 179 | u64 l64, sz64, mask64; |
253d2e54 | 180 | u16 orig_cmd; |
cf4d1cf5 | 181 | struct pci_bus_region region, inverted_region; |
6ac665c6 | 182 | |
1ed67439 | 183 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
6ac665c6 | 184 | |
0ff9514b | 185 | /* No printks while decoding is disabled! */ |
253d2e54 JP |
186 | if (!dev->mmio_always_on) { |
187 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); | |
808e34e2 ZK |
188 | if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { |
189 | pci_write_config_word(dev, PCI_COMMAND, | |
190 | orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); | |
191 | } | |
253d2e54 JP |
192 | } |
193 | ||
6ac665c6 MW |
194 | res->name = pci_name(dev); |
195 | ||
196 | pci_read_config_dword(dev, pos, &l); | |
1ed67439 | 197 | pci_write_config_dword(dev, pos, l | mask); |
6ac665c6 MW |
198 | pci_read_config_dword(dev, pos, &sz); |
199 | pci_write_config_dword(dev, pos, l); | |
200 | ||
201 | /* | |
202 | * All bits set in sz means the device isn't working properly. | |
45aa23b4 BH |
203 | * If the BAR isn't implemented, all bits must be 0. If it's a |
204 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
205 | * 1 must be clear. | |
6ac665c6 | 206 | */ |
f795d86a MS |
207 | if (sz == 0xffffffff) |
208 | sz = 0; | |
6ac665c6 MW |
209 | |
210 | /* | |
211 | * I don't know how l can have all bits set. Copied from old code. | |
212 | * Maybe it fixes a bug on some ancient platform. | |
213 | */ | |
214 | if (l == 0xffffffff) | |
215 | l = 0; | |
216 | ||
217 | if (type == pci_bar_unknown) { | |
28c6821a BH |
218 | res->flags = decode_bar(dev, l); |
219 | res->flags |= IORESOURCE_SIZEALIGN; | |
220 | if (res->flags & IORESOURCE_IO) { | |
f795d86a MS |
221 | l64 = l & PCI_BASE_ADDRESS_IO_MASK; |
222 | sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; | |
223 | mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; | |
6ac665c6 | 224 | } else { |
f795d86a MS |
225 | l64 = l & PCI_BASE_ADDRESS_MEM_MASK; |
226 | sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; | |
227 | mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
6ac665c6 MW |
228 | } |
229 | } else { | |
7a6d312b BH |
230 | if (l & PCI_ROM_ADDRESS_ENABLE) |
231 | res->flags |= IORESOURCE_ROM_ENABLE; | |
f795d86a MS |
232 | l64 = l & PCI_ROM_ADDRESS_MASK; |
233 | sz64 = sz & PCI_ROM_ADDRESS_MASK; | |
76dc5268 | 234 | mask64 = PCI_ROM_ADDRESS_MASK; |
6ac665c6 MW |
235 | } |
236 | ||
28c6821a | 237 | if (res->flags & IORESOURCE_MEM_64) { |
6ac665c6 MW |
238 | pci_read_config_dword(dev, pos + 4, &l); |
239 | pci_write_config_dword(dev, pos + 4, ~0); | |
240 | pci_read_config_dword(dev, pos + 4, &sz); | |
241 | pci_write_config_dword(dev, pos + 4, l); | |
242 | ||
243 | l64 |= ((u64)l << 32); | |
244 | sz64 |= ((u64)sz << 32); | |
f795d86a MS |
245 | mask64 |= ((u64)~0 << 32); |
246 | } | |
6ac665c6 | 247 | |
f795d86a MS |
248 | if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) |
249 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); | |
6ac665c6 | 250 | |
f795d86a MS |
251 | if (!sz64) |
252 | goto fail; | |
6ac665c6 | 253 | |
f795d86a | 254 | sz64 = pci_size(l64, sz64, mask64); |
7e79c5f8 MS |
255 | if (!sz64) { |
256 | dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", | |
257 | pos); | |
f795d86a | 258 | goto fail; |
7e79c5f8 | 259 | } |
f795d86a MS |
260 | |
261 | if (res->flags & IORESOURCE_MEM_64) { | |
3a9ad0b4 YL |
262 | if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) |
263 | && sz64 > 0x100000000ULL) { | |
23b13bc7 BH |
264 | res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; |
265 | res->start = 0; | |
266 | res->end = 0; | |
f795d86a MS |
267 | dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", |
268 | pos, (unsigned long long)sz64); | |
23b13bc7 | 269 | goto out; |
c7dabef8 BH |
270 | } |
271 | ||
3a9ad0b4 | 272 | if ((sizeof(pci_bus_addr_t) < 8) && l) { |
31e9dd25 | 273 | /* Above 32-bit boundary; try to reallocate */ |
c83bd900 | 274 | res->flags |= IORESOURCE_UNSET; |
72dc5601 BH |
275 | res->start = 0; |
276 | res->end = sz64; | |
f795d86a MS |
277 | dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", |
278 | pos, (unsigned long long)l64); | |
72dc5601 | 279 | goto out; |
6ac665c6 | 280 | } |
6ac665c6 MW |
281 | } |
282 | ||
f795d86a MS |
283 | region.start = l64; |
284 | region.end = l64 + sz64; | |
285 | ||
fc279850 YL |
286 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
287 | pcibios_resource_to_bus(dev->bus, &inverted_region, res); | |
cf4d1cf5 KH |
288 | |
289 | /* | |
290 | * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is | |
291 | * the corresponding resource address (the physical address used by | |
292 | * the CPU. Converting that resource address back to a bus address | |
293 | * should yield the original BAR value: | |
294 | * | |
295 | * resource_to_bus(bus_to_resource(A)) == A | |
296 | * | |
297 | * If it doesn't, CPU accesses to "bus_to_resource(A)" will not | |
298 | * be claimed by the device. | |
299 | */ | |
300 | if (inverted_region.start != region.start) { | |
cf4d1cf5 | 301 | res->flags |= IORESOURCE_UNSET; |
cf4d1cf5 | 302 | res->start = 0; |
26370fc6 | 303 | res->end = region.end - region.start; |
f795d86a MS |
304 | dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n", |
305 | pos, (unsigned long long)region.start); | |
cf4d1cf5 | 306 | } |
96ddef25 | 307 | |
0ff9514b BH |
308 | goto out; |
309 | ||
310 | ||
311 | fail: | |
312 | res->flags = 0; | |
313 | out: | |
31e9dd25 | 314 | if (res->flags) |
33963e30 | 315 | dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res); |
0ff9514b | 316 | |
28c6821a | 317 | return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; |
07eddf3d YL |
318 | } |
319 | ||
1da177e4 LT |
320 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
321 | { | |
6ac665c6 | 322 | unsigned int pos, reg; |
07eddf3d | 323 | |
ad67b437 PB |
324 | if (dev->non_compliant_bars) |
325 | return; | |
326 | ||
6ac665c6 MW |
327 | for (pos = 0; pos < howmany; pos++) { |
328 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 329 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 330 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 331 | } |
6ac665c6 | 332 | |
1da177e4 | 333 | if (rom) { |
6ac665c6 | 334 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 335 | dev->rom_base_reg = rom; |
6ac665c6 | 336 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
92b19ff5 | 337 | IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; |
6ac665c6 | 338 | __pci_read_base(dev, pci_bar_mem32, res, rom); |
1da177e4 LT |
339 | } |
340 | } | |
341 | ||
15856ad5 | 342 | static void pci_read_bridge_io(struct pci_bus *child) |
1da177e4 LT |
343 | { |
344 | struct pci_dev *dev = child->self; | |
345 | u8 io_base_lo, io_limit_lo; | |
2b28ae19 | 346 | unsigned long io_mask, io_granularity, base, limit; |
5bfa14ed | 347 | struct pci_bus_region region; |
2b28ae19 BH |
348 | struct resource *res; |
349 | ||
350 | io_mask = PCI_IO_RANGE_MASK; | |
351 | io_granularity = 0x1000; | |
352 | if (dev->io_window_1k) { | |
353 | /* Support 1K I/O space granularity */ | |
354 | io_mask = PCI_IO_1K_RANGE_MASK; | |
355 | io_granularity = 0x400; | |
356 | } | |
1da177e4 | 357 | |
1da177e4 LT |
358 | res = child->resource[0]; |
359 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
360 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
2b28ae19 BH |
361 | base = (io_base_lo & io_mask) << 8; |
362 | limit = (io_limit_lo & io_mask) << 8; | |
1da177e4 LT |
363 | |
364 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
365 | u16 io_base_hi, io_limit_hi; | |
8f38eaca | 366 | |
1da177e4 LT |
367 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); |
368 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
8f38eaca BH |
369 | base |= ((unsigned long) io_base_hi << 16); |
370 | limit |= ((unsigned long) io_limit_hi << 16); | |
1da177e4 LT |
371 | } |
372 | ||
5dde383e | 373 | if (base <= limit) { |
1da177e4 | 374 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
5bfa14ed | 375 | region.start = base; |
2b28ae19 | 376 | region.end = limit + io_granularity - 1; |
fc279850 | 377 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
c7dabef8 | 378 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 | 379 | } |
fa27b2d1 BH |
380 | } |
381 | ||
15856ad5 | 382 | static void pci_read_bridge_mmio(struct pci_bus *child) |
fa27b2d1 BH |
383 | { |
384 | struct pci_dev *dev = child->self; | |
385 | u16 mem_base_lo, mem_limit_lo; | |
386 | unsigned long base, limit; | |
5bfa14ed | 387 | struct pci_bus_region region; |
fa27b2d1 | 388 | struct resource *res; |
1da177e4 LT |
389 | |
390 | res = child->resource[1]; | |
391 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
392 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
8f38eaca BH |
393 | base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; |
394 | limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
5dde383e | 395 | if (base <= limit) { |
1da177e4 | 396 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
5bfa14ed BH |
397 | region.start = base; |
398 | region.end = limit + 0xfffff; | |
fc279850 | 399 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
c7dabef8 | 400 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 | 401 | } |
fa27b2d1 BH |
402 | } |
403 | ||
15856ad5 | 404 | static void pci_read_bridge_mmio_pref(struct pci_bus *child) |
fa27b2d1 BH |
405 | { |
406 | struct pci_dev *dev = child->self; | |
407 | u16 mem_base_lo, mem_limit_lo; | |
7fc986d8 | 408 | u64 base64, limit64; |
3a9ad0b4 | 409 | pci_bus_addr_t base, limit; |
5bfa14ed | 410 | struct pci_bus_region region; |
fa27b2d1 | 411 | struct resource *res; |
1da177e4 LT |
412 | |
413 | res = child->resource[2]; | |
414 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
415 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
7fc986d8 YL |
416 | base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; |
417 | limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
1da177e4 LT |
418 | |
419 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
420 | u32 mem_base_hi, mem_limit_hi; | |
8f38eaca | 421 | |
1da177e4 LT |
422 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); |
423 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
424 | ||
425 | /* | |
426 | * Some bridges set the base > limit by default, and some | |
427 | * (broken) BIOSes do not initialize them. If we find | |
428 | * this, just assume they are not being used. | |
429 | */ | |
430 | if (mem_base_hi <= mem_limit_hi) { | |
7fc986d8 YL |
431 | base64 |= (u64) mem_base_hi << 32; |
432 | limit64 |= (u64) mem_limit_hi << 32; | |
1da177e4 LT |
433 | } |
434 | } | |
7fc986d8 | 435 | |
3a9ad0b4 YL |
436 | base = (pci_bus_addr_t) base64; |
437 | limit = (pci_bus_addr_t) limit64; | |
7fc986d8 YL |
438 | |
439 | if (base != base64) { | |
440 | dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", | |
441 | (unsigned long long) base64); | |
442 | return; | |
443 | } | |
444 | ||
5dde383e | 445 | if (base <= limit) { |
1f82de10 YL |
446 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
447 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
448 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
449 | res->flags |= IORESOURCE_MEM_64; | |
5bfa14ed BH |
450 | region.start = base; |
451 | region.end = limit + 0xfffff; | |
fc279850 | 452 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
c7dabef8 | 453 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 LT |
454 | } |
455 | } | |
456 | ||
15856ad5 | 457 | void pci_read_bridge_bases(struct pci_bus *child) |
fa27b2d1 BH |
458 | { |
459 | struct pci_dev *dev = child->self; | |
2fe2abf8 | 460 | struct resource *res; |
fa27b2d1 BH |
461 | int i; |
462 | ||
463 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ | |
464 | return; | |
465 | ||
b918c62e YL |
466 | dev_info(&dev->dev, "PCI bridge to %pR%s\n", |
467 | &child->busn_res, | |
fa27b2d1 BH |
468 | dev->transparent ? " (subtractive decode)" : ""); |
469 | ||
2fe2abf8 BH |
470 | pci_bus_remove_resources(child); |
471 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
472 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
473 | ||
fa27b2d1 BH |
474 | pci_read_bridge_io(child); |
475 | pci_read_bridge_mmio(child); | |
476 | pci_read_bridge_mmio_pref(child); | |
2adf7516 BH |
477 | |
478 | if (dev->transparent) { | |
2fe2abf8 | 479 | pci_bus_for_each_resource(child->parent, res, i) { |
d739a099 | 480 | if (res && res->flags) { |
2fe2abf8 BH |
481 | pci_bus_add_resource(child, res, |
482 | PCI_SUBTRACTIVE_DECODE); | |
2adf7516 BH |
483 | dev_printk(KERN_DEBUG, &dev->dev, |
484 | " bridge window %pR (subtractive decode)\n", | |
2fe2abf8 BH |
485 | res); |
486 | } | |
2adf7516 BH |
487 | } |
488 | } | |
fa27b2d1 BH |
489 | } |
490 | ||
670ba0c8 | 491 | static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) |
1da177e4 LT |
492 | { |
493 | struct pci_bus *b; | |
494 | ||
f5afe806 | 495 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
05013486 BH |
496 | if (!b) |
497 | return NULL; | |
498 | ||
499 | INIT_LIST_HEAD(&b->node); | |
500 | INIT_LIST_HEAD(&b->children); | |
501 | INIT_LIST_HEAD(&b->devices); | |
502 | INIT_LIST_HEAD(&b->slots); | |
503 | INIT_LIST_HEAD(&b->resources); | |
504 | b->max_bus_speed = PCI_SPEED_UNKNOWN; | |
505 | b->cur_bus_speed = PCI_SPEED_UNKNOWN; | |
670ba0c8 CM |
506 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
507 | if (parent) | |
508 | b->domain_nr = parent->domain_nr; | |
509 | #endif | |
1da177e4 LT |
510 | return b; |
511 | } | |
512 | ||
5c3f18cc | 513 | static void devm_pci_release_host_bridge_dev(struct device *dev) |
70efde2a JL |
514 | { |
515 | struct pci_host_bridge *bridge = to_pci_host_bridge(dev); | |
516 | ||
517 | if (bridge->release_fn) | |
518 | bridge->release_fn(bridge); | |
5c3f18cc | 519 | } |
70efde2a | 520 | |
5c3f18cc LP |
521 | static void pci_release_host_bridge_dev(struct device *dev) |
522 | { | |
523 | devm_pci_release_host_bridge_dev(dev); | |
524 | pci_free_host_bridge(to_pci_host_bridge(dev)); | |
70efde2a JL |
525 | } |
526 | ||
a52d1443 | 527 | struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) |
7b543663 YL |
528 | { |
529 | struct pci_host_bridge *bridge; | |
530 | ||
59094065 | 531 | bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); |
05013486 BH |
532 | if (!bridge) |
533 | return NULL; | |
7b543663 | 534 | |
05013486 | 535 | INIT_LIST_HEAD(&bridge->windows); |
a1c0050a | 536 | bridge->dev.release = pci_release_host_bridge_dev; |
37d6a0a6 | 537 | |
7b543663 YL |
538 | return bridge; |
539 | } | |
a52d1443 | 540 | EXPORT_SYMBOL(pci_alloc_host_bridge); |
7b543663 | 541 | |
5c3f18cc LP |
542 | struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, |
543 | size_t priv) | |
544 | { | |
545 | struct pci_host_bridge *bridge; | |
546 | ||
547 | bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL); | |
548 | if (!bridge) | |
549 | return NULL; | |
550 | ||
551 | INIT_LIST_HEAD(&bridge->windows); | |
552 | bridge->dev.release = devm_pci_release_host_bridge_dev; | |
553 | ||
554 | return bridge; | |
555 | } | |
556 | EXPORT_SYMBOL(devm_pci_alloc_host_bridge); | |
557 | ||
dff79b91 LP |
558 | void pci_free_host_bridge(struct pci_host_bridge *bridge) |
559 | { | |
560 | pci_free_resource_list(&bridge->windows); | |
561 | ||
562 | kfree(bridge); | |
563 | } | |
564 | EXPORT_SYMBOL(pci_free_host_bridge); | |
565 | ||
0b950f0f | 566 | static const unsigned char pcix_bus_speed[] = { |
9be60ca0 MW |
567 | PCI_SPEED_UNKNOWN, /* 0 */ |
568 | PCI_SPEED_66MHz_PCIX, /* 1 */ | |
569 | PCI_SPEED_100MHz_PCIX, /* 2 */ | |
570 | PCI_SPEED_133MHz_PCIX, /* 3 */ | |
571 | PCI_SPEED_UNKNOWN, /* 4 */ | |
572 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ | |
573 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ | |
574 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ | |
575 | PCI_SPEED_UNKNOWN, /* 8 */ | |
576 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ | |
577 | PCI_SPEED_100MHz_PCIX_266, /* A */ | |
578 | PCI_SPEED_133MHz_PCIX_266, /* B */ | |
579 | PCI_SPEED_UNKNOWN, /* C */ | |
580 | PCI_SPEED_66MHz_PCIX_533, /* D */ | |
581 | PCI_SPEED_100MHz_PCIX_533, /* E */ | |
582 | PCI_SPEED_133MHz_PCIX_533 /* F */ | |
583 | }; | |
584 | ||
343e51ae | 585 | const unsigned char pcie_link_speed[] = { |
3749c51a MW |
586 | PCI_SPEED_UNKNOWN, /* 0 */ |
587 | PCIE_SPEED_2_5GT, /* 1 */ | |
588 | PCIE_SPEED_5_0GT, /* 2 */ | |
9dfd97fe | 589 | PCIE_SPEED_8_0GT, /* 3 */ |
3749c51a MW |
590 | PCI_SPEED_UNKNOWN, /* 4 */ |
591 | PCI_SPEED_UNKNOWN, /* 5 */ | |
592 | PCI_SPEED_UNKNOWN, /* 6 */ | |
593 | PCI_SPEED_UNKNOWN, /* 7 */ | |
594 | PCI_SPEED_UNKNOWN, /* 8 */ | |
595 | PCI_SPEED_UNKNOWN, /* 9 */ | |
596 | PCI_SPEED_UNKNOWN, /* A */ | |
597 | PCI_SPEED_UNKNOWN, /* B */ | |
598 | PCI_SPEED_UNKNOWN, /* C */ | |
599 | PCI_SPEED_UNKNOWN, /* D */ | |
600 | PCI_SPEED_UNKNOWN, /* E */ | |
601 | PCI_SPEED_UNKNOWN /* F */ | |
602 | }; | |
603 | ||
604 | void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) | |
605 | { | |
231afea1 | 606 | bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; |
3749c51a MW |
607 | } |
608 | EXPORT_SYMBOL_GPL(pcie_update_link_speed); | |
609 | ||
45b4cdd5 MW |
610 | static unsigned char agp_speeds[] = { |
611 | AGP_UNKNOWN, | |
612 | AGP_1X, | |
613 | AGP_2X, | |
614 | AGP_4X, | |
615 | AGP_8X | |
616 | }; | |
617 | ||
618 | static enum pci_bus_speed agp_speed(int agp3, int agpstat) | |
619 | { | |
620 | int index = 0; | |
621 | ||
622 | if (agpstat & 4) | |
623 | index = 3; | |
624 | else if (agpstat & 2) | |
625 | index = 2; | |
626 | else if (agpstat & 1) | |
627 | index = 1; | |
628 | else | |
629 | goto out; | |
f7625980 | 630 | |
45b4cdd5 MW |
631 | if (agp3) { |
632 | index += 2; | |
633 | if (index == 5) | |
634 | index = 0; | |
635 | } | |
636 | ||
637 | out: | |
638 | return agp_speeds[index]; | |
639 | } | |
640 | ||
9be60ca0 MW |
641 | static void pci_set_bus_speed(struct pci_bus *bus) |
642 | { | |
643 | struct pci_dev *bridge = bus->self; | |
644 | int pos; | |
645 | ||
45b4cdd5 MW |
646 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
647 | if (!pos) | |
648 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); | |
649 | if (pos) { | |
650 | u32 agpstat, agpcmd; | |
651 | ||
652 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); | |
653 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); | |
654 | ||
655 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); | |
656 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); | |
657 | } | |
658 | ||
9be60ca0 MW |
659 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
660 | if (pos) { | |
661 | u16 status; | |
662 | enum pci_bus_speed max; | |
9be60ca0 | 663 | |
7793eeab BH |
664 | pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, |
665 | &status); | |
666 | ||
667 | if (status & PCI_X_SSTATUS_533MHZ) { | |
9be60ca0 | 668 | max = PCI_SPEED_133MHz_PCIX_533; |
7793eeab | 669 | } else if (status & PCI_X_SSTATUS_266MHZ) { |
9be60ca0 | 670 | max = PCI_SPEED_133MHz_PCIX_266; |
7793eeab | 671 | } else if (status & PCI_X_SSTATUS_133MHZ) { |
3c78bc61 | 672 | if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) |
9be60ca0 | 673 | max = PCI_SPEED_133MHz_PCIX_ECC; |
3c78bc61 | 674 | else |
9be60ca0 | 675 | max = PCI_SPEED_133MHz_PCIX; |
9be60ca0 MW |
676 | } else { |
677 | max = PCI_SPEED_66MHz_PCIX; | |
678 | } | |
679 | ||
680 | bus->max_bus_speed = max; | |
7793eeab BH |
681 | bus->cur_bus_speed = pcix_bus_speed[ |
682 | (status & PCI_X_SSTATUS_FREQ) >> 6]; | |
9be60ca0 MW |
683 | |
684 | return; | |
685 | } | |
686 | ||
fdfe1511 | 687 | if (pci_is_pcie(bridge)) { |
9be60ca0 MW |
688 | u32 linkcap; |
689 | u16 linksta; | |
690 | ||
59875ae4 | 691 | pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); |
231afea1 | 692 | bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; |
9be60ca0 | 693 | |
59875ae4 | 694 | pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); |
9be60ca0 MW |
695 | pcie_update_link_speed(bus, linksta); |
696 | } | |
697 | } | |
698 | ||
44aa0c65 MZ |
699 | static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) |
700 | { | |
b165e2b6 MZ |
701 | struct irq_domain *d; |
702 | ||
44aa0c65 MZ |
703 | /* |
704 | * Any firmware interface that can resolve the msi_domain | |
705 | * should be called from here. | |
706 | */ | |
b165e2b6 | 707 | d = pci_host_bridge_of_msi_domain(bus); |
471036b2 SS |
708 | if (!d) |
709 | d = pci_host_bridge_acpi_msi_domain(bus); | |
44aa0c65 | 710 | |
788858eb JO |
711 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
712 | /* | |
713 | * If no IRQ domain was found via the OF tree, try looking it up | |
714 | * directly through the fwnode_handle. | |
715 | */ | |
716 | if (!d) { | |
717 | struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); | |
718 | ||
719 | if (fwnode) | |
720 | d = irq_find_matching_fwnode(fwnode, | |
721 | DOMAIN_BUS_PCI_MSI); | |
722 | } | |
723 | #endif | |
724 | ||
b165e2b6 | 725 | return d; |
44aa0c65 MZ |
726 | } |
727 | ||
728 | static void pci_set_bus_msi_domain(struct pci_bus *bus) | |
729 | { | |
730 | struct irq_domain *d; | |
38ea72bd | 731 | struct pci_bus *b; |
44aa0c65 MZ |
732 | |
733 | /* | |
38ea72bd AW |
734 | * The bus can be a root bus, a subordinate bus, or a virtual bus |
735 | * created by an SR-IOV device. Walk up to the first bridge device | |
736 | * found or derive the domain from the host bridge. | |
44aa0c65 | 737 | */ |
38ea72bd AW |
738 | for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { |
739 | if (b->self) | |
740 | d = dev_get_msi_domain(&b->self->dev); | |
741 | } | |
742 | ||
743 | if (!d) | |
744 | d = pci_host_bridge_msi_domain(b); | |
44aa0c65 MZ |
745 | |
746 | dev_set_msi_domain(&bus->dev, d); | |
747 | } | |
748 | ||
cea9bc0b | 749 | static int pci_register_host_bridge(struct pci_host_bridge *bridge) |
37d6a0a6 AB |
750 | { |
751 | struct device *parent = bridge->dev.parent; | |
752 | struct resource_entry *window, *n; | |
753 | struct pci_bus *bus, *b; | |
754 | resource_size_t offset; | |
755 | LIST_HEAD(resources); | |
756 | struct resource *res; | |
757 | char addr[64], *fmt; | |
758 | const char *name; | |
759 | int err; | |
760 | ||
761 | bus = pci_alloc_bus(NULL); | |
762 | if (!bus) | |
763 | return -ENOMEM; | |
764 | ||
765 | bridge->bus = bus; | |
766 | ||
767 | /* temporarily move resources off the list */ | |
768 | list_splice_init(&bridge->windows, &resources); | |
769 | bus->sysdata = bridge->sysdata; | |
770 | bus->msi = bridge->msi; | |
771 | bus->ops = bridge->ops; | |
772 | bus->number = bus->busn_res.start = bridge->busnr; | |
773 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
774 | bus->domain_nr = pci_bus_find_domain_nr(bus, parent); | |
775 | #endif | |
776 | ||
777 | b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); | |
778 | if (b) { | |
779 | /* If we already got to this bus through a different bridge, ignore it */ | |
780 | dev_dbg(&b->dev, "bus already known\n"); | |
781 | err = -EEXIST; | |
782 | goto free; | |
783 | } | |
784 | ||
785 | dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), | |
786 | bridge->busnr); | |
787 | ||
788 | err = pcibios_root_bridge_prepare(bridge); | |
789 | if (err) | |
790 | goto free; | |
791 | ||
792 | err = device_register(&bridge->dev); | |
793 | if (err) | |
794 | put_device(&bridge->dev); | |
795 | ||
796 | bus->bridge = get_device(&bridge->dev); | |
797 | device_enable_async_suspend(bus->bridge); | |
798 | pci_set_bus_of_node(bus); | |
799 | pci_set_bus_msi_domain(bus); | |
800 | ||
801 | if (!parent) | |
802 | set_dev_node(bus->bridge, pcibus_to_node(bus)); | |
803 | ||
804 | bus->dev.class = &pcibus_class; | |
805 | bus->dev.parent = bus->bridge; | |
806 | ||
807 | dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); | |
808 | name = dev_name(&bus->dev); | |
809 | ||
810 | err = device_register(&bus->dev); | |
811 | if (err) | |
812 | goto unregister; | |
813 | ||
814 | pcibios_add_bus(bus); | |
815 | ||
816 | /* Create legacy_io and legacy_mem files for this bus */ | |
817 | pci_create_legacy_files(bus); | |
818 | ||
819 | if (parent) | |
820 | dev_info(parent, "PCI host bridge to bus %s\n", name); | |
821 | else | |
822 | pr_info("PCI host bridge to bus %s\n", name); | |
823 | ||
824 | /* Add initial resources to the bus */ | |
825 | resource_list_for_each_entry_safe(window, n, &resources) { | |
826 | list_move_tail(&window->node, &bridge->windows); | |
827 | offset = window->offset; | |
828 | res = window->res; | |
829 | ||
830 | if (res->flags & IORESOURCE_BUS) | |
831 | pci_bus_insert_busn_res(bus, bus->number, res->end); | |
832 | else | |
833 | pci_bus_add_resource(bus, res, 0); | |
834 | ||
835 | if (offset) { | |
836 | if (resource_type(res) == IORESOURCE_IO) | |
837 | fmt = " (bus address [%#06llx-%#06llx])"; | |
838 | else | |
839 | fmt = " (bus address [%#010llx-%#010llx])"; | |
840 | ||
841 | snprintf(addr, sizeof(addr), fmt, | |
842 | (unsigned long long)(res->start - offset), | |
843 | (unsigned long long)(res->end - offset)); | |
844 | } else | |
845 | addr[0] = '\0'; | |
846 | ||
847 | dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); | |
848 | } | |
849 | ||
850 | down_write(&pci_bus_sem); | |
851 | list_add_tail(&bus->node, &pci_root_buses); | |
852 | up_write(&pci_bus_sem); | |
853 | ||
854 | return 0; | |
855 | ||
856 | unregister: | |
857 | put_device(&bridge->dev); | |
858 | device_unregister(&bridge->dev); | |
859 | ||
860 | free: | |
861 | kfree(bus); | |
862 | return err; | |
863 | } | |
864 | ||
cbd4e055 AB |
865 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
866 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
867 | { |
868 | struct pci_bus *child; | |
869 | int i; | |
4f535093 | 870 | int ret; |
1da177e4 LT |
871 | |
872 | /* | |
873 | * Allocate a new bus, and inherit stuff from the parent.. | |
874 | */ | |
670ba0c8 | 875 | child = pci_alloc_bus(parent); |
1da177e4 LT |
876 | if (!child) |
877 | return NULL; | |
878 | ||
1da177e4 LT |
879 | child->parent = parent; |
880 | child->ops = parent->ops; | |
0cbdcfcf | 881 | child->msi = parent->msi; |
1da177e4 | 882 | child->sysdata = parent->sysdata; |
6e325a62 | 883 | child->bus_flags = parent->bus_flags; |
1da177e4 | 884 | |
fd7d1ced | 885 | /* initialize some portions of the bus device, but don't register it |
4f535093 | 886 | * now as the parent is not properly set up yet. |
fd7d1ced GKH |
887 | */ |
888 | child->dev.class = &pcibus_class; | |
1a927133 | 889 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 LT |
890 | |
891 | /* | |
892 | * Set up the primary, secondary and subordinate | |
893 | * bus numbers. | |
894 | */ | |
b918c62e YL |
895 | child->number = child->busn_res.start = busnr; |
896 | child->primary = parent->busn_res.start; | |
897 | child->busn_res.end = 0xff; | |
1da177e4 | 898 | |
4f535093 YL |
899 | if (!bridge) { |
900 | child->dev.parent = parent->bridge; | |
901 | goto add_dev; | |
902 | } | |
3789fa8a YZ |
903 | |
904 | child->self = bridge; | |
905 | child->bridge = get_device(&bridge->dev); | |
4f535093 | 906 | child->dev.parent = child->bridge; |
98d9f30c | 907 | pci_set_bus_of_node(child); |
9be60ca0 MW |
908 | pci_set_bus_speed(child); |
909 | ||
1da177e4 | 910 | /* Set up default resource pointers and names.. */ |
fde09c6d | 911 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
912 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
913 | child->resource[i]->name = child->name; | |
914 | } | |
915 | bridge->subordinate = child; | |
916 | ||
4f535093 | 917 | add_dev: |
44aa0c65 | 918 | pci_set_bus_msi_domain(child); |
4f535093 YL |
919 | ret = device_register(&child->dev); |
920 | WARN_ON(ret < 0); | |
921 | ||
10a95747 JL |
922 | pcibios_add_bus(child); |
923 | ||
057bd2e0 TR |
924 | if (child->ops->add_bus) { |
925 | ret = child->ops->add_bus(child); | |
926 | if (WARN_ON(ret < 0)) | |
927 | dev_err(&child->dev, "failed to add bus: %d\n", ret); | |
928 | } | |
929 | ||
4f535093 YL |
930 | /* Create legacy_io and legacy_mem files for this bus */ |
931 | pci_create_legacy_files(child); | |
932 | ||
1da177e4 LT |
933 | return child; |
934 | } | |
935 | ||
3c78bc61 RD |
936 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
937 | int busnr) | |
1da177e4 LT |
938 | { |
939 | struct pci_bus *child; | |
940 | ||
941 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 942 | if (child) { |
d71374da | 943 | down_write(&pci_bus_sem); |
1da177e4 | 944 | list_add_tail(&child->node, &parent->children); |
d71374da | 945 | up_write(&pci_bus_sem); |
e4ea9bb7 | 946 | } |
1da177e4 LT |
947 | return child; |
948 | } | |
b7fe9434 | 949 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 | 950 | |
f3dbd802 RJ |
951 | static void pci_enable_crs(struct pci_dev *pdev) |
952 | { | |
953 | u16 root_cap = 0; | |
954 | ||
955 | /* Enable CRS Software Visibility if supported */ | |
956 | pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); | |
957 | if (root_cap & PCI_EXP_RTCAP_CRSVIS) | |
958 | pcie_capability_set_word(pdev, PCI_EXP_RTCTL, | |
959 | PCI_EXP_RTCTL_CRSSVE); | |
960 | } | |
961 | ||
1da177e4 LT |
962 | /* |
963 | * If it's a bridge, configure it and scan the bus behind it. | |
964 | * For CardBus bridges, we don't scan behind as the devices will | |
965 | * be handled by the bridge driver itself. | |
966 | * | |
967 | * We need to process bridges in two passes -- first we scan those | |
968 | * already configured by the BIOS and after we are done with all of | |
969 | * them, we proceed to assigning numbers to the remaining buses in | |
970 | * order to avoid overlaps between old and new bus numbers. | |
971 | */ | |
15856ad5 | 972 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
973 | { |
974 | struct pci_bus *child; | |
975 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 976 | u32 buses, i, j = 0; |
1da177e4 | 977 | u16 bctl; |
99ddd552 | 978 | u8 primary, secondary, subordinate; |
a1c19894 | 979 | int broken = 0; |
1da177e4 | 980 | |
d963f651 MW |
981 | /* |
982 | * Make sure the bridge is powered on to be able to access config | |
983 | * space of devices below it. | |
984 | */ | |
985 | pm_runtime_get_sync(&dev->dev); | |
986 | ||
1da177e4 | 987 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
99ddd552 BH |
988 | primary = buses & 0xFF; |
989 | secondary = (buses >> 8) & 0xFF; | |
990 | subordinate = (buses >> 16) & 0xFF; | |
1da177e4 | 991 | |
99ddd552 BH |
992 | dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", |
993 | secondary, subordinate, pass); | |
1da177e4 | 994 | |
71f6bd4a YL |
995 | if (!primary && (primary != bus->number) && secondary && subordinate) { |
996 | dev_warn(&dev->dev, "Primary bus is hard wired to 0\n"); | |
997 | primary = bus->number; | |
998 | } | |
999 | ||
a1c19894 BH |
1000 | /* Check if setup is sensible at all */ |
1001 | if (!pass && | |
1965f66e | 1002 | (primary != bus->number || secondary <= bus->number || |
12d87069 | 1003 | secondary > subordinate)) { |
1965f66e YL |
1004 | dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", |
1005 | secondary, subordinate); | |
a1c19894 BH |
1006 | broken = 1; |
1007 | } | |
1008 | ||
1da177e4 | 1009 | /* Disable MasterAbortMode during probing to avoid reporting |
f7625980 | 1010 | of bus errors (in some architectures) */ |
1da177e4 LT |
1011 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
1012 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
1013 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
1014 | ||
f3dbd802 RJ |
1015 | pci_enable_crs(dev); |
1016 | ||
99ddd552 BH |
1017 | if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
1018 | !is_cardbus && !broken) { | |
1019 | unsigned int cmax; | |
1da177e4 LT |
1020 | /* |
1021 | * Bus already configured by firmware, process it in the first | |
1022 | * pass and just note the configuration. | |
1023 | */ | |
1024 | if (pass) | |
bbe8f9a3 | 1025 | goto out; |
1da177e4 LT |
1026 | |
1027 | /* | |
2ed85823 AN |
1028 | * The bus might already exist for two reasons: Either we are |
1029 | * rescanning the bus or the bus is reachable through more than | |
1030 | * one bridge. The second case can happen with the i450NX | |
1031 | * chipset. | |
1da177e4 | 1032 | */ |
99ddd552 | 1033 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
74710ded | 1034 | if (!child) { |
99ddd552 | 1035 | child = pci_add_new_bus(bus, dev, secondary); |
74710ded AC |
1036 | if (!child) |
1037 | goto out; | |
99ddd552 | 1038 | child->primary = primary; |
bc76b731 | 1039 | pci_bus_insert_busn_res(child, secondary, subordinate); |
74710ded | 1040 | child->bridge_ctl = bctl; |
1da177e4 LT |
1041 | } |
1042 | ||
1da177e4 | 1043 | cmax = pci_scan_child_bus(child); |
c95b0bd6 AN |
1044 | if (cmax > subordinate) |
1045 | dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n", | |
1046 | subordinate, cmax); | |
1047 | /* subordinate should equal child->busn_res.end */ | |
1048 | if (subordinate > max) | |
1049 | max = subordinate; | |
1da177e4 LT |
1050 | } else { |
1051 | /* | |
1052 | * We need to assign a number to this bus which we always | |
1053 | * do in the second pass. | |
1054 | */ | |
12f44f46 | 1055 | if (!pass) { |
619c8c31 | 1056 | if (pcibios_assign_all_busses() || broken || is_cardbus) |
12f44f46 IK |
1057 | /* Temporarily disable forwarding of the |
1058 | configuration cycles on all bridges in | |
1059 | this bus segment to avoid possible | |
1060 | conflicts in the second pass between two | |
1061 | bridges programmed with overlapping | |
1062 | bus ranges. */ | |
1063 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
1064 | buses & ~0xffffff); | |
bbe8f9a3 | 1065 | goto out; |
12f44f46 | 1066 | } |
1da177e4 LT |
1067 | |
1068 | /* Clear errors */ | |
1069 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
1070 | ||
7a0b33d4 BH |
1071 | /* Prevent assigning a bus number that already exists. |
1072 | * This can happen when a bridge is hot-plugged, so in | |
1073 | * this case we only re-scan this bus. */ | |
b1a98b69 TC |
1074 | child = pci_find_bus(pci_domain_nr(bus), max+1); |
1075 | if (!child) { | |
9a4d7d87 | 1076 | child = pci_add_new_bus(bus, dev, max+1); |
b1a98b69 TC |
1077 | if (!child) |
1078 | goto out; | |
12d87069 | 1079 | pci_bus_insert_busn_res(child, max+1, 0xff); |
b1a98b69 | 1080 | } |
9a4d7d87 | 1081 | max++; |
1da177e4 LT |
1082 | buses = (buses & 0xff000000) |
1083 | | ((unsigned int)(child->primary) << 0) | |
b918c62e YL |
1084 | | ((unsigned int)(child->busn_res.start) << 8) |
1085 | | ((unsigned int)(child->busn_res.end) << 16); | |
1da177e4 LT |
1086 | |
1087 | /* | |
1088 | * yenta.c forces a secondary latency timer of 176. | |
1089 | * Copy that behaviour here. | |
1090 | */ | |
1091 | if (is_cardbus) { | |
1092 | buses &= ~0xff000000; | |
1093 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
1094 | } | |
7c867c88 | 1095 | |
1da177e4 LT |
1096 | /* |
1097 | * We need to blast all three values with a single write. | |
1098 | */ | |
1099 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
1100 | ||
1101 | if (!is_cardbus) { | |
11949255 | 1102 | child->bridge_ctl = bctl; |
1da177e4 LT |
1103 | max = pci_scan_child_bus(child); |
1104 | } else { | |
1105 | /* | |
1106 | * For CardBus bridges, we leave 4 bus numbers | |
1107 | * as cards with a PCI-to-PCI bridge can be | |
1108 | * inserted later. | |
1109 | */ | |
3c78bc61 | 1110 | for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { |
49887941 | 1111 | struct pci_bus *parent = bus; |
cc57450f RS |
1112 | if (pci_find_bus(pci_domain_nr(bus), |
1113 | max+i+1)) | |
1114 | break; | |
49887941 DB |
1115 | while (parent->parent) { |
1116 | if ((!pcibios_assign_all_busses()) && | |
b918c62e YL |
1117 | (parent->busn_res.end > max) && |
1118 | (parent->busn_res.end <= max+i)) { | |
49887941 DB |
1119 | j = 1; |
1120 | } | |
1121 | parent = parent->parent; | |
1122 | } | |
1123 | if (j) { | |
1124 | /* | |
1125 | * Often, there are two cardbus bridges | |
1126 | * -- try to leave one valid bus number | |
1127 | * for each one. | |
1128 | */ | |
1129 | i /= 2; | |
1130 | break; | |
1131 | } | |
1132 | } | |
cc57450f | 1133 | max += i; |
1da177e4 LT |
1134 | } |
1135 | /* | |
1136 | * Set the subordinate bus number to its real value. | |
1137 | */ | |
bc76b731 | 1138 | pci_bus_update_busn_res_end(child, max); |
1da177e4 LT |
1139 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
1140 | } | |
1141 | ||
cb3576fa GH |
1142 | sprintf(child->name, |
1143 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
1144 | pci_domain_nr(bus), child->number); | |
1da177e4 | 1145 | |
d55bef51 | 1146 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 | 1147 | while (bus->parent) { |
b918c62e YL |
1148 | if ((child->busn_res.end > bus->busn_res.end) || |
1149 | (child->number > bus->busn_res.end) || | |
49887941 | 1150 | (child->number < bus->number) || |
b918c62e | 1151 | (child->busn_res.end < bus->number)) { |
227f0647 | 1152 | dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n", |
b918c62e YL |
1153 | &child->busn_res, |
1154 | (bus->number > child->busn_res.end && | |
1155 | bus->busn_res.end < child->number) ? | |
a6f29a98 JP |
1156 | "wholly" : "partially", |
1157 | bus->self->transparent ? " transparent" : "", | |
865df576 | 1158 | dev_name(&bus->dev), |
b918c62e | 1159 | &bus->busn_res); |
49887941 DB |
1160 | } |
1161 | bus = bus->parent; | |
1162 | } | |
1163 | ||
bbe8f9a3 RB |
1164 | out: |
1165 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
1166 | ||
d963f651 MW |
1167 | pm_runtime_put(&dev->dev); |
1168 | ||
1da177e4 LT |
1169 | return max; |
1170 | } | |
b7fe9434 | 1171 | EXPORT_SYMBOL(pci_scan_bridge); |
1da177e4 LT |
1172 | |
1173 | /* | |
1174 | * Read interrupt line and base address registers. | |
1175 | * The architecture-dependent code can tweak these, of course. | |
1176 | */ | |
1177 | static void pci_read_irq(struct pci_dev *dev) | |
1178 | { | |
1179 | unsigned char irq; | |
1180 | ||
1181 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 1182 | dev->pin = irq; |
1da177e4 LT |
1183 | if (irq) |
1184 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
1185 | dev->irq = irq; | |
1186 | } | |
1187 | ||
bb209c82 | 1188 | void set_pcie_port_type(struct pci_dev *pdev) |
480b93b7 YZ |
1189 | { |
1190 | int pos; | |
1191 | u16 reg16; | |
d0751b98 YW |
1192 | int type; |
1193 | struct pci_dev *parent; | |
480b93b7 YZ |
1194 | |
1195 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
1196 | if (!pos) | |
1197 | return; | |
51ebfc92 | 1198 | |
0efea000 | 1199 | pdev->pcie_cap = pos; |
480b93b7 | 1200 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
786e2288 | 1201 | pdev->pcie_flags_reg = reg16; |
b03e7495 JM |
1202 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); |
1203 | pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; | |
d0751b98 YW |
1204 | |
1205 | /* | |
51ebfc92 BH |
1206 | * A Root Port or a PCI-to-PCIe bridge is always the upstream end |
1207 | * of a Link. No PCIe component has two Links. Two Links are | |
1208 | * connected by a Switch that has a Port on each Link and internal | |
1209 | * logic to connect the two Ports. | |
d0751b98 YW |
1210 | */ |
1211 | type = pci_pcie_type(pdev); | |
51ebfc92 BH |
1212 | if (type == PCI_EXP_TYPE_ROOT_PORT || |
1213 | type == PCI_EXP_TYPE_PCIE_BRIDGE) | |
d0751b98 YW |
1214 | pdev->has_secondary_link = 1; |
1215 | else if (type == PCI_EXP_TYPE_UPSTREAM || | |
1216 | type == PCI_EXP_TYPE_DOWNSTREAM) { | |
1217 | parent = pci_upstream_bridge(pdev); | |
b35b1df5 YW |
1218 | |
1219 | /* | |
1220 | * Usually there's an upstream device (Root Port or Switch | |
1221 | * Downstream Port), but we can't assume one exists. | |
1222 | */ | |
1223 | if (parent && !parent->has_secondary_link) | |
d0751b98 YW |
1224 | pdev->has_secondary_link = 1; |
1225 | } | |
480b93b7 YZ |
1226 | } |
1227 | ||
bb209c82 | 1228 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
28760489 | 1229 | { |
28760489 EB |
1230 | u32 reg32; |
1231 | ||
59875ae4 | 1232 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); |
28760489 EB |
1233 | if (reg32 & PCI_EXP_SLTCAP_HPC) |
1234 | pdev->is_hotplug_bridge = 1; | |
1235 | } | |
1236 | ||
8531e283 LW |
1237 | static void set_pcie_thunderbolt(struct pci_dev *dev) |
1238 | { | |
1239 | int vsec = 0; | |
1240 | u32 header; | |
1241 | ||
1242 | while ((vsec = pci_find_next_ext_capability(dev, vsec, | |
1243 | PCI_EXT_CAP_ID_VNDR))) { | |
1244 | pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header); | |
1245 | ||
1246 | /* Is the device part of a Thunderbolt controller? */ | |
1247 | if (dev->vendor == PCI_VENDOR_ID_INTEL && | |
1248 | PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) { | |
1249 | dev->is_thunderbolt = 1; | |
1250 | return; | |
1251 | } | |
1252 | } | |
1253 | } | |
1254 | ||
78916b00 AW |
1255 | /** |
1256 | * pci_ext_cfg_is_aliased - is ext config space just an alias of std config? | |
1257 | * @dev: PCI device | |
1258 | * | |
1259 | * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that | |
1260 | * when forwarding a type1 configuration request the bridge must check that | |
1261 | * the extended register address field is zero. The bridge is not permitted | |
1262 | * to forward the transactions and must handle it as an Unsupported Request. | |
1263 | * Some bridges do not follow this rule and simply drop the extended register | |
1264 | * bits, resulting in the standard config space being aliased, every 256 | |
1265 | * bytes across the entire configuration space. Test for this condition by | |
1266 | * comparing the first dword of each potential alias to the vendor/device ID. | |
1267 | * Known offenders: | |
1268 | * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) | |
1269 | * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) | |
1270 | */ | |
1271 | static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) | |
1272 | { | |
1273 | #ifdef CONFIG_PCI_QUIRKS | |
1274 | int pos; | |
1275 | u32 header, tmp; | |
1276 | ||
1277 | pci_read_config_dword(dev, PCI_VENDOR_ID, &header); | |
1278 | ||
1279 | for (pos = PCI_CFG_SPACE_SIZE; | |
1280 | pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { | |
1281 | if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL | |
1282 | || header != tmp) | |
1283 | return false; | |
1284 | } | |
1285 | ||
1286 | return true; | |
1287 | #else | |
1288 | return false; | |
1289 | #endif | |
1290 | } | |
1291 | ||
0b950f0f SH |
1292 | /** |
1293 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
1294 | * @dev: PCI device | |
1295 | * | |
1296 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
1297 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
1298 | * access it. Maybe we don't have a way to generate extended config space | |
1299 | * accesses, or the device is behind a reverse Express bridge. So we try | |
1300 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
1301 | * capability header. | |
1302 | */ | |
1303 | static int pci_cfg_space_size_ext(struct pci_dev *dev) | |
1304 | { | |
1305 | u32 status; | |
1306 | int pos = PCI_CFG_SPACE_SIZE; | |
1307 | ||
1308 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) | |
8e5a395a | 1309 | return PCI_CFG_SPACE_SIZE; |
78916b00 | 1310 | if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) |
8e5a395a | 1311 | return PCI_CFG_SPACE_SIZE; |
0b950f0f SH |
1312 | |
1313 | return PCI_CFG_SPACE_EXP_SIZE; | |
0b950f0f SH |
1314 | } |
1315 | ||
1316 | int pci_cfg_space_size(struct pci_dev *dev) | |
1317 | { | |
1318 | int pos; | |
1319 | u32 status; | |
1320 | u16 class; | |
1321 | ||
1322 | class = dev->class >> 8; | |
1323 | if (class == PCI_CLASS_BRIDGE_HOST) | |
1324 | return pci_cfg_space_size_ext(dev); | |
1325 | ||
8e5a395a BH |
1326 | if (pci_is_pcie(dev)) |
1327 | return pci_cfg_space_size_ext(dev); | |
0b950f0f | 1328 | |
8e5a395a BH |
1329 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
1330 | if (!pos) | |
1331 | return PCI_CFG_SPACE_SIZE; | |
0b950f0f | 1332 | |
8e5a395a BH |
1333 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); |
1334 | if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) | |
1335 | return pci_cfg_space_size_ext(dev); | |
0b950f0f | 1336 | |
0b950f0f SH |
1337 | return PCI_CFG_SPACE_SIZE; |
1338 | } | |
1339 | ||
01abc2aa | 1340 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 1341 | |
e80e7edc | 1342 | static void pci_msi_setup_pci_dev(struct pci_dev *dev) |
1851617c MT |
1343 | { |
1344 | /* | |
1345 | * Disable the MSI hardware to avoid screaming interrupts | |
1346 | * during boot. This is the power on reset default so | |
1347 | * usually this should be a noop. | |
1348 | */ | |
1349 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1350 | if (dev->msi_cap) | |
1351 | pci_msi_set_enable(dev, 0); | |
1352 | ||
1353 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1354 | if (dev->msix_cap) | |
1355 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); | |
1356 | } | |
1357 | ||
99b3c58f PG |
1358 | /** |
1359 | * pci_intx_mask_broken - test PCI_COMMAND_INTX_DISABLE writability | |
1360 | * @dev: PCI device | |
1361 | * | |
1362 | * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this | |
1363 | * at enumeration-time to avoid modifying PCI_COMMAND at run-time. | |
1364 | */ | |
1365 | static int pci_intx_mask_broken(struct pci_dev *dev) | |
1366 | { | |
1367 | u16 orig, toggle, new; | |
1368 | ||
1369 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
1370 | toggle = orig ^ PCI_COMMAND_INTX_DISABLE; | |
1371 | pci_write_config_word(dev, PCI_COMMAND, toggle); | |
1372 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
1373 | ||
1374 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
1375 | ||
1376 | /* | |
1377 | * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI | |
1378 | * r2.3, so strictly speaking, a device is not *broken* if it's not | |
1379 | * writable. But we'll live with the misnomer for now. | |
1380 | */ | |
1381 | if (new != toggle) | |
1382 | return 1; | |
1383 | return 0; | |
1384 | } | |
1385 | ||
1da177e4 LT |
1386 | /** |
1387 | * pci_setup_device - fill in class and map information of a device | |
1388 | * @dev: the device structure to fill | |
1389 | * | |
f7625980 | 1390 | * Initialize the device structure with information about the device's |
1da177e4 LT |
1391 | * vendor,class,memory and IO-space addresses,IRQ lines etc. |
1392 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
480b93b7 YZ |
1393 | * Returns 0 on success and negative if unknown type of device (not normal, |
1394 | * bridge or CardBus). | |
1da177e4 | 1395 | */ |
480b93b7 | 1396 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
1397 | { |
1398 | u32 class; | |
b84106b4 | 1399 | u16 cmd; |
480b93b7 | 1400 | u8 hdr_type; |
bc577d2b | 1401 | int pos = 0; |
5bfa14ed BH |
1402 | struct pci_bus_region region; |
1403 | struct resource *res; | |
480b93b7 YZ |
1404 | |
1405 | if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) | |
1406 | return -EIO; | |
1407 | ||
1408 | dev->sysdata = dev->bus->sysdata; | |
1409 | dev->dev.parent = dev->bus->bridge; | |
1410 | dev->dev.bus = &pci_bus_type; | |
1411 | dev->hdr_type = hdr_type & 0x7f; | |
1412 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
1413 | dev->error_state = pci_channel_io_normal; |
1414 | set_pcie_port_type(dev); | |
1415 | ||
017ffe64 | 1416 | pci_dev_assign_slot(dev); |
480b93b7 YZ |
1417 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) |
1418 | set this higher, assuming the system even supports it. */ | |
1419 | dev->dma_mask = 0xffffffff; | |
1da177e4 | 1420 | |
eebfcfb5 GKH |
1421 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
1422 | dev->bus->number, PCI_SLOT(dev->devfn), | |
1423 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
1424 | |
1425 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 1426 | dev->revision = class & 0xff; |
2dd8ba92 | 1427 | dev->class = class >> 8; /* upper 3 bytes */ |
1da177e4 | 1428 | |
2dd8ba92 YL |
1429 | dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n", |
1430 | dev->vendor, dev->device, dev->hdr_type, dev->class); | |
1da177e4 | 1431 | |
853346e4 YZ |
1432 | /* need to have dev->class ready */ |
1433 | dev->cfg_size = pci_cfg_space_size(dev); | |
1434 | ||
8531e283 LW |
1435 | /* need to have dev->cfg_size ready */ |
1436 | set_pcie_thunderbolt(dev); | |
1437 | ||
1da177e4 | 1438 | /* "Unknown power state" */ |
3fe9d19f | 1439 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
1440 | |
1441 | /* Early fixups, before probing the BARs */ | |
1442 | pci_fixup_device(pci_fixup_early, dev); | |
f79b1b14 YZ |
1443 | /* device class may be changed after fixup */ |
1444 | class = dev->class >> 8; | |
1da177e4 | 1445 | |
b84106b4 BH |
1446 | if (dev->non_compliant_bars) { |
1447 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1448 | if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { | |
1449 | dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); | |
1450 | cmd &= ~PCI_COMMAND_IO; | |
1451 | cmd &= ~PCI_COMMAND_MEMORY; | |
1452 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1453 | } | |
1454 | } | |
1455 | ||
99b3c58f PG |
1456 | dev->broken_intx_masking = pci_intx_mask_broken(dev); |
1457 | ||
1da177e4 LT |
1458 | switch (dev->hdr_type) { /* header type */ |
1459 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
1460 | if (class == PCI_CLASS_BRIDGE_PCI) | |
1461 | goto bad; | |
1462 | pci_read_irq(dev); | |
1463 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
1464 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1465 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
1466 | |
1467 | /* | |
075eb9e3 BH |
1468 | * Do the ugly legacy mode stuff here rather than broken chip |
1469 | * quirk code. Legacy mode ATA controllers have fixed | |
1470 | * addresses. These are not always echoed in BAR0-3, and | |
1471 | * BAR0-3 in a few cases contain junk! | |
368c73d4 AC |
1472 | */ |
1473 | if (class == PCI_CLASS_STORAGE_IDE) { | |
1474 | u8 progif; | |
1475 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1476 | if ((progif & 1) == 0) { | |
5bfa14ed BH |
1477 | region.start = 0x1F0; |
1478 | region.end = 0x1F7; | |
1479 | res = &dev->resource[0]; | |
1480 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1481 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1482 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n", |
1483 | res); | |
5bfa14ed BH |
1484 | region.start = 0x3F6; |
1485 | region.end = 0x3F6; | |
1486 | res = &dev->resource[1]; | |
1487 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1488 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1489 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n", |
1490 | res); | |
368c73d4 AC |
1491 | } |
1492 | if ((progif & 4) == 0) { | |
5bfa14ed BH |
1493 | region.start = 0x170; |
1494 | region.end = 0x177; | |
1495 | res = &dev->resource[2]; | |
1496 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1497 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1498 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n", |
1499 | res); | |
5bfa14ed BH |
1500 | region.start = 0x376; |
1501 | region.end = 0x376; | |
1502 | res = &dev->resource[3]; | |
1503 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1504 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1505 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n", |
1506 | res); | |
368c73d4 AC |
1507 | } |
1508 | } | |
1da177e4 LT |
1509 | break; |
1510 | ||
1511 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
1512 | if (class != PCI_CLASS_BRIDGE_PCI) | |
1513 | goto bad; | |
1514 | /* The PCI-to-PCI bridge spec requires that subtractive | |
1515 | decoding (i.e. transparent) bridge must have programming | |
f7625980 | 1516 | interface code of 0x01. */ |
3efd273b | 1517 | pci_read_irq(dev); |
1da177e4 LT |
1518 | dev->transparent = ((dev->class & 0xff) == 1); |
1519 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
28760489 | 1520 | set_pcie_hotplug_bridge(dev); |
bc577d2b GB |
1521 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
1522 | if (pos) { | |
1523 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); | |
1524 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); | |
1525 | } | |
1da177e4 LT |
1526 | break; |
1527 | ||
1528 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
1529 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
1530 | goto bad; | |
1531 | pci_read_irq(dev); | |
1532 | pci_read_bases(dev, 1, 0); | |
1533 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1534 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
1535 | break; | |
1536 | ||
1537 | default: /* unknown header */ | |
227f0647 RD |
1538 | dev_err(&dev->dev, "unknown header type %02x, ignoring device\n", |
1539 | dev->hdr_type); | |
480b93b7 | 1540 | return -EIO; |
1da177e4 LT |
1541 | |
1542 | bad: | |
227f0647 RD |
1543 | dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n", |
1544 | dev->class, dev->hdr_type); | |
2b4aed1d | 1545 | dev->class = PCI_CLASS_NOT_DEFINED << 8; |
1da177e4 LT |
1546 | } |
1547 | ||
1548 | /* We found a fine healthy device, go go go... */ | |
1549 | return 0; | |
1550 | } | |
1551 | ||
9dae3a97 BH |
1552 | static void pci_configure_mps(struct pci_dev *dev) |
1553 | { | |
1554 | struct pci_dev *bridge = pci_upstream_bridge(dev); | |
27d868b5 | 1555 | int mps, p_mps, rc; |
9dae3a97 BH |
1556 | |
1557 | if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge)) | |
1558 | return; | |
1559 | ||
1560 | mps = pcie_get_mps(dev); | |
1561 | p_mps = pcie_get_mps(bridge); | |
1562 | ||
1563 | if (mps == p_mps) | |
1564 | return; | |
1565 | ||
1566 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { | |
1567 | dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", | |
1568 | mps, pci_name(bridge), p_mps); | |
1569 | return; | |
1570 | } | |
27d868b5 KB |
1571 | |
1572 | /* | |
1573 | * Fancier MPS configuration is done later by | |
1574 | * pcie_bus_configure_settings() | |
1575 | */ | |
1576 | if (pcie_bus_config != PCIE_BUS_DEFAULT) | |
1577 | return; | |
1578 | ||
1579 | rc = pcie_set_mps(dev, p_mps); | |
1580 | if (rc) { | |
1581 | dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", | |
1582 | p_mps); | |
1583 | return; | |
1584 | } | |
1585 | ||
1586 | dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n", | |
1587 | p_mps, mps, 128 << dev->pcie_mpss); | |
9dae3a97 BH |
1588 | } |
1589 | ||
589fcc23 BH |
1590 | static struct hpp_type0 pci_default_type0 = { |
1591 | .revision = 1, | |
1592 | .cache_line_size = 8, | |
1593 | .latency_timer = 0x40, | |
1594 | .enable_serr = 0, | |
1595 | .enable_perr = 0, | |
1596 | }; | |
1597 | ||
1598 | static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp) | |
1599 | { | |
1600 | u16 pci_cmd, pci_bctl; | |
1601 | ||
c6285fc5 | 1602 | if (!hpp) |
589fcc23 | 1603 | hpp = &pci_default_type0; |
589fcc23 BH |
1604 | |
1605 | if (hpp->revision > 1) { | |
1606 | dev_warn(&dev->dev, | |
1607 | "PCI settings rev %d not supported; using defaults\n", | |
1608 | hpp->revision); | |
1609 | hpp = &pci_default_type0; | |
1610 | } | |
1611 | ||
1612 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); | |
1613 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer); | |
1614 | pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); | |
1615 | if (hpp->enable_serr) | |
1616 | pci_cmd |= PCI_COMMAND_SERR; | |
589fcc23 BH |
1617 | if (hpp->enable_perr) |
1618 | pci_cmd |= PCI_COMMAND_PARITY; | |
589fcc23 BH |
1619 | pci_write_config_word(dev, PCI_COMMAND, pci_cmd); |
1620 | ||
1621 | /* Program bridge control value */ | |
1622 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
1623 | pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, | |
1624 | hpp->latency_timer); | |
1625 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); | |
1626 | if (hpp->enable_serr) | |
1627 | pci_bctl |= PCI_BRIDGE_CTL_SERR; | |
589fcc23 BH |
1628 | if (hpp->enable_perr) |
1629 | pci_bctl |= PCI_BRIDGE_CTL_PARITY; | |
589fcc23 BH |
1630 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); |
1631 | } | |
1632 | } | |
1633 | ||
1634 | static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp) | |
1635 | { | |
977509f7 BH |
1636 | int pos; |
1637 | ||
1638 | if (!hpp) | |
1639 | return; | |
1640 | ||
1641 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1642 | if (!pos) | |
1643 | return; | |
1644 | ||
1645 | dev_warn(&dev->dev, "PCI-X settings not supported\n"); | |
589fcc23 BH |
1646 | } |
1647 | ||
e42010d8 JT |
1648 | static bool pcie_root_rcb_set(struct pci_dev *dev) |
1649 | { | |
1650 | struct pci_dev *rp = pcie_find_root_port(dev); | |
1651 | u16 lnkctl; | |
1652 | ||
1653 | if (!rp) | |
1654 | return false; | |
1655 | ||
1656 | pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); | |
1657 | if (lnkctl & PCI_EXP_LNKCTL_RCB) | |
1658 | return true; | |
1659 | ||
1660 | return false; | |
1661 | } | |
1662 | ||
589fcc23 BH |
1663 | static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) |
1664 | { | |
1665 | int pos; | |
1666 | u32 reg32; | |
1667 | ||
1668 | if (!hpp) | |
1669 | return; | |
1670 | ||
977509f7 BH |
1671 | if (!pci_is_pcie(dev)) |
1672 | return; | |
1673 | ||
589fcc23 BH |
1674 | if (hpp->revision > 1) { |
1675 | dev_warn(&dev->dev, "PCIe settings rev %d not supported\n", | |
1676 | hpp->revision); | |
1677 | return; | |
1678 | } | |
1679 | ||
302328c0 BH |
1680 | /* |
1681 | * Don't allow _HPX to change MPS or MRRS settings. We manage | |
1682 | * those to make sure they're consistent with the rest of the | |
1683 | * platform. | |
1684 | */ | |
1685 | hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD | | |
1686 | PCI_EXP_DEVCTL_READRQ; | |
1687 | hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD | | |
1688 | PCI_EXP_DEVCTL_READRQ); | |
1689 | ||
589fcc23 BH |
1690 | /* Initialize Device Control Register */ |
1691 | pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, | |
1692 | ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or); | |
1693 | ||
1694 | /* Initialize Link Control Register */ | |
e42010d8 JT |
1695 | if (pcie_cap_has_lnkctl(dev)) { |
1696 | ||
1697 | /* | |
1698 | * If the Root Port supports Read Completion Boundary of | |
1699 | * 128, set RCB to 128. Otherwise, clear it. | |
1700 | */ | |
1701 | hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB; | |
1702 | hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB; | |
1703 | if (pcie_root_rcb_set(dev)) | |
1704 | hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB; | |
1705 | ||
589fcc23 BH |
1706 | pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, |
1707 | ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or); | |
e42010d8 | 1708 | } |
589fcc23 BH |
1709 | |
1710 | /* Find Advanced Error Reporting Enhanced Capability */ | |
1711 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
1712 | if (!pos) | |
1713 | return; | |
1714 | ||
1715 | /* Initialize Uncorrectable Error Mask Register */ | |
1716 | pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); | |
1717 | reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or; | |
1718 | pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); | |
1719 | ||
1720 | /* Initialize Uncorrectable Error Severity Register */ | |
1721 | pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); | |
1722 | reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or; | |
1723 | pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); | |
1724 | ||
1725 | /* Initialize Correctable Error Mask Register */ | |
1726 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); | |
1727 | reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or; | |
1728 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); | |
1729 | ||
1730 | /* Initialize Advanced Error Capabilities and Control Register */ | |
1731 | pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); | |
1732 | reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or; | |
675734ba BH |
1733 | /* Don't enable ECRC generation or checking if unsupported */ |
1734 | if (!(reg32 & PCI_ERR_CAP_ECRC_GENC)) | |
1735 | reg32 &= ~PCI_ERR_CAP_ECRC_GENE; | |
1736 | if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC)) | |
1737 | reg32 &= ~PCI_ERR_CAP_ECRC_CHKE; | |
589fcc23 BH |
1738 | pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); |
1739 | ||
1740 | /* | |
1741 | * FIXME: The following two registers are not supported yet. | |
1742 | * | |
1743 | * o Secondary Uncorrectable Error Severity Register | |
1744 | * o Secondary Uncorrectable Error Mask Register | |
1745 | */ | |
1746 | } | |
1747 | ||
62ce94a7 | 1748 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign) |
60db3a4d | 1749 | { |
62ce94a7 SK |
1750 | struct pci_host_bridge *host; |
1751 | u32 cap; | |
1752 | u16 ctl; | |
60db3a4d SK |
1753 | int ret; |
1754 | ||
1755 | if (!pci_is_pcie(dev)) | |
62ce94a7 | 1756 | return 0; |
60db3a4d | 1757 | |
62ce94a7 | 1758 | ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
60db3a4d | 1759 | if (ret) |
62ce94a7 SK |
1760 | return 0; |
1761 | ||
1762 | if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) | |
1763 | return 0; | |
60db3a4d | 1764 | |
62ce94a7 SK |
1765 | ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
1766 | if (ret) | |
1767 | return 0; | |
1768 | ||
1769 | host = pci_find_host_bridge(dev->bus); | |
1770 | if (!host) | |
1771 | return 0; | |
1772 | ||
1773 | /* | |
1774 | * If some device in the hierarchy doesn't handle Extended Tags | |
1775 | * correctly, make sure they're disabled. | |
1776 | */ | |
1777 | if (host->no_ext_tags) { | |
1778 | if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { | |
1779 | dev_info(&dev->dev, "disabling Extended Tags\n"); | |
1780 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, | |
1781 | PCI_EXP_DEVCTL_EXT_TAG); | |
1782 | } | |
1783 | return 0; | |
1784 | } | |
1785 | ||
1786 | if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { | |
1787 | dev_info(&dev->dev, "enabling Extended Tags\n"); | |
60db3a4d SK |
1788 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, |
1789 | PCI_EXP_DEVCTL_EXT_TAG); | |
62ce94a7 SK |
1790 | } |
1791 | return 0; | |
60db3a4d SK |
1792 | } |
1793 | ||
6cd33649 BH |
1794 | static void pci_configure_device(struct pci_dev *dev) |
1795 | { | |
1796 | struct hotplug_params hpp; | |
1797 | int ret; | |
1798 | ||
9dae3a97 | 1799 | pci_configure_mps(dev); |
62ce94a7 | 1800 | pci_configure_extended_tags(dev, NULL); |
9dae3a97 | 1801 | |
6cd33649 BH |
1802 | memset(&hpp, 0, sizeof(hpp)); |
1803 | ret = pci_get_hp_params(dev, &hpp); | |
1804 | if (ret) | |
1805 | return; | |
1806 | ||
1807 | program_hpp_type2(dev, hpp.t2); | |
1808 | program_hpp_type1(dev, hpp.t1); | |
1809 | program_hpp_type0(dev, hpp.t0); | |
1810 | } | |
1811 | ||
201de56e ZY |
1812 | static void pci_release_capabilities(struct pci_dev *dev) |
1813 | { | |
1814 | pci_vpd_release(dev); | |
d1b054da | 1815 | pci_iov_release(dev); |
f796841e | 1816 | pci_free_cap_save_buffers(dev); |
201de56e ZY |
1817 | } |
1818 | ||
1da177e4 LT |
1819 | /** |
1820 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
1821 | * @dev: device that's been disconnected | |
1822 | * | |
1823 | * Will be called only by the device core when all users of this pci device are | |
1824 | * done. | |
1825 | */ | |
1826 | static void pci_release_dev(struct device *dev) | |
1827 | { | |
04480094 | 1828 | struct pci_dev *pci_dev; |
1da177e4 | 1829 | |
04480094 | 1830 | pci_dev = to_pci_dev(dev); |
201de56e | 1831 | pci_release_capabilities(pci_dev); |
98d9f30c | 1832 | pci_release_of_node(pci_dev); |
6ae32c53 | 1833 | pcibios_release_device(pci_dev); |
8b1fce04 | 1834 | pci_bus_put(pci_dev->bus); |
782a985d | 1835 | kfree(pci_dev->driver_override); |
338c3149 | 1836 | kfree(pci_dev->dma_alias_mask); |
1da177e4 LT |
1837 | kfree(pci_dev); |
1838 | } | |
1839 | ||
3c6e6ae7 | 1840 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus) |
65891215 ME |
1841 | { |
1842 | struct pci_dev *dev; | |
1843 | ||
1844 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
1845 | if (!dev) | |
1846 | return NULL; | |
1847 | ||
65891215 | 1848 | INIT_LIST_HEAD(&dev->bus_list); |
88e7b167 | 1849 | dev->dev.type = &pci_dev_type; |
3c6e6ae7 | 1850 | dev->bus = pci_bus_get(bus); |
65891215 ME |
1851 | |
1852 | return dev; | |
1853 | } | |
3c6e6ae7 GZ |
1854 | EXPORT_SYMBOL(pci_alloc_dev); |
1855 | ||
62bc6a6f SK |
1856 | static bool pci_bus_crs_vendor_id(u32 l) |
1857 | { | |
1858 | return (l & 0xffff) == 0x0001; | |
1859 | } | |
1860 | ||
efdc87da | 1861 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, |
3c78bc61 | 1862 | int crs_timeout) |
1da177e4 | 1863 | { |
1da177e4 LT |
1864 | int delay = 1; |
1865 | ||
efdc87da YL |
1866 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
1867 | return false; | |
1da177e4 LT |
1868 | |
1869 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
efdc87da YL |
1870 | if (*l == 0xffffffff || *l == 0x00000000 || |
1871 | *l == 0x0000ffff || *l == 0xffff0000) | |
1872 | return false; | |
1da177e4 | 1873 | |
89665a6a RJ |
1874 | /* |
1875 | * Configuration Request Retry Status. Some root ports return the | |
1876 | * actual device ID instead of the synthetic ID (0xFFFF) required | |
1877 | * by the PCIe spec. Ignore the device ID and only check for | |
1878 | * (vendor id == 1). | |
1879 | */ | |
62bc6a6f | 1880 | while (pci_bus_crs_vendor_id(*l)) { |
efdc87da YL |
1881 | if (!crs_timeout) |
1882 | return false; | |
1883 | ||
efdc87da | 1884 | if (delay > crs_timeout) { |
227f0647 RD |
1885 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n", |
1886 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
1887 | PCI_FUNC(devfn)); | |
efdc87da | 1888 | return false; |
1da177e4 | 1889 | } |
9f982756 BH |
1890 | |
1891 | msleep(delay); | |
1892 | delay *= 2; | |
1893 | ||
1894 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) | |
1895 | return false; | |
1da177e4 LT |
1896 | } |
1897 | ||
efdc87da YL |
1898 | return true; |
1899 | } | |
1900 | EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); | |
1901 | ||
1902 | /* | |
1903 | * Read the config data for a PCI device, sanity-check it | |
1904 | * and fill in the dev structure... | |
1905 | */ | |
1906 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) | |
1907 | { | |
1908 | struct pci_dev *dev; | |
1909 | u32 l; | |
1910 | ||
1911 | if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) | |
1912 | return NULL; | |
1913 | ||
8b1fce04 | 1914 | dev = pci_alloc_dev(bus); |
1da177e4 LT |
1915 | if (!dev) |
1916 | return NULL; | |
1917 | ||
1da177e4 | 1918 | dev->devfn = devfn; |
1da177e4 LT |
1919 | dev->vendor = l & 0xffff; |
1920 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 1921 | |
98d9f30c BH |
1922 | pci_set_of_node(dev); |
1923 | ||
480b93b7 | 1924 | if (pci_setup_device(dev)) { |
8b1fce04 | 1925 | pci_bus_put(dev->bus); |
1da177e4 LT |
1926 | kfree(dev); |
1927 | return NULL; | |
1928 | } | |
1da177e4 LT |
1929 | |
1930 | return dev; | |
1931 | } | |
1932 | ||
201de56e ZY |
1933 | static void pci_init_capabilities(struct pci_dev *dev) |
1934 | { | |
938174e5 SS |
1935 | /* Enhanced Allocation */ |
1936 | pci_ea_init(dev); | |
1937 | ||
e80e7edc GP |
1938 | /* Setup MSI caps & disable MSI/MSI-X interrupts */ |
1939 | pci_msi_setup_pci_dev(dev); | |
201de56e | 1940 | |
63f4898a RW |
1941 | /* Buffers for saving PCIe and PCI-X capabilities */ |
1942 | pci_allocate_cap_save_buffers(dev); | |
1943 | ||
201de56e ZY |
1944 | /* Power Management */ |
1945 | pci_pm_init(dev); | |
1946 | ||
1947 | /* Vital Product Data */ | |
f1cd93f9 | 1948 | pci_vpd_init(dev); |
58c3a727 YZ |
1949 | |
1950 | /* Alternative Routing-ID Forwarding */ | |
31ab2476 | 1951 | pci_configure_ari(dev); |
d1b054da YZ |
1952 | |
1953 | /* Single Root I/O Virtualization */ | |
1954 | pci_iov_init(dev); | |
ae21ee65 | 1955 | |
edc90fee BH |
1956 | /* Address Translation Services */ |
1957 | pci_ats_init(dev); | |
1958 | ||
ae21ee65 | 1959 | /* Enable ACS P2P upstream forwarding */ |
5d990b62 | 1960 | pci_enable_acs(dev); |
b07461a8 | 1961 | |
9bb04a0c JY |
1962 | /* Precision Time Measurement */ |
1963 | pci_ptm_init(dev); | |
4dc2db09 | 1964 | |
66b80809 KB |
1965 | /* Advanced Error Reporting */ |
1966 | pci_aer_init(dev); | |
201de56e ZY |
1967 | } |
1968 | ||
098259eb MZ |
1969 | /* |
1970 | * This is the equivalent of pci_host_bridge_msi_domain that acts on | |
1971 | * devices. Firmware interfaces that can select the MSI domain on a | |
1972 | * per-device basis should be called from here. | |
1973 | */ | |
1974 | static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) | |
1975 | { | |
1976 | struct irq_domain *d; | |
1977 | ||
1978 | /* | |
1979 | * If a domain has been set through the pcibios_add_device | |
1980 | * callback, then this is the one (platform code knows best). | |
1981 | */ | |
1982 | d = dev_get_msi_domain(&dev->dev); | |
1983 | if (d) | |
1984 | return d; | |
1985 | ||
54fa97ee MZ |
1986 | /* |
1987 | * Let's see if we have a firmware interface able to provide | |
1988 | * the domain. | |
1989 | */ | |
1990 | d = pci_msi_get_device_domain(dev); | |
1991 | if (d) | |
1992 | return d; | |
1993 | ||
098259eb MZ |
1994 | return NULL; |
1995 | } | |
1996 | ||
44aa0c65 MZ |
1997 | static void pci_set_msi_domain(struct pci_dev *dev) |
1998 | { | |
098259eb MZ |
1999 | struct irq_domain *d; |
2000 | ||
44aa0c65 | 2001 | /* |
098259eb MZ |
2002 | * If the platform or firmware interfaces cannot supply a |
2003 | * device-specific MSI domain, then inherit the default domain | |
2004 | * from the host bridge itself. | |
44aa0c65 | 2005 | */ |
098259eb MZ |
2006 | d = pci_dev_msi_domain(dev); |
2007 | if (!d) | |
2008 | d = dev_get_msi_domain(&dev->bus->dev); | |
2009 | ||
2010 | dev_set_msi_domain(&dev->dev, d); | |
44aa0c65 MZ |
2011 | } |
2012 | ||
96bde06a | 2013 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 2014 | { |
4f535093 YL |
2015 | int ret; |
2016 | ||
6cd33649 BH |
2017 | pci_configure_device(dev); |
2018 | ||
cdb9b9f7 PM |
2019 | device_initialize(&dev->dev); |
2020 | dev->dev.release = pci_release_dev; | |
1da177e4 | 2021 | |
7629d19a | 2022 | set_dev_node(&dev->dev, pcibus_to_node(bus)); |
cdb9b9f7 | 2023 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 2024 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 2025 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 2026 | |
4d57cdfa | 2027 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 2028 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 2029 | |
1da177e4 LT |
2030 | /* Fix up broken headers */ |
2031 | pci_fixup_device(pci_fixup_header, dev); | |
2032 | ||
2069ecfb YL |
2033 | /* moved out from quirk header fixup code */ |
2034 | pci_reassigndev_resource_alignment(dev); | |
2035 | ||
4b77b0a2 RW |
2036 | /* Clear the state_saved flag. */ |
2037 | dev->state_saved = false; | |
2038 | ||
201de56e ZY |
2039 | /* Initialize various capabilities */ |
2040 | pci_init_capabilities(dev); | |
eb9d0fe4 | 2041 | |
1da177e4 LT |
2042 | /* |
2043 | * Add the device to our list of discovered devices | |
2044 | * and the bus list for fixup functions, etc. | |
2045 | */ | |
d71374da | 2046 | down_write(&pci_bus_sem); |
1da177e4 | 2047 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 2048 | up_write(&pci_bus_sem); |
4f535093 | 2049 | |
4f535093 YL |
2050 | ret = pcibios_add_device(dev); |
2051 | WARN_ON(ret < 0); | |
2052 | ||
44aa0c65 MZ |
2053 | /* Setup MSI irq domain */ |
2054 | pci_set_msi_domain(dev); | |
2055 | ||
4f535093 YL |
2056 | /* Notifier could use PCI capabilities */ |
2057 | dev->match_driver = false; | |
2058 | ret = device_add(&dev->dev); | |
2059 | WARN_ON(ret < 0); | |
cdb9b9f7 PM |
2060 | } |
2061 | ||
10874f5a | 2062 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
2063 | { |
2064 | struct pci_dev *dev; | |
2065 | ||
90bdb311 TP |
2066 | dev = pci_get_slot(bus, devfn); |
2067 | if (dev) { | |
2068 | pci_dev_put(dev); | |
2069 | return dev; | |
2070 | } | |
2071 | ||
cdb9b9f7 PM |
2072 | dev = pci_scan_device(bus, devfn); |
2073 | if (!dev) | |
2074 | return NULL; | |
2075 | ||
2076 | pci_device_add(dev, bus); | |
1da177e4 LT |
2077 | |
2078 | return dev; | |
2079 | } | |
b73e9687 | 2080 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 | 2081 | |
b1bd58e4 | 2082 | static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) |
f07852d6 | 2083 | { |
b1bd58e4 YW |
2084 | int pos; |
2085 | u16 cap = 0; | |
2086 | unsigned next_fn; | |
4fb88c1a | 2087 | |
b1bd58e4 YW |
2088 | if (pci_ari_enabled(bus)) { |
2089 | if (!dev) | |
2090 | return 0; | |
2091 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); | |
2092 | if (!pos) | |
2093 | return 0; | |
4fb88c1a | 2094 | |
b1bd58e4 YW |
2095 | pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); |
2096 | next_fn = PCI_ARI_CAP_NFN(cap); | |
2097 | if (next_fn <= fn) | |
2098 | return 0; /* protect against malformed list */ | |
f07852d6 | 2099 | |
b1bd58e4 YW |
2100 | return next_fn; |
2101 | } | |
2102 | ||
2103 | /* dev may be NULL for non-contiguous multifunction devices */ | |
2104 | if (!dev || dev->multifunction) | |
2105 | return (fn + 1) % 8; | |
f07852d6 | 2106 | |
f07852d6 MW |
2107 | return 0; |
2108 | } | |
2109 | ||
2110 | static int only_one_child(struct pci_bus *bus) | |
2111 | { | |
2112 | struct pci_dev *parent = bus->self; | |
284f5f9d | 2113 | |
f07852d6 MW |
2114 | if (!parent || !pci_is_pcie(parent)) |
2115 | return 0; | |
62f87c0e | 2116 | if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT) |
284f5f9d | 2117 | return 1; |
5bbe029f BH |
2118 | |
2119 | /* | |
2120 | * PCIe downstream ports are bridges that normally lead to only a | |
2121 | * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all | |
2122 | * possible devices, not just device 0. See PCIe spec r3.0, | |
2123 | * sec 7.3.1. | |
2124 | */ | |
777e61ea | 2125 | if (parent->has_secondary_link && |
284f5f9d | 2126 | !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) |
f07852d6 MW |
2127 | return 1; |
2128 | return 0; | |
2129 | } | |
2130 | ||
1da177e4 LT |
2131 | /** |
2132 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
2133 | * @bus: PCI bus to scan | |
2134 | * @devfn: slot number to scan (must have zero function.) | |
2135 | * | |
2136 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
2137 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 2138 | * will not have is_added set. |
1b69dfc6 TP |
2139 | * |
2140 | * Returns the number of new devices found. | |
1da177e4 | 2141 | */ |
96bde06a | 2142 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 2143 | { |
f07852d6 | 2144 | unsigned fn, nr = 0; |
1b69dfc6 | 2145 | struct pci_dev *dev; |
f07852d6 MW |
2146 | |
2147 | if (only_one_child(bus) && (devfn > 0)) | |
2148 | return 0; /* Already scanned the entire slot */ | |
1da177e4 | 2149 | |
1b69dfc6 | 2150 | dev = pci_scan_single_device(bus, devfn); |
4fb88c1a MW |
2151 | if (!dev) |
2152 | return 0; | |
2153 | if (!dev->is_added) | |
1b69dfc6 TP |
2154 | nr++; |
2155 | ||
b1bd58e4 | 2156 | for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { |
f07852d6 MW |
2157 | dev = pci_scan_single_device(bus, devfn + fn); |
2158 | if (dev) { | |
2159 | if (!dev->is_added) | |
2160 | nr++; | |
2161 | dev->multifunction = 1; | |
1da177e4 LT |
2162 | } |
2163 | } | |
7d715a6c | 2164 | |
149e1637 SL |
2165 | /* only one slot has pcie device */ |
2166 | if (bus->self && nr) | |
7d715a6c SL |
2167 | pcie_aspm_init_link_state(bus->self); |
2168 | ||
1da177e4 LT |
2169 | return nr; |
2170 | } | |
b7fe9434 | 2171 | EXPORT_SYMBOL(pci_scan_slot); |
1da177e4 | 2172 | |
b03e7495 JM |
2173 | static int pcie_find_smpss(struct pci_dev *dev, void *data) |
2174 | { | |
2175 | u8 *smpss = data; | |
2176 | ||
2177 | if (!pci_is_pcie(dev)) | |
2178 | return 0; | |
2179 | ||
d4aa68f6 YW |
2180 | /* |
2181 | * We don't have a way to change MPS settings on devices that have | |
2182 | * drivers attached. A hot-added device might support only the minimum | |
2183 | * MPS setting (MPS=128). Therefore, if the fabric contains a bridge | |
2184 | * where devices may be hot-added, we limit the fabric MPS to 128 so | |
2185 | * hot-added devices will work correctly. | |
2186 | * | |
2187 | * However, if we hot-add a device to a slot directly below a Root | |
2188 | * Port, it's impossible for there to be other existing devices below | |
2189 | * the port. We don't limit the MPS in this case because we can | |
2190 | * reconfigure MPS on both the Root Port and the hot-added device, | |
2191 | * and there are no other devices involved. | |
2192 | * | |
2193 | * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. | |
b03e7495 | 2194 | */ |
d4aa68f6 YW |
2195 | if (dev->is_hotplug_bridge && |
2196 | pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) | |
b03e7495 JM |
2197 | *smpss = 0; |
2198 | ||
2199 | if (*smpss > dev->pcie_mpss) | |
2200 | *smpss = dev->pcie_mpss; | |
2201 | ||
2202 | return 0; | |
2203 | } | |
2204 | ||
2205 | static void pcie_write_mps(struct pci_dev *dev, int mps) | |
2206 | { | |
62f392ea | 2207 | int rc; |
b03e7495 JM |
2208 | |
2209 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
62f392ea | 2210 | mps = 128 << dev->pcie_mpss; |
b03e7495 | 2211 | |
62f87c0e YW |
2212 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && |
2213 | dev->bus->self) | |
62f392ea | 2214 | /* For "Performance", the assumption is made that |
b03e7495 JM |
2215 | * downstream communication will never be larger than |
2216 | * the MRRS. So, the MPS only needs to be configured | |
2217 | * for the upstream communication. This being the case, | |
2218 | * walk from the top down and set the MPS of the child | |
2219 | * to that of the parent bus. | |
62f392ea JM |
2220 | * |
2221 | * Configure the device MPS with the smaller of the | |
2222 | * device MPSS or the bridge MPS (which is assumed to be | |
2223 | * properly configured at this point to the largest | |
2224 | * allowable MPS based on its parent bus). | |
b03e7495 | 2225 | */ |
62f392ea | 2226 | mps = min(mps, pcie_get_mps(dev->bus->self)); |
b03e7495 JM |
2227 | } |
2228 | ||
2229 | rc = pcie_set_mps(dev, mps); | |
2230 | if (rc) | |
2231 | dev_err(&dev->dev, "Failed attempting to set the MPS\n"); | |
2232 | } | |
2233 | ||
62f392ea | 2234 | static void pcie_write_mrrs(struct pci_dev *dev) |
b03e7495 | 2235 | { |
62f392ea | 2236 | int rc, mrrs; |
b03e7495 | 2237 | |
ed2888e9 JM |
2238 | /* In the "safe" case, do not configure the MRRS. There appear to be |
2239 | * issues with setting MRRS to 0 on a number of devices. | |
2240 | */ | |
ed2888e9 JM |
2241 | if (pcie_bus_config != PCIE_BUS_PERFORMANCE) |
2242 | return; | |
2243 | ||
ed2888e9 JM |
2244 | /* For Max performance, the MRRS must be set to the largest supported |
2245 | * value. However, it cannot be configured larger than the MPS the | |
62f392ea JM |
2246 | * device or the bus can support. This should already be properly |
2247 | * configured by a prior call to pcie_write_mps. | |
ed2888e9 | 2248 | */ |
62f392ea | 2249 | mrrs = pcie_get_mps(dev); |
b03e7495 JM |
2250 | |
2251 | /* MRRS is a R/W register. Invalid values can be written, but a | |
ed2888e9 | 2252 | * subsequent read will verify if the value is acceptable or not. |
b03e7495 JM |
2253 | * If the MRRS value provided is not acceptable (e.g., too large), |
2254 | * shrink the value until it is acceptable to the HW. | |
f7625980 | 2255 | */ |
b03e7495 JM |
2256 | while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { |
2257 | rc = pcie_set_readrq(dev, mrrs); | |
62f392ea JM |
2258 | if (!rc) |
2259 | break; | |
b03e7495 | 2260 | |
62f392ea | 2261 | dev_warn(&dev->dev, "Failed attempting to set the MRRS\n"); |
b03e7495 JM |
2262 | mrrs /= 2; |
2263 | } | |
62f392ea JM |
2264 | |
2265 | if (mrrs < 128) | |
227f0647 | 2266 | dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); |
b03e7495 JM |
2267 | } |
2268 | ||
2269 | static int pcie_bus_configure_set(struct pci_dev *dev, void *data) | |
2270 | { | |
a513a99a | 2271 | int mps, orig_mps; |
b03e7495 JM |
2272 | |
2273 | if (!pci_is_pcie(dev)) | |
2274 | return 0; | |
2275 | ||
27d868b5 KB |
2276 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF || |
2277 | pcie_bus_config == PCIE_BUS_DEFAULT) | |
5895af79 | 2278 | return 0; |
5895af79 | 2279 | |
a513a99a JM |
2280 | mps = 128 << *(u8 *)data; |
2281 | orig_mps = pcie_get_mps(dev); | |
b03e7495 JM |
2282 | |
2283 | pcie_write_mps(dev, mps); | |
62f392ea | 2284 | pcie_write_mrrs(dev); |
b03e7495 | 2285 | |
227f0647 RD |
2286 | dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", |
2287 | pcie_get_mps(dev), 128 << dev->pcie_mpss, | |
a513a99a | 2288 | orig_mps, pcie_get_readrq(dev)); |
b03e7495 JM |
2289 | |
2290 | return 0; | |
2291 | } | |
2292 | ||
a513a99a | 2293 | /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, |
b03e7495 JM |
2294 | * parents then children fashion. If this changes, then this code will not |
2295 | * work as designed. | |
2296 | */ | |
a58674ff | 2297 | void pcie_bus_configure_settings(struct pci_bus *bus) |
b03e7495 | 2298 | { |
1e358f94 | 2299 | u8 smpss = 0; |
b03e7495 | 2300 | |
a58674ff | 2301 | if (!bus->self) |
b03e7495 JM |
2302 | return; |
2303 | ||
b03e7495 | 2304 | if (!pci_is_pcie(bus->self)) |
5f39e670 JM |
2305 | return; |
2306 | ||
2307 | /* FIXME - Peer to peer DMA is possible, though the endpoint would need | |
3315472c | 2308 | * to be aware of the MPS of the destination. To work around this, |
5f39e670 JM |
2309 | * simply force the MPS of the entire system to the smallest possible. |
2310 | */ | |
2311 | if (pcie_bus_config == PCIE_BUS_PEER2PEER) | |
2312 | smpss = 0; | |
2313 | ||
b03e7495 | 2314 | if (pcie_bus_config == PCIE_BUS_SAFE) { |
a58674ff | 2315 | smpss = bus->self->pcie_mpss; |
5f39e670 | 2316 | |
b03e7495 JM |
2317 | pcie_find_smpss(bus->self, &smpss); |
2318 | pci_walk_bus(bus, pcie_find_smpss, &smpss); | |
2319 | } | |
2320 | ||
2321 | pcie_bus_configure_set(bus->self, &smpss); | |
2322 | pci_walk_bus(bus, pcie_bus_configure_set, &smpss); | |
2323 | } | |
debc3b77 | 2324 | EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); |
b03e7495 | 2325 | |
15856ad5 | 2326 | unsigned int pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 | 2327 | { |
b918c62e | 2328 | unsigned int devfn, pass, max = bus->busn_res.start; |
1da177e4 LT |
2329 | struct pci_dev *dev; |
2330 | ||
0207c356 | 2331 | dev_dbg(&bus->dev, "scanning bus\n"); |
1da177e4 LT |
2332 | |
2333 | /* Go find them, Rover! */ | |
2334 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
2335 | pci_scan_slot(bus, devfn); | |
2336 | ||
a28724b0 YZ |
2337 | /* Reserve buses for SR-IOV capability. */ |
2338 | max += pci_iov_bus_range(bus); | |
2339 | ||
1da177e4 LT |
2340 | /* |
2341 | * After performing arch-dependent fixup of the bus, look behind | |
2342 | * all PCI-to-PCI bridges on this bus. | |
2343 | */ | |
74710ded | 2344 | if (!bus->is_added) { |
0207c356 | 2345 | dev_dbg(&bus->dev, "fixups for bus\n"); |
74710ded | 2346 | pcibios_fixup_bus(bus); |
981cf9ea | 2347 | bus->is_added = 1; |
74710ded AC |
2348 | } |
2349 | ||
3c78bc61 | 2350 | for (pass = 0; pass < 2; pass++) |
1da177e4 | 2351 | list_for_each_entry(dev, &bus->devices, bus_list) { |
6788a51f | 2352 | if (pci_is_bridge(dev)) |
1da177e4 LT |
2353 | max = pci_scan_bridge(bus, dev, max, pass); |
2354 | } | |
2355 | ||
e16b4660 KB |
2356 | /* |
2357 | * Make sure a hotplug bridge has at least the minimum requested | |
2358 | * number of buses. | |
2359 | */ | |
2360 | if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) { | |
2361 | if (max - bus->busn_res.start < pci_hotplug_bus_size - 1) | |
2362 | max = bus->busn_res.start + pci_hotplug_bus_size - 1; | |
2363 | } | |
2364 | ||
1da177e4 LT |
2365 | /* |
2366 | * We've scanned the bus and so we know all about what's on | |
2367 | * the other side of any bridges that may be on this bus plus | |
2368 | * any devices. | |
2369 | * | |
2370 | * Return how far we've got finding sub-buses. | |
2371 | */ | |
0207c356 | 2372 | dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); |
1da177e4 LT |
2373 | return max; |
2374 | } | |
b7fe9434 | 2375 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1da177e4 | 2376 | |
6c0cc950 RW |
2377 | /** |
2378 | * pcibios_root_bridge_prepare - Platform-specific host bridge setup. | |
2379 | * @bridge: Host bridge to set up. | |
2380 | * | |
2381 | * Default empty implementation. Replace with an architecture-specific setup | |
2382 | * routine, if necessary. | |
2383 | */ | |
2384 | int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) | |
2385 | { | |
2386 | return 0; | |
2387 | } | |
2388 | ||
10a95747 JL |
2389 | void __weak pcibios_add_bus(struct pci_bus *bus) |
2390 | { | |
2391 | } | |
2392 | ||
2393 | void __weak pcibios_remove_bus(struct pci_bus *bus) | |
2394 | { | |
2395 | } | |
2396 | ||
9ee8a1c4 LP |
2397 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
2398 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
1da177e4 | 2399 | { |
0efd5aab | 2400 | int error; |
5a21d70d | 2401 | struct pci_host_bridge *bridge; |
1da177e4 | 2402 | |
59094065 | 2403 | bridge = pci_alloc_host_bridge(0); |
7b543663 | 2404 | if (!bridge) |
37d6a0a6 | 2405 | return NULL; |
7b543663 YL |
2406 | |
2407 | bridge->dev.parent = parent; | |
a9d9f527 | 2408 | |
37d6a0a6 AB |
2409 | list_splice_init(resources, &bridge->windows); |
2410 | bridge->sysdata = sysdata; | |
2411 | bridge->busnr = bus; | |
2412 | bridge->ops = ops; | |
a9d9f527 | 2413 | |
37d6a0a6 AB |
2414 | error = pci_register_host_bridge(bridge); |
2415 | if (error < 0) | |
2416 | goto err_out; | |
a5390aa6 | 2417 | |
37d6a0a6 | 2418 | return bridge->bus; |
1da177e4 | 2419 | |
1da177e4 | 2420 | err_out: |
37d6a0a6 | 2421 | kfree(bridge); |
1da177e4 LT |
2422 | return NULL; |
2423 | } | |
e6b29dea | 2424 | EXPORT_SYMBOL_GPL(pci_create_root_bus); |
cdb9b9f7 | 2425 | |
98a35831 YL |
2426 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) |
2427 | { | |
2428 | struct resource *res = &b->busn_res; | |
2429 | struct resource *parent_res, *conflict; | |
2430 | ||
2431 | res->start = bus; | |
2432 | res->end = bus_max; | |
2433 | res->flags = IORESOURCE_BUS; | |
2434 | ||
2435 | if (!pci_is_root_bus(b)) | |
2436 | parent_res = &b->parent->busn_res; | |
2437 | else { | |
2438 | parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); | |
2439 | res->flags |= IORESOURCE_PCI_FIXED; | |
2440 | } | |
2441 | ||
ced04d15 | 2442 | conflict = request_resource_conflict(parent_res, res); |
98a35831 YL |
2443 | |
2444 | if (conflict) | |
2445 | dev_printk(KERN_DEBUG, &b->dev, | |
2446 | "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", | |
2447 | res, pci_is_root_bus(b) ? "domain " : "", | |
2448 | parent_res, conflict->name, conflict); | |
98a35831 YL |
2449 | |
2450 | return conflict == NULL; | |
2451 | } | |
2452 | ||
2453 | int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) | |
2454 | { | |
2455 | struct resource *res = &b->busn_res; | |
2456 | struct resource old_res = *res; | |
2457 | resource_size_t size; | |
2458 | int ret; | |
2459 | ||
2460 | if (res->start > bus_max) | |
2461 | return -EINVAL; | |
2462 | ||
2463 | size = bus_max - res->start + 1; | |
2464 | ret = adjust_resource(res, res->start, size); | |
2465 | dev_printk(KERN_DEBUG, &b->dev, | |
2466 | "busn_res: %pR end %s updated to %02x\n", | |
2467 | &old_res, ret ? "can not be" : "is", bus_max); | |
2468 | ||
2469 | if (!ret && !res->parent) | |
2470 | pci_bus_insert_busn_res(b, res->start, res->end); | |
2471 | ||
2472 | return ret; | |
2473 | } | |
2474 | ||
2475 | void pci_bus_release_busn_res(struct pci_bus *b) | |
2476 | { | |
2477 | struct resource *res = &b->busn_res; | |
2478 | int ret; | |
2479 | ||
2480 | if (!res->flags || !res->parent) | |
2481 | return; | |
2482 | ||
2483 | ret = release_resource(res); | |
2484 | dev_printk(KERN_DEBUG, &b->dev, | |
2485 | "busn_res: %pR %s released\n", | |
2486 | res, ret ? "can not be" : "is"); | |
2487 | } | |
2488 | ||
1228c4b6 | 2489 | int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) |
a2ebb827 | 2490 | { |
14d76b68 | 2491 | struct resource_entry *window; |
4d99f524 | 2492 | bool found = false; |
a2ebb827 | 2493 | struct pci_bus *b; |
1228c4b6 | 2494 | int max, bus, ret; |
4d99f524 | 2495 | |
1228c4b6 LP |
2496 | if (!bridge) |
2497 | return -EINVAL; | |
2498 | ||
2499 | resource_list_for_each_entry(window, &bridge->windows) | |
4d99f524 YL |
2500 | if (window->res->flags & IORESOURCE_BUS) { |
2501 | found = true; | |
2502 | break; | |
2503 | } | |
a2ebb827 | 2504 | |
1228c4b6 LP |
2505 | ret = pci_register_host_bridge(bridge); |
2506 | if (ret < 0) | |
2507 | return ret; | |
2508 | ||
2509 | b = bridge->bus; | |
2510 | bus = bridge->busnr; | |
a2ebb827 | 2511 | |
4d99f524 YL |
2512 | if (!found) { |
2513 | dev_info(&b->dev, | |
2514 | "No busn resource found for root bus, will use [bus %02x-ff]\n", | |
2515 | bus); | |
2516 | pci_bus_insert_busn_res(b, bus, 255); | |
2517 | } | |
2518 | ||
2519 | max = pci_scan_child_bus(b); | |
2520 | ||
2521 | if (!found) | |
2522 | pci_bus_update_busn_res_end(b, max); | |
2523 | ||
1228c4b6 | 2524 | return 0; |
a2ebb827 | 2525 | } |
1228c4b6 | 2526 | EXPORT_SYMBOL(pci_scan_root_bus_bridge); |
d2a7926d LP |
2527 | |
2528 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, | |
2529 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
2530 | { | |
14d76b68 | 2531 | struct resource_entry *window; |
4d99f524 | 2532 | bool found = false; |
a2ebb827 | 2533 | struct pci_bus *b; |
4d99f524 YL |
2534 | int max; |
2535 | ||
14d76b68 | 2536 | resource_list_for_each_entry(window, resources) |
4d99f524 YL |
2537 | if (window->res->flags & IORESOURCE_BUS) { |
2538 | found = true; | |
2539 | break; | |
2540 | } | |
a2ebb827 | 2541 | |
9ee8a1c4 | 2542 | b = pci_create_root_bus(parent, bus, ops, sysdata, resources); |
a2ebb827 BH |
2543 | if (!b) |
2544 | return NULL; | |
2545 | ||
4d99f524 YL |
2546 | if (!found) { |
2547 | dev_info(&b->dev, | |
2548 | "No busn resource found for root bus, will use [bus %02x-ff]\n", | |
2549 | bus); | |
2550 | pci_bus_insert_busn_res(b, bus, 255); | |
2551 | } | |
2552 | ||
2553 | max = pci_scan_child_bus(b); | |
2554 | ||
2555 | if (!found) | |
2556 | pci_bus_update_busn_res_end(b, max); | |
2557 | ||
a2ebb827 | 2558 | return b; |
d2a7926d | 2559 | } |
a2ebb827 BH |
2560 | EXPORT_SYMBOL(pci_scan_root_bus); |
2561 | ||
15856ad5 | 2562 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, |
de4b2f76 BH |
2563 | void *sysdata) |
2564 | { | |
2565 | LIST_HEAD(resources); | |
2566 | struct pci_bus *b; | |
2567 | ||
2568 | pci_add_resource(&resources, &ioport_resource); | |
2569 | pci_add_resource(&resources, &iomem_resource); | |
857c3b66 | 2570 | pci_add_resource(&resources, &busn_resource); |
de4b2f76 BH |
2571 | b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); |
2572 | if (b) { | |
857c3b66 | 2573 | pci_scan_child_bus(b); |
de4b2f76 BH |
2574 | } else { |
2575 | pci_free_resource_list(&resources); | |
2576 | } | |
2577 | return b; | |
2578 | } | |
2579 | EXPORT_SYMBOL(pci_scan_bus); | |
2580 | ||
2f320521 YL |
2581 | /** |
2582 | * pci_rescan_bus_bridge_resize - scan a PCI bus for devices. | |
2583 | * @bridge: PCI bridge for the bus to scan | |
2584 | * | |
2585 | * Scan a PCI bus and child buses for new devices, add them, | |
2586 | * and enable them, resizing bridge mmio/io resource if necessary | |
2587 | * and possible. The caller must ensure the child devices are already | |
2588 | * removed for resizing to occur. | |
2589 | * | |
2590 | * Returns the max number of subordinate bus discovered. | |
2591 | */ | |
10874f5a | 2592 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) |
2f320521 YL |
2593 | { |
2594 | unsigned int max; | |
2595 | struct pci_bus *bus = bridge->subordinate; | |
2596 | ||
2597 | max = pci_scan_child_bus(bus); | |
2598 | ||
2599 | pci_assign_unassigned_bridge_resources(bridge); | |
2600 | ||
2601 | pci_bus_add_devices(bus); | |
2602 | ||
2603 | return max; | |
2604 | } | |
2605 | ||
a5213a31 YL |
2606 | /** |
2607 | * pci_rescan_bus - scan a PCI bus for devices. | |
2608 | * @bus: PCI bus to scan | |
2609 | * | |
2610 | * Scan a PCI bus and child buses for new devices, adds them, | |
2611 | * and enables them. | |
2612 | * | |
2613 | * Returns the max number of subordinate bus discovered. | |
2614 | */ | |
10874f5a | 2615 | unsigned int pci_rescan_bus(struct pci_bus *bus) |
a5213a31 YL |
2616 | { |
2617 | unsigned int max; | |
2618 | ||
2619 | max = pci_scan_child_bus(bus); | |
2620 | pci_assign_unassigned_bus_resources(bus); | |
2621 | pci_bus_add_devices(bus); | |
2622 | ||
2623 | return max; | |
2624 | } | |
2625 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
2626 | ||
9d16947b RW |
2627 | /* |
2628 | * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal | |
2629 | * routines should always be executed under this mutex. | |
2630 | */ | |
2631 | static DEFINE_MUTEX(pci_rescan_remove_lock); | |
2632 | ||
2633 | void pci_lock_rescan_remove(void) | |
2634 | { | |
2635 | mutex_lock(&pci_rescan_remove_lock); | |
2636 | } | |
2637 | EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); | |
2638 | ||
2639 | void pci_unlock_rescan_remove(void) | |
2640 | { | |
2641 | mutex_unlock(&pci_rescan_remove_lock); | |
2642 | } | |
2643 | EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); | |
2644 | ||
3c78bc61 RD |
2645 | static int __init pci_sort_bf_cmp(const struct device *d_a, |
2646 | const struct device *d_b) | |
6b4b78fe | 2647 | { |
99178b03 GKH |
2648 | const struct pci_dev *a = to_pci_dev(d_a); |
2649 | const struct pci_dev *b = to_pci_dev(d_b); | |
2650 | ||
6b4b78fe MD |
2651 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
2652 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
2653 | ||
2654 | if (a->bus->number < b->bus->number) return -1; | |
2655 | else if (a->bus->number > b->bus->number) return 1; | |
2656 | ||
2657 | if (a->devfn < b->devfn) return -1; | |
2658 | else if (a->devfn > b->devfn) return 1; | |
2659 | ||
2660 | return 0; | |
2661 | } | |
2662 | ||
5ff580c1 | 2663 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 2664 | { |
99178b03 | 2665 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 2666 | } |