Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
de335bb4 | 9 | #include <linux/of_pci.h> |
589fcc23 | 10 | #include <linux/pci_hotplug.h> |
1da177e4 LT |
11 | #include <linux/slab.h> |
12 | #include <linux/module.h> | |
13 | #include <linux/cpumask.h> | |
7d715a6c | 14 | #include <linux/pci-aspm.h> |
284f5f9d | 15 | #include <asm-generic/pci-bridge.h> |
bc56b9e0 | 16 | #include "pci.h" |
1da177e4 LT |
17 | |
18 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
19 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 | 20 | |
0b950f0f | 21 | static struct resource busn_resource = { |
67cdc827 YL |
22 | .name = "PCI busn", |
23 | .start = 0, | |
24 | .end = 255, | |
25 | .flags = IORESOURCE_BUS, | |
26 | }; | |
27 | ||
1da177e4 LT |
28 | /* Ugh. Need to stop exporting this to modules. */ |
29 | LIST_HEAD(pci_root_buses); | |
30 | EXPORT_SYMBOL(pci_root_buses); | |
31 | ||
5cc62c20 YL |
32 | static LIST_HEAD(pci_domain_busn_res_list); |
33 | ||
34 | struct pci_domain_busn_res { | |
35 | struct list_head list; | |
36 | struct resource res; | |
37 | int domain_nr; | |
38 | }; | |
39 | ||
40 | static struct resource *get_pci_domain_busn_res(int domain_nr) | |
41 | { | |
42 | struct pci_domain_busn_res *r; | |
43 | ||
44 | list_for_each_entry(r, &pci_domain_busn_res_list, list) | |
45 | if (r->domain_nr == domain_nr) | |
46 | return &r->res; | |
47 | ||
48 | r = kzalloc(sizeof(*r), GFP_KERNEL); | |
49 | if (!r) | |
50 | return NULL; | |
51 | ||
52 | r->domain_nr = domain_nr; | |
53 | r->res.start = 0; | |
54 | r->res.end = 0xff; | |
55 | r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; | |
56 | ||
57 | list_add_tail(&r->list, &pci_domain_busn_res_list); | |
58 | ||
59 | return &r->res; | |
60 | } | |
61 | ||
70308923 GKH |
62 | static int find_anything(struct device *dev, void *data) |
63 | { | |
64 | return 1; | |
65 | } | |
1da177e4 | 66 | |
ed4aaadb ZY |
67 | /* |
68 | * Some device drivers need know if pci is initiated. | |
69 | * Basically, we think pci is not initiated when there | |
70308923 | 70 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
71 | */ |
72 | int no_pci_devices(void) | |
73 | { | |
70308923 GKH |
74 | struct device *dev; |
75 | int no_devices; | |
ed4aaadb | 76 | |
70308923 GKH |
77 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
78 | no_devices = (dev == NULL); | |
79 | put_device(dev); | |
80 | return no_devices; | |
81 | } | |
ed4aaadb ZY |
82 | EXPORT_SYMBOL(no_pci_devices); |
83 | ||
1da177e4 LT |
84 | /* |
85 | * PCI Bus Class | |
86 | */ | |
fd7d1ced | 87 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 88 | { |
fd7d1ced | 89 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 | 90 | |
ff0387c3 | 91 | put_device(pci_bus->bridge); |
2fe2abf8 | 92 | pci_bus_remove_resources(pci_bus); |
98d9f30c | 93 | pci_release_bus_of_node(pci_bus); |
1da177e4 LT |
94 | kfree(pci_bus); |
95 | } | |
96 | ||
97 | static struct class pcibus_class = { | |
98 | .name = "pci_bus", | |
fd7d1ced | 99 | .dev_release = &release_pcibus_dev, |
56039e65 | 100 | .dev_groups = pcibus_groups, |
1da177e4 LT |
101 | }; |
102 | ||
103 | static int __init pcibus_class_init(void) | |
104 | { | |
105 | return class_register(&pcibus_class); | |
106 | } | |
107 | postcore_initcall(pcibus_class_init); | |
108 | ||
6ac665c6 | 109 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 110 | { |
6ac665c6 | 111 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
112 | if (!size) |
113 | return 0; | |
114 | ||
115 | /* Get the lowest of them to find the decode size, and | |
116 | from that the extent. */ | |
117 | size = (size & ~(size-1)) - 1; | |
118 | ||
119 | /* base == maxbase can be valid only if the BAR has | |
120 | already been programmed with all 1s. */ | |
121 | if (base == maxbase && ((base | size) & mask) != mask) | |
122 | return 0; | |
123 | ||
124 | return size; | |
125 | } | |
126 | ||
28c6821a | 127 | static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) |
6ac665c6 | 128 | { |
8d6a6a47 | 129 | u32 mem_type; |
28c6821a | 130 | unsigned long flags; |
8d6a6a47 | 131 | |
6ac665c6 | 132 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
28c6821a BH |
133 | flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
134 | flags |= IORESOURCE_IO; | |
135 | return flags; | |
6ac665c6 | 136 | } |
07eddf3d | 137 | |
28c6821a BH |
138 | flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
139 | flags |= IORESOURCE_MEM; | |
140 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
141 | flags |= IORESOURCE_PREFETCH; | |
07eddf3d | 142 | |
8d6a6a47 BH |
143 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
144 | switch (mem_type) { | |
145 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
146 | break; | |
147 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
0ff9514b | 148 | /* 1M mem BAR treated as 32-bit BAR */ |
8d6a6a47 BH |
149 | break; |
150 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
28c6821a BH |
151 | flags |= IORESOURCE_MEM_64; |
152 | break; | |
8d6a6a47 | 153 | default: |
0ff9514b | 154 | /* mem unknown type treated as 32-bit BAR */ |
8d6a6a47 BH |
155 | break; |
156 | } | |
28c6821a | 157 | return flags; |
07eddf3d YL |
158 | } |
159 | ||
808e34e2 ZK |
160 | #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) |
161 | ||
0b400c7e YZ |
162 | /** |
163 | * pci_read_base - read a PCI BAR | |
164 | * @dev: the PCI device | |
165 | * @type: type of the BAR | |
166 | * @res: resource buffer to be filled in | |
167 | * @pos: BAR position in the config space | |
168 | * | |
169 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 170 | */ |
0b400c7e | 171 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
3c78bc61 | 172 | struct resource *res, unsigned int pos) |
07eddf3d | 173 | { |
6ac665c6 | 174 | u32 l, sz, mask; |
23b13bc7 | 175 | u64 l64, sz64, mask64; |
253d2e54 | 176 | u16 orig_cmd; |
cf4d1cf5 | 177 | struct pci_bus_region region, inverted_region; |
6ac665c6 | 178 | |
1ed67439 | 179 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
6ac665c6 | 180 | |
0ff9514b | 181 | /* No printks while decoding is disabled! */ |
253d2e54 JP |
182 | if (!dev->mmio_always_on) { |
183 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); | |
808e34e2 ZK |
184 | if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { |
185 | pci_write_config_word(dev, PCI_COMMAND, | |
186 | orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); | |
187 | } | |
253d2e54 JP |
188 | } |
189 | ||
6ac665c6 MW |
190 | res->name = pci_name(dev); |
191 | ||
192 | pci_read_config_dword(dev, pos, &l); | |
1ed67439 | 193 | pci_write_config_dword(dev, pos, l | mask); |
6ac665c6 MW |
194 | pci_read_config_dword(dev, pos, &sz); |
195 | pci_write_config_dword(dev, pos, l); | |
196 | ||
197 | /* | |
198 | * All bits set in sz means the device isn't working properly. | |
45aa23b4 BH |
199 | * If the BAR isn't implemented, all bits must be 0. If it's a |
200 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
201 | * 1 must be clear. | |
6ac665c6 | 202 | */ |
f795d86a MS |
203 | if (sz == 0xffffffff) |
204 | sz = 0; | |
6ac665c6 MW |
205 | |
206 | /* | |
207 | * I don't know how l can have all bits set. Copied from old code. | |
208 | * Maybe it fixes a bug on some ancient platform. | |
209 | */ | |
210 | if (l == 0xffffffff) | |
211 | l = 0; | |
212 | ||
213 | if (type == pci_bar_unknown) { | |
28c6821a BH |
214 | res->flags = decode_bar(dev, l); |
215 | res->flags |= IORESOURCE_SIZEALIGN; | |
216 | if (res->flags & IORESOURCE_IO) { | |
f795d86a MS |
217 | l64 = l & PCI_BASE_ADDRESS_IO_MASK; |
218 | sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; | |
219 | mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; | |
6ac665c6 | 220 | } else { |
f795d86a MS |
221 | l64 = l & PCI_BASE_ADDRESS_MEM_MASK; |
222 | sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; | |
223 | mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
6ac665c6 MW |
224 | } |
225 | } else { | |
226 | res->flags |= (l & IORESOURCE_ROM_ENABLE); | |
f795d86a MS |
227 | l64 = l & PCI_ROM_ADDRESS_MASK; |
228 | sz64 = sz & PCI_ROM_ADDRESS_MASK; | |
229 | mask64 = (u32)PCI_ROM_ADDRESS_MASK; | |
6ac665c6 MW |
230 | } |
231 | ||
28c6821a | 232 | if (res->flags & IORESOURCE_MEM_64) { |
6ac665c6 MW |
233 | pci_read_config_dword(dev, pos + 4, &l); |
234 | pci_write_config_dword(dev, pos + 4, ~0); | |
235 | pci_read_config_dword(dev, pos + 4, &sz); | |
236 | pci_write_config_dword(dev, pos + 4, l); | |
237 | ||
238 | l64 |= ((u64)l << 32); | |
239 | sz64 |= ((u64)sz << 32); | |
f795d86a MS |
240 | mask64 |= ((u64)~0 << 32); |
241 | } | |
6ac665c6 | 242 | |
f795d86a MS |
243 | if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) |
244 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); | |
6ac665c6 | 245 | |
f795d86a MS |
246 | if (!sz64) |
247 | goto fail; | |
6ac665c6 | 248 | |
f795d86a | 249 | sz64 = pci_size(l64, sz64, mask64); |
7e79c5f8 MS |
250 | if (!sz64) { |
251 | dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", | |
252 | pos); | |
f795d86a | 253 | goto fail; |
7e79c5f8 | 254 | } |
f795d86a MS |
255 | |
256 | if (res->flags & IORESOURCE_MEM_64) { | |
3a9ad0b4 YL |
257 | if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) |
258 | && sz64 > 0x100000000ULL) { | |
23b13bc7 BH |
259 | res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; |
260 | res->start = 0; | |
261 | res->end = 0; | |
f795d86a MS |
262 | dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", |
263 | pos, (unsigned long long)sz64); | |
23b13bc7 | 264 | goto out; |
c7dabef8 BH |
265 | } |
266 | ||
3a9ad0b4 | 267 | if ((sizeof(pci_bus_addr_t) < 8) && l) { |
31e9dd25 | 268 | /* Above 32-bit boundary; try to reallocate */ |
c83bd900 | 269 | res->flags |= IORESOURCE_UNSET; |
72dc5601 BH |
270 | res->start = 0; |
271 | res->end = sz64; | |
f795d86a MS |
272 | dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", |
273 | pos, (unsigned long long)l64); | |
72dc5601 | 274 | goto out; |
6ac665c6 | 275 | } |
6ac665c6 MW |
276 | } |
277 | ||
f795d86a MS |
278 | region.start = l64; |
279 | region.end = l64 + sz64; | |
280 | ||
fc279850 YL |
281 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
282 | pcibios_resource_to_bus(dev->bus, &inverted_region, res); | |
cf4d1cf5 KH |
283 | |
284 | /* | |
285 | * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is | |
286 | * the corresponding resource address (the physical address used by | |
287 | * the CPU. Converting that resource address back to a bus address | |
288 | * should yield the original BAR value: | |
289 | * | |
290 | * resource_to_bus(bus_to_resource(A)) == A | |
291 | * | |
292 | * If it doesn't, CPU accesses to "bus_to_resource(A)" will not | |
293 | * be claimed by the device. | |
294 | */ | |
295 | if (inverted_region.start != region.start) { | |
cf4d1cf5 | 296 | res->flags |= IORESOURCE_UNSET; |
cf4d1cf5 | 297 | res->start = 0; |
26370fc6 | 298 | res->end = region.end - region.start; |
f795d86a MS |
299 | dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n", |
300 | pos, (unsigned long long)region.start); | |
cf4d1cf5 | 301 | } |
96ddef25 | 302 | |
0ff9514b BH |
303 | goto out; |
304 | ||
305 | ||
306 | fail: | |
307 | res->flags = 0; | |
308 | out: | |
31e9dd25 | 309 | if (res->flags) |
33963e30 | 310 | dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res); |
0ff9514b | 311 | |
28c6821a | 312 | return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; |
07eddf3d YL |
313 | } |
314 | ||
1da177e4 LT |
315 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
316 | { | |
6ac665c6 | 317 | unsigned int pos, reg; |
07eddf3d | 318 | |
6ac665c6 MW |
319 | for (pos = 0; pos < howmany; pos++) { |
320 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 321 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 322 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 323 | } |
6ac665c6 | 324 | |
1da177e4 | 325 | if (rom) { |
6ac665c6 | 326 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 327 | dev->rom_base_reg = rom; |
6ac665c6 | 328 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
92b19ff5 | 329 | IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; |
6ac665c6 | 330 | __pci_read_base(dev, pci_bar_mem32, res, rom); |
1da177e4 LT |
331 | } |
332 | } | |
333 | ||
15856ad5 | 334 | static void pci_read_bridge_io(struct pci_bus *child) |
1da177e4 LT |
335 | { |
336 | struct pci_dev *dev = child->self; | |
337 | u8 io_base_lo, io_limit_lo; | |
2b28ae19 | 338 | unsigned long io_mask, io_granularity, base, limit; |
5bfa14ed | 339 | struct pci_bus_region region; |
2b28ae19 BH |
340 | struct resource *res; |
341 | ||
342 | io_mask = PCI_IO_RANGE_MASK; | |
343 | io_granularity = 0x1000; | |
344 | if (dev->io_window_1k) { | |
345 | /* Support 1K I/O space granularity */ | |
346 | io_mask = PCI_IO_1K_RANGE_MASK; | |
347 | io_granularity = 0x400; | |
348 | } | |
1da177e4 | 349 | |
1da177e4 LT |
350 | res = child->resource[0]; |
351 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
352 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
2b28ae19 BH |
353 | base = (io_base_lo & io_mask) << 8; |
354 | limit = (io_limit_lo & io_mask) << 8; | |
1da177e4 LT |
355 | |
356 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
357 | u16 io_base_hi, io_limit_hi; | |
8f38eaca | 358 | |
1da177e4 LT |
359 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); |
360 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
8f38eaca BH |
361 | base |= ((unsigned long) io_base_hi << 16); |
362 | limit |= ((unsigned long) io_limit_hi << 16); | |
1da177e4 LT |
363 | } |
364 | ||
5dde383e | 365 | if (base <= limit) { |
1da177e4 | 366 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
5bfa14ed | 367 | region.start = base; |
2b28ae19 | 368 | region.end = limit + io_granularity - 1; |
fc279850 | 369 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
c7dabef8 | 370 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 | 371 | } |
fa27b2d1 BH |
372 | } |
373 | ||
15856ad5 | 374 | static void pci_read_bridge_mmio(struct pci_bus *child) |
fa27b2d1 BH |
375 | { |
376 | struct pci_dev *dev = child->self; | |
377 | u16 mem_base_lo, mem_limit_lo; | |
378 | unsigned long base, limit; | |
5bfa14ed | 379 | struct pci_bus_region region; |
fa27b2d1 | 380 | struct resource *res; |
1da177e4 LT |
381 | |
382 | res = child->resource[1]; | |
383 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
384 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
8f38eaca BH |
385 | base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; |
386 | limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
5dde383e | 387 | if (base <= limit) { |
1da177e4 | 388 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
5bfa14ed BH |
389 | region.start = base; |
390 | region.end = limit + 0xfffff; | |
fc279850 | 391 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
c7dabef8 | 392 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 | 393 | } |
fa27b2d1 BH |
394 | } |
395 | ||
15856ad5 | 396 | static void pci_read_bridge_mmio_pref(struct pci_bus *child) |
fa27b2d1 BH |
397 | { |
398 | struct pci_dev *dev = child->self; | |
399 | u16 mem_base_lo, mem_limit_lo; | |
7fc986d8 | 400 | u64 base64, limit64; |
3a9ad0b4 | 401 | pci_bus_addr_t base, limit; |
5bfa14ed | 402 | struct pci_bus_region region; |
fa27b2d1 | 403 | struct resource *res; |
1da177e4 LT |
404 | |
405 | res = child->resource[2]; | |
406 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
407 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
7fc986d8 YL |
408 | base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; |
409 | limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
1da177e4 LT |
410 | |
411 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
412 | u32 mem_base_hi, mem_limit_hi; | |
8f38eaca | 413 | |
1da177e4 LT |
414 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); |
415 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
416 | ||
417 | /* | |
418 | * Some bridges set the base > limit by default, and some | |
419 | * (broken) BIOSes do not initialize them. If we find | |
420 | * this, just assume they are not being used. | |
421 | */ | |
422 | if (mem_base_hi <= mem_limit_hi) { | |
7fc986d8 YL |
423 | base64 |= (u64) mem_base_hi << 32; |
424 | limit64 |= (u64) mem_limit_hi << 32; | |
1da177e4 LT |
425 | } |
426 | } | |
7fc986d8 | 427 | |
3a9ad0b4 YL |
428 | base = (pci_bus_addr_t) base64; |
429 | limit = (pci_bus_addr_t) limit64; | |
7fc986d8 YL |
430 | |
431 | if (base != base64) { | |
432 | dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", | |
433 | (unsigned long long) base64); | |
434 | return; | |
435 | } | |
436 | ||
5dde383e | 437 | if (base <= limit) { |
1f82de10 YL |
438 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
439 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
440 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
441 | res->flags |= IORESOURCE_MEM_64; | |
5bfa14ed BH |
442 | region.start = base; |
443 | region.end = limit + 0xfffff; | |
fc279850 | 444 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
c7dabef8 | 445 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 LT |
446 | } |
447 | } | |
448 | ||
15856ad5 | 449 | void pci_read_bridge_bases(struct pci_bus *child) |
fa27b2d1 BH |
450 | { |
451 | struct pci_dev *dev = child->self; | |
2fe2abf8 | 452 | struct resource *res; |
fa27b2d1 BH |
453 | int i; |
454 | ||
455 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ | |
456 | return; | |
457 | ||
b918c62e YL |
458 | dev_info(&dev->dev, "PCI bridge to %pR%s\n", |
459 | &child->busn_res, | |
fa27b2d1 BH |
460 | dev->transparent ? " (subtractive decode)" : ""); |
461 | ||
2fe2abf8 BH |
462 | pci_bus_remove_resources(child); |
463 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
464 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
465 | ||
fa27b2d1 BH |
466 | pci_read_bridge_io(child); |
467 | pci_read_bridge_mmio(child); | |
468 | pci_read_bridge_mmio_pref(child); | |
2adf7516 BH |
469 | |
470 | if (dev->transparent) { | |
2fe2abf8 | 471 | pci_bus_for_each_resource(child->parent, res, i) { |
d739a099 | 472 | if (res && res->flags) { |
2fe2abf8 BH |
473 | pci_bus_add_resource(child, res, |
474 | PCI_SUBTRACTIVE_DECODE); | |
2adf7516 BH |
475 | dev_printk(KERN_DEBUG, &dev->dev, |
476 | " bridge window %pR (subtractive decode)\n", | |
2fe2abf8 BH |
477 | res); |
478 | } | |
2adf7516 BH |
479 | } |
480 | } | |
fa27b2d1 BH |
481 | } |
482 | ||
670ba0c8 | 483 | static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) |
1da177e4 LT |
484 | { |
485 | struct pci_bus *b; | |
486 | ||
f5afe806 | 487 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
05013486 BH |
488 | if (!b) |
489 | return NULL; | |
490 | ||
491 | INIT_LIST_HEAD(&b->node); | |
492 | INIT_LIST_HEAD(&b->children); | |
493 | INIT_LIST_HEAD(&b->devices); | |
494 | INIT_LIST_HEAD(&b->slots); | |
495 | INIT_LIST_HEAD(&b->resources); | |
496 | b->max_bus_speed = PCI_SPEED_UNKNOWN; | |
497 | b->cur_bus_speed = PCI_SPEED_UNKNOWN; | |
670ba0c8 CM |
498 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
499 | if (parent) | |
500 | b->domain_nr = parent->domain_nr; | |
501 | #endif | |
1da177e4 LT |
502 | return b; |
503 | } | |
504 | ||
70efde2a JL |
505 | static void pci_release_host_bridge_dev(struct device *dev) |
506 | { | |
507 | struct pci_host_bridge *bridge = to_pci_host_bridge(dev); | |
508 | ||
509 | if (bridge->release_fn) | |
510 | bridge->release_fn(bridge); | |
511 | ||
512 | pci_free_resource_list(&bridge->windows); | |
513 | ||
514 | kfree(bridge); | |
515 | } | |
516 | ||
7b543663 YL |
517 | static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b) |
518 | { | |
519 | struct pci_host_bridge *bridge; | |
520 | ||
521 | bridge = kzalloc(sizeof(*bridge), GFP_KERNEL); | |
05013486 BH |
522 | if (!bridge) |
523 | return NULL; | |
7b543663 | 524 | |
05013486 BH |
525 | INIT_LIST_HEAD(&bridge->windows); |
526 | bridge->bus = b; | |
7b543663 YL |
527 | return bridge; |
528 | } | |
529 | ||
0b950f0f | 530 | static const unsigned char pcix_bus_speed[] = { |
9be60ca0 MW |
531 | PCI_SPEED_UNKNOWN, /* 0 */ |
532 | PCI_SPEED_66MHz_PCIX, /* 1 */ | |
533 | PCI_SPEED_100MHz_PCIX, /* 2 */ | |
534 | PCI_SPEED_133MHz_PCIX, /* 3 */ | |
535 | PCI_SPEED_UNKNOWN, /* 4 */ | |
536 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ | |
537 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ | |
538 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ | |
539 | PCI_SPEED_UNKNOWN, /* 8 */ | |
540 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ | |
541 | PCI_SPEED_100MHz_PCIX_266, /* A */ | |
542 | PCI_SPEED_133MHz_PCIX_266, /* B */ | |
543 | PCI_SPEED_UNKNOWN, /* C */ | |
544 | PCI_SPEED_66MHz_PCIX_533, /* D */ | |
545 | PCI_SPEED_100MHz_PCIX_533, /* E */ | |
546 | PCI_SPEED_133MHz_PCIX_533 /* F */ | |
547 | }; | |
548 | ||
343e51ae | 549 | const unsigned char pcie_link_speed[] = { |
3749c51a MW |
550 | PCI_SPEED_UNKNOWN, /* 0 */ |
551 | PCIE_SPEED_2_5GT, /* 1 */ | |
552 | PCIE_SPEED_5_0GT, /* 2 */ | |
9dfd97fe | 553 | PCIE_SPEED_8_0GT, /* 3 */ |
3749c51a MW |
554 | PCI_SPEED_UNKNOWN, /* 4 */ |
555 | PCI_SPEED_UNKNOWN, /* 5 */ | |
556 | PCI_SPEED_UNKNOWN, /* 6 */ | |
557 | PCI_SPEED_UNKNOWN, /* 7 */ | |
558 | PCI_SPEED_UNKNOWN, /* 8 */ | |
559 | PCI_SPEED_UNKNOWN, /* 9 */ | |
560 | PCI_SPEED_UNKNOWN, /* A */ | |
561 | PCI_SPEED_UNKNOWN, /* B */ | |
562 | PCI_SPEED_UNKNOWN, /* C */ | |
563 | PCI_SPEED_UNKNOWN, /* D */ | |
564 | PCI_SPEED_UNKNOWN, /* E */ | |
565 | PCI_SPEED_UNKNOWN /* F */ | |
566 | }; | |
567 | ||
568 | void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) | |
569 | { | |
231afea1 | 570 | bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; |
3749c51a MW |
571 | } |
572 | EXPORT_SYMBOL_GPL(pcie_update_link_speed); | |
573 | ||
45b4cdd5 MW |
574 | static unsigned char agp_speeds[] = { |
575 | AGP_UNKNOWN, | |
576 | AGP_1X, | |
577 | AGP_2X, | |
578 | AGP_4X, | |
579 | AGP_8X | |
580 | }; | |
581 | ||
582 | static enum pci_bus_speed agp_speed(int agp3, int agpstat) | |
583 | { | |
584 | int index = 0; | |
585 | ||
586 | if (agpstat & 4) | |
587 | index = 3; | |
588 | else if (agpstat & 2) | |
589 | index = 2; | |
590 | else if (agpstat & 1) | |
591 | index = 1; | |
592 | else | |
593 | goto out; | |
f7625980 | 594 | |
45b4cdd5 MW |
595 | if (agp3) { |
596 | index += 2; | |
597 | if (index == 5) | |
598 | index = 0; | |
599 | } | |
600 | ||
601 | out: | |
602 | return agp_speeds[index]; | |
603 | } | |
604 | ||
9be60ca0 MW |
605 | static void pci_set_bus_speed(struct pci_bus *bus) |
606 | { | |
607 | struct pci_dev *bridge = bus->self; | |
608 | int pos; | |
609 | ||
45b4cdd5 MW |
610 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
611 | if (!pos) | |
612 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); | |
613 | if (pos) { | |
614 | u32 agpstat, agpcmd; | |
615 | ||
616 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); | |
617 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); | |
618 | ||
619 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); | |
620 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); | |
621 | } | |
622 | ||
9be60ca0 MW |
623 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
624 | if (pos) { | |
625 | u16 status; | |
626 | enum pci_bus_speed max; | |
9be60ca0 | 627 | |
7793eeab BH |
628 | pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, |
629 | &status); | |
630 | ||
631 | if (status & PCI_X_SSTATUS_533MHZ) { | |
9be60ca0 | 632 | max = PCI_SPEED_133MHz_PCIX_533; |
7793eeab | 633 | } else if (status & PCI_X_SSTATUS_266MHZ) { |
9be60ca0 | 634 | max = PCI_SPEED_133MHz_PCIX_266; |
7793eeab | 635 | } else if (status & PCI_X_SSTATUS_133MHZ) { |
3c78bc61 | 636 | if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) |
9be60ca0 | 637 | max = PCI_SPEED_133MHz_PCIX_ECC; |
3c78bc61 | 638 | else |
9be60ca0 | 639 | max = PCI_SPEED_133MHz_PCIX; |
9be60ca0 MW |
640 | } else { |
641 | max = PCI_SPEED_66MHz_PCIX; | |
642 | } | |
643 | ||
644 | bus->max_bus_speed = max; | |
7793eeab BH |
645 | bus->cur_bus_speed = pcix_bus_speed[ |
646 | (status & PCI_X_SSTATUS_FREQ) >> 6]; | |
9be60ca0 MW |
647 | |
648 | return; | |
649 | } | |
650 | ||
fdfe1511 | 651 | if (pci_is_pcie(bridge)) { |
9be60ca0 MW |
652 | u32 linkcap; |
653 | u16 linksta; | |
654 | ||
59875ae4 | 655 | pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); |
231afea1 | 656 | bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; |
9be60ca0 | 657 | |
59875ae4 | 658 | pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); |
9be60ca0 MW |
659 | pcie_update_link_speed(bus, linksta); |
660 | } | |
661 | } | |
662 | ||
44aa0c65 MZ |
663 | static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) |
664 | { | |
b165e2b6 MZ |
665 | struct irq_domain *d; |
666 | ||
44aa0c65 MZ |
667 | /* |
668 | * Any firmware interface that can resolve the msi_domain | |
669 | * should be called from here. | |
670 | */ | |
b165e2b6 | 671 | d = pci_host_bridge_of_msi_domain(bus); |
44aa0c65 | 672 | |
b165e2b6 | 673 | return d; |
44aa0c65 MZ |
674 | } |
675 | ||
676 | static void pci_set_bus_msi_domain(struct pci_bus *bus) | |
677 | { | |
678 | struct irq_domain *d; | |
38ea72bd | 679 | struct pci_bus *b; |
44aa0c65 MZ |
680 | |
681 | /* | |
38ea72bd AW |
682 | * The bus can be a root bus, a subordinate bus, or a virtual bus |
683 | * created by an SR-IOV device. Walk up to the first bridge device | |
684 | * found or derive the domain from the host bridge. | |
44aa0c65 | 685 | */ |
38ea72bd AW |
686 | for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { |
687 | if (b->self) | |
688 | d = dev_get_msi_domain(&b->self->dev); | |
689 | } | |
690 | ||
691 | if (!d) | |
692 | d = pci_host_bridge_msi_domain(b); | |
44aa0c65 MZ |
693 | |
694 | dev_set_msi_domain(&bus->dev, d); | |
695 | } | |
696 | ||
cbd4e055 AB |
697 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
698 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
699 | { |
700 | struct pci_bus *child; | |
701 | int i; | |
4f535093 | 702 | int ret; |
1da177e4 LT |
703 | |
704 | /* | |
705 | * Allocate a new bus, and inherit stuff from the parent.. | |
706 | */ | |
670ba0c8 | 707 | child = pci_alloc_bus(parent); |
1da177e4 LT |
708 | if (!child) |
709 | return NULL; | |
710 | ||
1da177e4 LT |
711 | child->parent = parent; |
712 | child->ops = parent->ops; | |
0cbdcfcf | 713 | child->msi = parent->msi; |
1da177e4 | 714 | child->sysdata = parent->sysdata; |
6e325a62 | 715 | child->bus_flags = parent->bus_flags; |
1da177e4 | 716 | |
fd7d1ced | 717 | /* initialize some portions of the bus device, but don't register it |
4f535093 | 718 | * now as the parent is not properly set up yet. |
fd7d1ced GKH |
719 | */ |
720 | child->dev.class = &pcibus_class; | |
1a927133 | 721 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 LT |
722 | |
723 | /* | |
724 | * Set up the primary, secondary and subordinate | |
725 | * bus numbers. | |
726 | */ | |
b918c62e YL |
727 | child->number = child->busn_res.start = busnr; |
728 | child->primary = parent->busn_res.start; | |
729 | child->busn_res.end = 0xff; | |
1da177e4 | 730 | |
4f535093 YL |
731 | if (!bridge) { |
732 | child->dev.parent = parent->bridge; | |
733 | goto add_dev; | |
734 | } | |
3789fa8a YZ |
735 | |
736 | child->self = bridge; | |
737 | child->bridge = get_device(&bridge->dev); | |
4f535093 | 738 | child->dev.parent = child->bridge; |
98d9f30c | 739 | pci_set_bus_of_node(child); |
9be60ca0 MW |
740 | pci_set_bus_speed(child); |
741 | ||
1da177e4 | 742 | /* Set up default resource pointers and names.. */ |
fde09c6d | 743 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
744 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
745 | child->resource[i]->name = child->name; | |
746 | } | |
747 | bridge->subordinate = child; | |
748 | ||
4f535093 | 749 | add_dev: |
44aa0c65 | 750 | pci_set_bus_msi_domain(child); |
4f535093 YL |
751 | ret = device_register(&child->dev); |
752 | WARN_ON(ret < 0); | |
753 | ||
10a95747 JL |
754 | pcibios_add_bus(child); |
755 | ||
4f535093 YL |
756 | /* Create legacy_io and legacy_mem files for this bus */ |
757 | pci_create_legacy_files(child); | |
758 | ||
1da177e4 LT |
759 | return child; |
760 | } | |
761 | ||
3c78bc61 RD |
762 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
763 | int busnr) | |
1da177e4 LT |
764 | { |
765 | struct pci_bus *child; | |
766 | ||
767 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 768 | if (child) { |
d71374da | 769 | down_write(&pci_bus_sem); |
1da177e4 | 770 | list_add_tail(&child->node, &parent->children); |
d71374da | 771 | up_write(&pci_bus_sem); |
e4ea9bb7 | 772 | } |
1da177e4 LT |
773 | return child; |
774 | } | |
b7fe9434 | 775 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 | 776 | |
f3dbd802 RJ |
777 | static void pci_enable_crs(struct pci_dev *pdev) |
778 | { | |
779 | u16 root_cap = 0; | |
780 | ||
781 | /* Enable CRS Software Visibility if supported */ | |
782 | pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); | |
783 | if (root_cap & PCI_EXP_RTCAP_CRSVIS) | |
784 | pcie_capability_set_word(pdev, PCI_EXP_RTCTL, | |
785 | PCI_EXP_RTCTL_CRSSVE); | |
786 | } | |
787 | ||
1da177e4 LT |
788 | /* |
789 | * If it's a bridge, configure it and scan the bus behind it. | |
790 | * For CardBus bridges, we don't scan behind as the devices will | |
791 | * be handled by the bridge driver itself. | |
792 | * | |
793 | * We need to process bridges in two passes -- first we scan those | |
794 | * already configured by the BIOS and after we are done with all of | |
795 | * them, we proceed to assigning numbers to the remaining buses in | |
796 | * order to avoid overlaps between old and new bus numbers. | |
797 | */ | |
15856ad5 | 798 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
799 | { |
800 | struct pci_bus *child; | |
801 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 802 | u32 buses, i, j = 0; |
1da177e4 | 803 | u16 bctl; |
99ddd552 | 804 | u8 primary, secondary, subordinate; |
a1c19894 | 805 | int broken = 0; |
1da177e4 LT |
806 | |
807 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
99ddd552 BH |
808 | primary = buses & 0xFF; |
809 | secondary = (buses >> 8) & 0xFF; | |
810 | subordinate = (buses >> 16) & 0xFF; | |
1da177e4 | 811 | |
99ddd552 BH |
812 | dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", |
813 | secondary, subordinate, pass); | |
1da177e4 | 814 | |
71f6bd4a YL |
815 | if (!primary && (primary != bus->number) && secondary && subordinate) { |
816 | dev_warn(&dev->dev, "Primary bus is hard wired to 0\n"); | |
817 | primary = bus->number; | |
818 | } | |
819 | ||
a1c19894 BH |
820 | /* Check if setup is sensible at all */ |
821 | if (!pass && | |
1965f66e | 822 | (primary != bus->number || secondary <= bus->number || |
12d87069 | 823 | secondary > subordinate)) { |
1965f66e YL |
824 | dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", |
825 | secondary, subordinate); | |
a1c19894 BH |
826 | broken = 1; |
827 | } | |
828 | ||
1da177e4 | 829 | /* Disable MasterAbortMode during probing to avoid reporting |
f7625980 | 830 | of bus errors (in some architectures) */ |
1da177e4 LT |
831 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
832 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
833 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
834 | ||
f3dbd802 RJ |
835 | pci_enable_crs(dev); |
836 | ||
99ddd552 BH |
837 | if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
838 | !is_cardbus && !broken) { | |
839 | unsigned int cmax; | |
1da177e4 LT |
840 | /* |
841 | * Bus already configured by firmware, process it in the first | |
842 | * pass and just note the configuration. | |
843 | */ | |
844 | if (pass) | |
bbe8f9a3 | 845 | goto out; |
1da177e4 LT |
846 | |
847 | /* | |
2ed85823 AN |
848 | * The bus might already exist for two reasons: Either we are |
849 | * rescanning the bus or the bus is reachable through more than | |
850 | * one bridge. The second case can happen with the i450NX | |
851 | * chipset. | |
1da177e4 | 852 | */ |
99ddd552 | 853 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
74710ded | 854 | if (!child) { |
99ddd552 | 855 | child = pci_add_new_bus(bus, dev, secondary); |
74710ded AC |
856 | if (!child) |
857 | goto out; | |
99ddd552 | 858 | child->primary = primary; |
bc76b731 | 859 | pci_bus_insert_busn_res(child, secondary, subordinate); |
74710ded | 860 | child->bridge_ctl = bctl; |
1da177e4 LT |
861 | } |
862 | ||
1da177e4 | 863 | cmax = pci_scan_child_bus(child); |
c95b0bd6 AN |
864 | if (cmax > subordinate) |
865 | dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n", | |
866 | subordinate, cmax); | |
867 | /* subordinate should equal child->busn_res.end */ | |
868 | if (subordinate > max) | |
869 | max = subordinate; | |
1da177e4 LT |
870 | } else { |
871 | /* | |
872 | * We need to assign a number to this bus which we always | |
873 | * do in the second pass. | |
874 | */ | |
12f44f46 | 875 | if (!pass) { |
619c8c31 | 876 | if (pcibios_assign_all_busses() || broken || is_cardbus) |
12f44f46 IK |
877 | /* Temporarily disable forwarding of the |
878 | configuration cycles on all bridges in | |
879 | this bus segment to avoid possible | |
880 | conflicts in the second pass between two | |
881 | bridges programmed with overlapping | |
882 | bus ranges. */ | |
883 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
884 | buses & ~0xffffff); | |
bbe8f9a3 | 885 | goto out; |
12f44f46 | 886 | } |
1da177e4 LT |
887 | |
888 | /* Clear errors */ | |
889 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
890 | ||
7a0b33d4 BH |
891 | /* Prevent assigning a bus number that already exists. |
892 | * This can happen when a bridge is hot-plugged, so in | |
893 | * this case we only re-scan this bus. */ | |
b1a98b69 TC |
894 | child = pci_find_bus(pci_domain_nr(bus), max+1); |
895 | if (!child) { | |
9a4d7d87 | 896 | child = pci_add_new_bus(bus, dev, max+1); |
b1a98b69 TC |
897 | if (!child) |
898 | goto out; | |
12d87069 | 899 | pci_bus_insert_busn_res(child, max+1, 0xff); |
b1a98b69 | 900 | } |
9a4d7d87 | 901 | max++; |
1da177e4 LT |
902 | buses = (buses & 0xff000000) |
903 | | ((unsigned int)(child->primary) << 0) | |
b918c62e YL |
904 | | ((unsigned int)(child->busn_res.start) << 8) |
905 | | ((unsigned int)(child->busn_res.end) << 16); | |
1da177e4 LT |
906 | |
907 | /* | |
908 | * yenta.c forces a secondary latency timer of 176. | |
909 | * Copy that behaviour here. | |
910 | */ | |
911 | if (is_cardbus) { | |
912 | buses &= ~0xff000000; | |
913 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
914 | } | |
7c867c88 | 915 | |
1da177e4 LT |
916 | /* |
917 | * We need to blast all three values with a single write. | |
918 | */ | |
919 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
920 | ||
921 | if (!is_cardbus) { | |
11949255 | 922 | child->bridge_ctl = bctl; |
1da177e4 LT |
923 | max = pci_scan_child_bus(child); |
924 | } else { | |
925 | /* | |
926 | * For CardBus bridges, we leave 4 bus numbers | |
927 | * as cards with a PCI-to-PCI bridge can be | |
928 | * inserted later. | |
929 | */ | |
3c78bc61 | 930 | for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { |
49887941 | 931 | struct pci_bus *parent = bus; |
cc57450f RS |
932 | if (pci_find_bus(pci_domain_nr(bus), |
933 | max+i+1)) | |
934 | break; | |
49887941 DB |
935 | while (parent->parent) { |
936 | if ((!pcibios_assign_all_busses()) && | |
b918c62e YL |
937 | (parent->busn_res.end > max) && |
938 | (parent->busn_res.end <= max+i)) { | |
49887941 DB |
939 | j = 1; |
940 | } | |
941 | parent = parent->parent; | |
942 | } | |
943 | if (j) { | |
944 | /* | |
945 | * Often, there are two cardbus bridges | |
946 | * -- try to leave one valid bus number | |
947 | * for each one. | |
948 | */ | |
949 | i /= 2; | |
950 | break; | |
951 | } | |
952 | } | |
cc57450f | 953 | max += i; |
1da177e4 LT |
954 | } |
955 | /* | |
956 | * Set the subordinate bus number to its real value. | |
957 | */ | |
bc76b731 | 958 | pci_bus_update_busn_res_end(child, max); |
1da177e4 LT |
959 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
960 | } | |
961 | ||
cb3576fa GH |
962 | sprintf(child->name, |
963 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
964 | pci_domain_nr(bus), child->number); | |
1da177e4 | 965 | |
d55bef51 | 966 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 | 967 | while (bus->parent) { |
b918c62e YL |
968 | if ((child->busn_res.end > bus->busn_res.end) || |
969 | (child->number > bus->busn_res.end) || | |
49887941 | 970 | (child->number < bus->number) || |
b918c62e | 971 | (child->busn_res.end < bus->number)) { |
227f0647 | 972 | dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n", |
b918c62e YL |
973 | &child->busn_res, |
974 | (bus->number > child->busn_res.end && | |
975 | bus->busn_res.end < child->number) ? | |
a6f29a98 JP |
976 | "wholly" : "partially", |
977 | bus->self->transparent ? " transparent" : "", | |
865df576 | 978 | dev_name(&bus->dev), |
b918c62e | 979 | &bus->busn_res); |
49887941 DB |
980 | } |
981 | bus = bus->parent; | |
982 | } | |
983 | ||
bbe8f9a3 RB |
984 | out: |
985 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
986 | ||
1da177e4 LT |
987 | return max; |
988 | } | |
b7fe9434 | 989 | EXPORT_SYMBOL(pci_scan_bridge); |
1da177e4 LT |
990 | |
991 | /* | |
992 | * Read interrupt line and base address registers. | |
993 | * The architecture-dependent code can tweak these, of course. | |
994 | */ | |
995 | static void pci_read_irq(struct pci_dev *dev) | |
996 | { | |
997 | unsigned char irq; | |
998 | ||
999 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 1000 | dev->pin = irq; |
1da177e4 LT |
1001 | if (irq) |
1002 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
1003 | dev->irq = irq; | |
1004 | } | |
1005 | ||
bb209c82 | 1006 | void set_pcie_port_type(struct pci_dev *pdev) |
480b93b7 YZ |
1007 | { |
1008 | int pos; | |
1009 | u16 reg16; | |
d0751b98 YW |
1010 | int type; |
1011 | struct pci_dev *parent; | |
480b93b7 YZ |
1012 | |
1013 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
1014 | if (!pos) | |
1015 | return; | |
0efea000 | 1016 | pdev->pcie_cap = pos; |
480b93b7 | 1017 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
786e2288 | 1018 | pdev->pcie_flags_reg = reg16; |
b03e7495 JM |
1019 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); |
1020 | pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; | |
d0751b98 YW |
1021 | |
1022 | /* | |
1023 | * A Root Port is always the upstream end of a Link. No PCIe | |
1024 | * component has two Links. Two Links are connected by a Switch | |
1025 | * that has a Port on each Link and internal logic to connect the | |
1026 | * two Ports. | |
1027 | */ | |
1028 | type = pci_pcie_type(pdev); | |
1029 | if (type == PCI_EXP_TYPE_ROOT_PORT) | |
1030 | pdev->has_secondary_link = 1; | |
1031 | else if (type == PCI_EXP_TYPE_UPSTREAM || | |
1032 | type == PCI_EXP_TYPE_DOWNSTREAM) { | |
1033 | parent = pci_upstream_bridge(pdev); | |
b35b1df5 YW |
1034 | |
1035 | /* | |
1036 | * Usually there's an upstream device (Root Port or Switch | |
1037 | * Downstream Port), but we can't assume one exists. | |
1038 | */ | |
1039 | if (parent && !parent->has_secondary_link) | |
d0751b98 YW |
1040 | pdev->has_secondary_link = 1; |
1041 | } | |
480b93b7 YZ |
1042 | } |
1043 | ||
bb209c82 | 1044 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
28760489 | 1045 | { |
28760489 EB |
1046 | u32 reg32; |
1047 | ||
59875ae4 | 1048 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); |
28760489 EB |
1049 | if (reg32 & PCI_EXP_SLTCAP_HPC) |
1050 | pdev->is_hotplug_bridge = 1; | |
1051 | } | |
1052 | ||
78916b00 AW |
1053 | /** |
1054 | * pci_ext_cfg_is_aliased - is ext config space just an alias of std config? | |
1055 | * @dev: PCI device | |
1056 | * | |
1057 | * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that | |
1058 | * when forwarding a type1 configuration request the bridge must check that | |
1059 | * the extended register address field is zero. The bridge is not permitted | |
1060 | * to forward the transactions and must handle it as an Unsupported Request. | |
1061 | * Some bridges do not follow this rule and simply drop the extended register | |
1062 | * bits, resulting in the standard config space being aliased, every 256 | |
1063 | * bytes across the entire configuration space. Test for this condition by | |
1064 | * comparing the first dword of each potential alias to the vendor/device ID. | |
1065 | * Known offenders: | |
1066 | * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) | |
1067 | * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) | |
1068 | */ | |
1069 | static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) | |
1070 | { | |
1071 | #ifdef CONFIG_PCI_QUIRKS | |
1072 | int pos; | |
1073 | u32 header, tmp; | |
1074 | ||
1075 | pci_read_config_dword(dev, PCI_VENDOR_ID, &header); | |
1076 | ||
1077 | for (pos = PCI_CFG_SPACE_SIZE; | |
1078 | pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { | |
1079 | if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL | |
1080 | || header != tmp) | |
1081 | return false; | |
1082 | } | |
1083 | ||
1084 | return true; | |
1085 | #else | |
1086 | return false; | |
1087 | #endif | |
1088 | } | |
1089 | ||
0b950f0f SH |
1090 | /** |
1091 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
1092 | * @dev: PCI device | |
1093 | * | |
1094 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
1095 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
1096 | * access it. Maybe we don't have a way to generate extended config space | |
1097 | * accesses, or the device is behind a reverse Express bridge. So we try | |
1098 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
1099 | * capability header. | |
1100 | */ | |
1101 | static int pci_cfg_space_size_ext(struct pci_dev *dev) | |
1102 | { | |
1103 | u32 status; | |
1104 | int pos = PCI_CFG_SPACE_SIZE; | |
1105 | ||
1106 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) | |
1107 | goto fail; | |
78916b00 | 1108 | if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) |
0b950f0f SH |
1109 | goto fail; |
1110 | ||
1111 | return PCI_CFG_SPACE_EXP_SIZE; | |
1112 | ||
1113 | fail: | |
1114 | return PCI_CFG_SPACE_SIZE; | |
1115 | } | |
1116 | ||
1117 | int pci_cfg_space_size(struct pci_dev *dev) | |
1118 | { | |
1119 | int pos; | |
1120 | u32 status; | |
1121 | u16 class; | |
1122 | ||
1123 | class = dev->class >> 8; | |
1124 | if (class == PCI_CLASS_BRIDGE_HOST) | |
1125 | return pci_cfg_space_size_ext(dev); | |
1126 | ||
1127 | if (!pci_is_pcie(dev)) { | |
1128 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1129 | if (!pos) | |
1130 | goto fail; | |
1131 | ||
1132 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
1133 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
1134 | goto fail; | |
1135 | } | |
1136 | ||
1137 | return pci_cfg_space_size_ext(dev); | |
1138 | ||
1139 | fail: | |
1140 | return PCI_CFG_SPACE_SIZE; | |
1141 | } | |
1142 | ||
01abc2aa | 1143 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 1144 | |
22b6839b | 1145 | void pci_msi_setup_pci_dev(struct pci_dev *dev) |
1851617c MT |
1146 | { |
1147 | /* | |
1148 | * Disable the MSI hardware to avoid screaming interrupts | |
1149 | * during boot. This is the power on reset default so | |
1150 | * usually this should be a noop. | |
1151 | */ | |
1152 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1153 | if (dev->msi_cap) | |
1154 | pci_msi_set_enable(dev, 0); | |
1155 | ||
1156 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1157 | if (dev->msix_cap) | |
1158 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); | |
1159 | } | |
1160 | ||
1da177e4 LT |
1161 | /** |
1162 | * pci_setup_device - fill in class and map information of a device | |
1163 | * @dev: the device structure to fill | |
1164 | * | |
f7625980 | 1165 | * Initialize the device structure with information about the device's |
1da177e4 LT |
1166 | * vendor,class,memory and IO-space addresses,IRQ lines etc. |
1167 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
480b93b7 YZ |
1168 | * Returns 0 on success and negative if unknown type of device (not normal, |
1169 | * bridge or CardBus). | |
1da177e4 | 1170 | */ |
480b93b7 | 1171 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
1172 | { |
1173 | u32 class; | |
480b93b7 | 1174 | u8 hdr_type; |
bc577d2b | 1175 | int pos = 0; |
5bfa14ed BH |
1176 | struct pci_bus_region region; |
1177 | struct resource *res; | |
480b93b7 YZ |
1178 | |
1179 | if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) | |
1180 | return -EIO; | |
1181 | ||
1182 | dev->sysdata = dev->bus->sysdata; | |
1183 | dev->dev.parent = dev->bus->bridge; | |
1184 | dev->dev.bus = &pci_bus_type; | |
1185 | dev->hdr_type = hdr_type & 0x7f; | |
1186 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
1187 | dev->error_state = pci_channel_io_normal; |
1188 | set_pcie_port_type(dev); | |
1189 | ||
017ffe64 | 1190 | pci_dev_assign_slot(dev); |
480b93b7 YZ |
1191 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) |
1192 | set this higher, assuming the system even supports it. */ | |
1193 | dev->dma_mask = 0xffffffff; | |
1da177e4 | 1194 | |
eebfcfb5 GKH |
1195 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
1196 | dev->bus->number, PCI_SLOT(dev->devfn), | |
1197 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
1198 | |
1199 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 1200 | dev->revision = class & 0xff; |
2dd8ba92 | 1201 | dev->class = class >> 8; /* upper 3 bytes */ |
1da177e4 | 1202 | |
2dd8ba92 YL |
1203 | dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n", |
1204 | dev->vendor, dev->device, dev->hdr_type, dev->class); | |
1da177e4 | 1205 | |
853346e4 YZ |
1206 | /* need to have dev->class ready */ |
1207 | dev->cfg_size = pci_cfg_space_size(dev); | |
1208 | ||
1da177e4 | 1209 | /* "Unknown power state" */ |
3fe9d19f | 1210 | dev->current_state = PCI_UNKNOWN; |
1da177e4 | 1211 | |
1851617c MT |
1212 | pci_msi_setup_pci_dev(dev); |
1213 | ||
1da177e4 LT |
1214 | /* Early fixups, before probing the BARs */ |
1215 | pci_fixup_device(pci_fixup_early, dev); | |
f79b1b14 YZ |
1216 | /* device class may be changed after fixup */ |
1217 | class = dev->class >> 8; | |
1da177e4 LT |
1218 | |
1219 | switch (dev->hdr_type) { /* header type */ | |
1220 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
1221 | if (class == PCI_CLASS_BRIDGE_PCI) | |
1222 | goto bad; | |
1223 | pci_read_irq(dev); | |
1224 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
1225 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1226 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
1227 | |
1228 | /* | |
075eb9e3 BH |
1229 | * Do the ugly legacy mode stuff here rather than broken chip |
1230 | * quirk code. Legacy mode ATA controllers have fixed | |
1231 | * addresses. These are not always echoed in BAR0-3, and | |
1232 | * BAR0-3 in a few cases contain junk! | |
368c73d4 AC |
1233 | */ |
1234 | if (class == PCI_CLASS_STORAGE_IDE) { | |
1235 | u8 progif; | |
1236 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1237 | if ((progif & 1) == 0) { | |
5bfa14ed BH |
1238 | region.start = 0x1F0; |
1239 | region.end = 0x1F7; | |
1240 | res = &dev->resource[0]; | |
1241 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1242 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1243 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n", |
1244 | res); | |
5bfa14ed BH |
1245 | region.start = 0x3F6; |
1246 | region.end = 0x3F6; | |
1247 | res = &dev->resource[1]; | |
1248 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1249 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1250 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n", |
1251 | res); | |
368c73d4 AC |
1252 | } |
1253 | if ((progif & 4) == 0) { | |
5bfa14ed BH |
1254 | region.start = 0x170; |
1255 | region.end = 0x177; | |
1256 | res = &dev->resource[2]; | |
1257 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1258 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1259 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n", |
1260 | res); | |
5bfa14ed BH |
1261 | region.start = 0x376; |
1262 | region.end = 0x376; | |
1263 | res = &dev->resource[3]; | |
1264 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1265 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1266 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n", |
1267 | res); | |
368c73d4 AC |
1268 | } |
1269 | } | |
1da177e4 LT |
1270 | break; |
1271 | ||
1272 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
1273 | if (class != PCI_CLASS_BRIDGE_PCI) | |
1274 | goto bad; | |
1275 | /* The PCI-to-PCI bridge spec requires that subtractive | |
1276 | decoding (i.e. transparent) bridge must have programming | |
f7625980 | 1277 | interface code of 0x01. */ |
3efd273b | 1278 | pci_read_irq(dev); |
1da177e4 LT |
1279 | dev->transparent = ((dev->class & 0xff) == 1); |
1280 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
28760489 | 1281 | set_pcie_hotplug_bridge(dev); |
bc577d2b GB |
1282 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
1283 | if (pos) { | |
1284 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); | |
1285 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); | |
1286 | } | |
1da177e4 LT |
1287 | break; |
1288 | ||
1289 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
1290 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
1291 | goto bad; | |
1292 | pci_read_irq(dev); | |
1293 | pci_read_bases(dev, 1, 0); | |
1294 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1295 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
1296 | break; | |
1297 | ||
1298 | default: /* unknown header */ | |
227f0647 RD |
1299 | dev_err(&dev->dev, "unknown header type %02x, ignoring device\n", |
1300 | dev->hdr_type); | |
480b93b7 | 1301 | return -EIO; |
1da177e4 LT |
1302 | |
1303 | bad: | |
227f0647 RD |
1304 | dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n", |
1305 | dev->class, dev->hdr_type); | |
2b4aed1d | 1306 | dev->class = PCI_CLASS_NOT_DEFINED << 8; |
1da177e4 LT |
1307 | } |
1308 | ||
1309 | /* We found a fine healthy device, go go go... */ | |
1310 | return 0; | |
1311 | } | |
1312 | ||
9dae3a97 BH |
1313 | static void pci_configure_mps(struct pci_dev *dev) |
1314 | { | |
1315 | struct pci_dev *bridge = pci_upstream_bridge(dev); | |
27d868b5 | 1316 | int mps, p_mps, rc; |
9dae3a97 BH |
1317 | |
1318 | if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge)) | |
1319 | return; | |
1320 | ||
1321 | mps = pcie_get_mps(dev); | |
1322 | p_mps = pcie_get_mps(bridge); | |
1323 | ||
1324 | if (mps == p_mps) | |
1325 | return; | |
1326 | ||
1327 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { | |
1328 | dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", | |
1329 | mps, pci_name(bridge), p_mps); | |
1330 | return; | |
1331 | } | |
27d868b5 KB |
1332 | |
1333 | /* | |
1334 | * Fancier MPS configuration is done later by | |
1335 | * pcie_bus_configure_settings() | |
1336 | */ | |
1337 | if (pcie_bus_config != PCIE_BUS_DEFAULT) | |
1338 | return; | |
1339 | ||
1340 | rc = pcie_set_mps(dev, p_mps); | |
1341 | if (rc) { | |
1342 | dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", | |
1343 | p_mps); | |
1344 | return; | |
1345 | } | |
1346 | ||
1347 | dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n", | |
1348 | p_mps, mps, 128 << dev->pcie_mpss); | |
9dae3a97 BH |
1349 | } |
1350 | ||
589fcc23 BH |
1351 | static struct hpp_type0 pci_default_type0 = { |
1352 | .revision = 1, | |
1353 | .cache_line_size = 8, | |
1354 | .latency_timer = 0x40, | |
1355 | .enable_serr = 0, | |
1356 | .enable_perr = 0, | |
1357 | }; | |
1358 | ||
1359 | static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp) | |
1360 | { | |
1361 | u16 pci_cmd, pci_bctl; | |
1362 | ||
c6285fc5 | 1363 | if (!hpp) |
589fcc23 | 1364 | hpp = &pci_default_type0; |
589fcc23 BH |
1365 | |
1366 | if (hpp->revision > 1) { | |
1367 | dev_warn(&dev->dev, | |
1368 | "PCI settings rev %d not supported; using defaults\n", | |
1369 | hpp->revision); | |
1370 | hpp = &pci_default_type0; | |
1371 | } | |
1372 | ||
1373 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); | |
1374 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer); | |
1375 | pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); | |
1376 | if (hpp->enable_serr) | |
1377 | pci_cmd |= PCI_COMMAND_SERR; | |
589fcc23 BH |
1378 | if (hpp->enable_perr) |
1379 | pci_cmd |= PCI_COMMAND_PARITY; | |
589fcc23 BH |
1380 | pci_write_config_word(dev, PCI_COMMAND, pci_cmd); |
1381 | ||
1382 | /* Program bridge control value */ | |
1383 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
1384 | pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, | |
1385 | hpp->latency_timer); | |
1386 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); | |
1387 | if (hpp->enable_serr) | |
1388 | pci_bctl |= PCI_BRIDGE_CTL_SERR; | |
589fcc23 BH |
1389 | if (hpp->enable_perr) |
1390 | pci_bctl |= PCI_BRIDGE_CTL_PARITY; | |
589fcc23 BH |
1391 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); |
1392 | } | |
1393 | } | |
1394 | ||
1395 | static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp) | |
1396 | { | |
1397 | if (hpp) | |
1398 | dev_warn(&dev->dev, "PCI-X settings not supported\n"); | |
1399 | } | |
1400 | ||
1401 | static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) | |
1402 | { | |
1403 | int pos; | |
1404 | u32 reg32; | |
1405 | ||
1406 | if (!hpp) | |
1407 | return; | |
1408 | ||
1409 | if (hpp->revision > 1) { | |
1410 | dev_warn(&dev->dev, "PCIe settings rev %d not supported\n", | |
1411 | hpp->revision); | |
1412 | return; | |
1413 | } | |
1414 | ||
302328c0 BH |
1415 | /* |
1416 | * Don't allow _HPX to change MPS or MRRS settings. We manage | |
1417 | * those to make sure they're consistent with the rest of the | |
1418 | * platform. | |
1419 | */ | |
1420 | hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD | | |
1421 | PCI_EXP_DEVCTL_READRQ; | |
1422 | hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD | | |
1423 | PCI_EXP_DEVCTL_READRQ); | |
1424 | ||
589fcc23 BH |
1425 | /* Initialize Device Control Register */ |
1426 | pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, | |
1427 | ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or); | |
1428 | ||
1429 | /* Initialize Link Control Register */ | |
7a1562d4 | 1430 | if (pcie_cap_has_lnkctl(dev)) |
589fcc23 BH |
1431 | pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, |
1432 | ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or); | |
1433 | ||
1434 | /* Find Advanced Error Reporting Enhanced Capability */ | |
1435 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
1436 | if (!pos) | |
1437 | return; | |
1438 | ||
1439 | /* Initialize Uncorrectable Error Mask Register */ | |
1440 | pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); | |
1441 | reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or; | |
1442 | pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); | |
1443 | ||
1444 | /* Initialize Uncorrectable Error Severity Register */ | |
1445 | pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); | |
1446 | reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or; | |
1447 | pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); | |
1448 | ||
1449 | /* Initialize Correctable Error Mask Register */ | |
1450 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); | |
1451 | reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or; | |
1452 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); | |
1453 | ||
1454 | /* Initialize Advanced Error Capabilities and Control Register */ | |
1455 | pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); | |
1456 | reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or; | |
1457 | pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); | |
1458 | ||
1459 | /* | |
1460 | * FIXME: The following two registers are not supported yet. | |
1461 | * | |
1462 | * o Secondary Uncorrectable Error Severity Register | |
1463 | * o Secondary Uncorrectable Error Mask Register | |
1464 | */ | |
1465 | } | |
1466 | ||
6cd33649 BH |
1467 | static void pci_configure_device(struct pci_dev *dev) |
1468 | { | |
1469 | struct hotplug_params hpp; | |
1470 | int ret; | |
1471 | ||
9dae3a97 BH |
1472 | pci_configure_mps(dev); |
1473 | ||
6cd33649 BH |
1474 | memset(&hpp, 0, sizeof(hpp)); |
1475 | ret = pci_get_hp_params(dev, &hpp); | |
1476 | if (ret) | |
1477 | return; | |
1478 | ||
1479 | program_hpp_type2(dev, hpp.t2); | |
1480 | program_hpp_type1(dev, hpp.t1); | |
1481 | program_hpp_type0(dev, hpp.t0); | |
1482 | } | |
1483 | ||
201de56e ZY |
1484 | static void pci_release_capabilities(struct pci_dev *dev) |
1485 | { | |
1486 | pci_vpd_release(dev); | |
d1b054da | 1487 | pci_iov_release(dev); |
f796841e | 1488 | pci_free_cap_save_buffers(dev); |
201de56e ZY |
1489 | } |
1490 | ||
1da177e4 LT |
1491 | /** |
1492 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
1493 | * @dev: device that's been disconnected | |
1494 | * | |
1495 | * Will be called only by the device core when all users of this pci device are | |
1496 | * done. | |
1497 | */ | |
1498 | static void pci_release_dev(struct device *dev) | |
1499 | { | |
04480094 | 1500 | struct pci_dev *pci_dev; |
1da177e4 | 1501 | |
04480094 | 1502 | pci_dev = to_pci_dev(dev); |
201de56e | 1503 | pci_release_capabilities(pci_dev); |
98d9f30c | 1504 | pci_release_of_node(pci_dev); |
6ae32c53 | 1505 | pcibios_release_device(pci_dev); |
8b1fce04 | 1506 | pci_bus_put(pci_dev->bus); |
782a985d | 1507 | kfree(pci_dev->driver_override); |
1da177e4 LT |
1508 | kfree(pci_dev); |
1509 | } | |
1510 | ||
3c6e6ae7 | 1511 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus) |
65891215 ME |
1512 | { |
1513 | struct pci_dev *dev; | |
1514 | ||
1515 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
1516 | if (!dev) | |
1517 | return NULL; | |
1518 | ||
65891215 | 1519 | INIT_LIST_HEAD(&dev->bus_list); |
88e7b167 | 1520 | dev->dev.type = &pci_dev_type; |
3c6e6ae7 | 1521 | dev->bus = pci_bus_get(bus); |
65891215 ME |
1522 | |
1523 | return dev; | |
1524 | } | |
3c6e6ae7 GZ |
1525 | EXPORT_SYMBOL(pci_alloc_dev); |
1526 | ||
efdc87da | 1527 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, |
3c78bc61 | 1528 | int crs_timeout) |
1da177e4 | 1529 | { |
1da177e4 LT |
1530 | int delay = 1; |
1531 | ||
efdc87da YL |
1532 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
1533 | return false; | |
1da177e4 LT |
1534 | |
1535 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
efdc87da YL |
1536 | if (*l == 0xffffffff || *l == 0x00000000 || |
1537 | *l == 0x0000ffff || *l == 0xffff0000) | |
1538 | return false; | |
1da177e4 | 1539 | |
89665a6a RJ |
1540 | /* |
1541 | * Configuration Request Retry Status. Some root ports return the | |
1542 | * actual device ID instead of the synthetic ID (0xFFFF) required | |
1543 | * by the PCIe spec. Ignore the device ID and only check for | |
1544 | * (vendor id == 1). | |
1545 | */ | |
1546 | while ((*l & 0xffff) == 0x0001) { | |
efdc87da YL |
1547 | if (!crs_timeout) |
1548 | return false; | |
1549 | ||
1da177e4 LT |
1550 | msleep(delay); |
1551 | delay *= 2; | |
efdc87da YL |
1552 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
1553 | return false; | |
1da177e4 | 1554 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
efdc87da | 1555 | if (delay > crs_timeout) { |
227f0647 RD |
1556 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n", |
1557 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
1558 | PCI_FUNC(devfn)); | |
efdc87da | 1559 | return false; |
1da177e4 LT |
1560 | } |
1561 | } | |
1562 | ||
efdc87da YL |
1563 | return true; |
1564 | } | |
1565 | EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); | |
1566 | ||
1567 | /* | |
1568 | * Read the config data for a PCI device, sanity-check it | |
1569 | * and fill in the dev structure... | |
1570 | */ | |
1571 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) | |
1572 | { | |
1573 | struct pci_dev *dev; | |
1574 | u32 l; | |
1575 | ||
1576 | if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) | |
1577 | return NULL; | |
1578 | ||
8b1fce04 | 1579 | dev = pci_alloc_dev(bus); |
1da177e4 LT |
1580 | if (!dev) |
1581 | return NULL; | |
1582 | ||
1da177e4 | 1583 | dev->devfn = devfn; |
1da177e4 LT |
1584 | dev->vendor = l & 0xffff; |
1585 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 1586 | |
98d9f30c BH |
1587 | pci_set_of_node(dev); |
1588 | ||
480b93b7 | 1589 | if (pci_setup_device(dev)) { |
8b1fce04 | 1590 | pci_bus_put(dev->bus); |
1da177e4 LT |
1591 | kfree(dev); |
1592 | return NULL; | |
1593 | } | |
1da177e4 LT |
1594 | |
1595 | return dev; | |
1596 | } | |
1597 | ||
201de56e ZY |
1598 | static void pci_init_capabilities(struct pci_dev *dev) |
1599 | { | |
1600 | /* MSI/MSI-X list */ | |
1601 | pci_msi_init_pci_dev(dev); | |
1602 | ||
63f4898a RW |
1603 | /* Buffers for saving PCIe and PCI-X capabilities */ |
1604 | pci_allocate_cap_save_buffers(dev); | |
1605 | ||
201de56e ZY |
1606 | /* Power Management */ |
1607 | pci_pm_init(dev); | |
1608 | ||
1609 | /* Vital Product Data */ | |
1610 | pci_vpd_pci22_init(dev); | |
58c3a727 YZ |
1611 | |
1612 | /* Alternative Routing-ID Forwarding */ | |
31ab2476 | 1613 | pci_configure_ari(dev); |
d1b054da YZ |
1614 | |
1615 | /* Single Root I/O Virtualization */ | |
1616 | pci_iov_init(dev); | |
ae21ee65 | 1617 | |
edc90fee BH |
1618 | /* Address Translation Services */ |
1619 | pci_ats_init(dev); | |
1620 | ||
ae21ee65 | 1621 | /* Enable ACS P2P upstream forwarding */ |
5d990b62 | 1622 | pci_enable_acs(dev); |
201de56e ZY |
1623 | } |
1624 | ||
098259eb MZ |
1625 | /* |
1626 | * This is the equivalent of pci_host_bridge_msi_domain that acts on | |
1627 | * devices. Firmware interfaces that can select the MSI domain on a | |
1628 | * per-device basis should be called from here. | |
1629 | */ | |
1630 | static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) | |
1631 | { | |
1632 | struct irq_domain *d; | |
1633 | ||
1634 | /* | |
1635 | * If a domain has been set through the pcibios_add_device | |
1636 | * callback, then this is the one (platform code knows best). | |
1637 | */ | |
1638 | d = dev_get_msi_domain(&dev->dev); | |
1639 | if (d) | |
1640 | return d; | |
1641 | ||
54fa97ee MZ |
1642 | /* |
1643 | * Let's see if we have a firmware interface able to provide | |
1644 | * the domain. | |
1645 | */ | |
1646 | d = pci_msi_get_device_domain(dev); | |
1647 | if (d) | |
1648 | return d; | |
1649 | ||
098259eb MZ |
1650 | return NULL; |
1651 | } | |
1652 | ||
44aa0c65 MZ |
1653 | static void pci_set_msi_domain(struct pci_dev *dev) |
1654 | { | |
098259eb MZ |
1655 | struct irq_domain *d; |
1656 | ||
44aa0c65 | 1657 | /* |
098259eb MZ |
1658 | * If the platform or firmware interfaces cannot supply a |
1659 | * device-specific MSI domain, then inherit the default domain | |
1660 | * from the host bridge itself. | |
44aa0c65 | 1661 | */ |
098259eb MZ |
1662 | d = pci_dev_msi_domain(dev); |
1663 | if (!d) | |
1664 | d = dev_get_msi_domain(&dev->bus->dev); | |
1665 | ||
1666 | dev_set_msi_domain(&dev->dev, d); | |
44aa0c65 MZ |
1667 | } |
1668 | ||
96bde06a | 1669 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 1670 | { |
4f535093 YL |
1671 | int ret; |
1672 | ||
6cd33649 BH |
1673 | pci_configure_device(dev); |
1674 | ||
cdb9b9f7 PM |
1675 | device_initialize(&dev->dev); |
1676 | dev->dev.release = pci_release_dev; | |
1da177e4 | 1677 | |
7629d19a | 1678 | set_dev_node(&dev->dev, pcibus_to_node(bus)); |
cdb9b9f7 | 1679 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 1680 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 1681 | dev->dev.coherent_dma_mask = 0xffffffffull; |
de335bb4 | 1682 | of_pci_dma_configure(dev); |
1da177e4 | 1683 | |
4d57cdfa | 1684 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 1685 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 1686 | |
1da177e4 LT |
1687 | /* Fix up broken headers */ |
1688 | pci_fixup_device(pci_fixup_header, dev); | |
1689 | ||
2069ecfb YL |
1690 | /* moved out from quirk header fixup code */ |
1691 | pci_reassigndev_resource_alignment(dev); | |
1692 | ||
4b77b0a2 RW |
1693 | /* Clear the state_saved flag. */ |
1694 | dev->state_saved = false; | |
1695 | ||
201de56e ZY |
1696 | /* Initialize various capabilities */ |
1697 | pci_init_capabilities(dev); | |
eb9d0fe4 | 1698 | |
1da177e4 LT |
1699 | /* |
1700 | * Add the device to our list of discovered devices | |
1701 | * and the bus list for fixup functions, etc. | |
1702 | */ | |
d71374da | 1703 | down_write(&pci_bus_sem); |
1da177e4 | 1704 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1705 | up_write(&pci_bus_sem); |
4f535093 | 1706 | |
4f535093 YL |
1707 | ret = pcibios_add_device(dev); |
1708 | WARN_ON(ret < 0); | |
1709 | ||
44aa0c65 MZ |
1710 | /* Setup MSI irq domain */ |
1711 | pci_set_msi_domain(dev); | |
1712 | ||
4f535093 YL |
1713 | /* Notifier could use PCI capabilities */ |
1714 | dev->match_driver = false; | |
1715 | ret = device_add(&dev->dev); | |
1716 | WARN_ON(ret < 0); | |
cdb9b9f7 PM |
1717 | } |
1718 | ||
10874f5a | 1719 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1720 | { |
1721 | struct pci_dev *dev; | |
1722 | ||
90bdb311 TP |
1723 | dev = pci_get_slot(bus, devfn); |
1724 | if (dev) { | |
1725 | pci_dev_put(dev); | |
1726 | return dev; | |
1727 | } | |
1728 | ||
cdb9b9f7 PM |
1729 | dev = pci_scan_device(bus, devfn); |
1730 | if (!dev) | |
1731 | return NULL; | |
1732 | ||
1733 | pci_device_add(dev, bus); | |
1da177e4 LT |
1734 | |
1735 | return dev; | |
1736 | } | |
b73e9687 | 1737 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 | 1738 | |
b1bd58e4 | 1739 | static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) |
f07852d6 | 1740 | { |
b1bd58e4 YW |
1741 | int pos; |
1742 | u16 cap = 0; | |
1743 | unsigned next_fn; | |
4fb88c1a | 1744 | |
b1bd58e4 YW |
1745 | if (pci_ari_enabled(bus)) { |
1746 | if (!dev) | |
1747 | return 0; | |
1748 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); | |
1749 | if (!pos) | |
1750 | return 0; | |
4fb88c1a | 1751 | |
b1bd58e4 YW |
1752 | pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); |
1753 | next_fn = PCI_ARI_CAP_NFN(cap); | |
1754 | if (next_fn <= fn) | |
1755 | return 0; /* protect against malformed list */ | |
f07852d6 | 1756 | |
b1bd58e4 YW |
1757 | return next_fn; |
1758 | } | |
1759 | ||
1760 | /* dev may be NULL for non-contiguous multifunction devices */ | |
1761 | if (!dev || dev->multifunction) | |
1762 | return (fn + 1) % 8; | |
f07852d6 | 1763 | |
f07852d6 MW |
1764 | return 0; |
1765 | } | |
1766 | ||
1767 | static int only_one_child(struct pci_bus *bus) | |
1768 | { | |
1769 | struct pci_dev *parent = bus->self; | |
284f5f9d | 1770 | |
f07852d6 MW |
1771 | if (!parent || !pci_is_pcie(parent)) |
1772 | return 0; | |
62f87c0e | 1773 | if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT) |
284f5f9d | 1774 | return 1; |
777e61ea | 1775 | if (parent->has_secondary_link && |
284f5f9d | 1776 | !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) |
f07852d6 MW |
1777 | return 1; |
1778 | return 0; | |
1779 | } | |
1780 | ||
1da177e4 LT |
1781 | /** |
1782 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1783 | * @bus: PCI bus to scan | |
1784 | * @devfn: slot number to scan (must have zero function.) | |
1785 | * | |
1786 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1787 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1788 | * will not have is_added set. |
1b69dfc6 TP |
1789 | * |
1790 | * Returns the number of new devices found. | |
1da177e4 | 1791 | */ |
96bde06a | 1792 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 1793 | { |
f07852d6 | 1794 | unsigned fn, nr = 0; |
1b69dfc6 | 1795 | struct pci_dev *dev; |
f07852d6 MW |
1796 | |
1797 | if (only_one_child(bus) && (devfn > 0)) | |
1798 | return 0; /* Already scanned the entire slot */ | |
1da177e4 | 1799 | |
1b69dfc6 | 1800 | dev = pci_scan_single_device(bus, devfn); |
4fb88c1a MW |
1801 | if (!dev) |
1802 | return 0; | |
1803 | if (!dev->is_added) | |
1b69dfc6 TP |
1804 | nr++; |
1805 | ||
b1bd58e4 | 1806 | for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { |
f07852d6 MW |
1807 | dev = pci_scan_single_device(bus, devfn + fn); |
1808 | if (dev) { | |
1809 | if (!dev->is_added) | |
1810 | nr++; | |
1811 | dev->multifunction = 1; | |
1da177e4 LT |
1812 | } |
1813 | } | |
7d715a6c | 1814 | |
149e1637 SL |
1815 | /* only one slot has pcie device */ |
1816 | if (bus->self && nr) | |
7d715a6c SL |
1817 | pcie_aspm_init_link_state(bus->self); |
1818 | ||
1da177e4 LT |
1819 | return nr; |
1820 | } | |
b7fe9434 | 1821 | EXPORT_SYMBOL(pci_scan_slot); |
1da177e4 | 1822 | |
b03e7495 JM |
1823 | static int pcie_find_smpss(struct pci_dev *dev, void *data) |
1824 | { | |
1825 | u8 *smpss = data; | |
1826 | ||
1827 | if (!pci_is_pcie(dev)) | |
1828 | return 0; | |
1829 | ||
d4aa68f6 YW |
1830 | /* |
1831 | * We don't have a way to change MPS settings on devices that have | |
1832 | * drivers attached. A hot-added device might support only the minimum | |
1833 | * MPS setting (MPS=128). Therefore, if the fabric contains a bridge | |
1834 | * where devices may be hot-added, we limit the fabric MPS to 128 so | |
1835 | * hot-added devices will work correctly. | |
1836 | * | |
1837 | * However, if we hot-add a device to a slot directly below a Root | |
1838 | * Port, it's impossible for there to be other existing devices below | |
1839 | * the port. We don't limit the MPS in this case because we can | |
1840 | * reconfigure MPS on both the Root Port and the hot-added device, | |
1841 | * and there are no other devices involved. | |
1842 | * | |
1843 | * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. | |
b03e7495 | 1844 | */ |
d4aa68f6 YW |
1845 | if (dev->is_hotplug_bridge && |
1846 | pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) | |
b03e7495 JM |
1847 | *smpss = 0; |
1848 | ||
1849 | if (*smpss > dev->pcie_mpss) | |
1850 | *smpss = dev->pcie_mpss; | |
1851 | ||
1852 | return 0; | |
1853 | } | |
1854 | ||
1855 | static void pcie_write_mps(struct pci_dev *dev, int mps) | |
1856 | { | |
62f392ea | 1857 | int rc; |
b03e7495 JM |
1858 | |
1859 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
62f392ea | 1860 | mps = 128 << dev->pcie_mpss; |
b03e7495 | 1861 | |
62f87c0e YW |
1862 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && |
1863 | dev->bus->self) | |
62f392ea | 1864 | /* For "Performance", the assumption is made that |
b03e7495 JM |
1865 | * downstream communication will never be larger than |
1866 | * the MRRS. So, the MPS only needs to be configured | |
1867 | * for the upstream communication. This being the case, | |
1868 | * walk from the top down and set the MPS of the child | |
1869 | * to that of the parent bus. | |
62f392ea JM |
1870 | * |
1871 | * Configure the device MPS with the smaller of the | |
1872 | * device MPSS or the bridge MPS (which is assumed to be | |
1873 | * properly configured at this point to the largest | |
1874 | * allowable MPS based on its parent bus). | |
b03e7495 | 1875 | */ |
62f392ea | 1876 | mps = min(mps, pcie_get_mps(dev->bus->self)); |
b03e7495 JM |
1877 | } |
1878 | ||
1879 | rc = pcie_set_mps(dev, mps); | |
1880 | if (rc) | |
1881 | dev_err(&dev->dev, "Failed attempting to set the MPS\n"); | |
1882 | } | |
1883 | ||
62f392ea | 1884 | static void pcie_write_mrrs(struct pci_dev *dev) |
b03e7495 | 1885 | { |
62f392ea | 1886 | int rc, mrrs; |
b03e7495 | 1887 | |
ed2888e9 JM |
1888 | /* In the "safe" case, do not configure the MRRS. There appear to be |
1889 | * issues with setting MRRS to 0 on a number of devices. | |
1890 | */ | |
ed2888e9 JM |
1891 | if (pcie_bus_config != PCIE_BUS_PERFORMANCE) |
1892 | return; | |
1893 | ||
ed2888e9 JM |
1894 | /* For Max performance, the MRRS must be set to the largest supported |
1895 | * value. However, it cannot be configured larger than the MPS the | |
62f392ea JM |
1896 | * device or the bus can support. This should already be properly |
1897 | * configured by a prior call to pcie_write_mps. | |
ed2888e9 | 1898 | */ |
62f392ea | 1899 | mrrs = pcie_get_mps(dev); |
b03e7495 JM |
1900 | |
1901 | /* MRRS is a R/W register. Invalid values can be written, but a | |
ed2888e9 | 1902 | * subsequent read will verify if the value is acceptable or not. |
b03e7495 JM |
1903 | * If the MRRS value provided is not acceptable (e.g., too large), |
1904 | * shrink the value until it is acceptable to the HW. | |
f7625980 | 1905 | */ |
b03e7495 JM |
1906 | while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { |
1907 | rc = pcie_set_readrq(dev, mrrs); | |
62f392ea JM |
1908 | if (!rc) |
1909 | break; | |
b03e7495 | 1910 | |
62f392ea | 1911 | dev_warn(&dev->dev, "Failed attempting to set the MRRS\n"); |
b03e7495 JM |
1912 | mrrs /= 2; |
1913 | } | |
62f392ea JM |
1914 | |
1915 | if (mrrs < 128) | |
227f0647 | 1916 | dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); |
b03e7495 JM |
1917 | } |
1918 | ||
1919 | static int pcie_bus_configure_set(struct pci_dev *dev, void *data) | |
1920 | { | |
a513a99a | 1921 | int mps, orig_mps; |
b03e7495 JM |
1922 | |
1923 | if (!pci_is_pcie(dev)) | |
1924 | return 0; | |
1925 | ||
27d868b5 KB |
1926 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF || |
1927 | pcie_bus_config == PCIE_BUS_DEFAULT) | |
5895af79 | 1928 | return 0; |
5895af79 | 1929 | |
a513a99a JM |
1930 | mps = 128 << *(u8 *)data; |
1931 | orig_mps = pcie_get_mps(dev); | |
b03e7495 JM |
1932 | |
1933 | pcie_write_mps(dev, mps); | |
62f392ea | 1934 | pcie_write_mrrs(dev); |
b03e7495 | 1935 | |
227f0647 RD |
1936 | dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", |
1937 | pcie_get_mps(dev), 128 << dev->pcie_mpss, | |
a513a99a | 1938 | orig_mps, pcie_get_readrq(dev)); |
b03e7495 JM |
1939 | |
1940 | return 0; | |
1941 | } | |
1942 | ||
a513a99a | 1943 | /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, |
b03e7495 JM |
1944 | * parents then children fashion. If this changes, then this code will not |
1945 | * work as designed. | |
1946 | */ | |
a58674ff | 1947 | void pcie_bus_configure_settings(struct pci_bus *bus) |
b03e7495 | 1948 | { |
1e358f94 | 1949 | u8 smpss = 0; |
b03e7495 | 1950 | |
a58674ff | 1951 | if (!bus->self) |
b03e7495 JM |
1952 | return; |
1953 | ||
b03e7495 | 1954 | if (!pci_is_pcie(bus->self)) |
5f39e670 JM |
1955 | return; |
1956 | ||
1957 | /* FIXME - Peer to peer DMA is possible, though the endpoint would need | |
3315472c | 1958 | * to be aware of the MPS of the destination. To work around this, |
5f39e670 JM |
1959 | * simply force the MPS of the entire system to the smallest possible. |
1960 | */ | |
1961 | if (pcie_bus_config == PCIE_BUS_PEER2PEER) | |
1962 | smpss = 0; | |
1963 | ||
b03e7495 | 1964 | if (pcie_bus_config == PCIE_BUS_SAFE) { |
a58674ff | 1965 | smpss = bus->self->pcie_mpss; |
5f39e670 | 1966 | |
b03e7495 JM |
1967 | pcie_find_smpss(bus->self, &smpss); |
1968 | pci_walk_bus(bus, pcie_find_smpss, &smpss); | |
1969 | } | |
1970 | ||
1971 | pcie_bus_configure_set(bus->self, &smpss); | |
1972 | pci_walk_bus(bus, pcie_bus_configure_set, &smpss); | |
1973 | } | |
debc3b77 | 1974 | EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); |
b03e7495 | 1975 | |
15856ad5 | 1976 | unsigned int pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 | 1977 | { |
b918c62e | 1978 | unsigned int devfn, pass, max = bus->busn_res.start; |
1da177e4 LT |
1979 | struct pci_dev *dev; |
1980 | ||
0207c356 | 1981 | dev_dbg(&bus->dev, "scanning bus\n"); |
1da177e4 LT |
1982 | |
1983 | /* Go find them, Rover! */ | |
1984 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1985 | pci_scan_slot(bus, devfn); | |
1986 | ||
a28724b0 YZ |
1987 | /* Reserve buses for SR-IOV capability. */ |
1988 | max += pci_iov_bus_range(bus); | |
1989 | ||
1da177e4 LT |
1990 | /* |
1991 | * After performing arch-dependent fixup of the bus, look behind | |
1992 | * all PCI-to-PCI bridges on this bus. | |
1993 | */ | |
74710ded | 1994 | if (!bus->is_added) { |
0207c356 | 1995 | dev_dbg(&bus->dev, "fixups for bus\n"); |
74710ded | 1996 | pcibios_fixup_bus(bus); |
981cf9ea | 1997 | bus->is_added = 1; |
74710ded AC |
1998 | } |
1999 | ||
3c78bc61 | 2000 | for (pass = 0; pass < 2; pass++) |
1da177e4 | 2001 | list_for_each_entry(dev, &bus->devices, bus_list) { |
6788a51f | 2002 | if (pci_is_bridge(dev)) |
1da177e4 LT |
2003 | max = pci_scan_bridge(bus, dev, max, pass); |
2004 | } | |
2005 | ||
2006 | /* | |
2007 | * We've scanned the bus and so we know all about what's on | |
2008 | * the other side of any bridges that may be on this bus plus | |
2009 | * any devices. | |
2010 | * | |
2011 | * Return how far we've got finding sub-buses. | |
2012 | */ | |
0207c356 | 2013 | dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); |
1da177e4 LT |
2014 | return max; |
2015 | } | |
b7fe9434 | 2016 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1da177e4 | 2017 | |
6c0cc950 RW |
2018 | /** |
2019 | * pcibios_root_bridge_prepare - Platform-specific host bridge setup. | |
2020 | * @bridge: Host bridge to set up. | |
2021 | * | |
2022 | * Default empty implementation. Replace with an architecture-specific setup | |
2023 | * routine, if necessary. | |
2024 | */ | |
2025 | int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) | |
2026 | { | |
2027 | return 0; | |
2028 | } | |
2029 | ||
10a95747 JL |
2030 | void __weak pcibios_add_bus(struct pci_bus *bus) |
2031 | { | |
2032 | } | |
2033 | ||
2034 | void __weak pcibios_remove_bus(struct pci_bus *bus) | |
2035 | { | |
2036 | } | |
2037 | ||
166c6370 BH |
2038 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
2039 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
1da177e4 | 2040 | { |
0efd5aab | 2041 | int error; |
5a21d70d | 2042 | struct pci_host_bridge *bridge; |
0207c356 | 2043 | struct pci_bus *b, *b2; |
14d76b68 | 2044 | struct resource_entry *window, *n; |
a9d9f527 | 2045 | struct resource *res; |
0efd5aab BH |
2046 | resource_size_t offset; |
2047 | char bus_addr[64]; | |
2048 | char *fmt; | |
1da177e4 | 2049 | |
670ba0c8 | 2050 | b = pci_alloc_bus(NULL); |
1da177e4 | 2051 | if (!b) |
7b543663 | 2052 | return NULL; |
1da177e4 LT |
2053 | |
2054 | b->sysdata = sysdata; | |
2055 | b->ops = ops; | |
4f535093 | 2056 | b->number = b->busn_res.start = bus; |
670ba0c8 | 2057 | pci_bus_assign_domain_nr(b, parent); |
0207c356 BH |
2058 | b2 = pci_find_bus(pci_domain_nr(b), bus); |
2059 | if (b2) { | |
1da177e4 | 2060 | /* If we already got to this bus through a different bridge, ignore it */ |
0207c356 | 2061 | dev_dbg(&b2->dev, "bus already known\n"); |
1da177e4 LT |
2062 | goto err_out; |
2063 | } | |
d71374da | 2064 | |
7b543663 YL |
2065 | bridge = pci_alloc_host_bridge(b); |
2066 | if (!bridge) | |
2067 | goto err_out; | |
2068 | ||
2069 | bridge->dev.parent = parent; | |
70efde2a | 2070 | bridge->dev.release = pci_release_host_bridge_dev; |
7b543663 | 2071 | dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus); |
6c0cc950 | 2072 | error = pcibios_root_bridge_prepare(bridge); |
343df771 JL |
2073 | if (error) { |
2074 | kfree(bridge); | |
2075 | goto err_out; | |
2076 | } | |
6c0cc950 | 2077 | |
7b543663 | 2078 | error = device_register(&bridge->dev); |
343df771 JL |
2079 | if (error) { |
2080 | put_device(&bridge->dev); | |
2081 | goto err_out; | |
2082 | } | |
7b543663 | 2083 | b->bridge = get_device(&bridge->dev); |
a1e4d72c | 2084 | device_enable_async_suspend(b->bridge); |
98d9f30c | 2085 | pci_set_bus_of_node(b); |
44aa0c65 | 2086 | pci_set_bus_msi_domain(b); |
1da177e4 | 2087 | |
0d358f22 YL |
2088 | if (!parent) |
2089 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
2090 | ||
fd7d1ced GKH |
2091 | b->dev.class = &pcibus_class; |
2092 | b->dev.parent = b->bridge; | |
1a927133 | 2093 | dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); |
fd7d1ced | 2094 | error = device_register(&b->dev); |
1da177e4 LT |
2095 | if (error) |
2096 | goto class_dev_reg_err; | |
1da177e4 | 2097 | |
10a95747 JL |
2098 | pcibios_add_bus(b); |
2099 | ||
1da177e4 LT |
2100 | /* Create legacy_io and legacy_mem files for this bus */ |
2101 | pci_create_legacy_files(b); | |
2102 | ||
a9d9f527 BH |
2103 | if (parent) |
2104 | dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev)); | |
2105 | else | |
2106 | printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev)); | |
2107 | ||
0efd5aab | 2108 | /* Add initial resources to the bus */ |
14d76b68 JL |
2109 | resource_list_for_each_entry_safe(window, n, resources) { |
2110 | list_move_tail(&window->node, &bridge->windows); | |
0efd5aab BH |
2111 | res = window->res; |
2112 | offset = window->offset; | |
f848ffb1 YL |
2113 | if (res->flags & IORESOURCE_BUS) |
2114 | pci_bus_insert_busn_res(b, bus, res->end); | |
2115 | else | |
2116 | pci_bus_add_resource(b, res, 0); | |
0efd5aab BH |
2117 | if (offset) { |
2118 | if (resource_type(res) == IORESOURCE_IO) | |
2119 | fmt = " (bus address [%#06llx-%#06llx])"; | |
2120 | else | |
2121 | fmt = " (bus address [%#010llx-%#010llx])"; | |
2122 | snprintf(bus_addr, sizeof(bus_addr), fmt, | |
2123 | (unsigned long long) (res->start - offset), | |
2124 | (unsigned long long) (res->end - offset)); | |
2125 | } else | |
2126 | bus_addr[0] = '\0'; | |
2127 | dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr); | |
a9d9f527 BH |
2128 | } |
2129 | ||
a5390aa6 BH |
2130 | down_write(&pci_bus_sem); |
2131 | list_add_tail(&b->node, &pci_root_buses); | |
2132 | up_write(&pci_bus_sem); | |
2133 | ||
1da177e4 LT |
2134 | return b; |
2135 | ||
1da177e4 | 2136 | class_dev_reg_err: |
7b543663 YL |
2137 | put_device(&bridge->dev); |
2138 | device_unregister(&bridge->dev); | |
1da177e4 | 2139 | err_out: |
1da177e4 LT |
2140 | kfree(b); |
2141 | return NULL; | |
2142 | } | |
e6b29dea | 2143 | EXPORT_SYMBOL_GPL(pci_create_root_bus); |
cdb9b9f7 | 2144 | |
98a35831 YL |
2145 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) |
2146 | { | |
2147 | struct resource *res = &b->busn_res; | |
2148 | struct resource *parent_res, *conflict; | |
2149 | ||
2150 | res->start = bus; | |
2151 | res->end = bus_max; | |
2152 | res->flags = IORESOURCE_BUS; | |
2153 | ||
2154 | if (!pci_is_root_bus(b)) | |
2155 | parent_res = &b->parent->busn_res; | |
2156 | else { | |
2157 | parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); | |
2158 | res->flags |= IORESOURCE_PCI_FIXED; | |
2159 | } | |
2160 | ||
ced04d15 | 2161 | conflict = request_resource_conflict(parent_res, res); |
98a35831 YL |
2162 | |
2163 | if (conflict) | |
2164 | dev_printk(KERN_DEBUG, &b->dev, | |
2165 | "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", | |
2166 | res, pci_is_root_bus(b) ? "domain " : "", | |
2167 | parent_res, conflict->name, conflict); | |
98a35831 YL |
2168 | |
2169 | return conflict == NULL; | |
2170 | } | |
2171 | ||
2172 | int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) | |
2173 | { | |
2174 | struct resource *res = &b->busn_res; | |
2175 | struct resource old_res = *res; | |
2176 | resource_size_t size; | |
2177 | int ret; | |
2178 | ||
2179 | if (res->start > bus_max) | |
2180 | return -EINVAL; | |
2181 | ||
2182 | size = bus_max - res->start + 1; | |
2183 | ret = adjust_resource(res, res->start, size); | |
2184 | dev_printk(KERN_DEBUG, &b->dev, | |
2185 | "busn_res: %pR end %s updated to %02x\n", | |
2186 | &old_res, ret ? "can not be" : "is", bus_max); | |
2187 | ||
2188 | if (!ret && !res->parent) | |
2189 | pci_bus_insert_busn_res(b, res->start, res->end); | |
2190 | ||
2191 | return ret; | |
2192 | } | |
2193 | ||
2194 | void pci_bus_release_busn_res(struct pci_bus *b) | |
2195 | { | |
2196 | struct resource *res = &b->busn_res; | |
2197 | int ret; | |
2198 | ||
2199 | if (!res->flags || !res->parent) | |
2200 | return; | |
2201 | ||
2202 | ret = release_resource(res); | |
2203 | dev_printk(KERN_DEBUG, &b->dev, | |
2204 | "busn_res: %pR %s released\n", | |
2205 | res, ret ? "can not be" : "is"); | |
2206 | } | |
2207 | ||
d2a7926d LP |
2208 | struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, |
2209 | struct pci_ops *ops, void *sysdata, | |
2210 | struct list_head *resources, struct msi_controller *msi) | |
a2ebb827 | 2211 | { |
14d76b68 | 2212 | struct resource_entry *window; |
4d99f524 | 2213 | bool found = false; |
a2ebb827 | 2214 | struct pci_bus *b; |
4d99f524 YL |
2215 | int max; |
2216 | ||
14d76b68 | 2217 | resource_list_for_each_entry(window, resources) |
4d99f524 YL |
2218 | if (window->res->flags & IORESOURCE_BUS) { |
2219 | found = true; | |
2220 | break; | |
2221 | } | |
a2ebb827 BH |
2222 | |
2223 | b = pci_create_root_bus(parent, bus, ops, sysdata, resources); | |
2224 | if (!b) | |
2225 | return NULL; | |
2226 | ||
d2a7926d LP |
2227 | b->msi = msi; |
2228 | ||
4d99f524 YL |
2229 | if (!found) { |
2230 | dev_info(&b->dev, | |
2231 | "No busn resource found for root bus, will use [bus %02x-ff]\n", | |
2232 | bus); | |
2233 | pci_bus_insert_busn_res(b, bus, 255); | |
2234 | } | |
2235 | ||
2236 | max = pci_scan_child_bus(b); | |
2237 | ||
2238 | if (!found) | |
2239 | pci_bus_update_busn_res_end(b, max); | |
2240 | ||
a2ebb827 BH |
2241 | return b; |
2242 | } | |
d2a7926d LP |
2243 | |
2244 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, | |
2245 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
2246 | { | |
2247 | return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources, | |
2248 | NULL); | |
2249 | } | |
a2ebb827 BH |
2250 | EXPORT_SYMBOL(pci_scan_root_bus); |
2251 | ||
15856ad5 | 2252 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, |
de4b2f76 BH |
2253 | void *sysdata) |
2254 | { | |
2255 | LIST_HEAD(resources); | |
2256 | struct pci_bus *b; | |
2257 | ||
2258 | pci_add_resource(&resources, &ioport_resource); | |
2259 | pci_add_resource(&resources, &iomem_resource); | |
857c3b66 | 2260 | pci_add_resource(&resources, &busn_resource); |
de4b2f76 BH |
2261 | b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); |
2262 | if (b) { | |
857c3b66 | 2263 | pci_scan_child_bus(b); |
de4b2f76 BH |
2264 | } else { |
2265 | pci_free_resource_list(&resources); | |
2266 | } | |
2267 | return b; | |
2268 | } | |
2269 | EXPORT_SYMBOL(pci_scan_bus); | |
2270 | ||
2f320521 YL |
2271 | /** |
2272 | * pci_rescan_bus_bridge_resize - scan a PCI bus for devices. | |
2273 | * @bridge: PCI bridge for the bus to scan | |
2274 | * | |
2275 | * Scan a PCI bus and child buses for new devices, add them, | |
2276 | * and enable them, resizing bridge mmio/io resource if necessary | |
2277 | * and possible. The caller must ensure the child devices are already | |
2278 | * removed for resizing to occur. | |
2279 | * | |
2280 | * Returns the max number of subordinate bus discovered. | |
2281 | */ | |
10874f5a | 2282 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) |
2f320521 YL |
2283 | { |
2284 | unsigned int max; | |
2285 | struct pci_bus *bus = bridge->subordinate; | |
2286 | ||
2287 | max = pci_scan_child_bus(bus); | |
2288 | ||
2289 | pci_assign_unassigned_bridge_resources(bridge); | |
2290 | ||
2291 | pci_bus_add_devices(bus); | |
2292 | ||
2293 | return max; | |
2294 | } | |
2295 | ||
a5213a31 YL |
2296 | /** |
2297 | * pci_rescan_bus - scan a PCI bus for devices. | |
2298 | * @bus: PCI bus to scan | |
2299 | * | |
2300 | * Scan a PCI bus and child buses for new devices, adds them, | |
2301 | * and enables them. | |
2302 | * | |
2303 | * Returns the max number of subordinate bus discovered. | |
2304 | */ | |
10874f5a | 2305 | unsigned int pci_rescan_bus(struct pci_bus *bus) |
a5213a31 YL |
2306 | { |
2307 | unsigned int max; | |
2308 | ||
2309 | max = pci_scan_child_bus(bus); | |
2310 | pci_assign_unassigned_bus_resources(bus); | |
2311 | pci_bus_add_devices(bus); | |
2312 | ||
2313 | return max; | |
2314 | } | |
2315 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
2316 | ||
9d16947b RW |
2317 | /* |
2318 | * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal | |
2319 | * routines should always be executed under this mutex. | |
2320 | */ | |
2321 | static DEFINE_MUTEX(pci_rescan_remove_lock); | |
2322 | ||
2323 | void pci_lock_rescan_remove(void) | |
2324 | { | |
2325 | mutex_lock(&pci_rescan_remove_lock); | |
2326 | } | |
2327 | EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); | |
2328 | ||
2329 | void pci_unlock_rescan_remove(void) | |
2330 | { | |
2331 | mutex_unlock(&pci_rescan_remove_lock); | |
2332 | } | |
2333 | EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); | |
2334 | ||
3c78bc61 RD |
2335 | static int __init pci_sort_bf_cmp(const struct device *d_a, |
2336 | const struct device *d_b) | |
6b4b78fe | 2337 | { |
99178b03 GKH |
2338 | const struct pci_dev *a = to_pci_dev(d_a); |
2339 | const struct pci_dev *b = to_pci_dev(d_b); | |
2340 | ||
6b4b78fe MD |
2341 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
2342 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
2343 | ||
2344 | if (a->bus->number < b->bus->number) return -1; | |
2345 | else if (a->bus->number > b->bus->number) return 1; | |
2346 | ||
2347 | if (a->devfn < b->devfn) return -1; | |
2348 | else if (a->devfn > b->devfn) return 1; | |
2349 | ||
2350 | return 0; | |
2351 | } | |
2352 | ||
5ff580c1 | 2353 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 2354 | { |
99178b03 | 2355 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 2356 | } |