Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/cpumask.h> | |
7d715a6c | 12 | #include <linux/pci-aspm.h> |
bc56b9e0 | 13 | #include "pci.h" |
1da177e4 LT |
14 | |
15 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
16 | #define CARDBUS_RESERVE_BUSNR 3 | |
17 | #define PCI_CFG_SPACE_SIZE 256 | |
18 | #define PCI_CFG_SPACE_EXP_SIZE 4096 | |
19 | ||
20 | /* Ugh. Need to stop exporting this to modules. */ | |
21 | LIST_HEAD(pci_root_buses); | |
22 | EXPORT_SYMBOL(pci_root_buses); | |
23 | ||
70308923 GKH |
24 | |
25 | static int find_anything(struct device *dev, void *data) | |
26 | { | |
27 | return 1; | |
28 | } | |
1da177e4 | 29 | |
ed4aaadb ZY |
30 | /* |
31 | * Some device drivers need know if pci is initiated. | |
32 | * Basically, we think pci is not initiated when there | |
70308923 | 33 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
34 | */ |
35 | int no_pci_devices(void) | |
36 | { | |
70308923 GKH |
37 | struct device *dev; |
38 | int no_devices; | |
ed4aaadb | 39 | |
70308923 GKH |
40 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
41 | no_devices = (dev == NULL); | |
42 | put_device(dev); | |
43 | return no_devices; | |
44 | } | |
ed4aaadb ZY |
45 | EXPORT_SYMBOL(no_pci_devices); |
46 | ||
1da177e4 LT |
47 | #ifdef HAVE_PCI_LEGACY |
48 | /** | |
49 | * pci_create_legacy_files - create legacy I/O port and memory files | |
50 | * @b: bus to create files under | |
51 | * | |
52 | * Some platforms allow access to legacy I/O port and ISA memory space on | |
53 | * a per-bus basis. This routine creates the files and ties them into | |
54 | * their associated read, write and mmap files from pci-sysfs.c | |
55 | */ | |
56 | static void pci_create_legacy_files(struct pci_bus *b) | |
57 | { | |
f5afe806 | 58 | b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2, |
1da177e4 LT |
59 | GFP_ATOMIC); |
60 | if (b->legacy_io) { | |
1da177e4 LT |
61 | b->legacy_io->attr.name = "legacy_io"; |
62 | b->legacy_io->size = 0xffff; | |
63 | b->legacy_io->attr.mode = S_IRUSR | S_IWUSR; | |
1da177e4 LT |
64 | b->legacy_io->read = pci_read_legacy_io; |
65 | b->legacy_io->write = pci_write_legacy_io; | |
fd7d1ced | 66 | device_create_bin_file(&b->dev, b->legacy_io); |
1da177e4 LT |
67 | |
68 | /* Allocated above after the legacy_io struct */ | |
69 | b->legacy_mem = b->legacy_io + 1; | |
70 | b->legacy_mem->attr.name = "legacy_mem"; | |
71 | b->legacy_mem->size = 1024*1024; | |
72 | b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR; | |
1da177e4 | 73 | b->legacy_mem->mmap = pci_mmap_legacy_mem; |
fd7d1ced | 74 | device_create_bin_file(&b->dev, b->legacy_mem); |
1da177e4 LT |
75 | } |
76 | } | |
77 | ||
78 | void pci_remove_legacy_files(struct pci_bus *b) | |
79 | { | |
80 | if (b->legacy_io) { | |
fd7d1ced GKH |
81 | device_remove_bin_file(&b->dev, b->legacy_io); |
82 | device_remove_bin_file(&b->dev, b->legacy_mem); | |
1da177e4 LT |
83 | kfree(b->legacy_io); /* both are allocated here */ |
84 | } | |
85 | } | |
86 | #else /* !HAVE_PCI_LEGACY */ | |
87 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
88 | void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
89 | #endif /* HAVE_PCI_LEGACY */ | |
90 | ||
91 | /* | |
92 | * PCI Bus Class Devices | |
93 | */ | |
fd7d1ced | 94 | static ssize_t pci_bus_show_cpuaffinity(struct device *dev, |
39106dcf | 95 | int type, |
fd7d1ced | 96 | struct device_attribute *attr, |
4327edf6 | 97 | char *buf) |
1da177e4 | 98 | { |
1da177e4 | 99 | int ret; |
4327edf6 | 100 | cpumask_t cpumask; |
1da177e4 | 101 | |
fd7d1ced | 102 | cpumask = pcibus_to_cpumask(to_pci_bus(dev)); |
39106dcf MT |
103 | ret = type? |
104 | cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask): | |
105 | cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); | |
106 | buf[ret++] = '\n'; | |
107 | buf[ret] = '\0'; | |
1da177e4 LT |
108 | return ret; |
109 | } | |
39106dcf MT |
110 | |
111 | static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, | |
112 | struct device_attribute *attr, | |
113 | char *buf) | |
114 | { | |
115 | return pci_bus_show_cpuaffinity(dev, 0, attr, buf); | |
116 | } | |
117 | ||
118 | static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, | |
119 | struct device_attribute *attr, | |
120 | char *buf) | |
121 | { | |
122 | return pci_bus_show_cpuaffinity(dev, 1, attr, buf); | |
123 | } | |
124 | ||
125 | DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); | |
126 | DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); | |
1da177e4 LT |
127 | |
128 | /* | |
129 | * PCI Bus Class | |
130 | */ | |
fd7d1ced | 131 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 132 | { |
fd7d1ced | 133 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
134 | |
135 | if (pci_bus->bridge) | |
136 | put_device(pci_bus->bridge); | |
137 | kfree(pci_bus); | |
138 | } | |
139 | ||
140 | static struct class pcibus_class = { | |
141 | .name = "pci_bus", | |
fd7d1ced | 142 | .dev_release = &release_pcibus_dev, |
1da177e4 LT |
143 | }; |
144 | ||
145 | static int __init pcibus_class_init(void) | |
146 | { | |
147 | return class_register(&pcibus_class); | |
148 | } | |
149 | postcore_initcall(pcibus_class_init); | |
150 | ||
151 | /* | |
152 | * Translate the low bits of the PCI base | |
153 | * to the resource type | |
154 | */ | |
155 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) | |
156 | { | |
157 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) | |
158 | return IORESOURCE_IO; | |
159 | ||
160 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
161 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
162 | ||
163 | return IORESOURCE_MEM; | |
164 | } | |
165 | ||
6ac665c6 | 166 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 167 | { |
6ac665c6 | 168 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
169 | if (!size) |
170 | return 0; | |
171 | ||
172 | /* Get the lowest of them to find the decode size, and | |
173 | from that the extent. */ | |
174 | size = (size & ~(size-1)) - 1; | |
175 | ||
176 | /* base == maxbase can be valid only if the BAR has | |
177 | already been programmed with all 1s. */ | |
178 | if (base == maxbase && ((base | size) & mask) != mask) | |
179 | return 0; | |
180 | ||
181 | return size; | |
182 | } | |
183 | ||
6ac665c6 MW |
184 | enum pci_bar_type { |
185 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
186 | pci_bar_io, /* An io port BAR */ | |
187 | pci_bar_mem32, /* A 32-bit memory BAR */ | |
188 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
189 | }; | |
07eddf3d | 190 | |
6ac665c6 MW |
191 | static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) |
192 | { | |
193 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { | |
194 | res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; | |
195 | return pci_bar_io; | |
196 | } | |
07eddf3d | 197 | |
6ac665c6 | 198 | res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
07eddf3d | 199 | |
6ac665c6 MW |
200 | if (res->flags == PCI_BASE_ADDRESS_MEM_TYPE_64) |
201 | return pci_bar_mem64; | |
202 | return pci_bar_mem32; | |
07eddf3d YL |
203 | } |
204 | ||
6ac665c6 MW |
205 | /* |
206 | * If the type is not unknown, we assume that the lowest bit is 'enable'. | |
207 | * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit. | |
208 | */ | |
209 | static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
210 | struct resource *res, unsigned int pos) | |
07eddf3d | 211 | { |
6ac665c6 MW |
212 | u32 l, sz, mask; |
213 | ||
214 | mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0; | |
215 | ||
216 | res->name = pci_name(dev); | |
217 | ||
218 | pci_read_config_dword(dev, pos, &l); | |
219 | pci_write_config_dword(dev, pos, mask); | |
220 | pci_read_config_dword(dev, pos, &sz); | |
221 | pci_write_config_dword(dev, pos, l); | |
222 | ||
223 | /* | |
224 | * All bits set in sz means the device isn't working properly. | |
225 | * If the BAR isn't implemented, all bits must be 0. If it's a | |
226 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
227 | * 1 must be clear. | |
228 | */ | |
229 | if (!sz || sz == 0xffffffff) | |
230 | goto fail; | |
231 | ||
232 | /* | |
233 | * I don't know how l can have all bits set. Copied from old code. | |
234 | * Maybe it fixes a bug on some ancient platform. | |
235 | */ | |
236 | if (l == 0xffffffff) | |
237 | l = 0; | |
238 | ||
239 | if (type == pci_bar_unknown) { | |
240 | type = decode_bar(res, l); | |
241 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; | |
242 | if (type == pci_bar_io) { | |
243 | l &= PCI_BASE_ADDRESS_IO_MASK; | |
244 | mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff; | |
245 | } else { | |
246 | l &= PCI_BASE_ADDRESS_MEM_MASK; | |
247 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
248 | } | |
249 | } else { | |
250 | res->flags |= (l & IORESOURCE_ROM_ENABLE); | |
251 | l &= PCI_ROM_ADDRESS_MASK; | |
252 | mask = (u32)PCI_ROM_ADDRESS_MASK; | |
253 | } | |
254 | ||
255 | if (type == pci_bar_mem64) { | |
256 | u64 l64 = l; | |
257 | u64 sz64 = sz; | |
258 | u64 mask64 = mask | (u64)~0 << 32; | |
259 | ||
260 | pci_read_config_dword(dev, pos + 4, &l); | |
261 | pci_write_config_dword(dev, pos + 4, ~0); | |
262 | pci_read_config_dword(dev, pos + 4, &sz); | |
263 | pci_write_config_dword(dev, pos + 4, l); | |
264 | ||
265 | l64 |= ((u64)l << 32); | |
266 | sz64 |= ((u64)sz << 32); | |
267 | ||
268 | sz64 = pci_size(l64, sz64, mask64); | |
269 | ||
270 | if (!sz64) | |
271 | goto fail; | |
272 | ||
cc5499c3 | 273 | if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
6ac665c6 MW |
274 | dev_err(&dev->dev, "can't handle 64-bit BAR\n"); |
275 | goto fail; | |
cc5499c3 | 276 | } else if ((sizeof(resource_size_t) < 8) && l) { |
6ac665c6 MW |
277 | /* Address above 32-bit boundary; disable the BAR */ |
278 | pci_write_config_dword(dev, pos, 0); | |
279 | pci_write_config_dword(dev, pos + 4, 0); | |
280 | res->start = 0; | |
281 | res->end = sz64; | |
282 | } else { | |
283 | res->start = l64; | |
284 | res->end = l64 + sz64; | |
285 | } | |
286 | } else { | |
287 | sz = pci_size(l, sz, mask); | |
288 | ||
289 | if (!sz) | |
290 | goto fail; | |
291 | ||
292 | res->start = l; | |
293 | res->end = l + sz; | |
294 | } | |
295 | ||
296 | out: | |
297 | return (type == pci_bar_mem64) ? 1 : 0; | |
298 | fail: | |
299 | res->flags = 0; | |
300 | goto out; | |
07eddf3d YL |
301 | } |
302 | ||
1da177e4 LT |
303 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
304 | { | |
6ac665c6 | 305 | unsigned int pos, reg; |
07eddf3d | 306 | |
6ac665c6 MW |
307 | for (pos = 0; pos < howmany; pos++) { |
308 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 309 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 310 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 311 | } |
6ac665c6 | 312 | |
1da177e4 | 313 | if (rom) { |
6ac665c6 | 314 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 315 | dev->rom_base_reg = rom; |
6ac665c6 MW |
316 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
317 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | | |
318 | IORESOURCE_SIZEALIGN; | |
319 | __pci_read_base(dev, pci_bar_mem32, res, rom); | |
1da177e4 LT |
320 | } |
321 | } | |
322 | ||
0ab2b57f | 323 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
1da177e4 LT |
324 | { |
325 | struct pci_dev *dev = child->self; | |
326 | u8 io_base_lo, io_limit_lo; | |
327 | u16 mem_base_lo, mem_limit_lo; | |
328 | unsigned long base, limit; | |
329 | struct resource *res; | |
330 | int i; | |
331 | ||
332 | if (!dev) /* It's a host bus, nothing to read */ | |
333 | return; | |
334 | ||
335 | if (dev->transparent) { | |
80ccba11 | 336 | dev_info(&dev->dev, "transparent bridge\n"); |
90b54929 IK |
337 | for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) |
338 | child->resource[i] = child->parent->resource[i - 3]; | |
1da177e4 LT |
339 | } |
340 | ||
341 | for(i=0; i<3; i++) | |
342 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
343 | ||
344 | res = child->resource[0]; | |
345 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
346 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
347 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
348 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
349 | ||
350 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
351 | u16 io_base_hi, io_limit_hi; | |
352 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
353 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
354 | base |= (io_base_hi << 16); | |
355 | limit |= (io_limit_hi << 16); | |
356 | } | |
357 | ||
358 | if (base <= limit) { | |
359 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
9d265124 DY |
360 | if (!res->start) |
361 | res->start = base; | |
362 | if (!res->end) | |
363 | res->end = limit + 0xfff; | |
1da177e4 LT |
364 | } |
365 | ||
366 | res = child->resource[1]; | |
367 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
368 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
369 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
370 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
371 | if (base <= limit) { | |
372 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; | |
373 | res->start = base; | |
374 | res->end = limit + 0xfffff; | |
375 | } | |
376 | ||
377 | res = child->resource[2]; | |
378 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
379 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
380 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
381 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
382 | ||
383 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
384 | u32 mem_base_hi, mem_limit_hi; | |
385 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
386 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
387 | ||
388 | /* | |
389 | * Some bridges set the base > limit by default, and some | |
390 | * (broken) BIOSes do not initialize them. If we find | |
391 | * this, just assume they are not being used. | |
392 | */ | |
393 | if (mem_base_hi <= mem_limit_hi) { | |
394 | #if BITS_PER_LONG == 64 | |
395 | base |= ((long) mem_base_hi) << 32; | |
396 | limit |= ((long) mem_limit_hi) << 32; | |
397 | #else | |
398 | if (mem_base_hi || mem_limit_hi) { | |
80ccba11 BH |
399 | dev_err(&dev->dev, "can't handle 64-bit " |
400 | "address space for bridge\n"); | |
1da177e4 LT |
401 | return; |
402 | } | |
403 | #endif | |
404 | } | |
405 | } | |
406 | if (base <= limit) { | |
407 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
408 | res->start = base; | |
409 | res->end = limit + 0xfffff; | |
410 | } | |
411 | } | |
412 | ||
96bde06a | 413 | static struct pci_bus * pci_alloc_bus(void) |
1da177e4 LT |
414 | { |
415 | struct pci_bus *b; | |
416 | ||
f5afe806 | 417 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
1da177e4 | 418 | if (b) { |
1da177e4 LT |
419 | INIT_LIST_HEAD(&b->node); |
420 | INIT_LIST_HEAD(&b->children); | |
421 | INIT_LIST_HEAD(&b->devices); | |
f46753c5 | 422 | INIT_LIST_HEAD(&b->slots); |
1da177e4 LT |
423 | } |
424 | return b; | |
425 | } | |
426 | ||
cbd4e055 AB |
427 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
428 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
429 | { |
430 | struct pci_bus *child; | |
431 | int i; | |
432 | ||
433 | /* | |
434 | * Allocate a new bus, and inherit stuff from the parent.. | |
435 | */ | |
436 | child = pci_alloc_bus(); | |
437 | if (!child) | |
438 | return NULL; | |
439 | ||
440 | child->self = bridge; | |
441 | child->parent = parent; | |
442 | child->ops = parent->ops; | |
443 | child->sysdata = parent->sysdata; | |
6e325a62 | 444 | child->bus_flags = parent->bus_flags; |
1da177e4 LT |
445 | child->bridge = get_device(&bridge->dev); |
446 | ||
fd7d1ced GKH |
447 | /* initialize some portions of the bus device, but don't register it |
448 | * now as the parent is not properly set up yet. This device will get | |
449 | * registered later in pci_bus_add_devices() | |
450 | */ | |
451 | child->dev.class = &pcibus_class; | |
452 | sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr); | |
1da177e4 LT |
453 | |
454 | /* | |
455 | * Set up the primary, secondary and subordinate | |
456 | * bus numbers. | |
457 | */ | |
458 | child->number = child->secondary = busnr; | |
459 | child->primary = parent->secondary; | |
460 | child->subordinate = 0xff; | |
461 | ||
462 | /* Set up default resource pointers and names.. */ | |
463 | for (i = 0; i < 4; i++) { | |
464 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; | |
465 | child->resource[i]->name = child->name; | |
466 | } | |
467 | bridge->subordinate = child; | |
468 | ||
469 | return child; | |
470 | } | |
471 | ||
451124a7 | 472 | struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4 LT |
473 | { |
474 | struct pci_bus *child; | |
475 | ||
476 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 477 | if (child) { |
d71374da | 478 | down_write(&pci_bus_sem); |
1da177e4 | 479 | list_add_tail(&child->node, &parent->children); |
d71374da | 480 | up_write(&pci_bus_sem); |
e4ea9bb7 | 481 | } |
1da177e4 LT |
482 | return child; |
483 | } | |
484 | ||
96bde06a | 485 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
26f674ae GKH |
486 | { |
487 | struct pci_bus *parent = child->parent; | |
12f44f46 IK |
488 | |
489 | /* Attempts to fix that up are really dangerous unless | |
490 | we're going to re-assign all bus numbers. */ | |
491 | if (!pcibios_assign_all_busses()) | |
492 | return; | |
493 | ||
26f674ae GKH |
494 | while (parent->parent && parent->subordinate < max) { |
495 | parent->subordinate = max; | |
496 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); | |
497 | parent = parent->parent; | |
498 | } | |
499 | } | |
500 | ||
1da177e4 LT |
501 | /* |
502 | * If it's a bridge, configure it and scan the bus behind it. | |
503 | * For CardBus bridges, we don't scan behind as the devices will | |
504 | * be handled by the bridge driver itself. | |
505 | * | |
506 | * We need to process bridges in two passes -- first we scan those | |
507 | * already configured by the BIOS and after we are done with all of | |
508 | * them, we proceed to assigning numbers to the remaining buses in | |
509 | * order to avoid overlaps between old and new bus numbers. | |
510 | */ | |
0ab2b57f | 511 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
512 | { |
513 | struct pci_bus *child; | |
514 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 515 | u32 buses, i, j = 0; |
1da177e4 LT |
516 | u16 bctl; |
517 | ||
518 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
519 | ||
80ccba11 BH |
520 | dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n", |
521 | buses & 0xffffff, pass); | |
1da177e4 LT |
522 | |
523 | /* Disable MasterAbortMode during probing to avoid reporting | |
524 | of bus errors (in some architectures) */ | |
525 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | |
526 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
527 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
528 | ||
1da177e4 LT |
529 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) { |
530 | unsigned int cmax, busnr; | |
531 | /* | |
532 | * Bus already configured by firmware, process it in the first | |
533 | * pass and just note the configuration. | |
534 | */ | |
535 | if (pass) | |
bbe8f9a3 | 536 | goto out; |
1da177e4 LT |
537 | busnr = (buses >> 8) & 0xFF; |
538 | ||
539 | /* | |
540 | * If we already got to this bus through a different bridge, | |
541 | * ignore it. This can happen with the i450NX chipset. | |
542 | */ | |
543 | if (pci_find_bus(pci_domain_nr(bus), busnr)) { | |
80ccba11 BH |
544 | dev_info(&dev->dev, "bus %04x:%02x already known\n", |
545 | pci_domain_nr(bus), busnr); | |
bbe8f9a3 | 546 | goto out; |
1da177e4 LT |
547 | } |
548 | ||
6ef6f0e3 | 549 | child = pci_add_new_bus(bus, dev, busnr); |
1da177e4 | 550 | if (!child) |
bbe8f9a3 | 551 | goto out; |
1da177e4 LT |
552 | child->primary = buses & 0xFF; |
553 | child->subordinate = (buses >> 16) & 0xFF; | |
11949255 | 554 | child->bridge_ctl = bctl; |
1da177e4 LT |
555 | |
556 | cmax = pci_scan_child_bus(child); | |
557 | if (cmax > max) | |
558 | max = cmax; | |
559 | if (child->subordinate > max) | |
560 | max = child->subordinate; | |
561 | } else { | |
562 | /* | |
563 | * We need to assign a number to this bus which we always | |
564 | * do in the second pass. | |
565 | */ | |
12f44f46 IK |
566 | if (!pass) { |
567 | if (pcibios_assign_all_busses()) | |
568 | /* Temporarily disable forwarding of the | |
569 | configuration cycles on all bridges in | |
570 | this bus segment to avoid possible | |
571 | conflicts in the second pass between two | |
572 | bridges programmed with overlapping | |
573 | bus ranges. */ | |
574 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
575 | buses & ~0xffffff); | |
bbe8f9a3 | 576 | goto out; |
12f44f46 | 577 | } |
1da177e4 LT |
578 | |
579 | /* Clear errors */ | |
580 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
581 | ||
cc57450f RS |
582 | /* Prevent assigning a bus number that already exists. |
583 | * This can happen when a bridge is hot-plugged */ | |
584 | if (pci_find_bus(pci_domain_nr(bus), max+1)) | |
bbe8f9a3 | 585 | goto out; |
6ef6f0e3 | 586 | child = pci_add_new_bus(bus, dev, ++max); |
1da177e4 LT |
587 | buses = (buses & 0xff000000) |
588 | | ((unsigned int)(child->primary) << 0) | |
589 | | ((unsigned int)(child->secondary) << 8) | |
590 | | ((unsigned int)(child->subordinate) << 16); | |
591 | ||
592 | /* | |
593 | * yenta.c forces a secondary latency timer of 176. | |
594 | * Copy that behaviour here. | |
595 | */ | |
596 | if (is_cardbus) { | |
597 | buses &= ~0xff000000; | |
598 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
599 | } | |
600 | ||
601 | /* | |
602 | * We need to blast all three values with a single write. | |
603 | */ | |
604 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
605 | ||
606 | if (!is_cardbus) { | |
11949255 | 607 | child->bridge_ctl = bctl; |
26f674ae GKH |
608 | /* |
609 | * Adjust subordinate busnr in parent buses. | |
610 | * We do this before scanning for children because | |
611 | * some devices may not be detected if the bios | |
612 | * was lazy. | |
613 | */ | |
614 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
615 | /* Now we can scan all subordinate buses... */ |
616 | max = pci_scan_child_bus(child); | |
e3ac86d8 KA |
617 | /* |
618 | * now fix it up again since we have found | |
619 | * the real value of max. | |
620 | */ | |
621 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
622 | } else { |
623 | /* | |
624 | * For CardBus bridges, we leave 4 bus numbers | |
625 | * as cards with a PCI-to-PCI bridge can be | |
626 | * inserted later. | |
627 | */ | |
49887941 DB |
628 | for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
629 | struct pci_bus *parent = bus; | |
cc57450f RS |
630 | if (pci_find_bus(pci_domain_nr(bus), |
631 | max+i+1)) | |
632 | break; | |
49887941 DB |
633 | while (parent->parent) { |
634 | if ((!pcibios_assign_all_busses()) && | |
635 | (parent->subordinate > max) && | |
636 | (parent->subordinate <= max+i)) { | |
637 | j = 1; | |
638 | } | |
639 | parent = parent->parent; | |
640 | } | |
641 | if (j) { | |
642 | /* | |
643 | * Often, there are two cardbus bridges | |
644 | * -- try to leave one valid bus number | |
645 | * for each one. | |
646 | */ | |
647 | i /= 2; | |
648 | break; | |
649 | } | |
650 | } | |
cc57450f | 651 | max += i; |
26f674ae | 652 | pci_fixup_parent_subordinate_busnr(child, max); |
1da177e4 LT |
653 | } |
654 | /* | |
655 | * Set the subordinate bus number to its real value. | |
656 | */ | |
657 | child->subordinate = max; | |
658 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); | |
659 | } | |
660 | ||
cb3576fa GH |
661 | sprintf(child->name, |
662 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
663 | pci_domain_nr(bus), child->number); | |
1da177e4 | 664 | |
d55bef51 | 665 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 DB |
666 | while (bus->parent) { |
667 | if ((child->subordinate > bus->subordinate) || | |
668 | (child->number > bus->subordinate) || | |
669 | (child->number < bus->number) || | |
670 | (child->subordinate < bus->number)) { | |
a6f29a98 | 671 | pr_debug("PCI: Bus #%02x (-#%02x) is %s " |
d55bef51 BK |
672 | "hidden behind%s bridge #%02x (-#%02x)\n", |
673 | child->number, child->subordinate, | |
674 | (bus->number > child->subordinate && | |
675 | bus->subordinate < child->number) ? | |
a6f29a98 JP |
676 | "wholly" : "partially", |
677 | bus->self->transparent ? " transparent" : "", | |
d55bef51 | 678 | bus->number, bus->subordinate); |
49887941 DB |
679 | } |
680 | bus = bus->parent; | |
681 | } | |
682 | ||
bbe8f9a3 RB |
683 | out: |
684 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
685 | ||
1da177e4 LT |
686 | return max; |
687 | } | |
688 | ||
689 | /* | |
690 | * Read interrupt line and base address registers. | |
691 | * The architecture-dependent code can tweak these, of course. | |
692 | */ | |
693 | static void pci_read_irq(struct pci_dev *dev) | |
694 | { | |
695 | unsigned char irq; | |
696 | ||
697 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 698 | dev->pin = irq; |
1da177e4 LT |
699 | if (irq) |
700 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
701 | dev->irq = irq; | |
702 | } | |
703 | ||
01abc2aa | 704 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 705 | |
1da177e4 LT |
706 | /** |
707 | * pci_setup_device - fill in class and map information of a device | |
708 | * @dev: the device structure to fill | |
709 | * | |
710 | * Initialize the device structure with information about the device's | |
711 | * vendor,class,memory and IO-space addresses,IRQ lines etc. | |
712 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
713 | * Returns 0 on success and -1 if unknown type of device (not normal, bridge | |
714 | * or CardBus). | |
715 | */ | |
716 | static int pci_setup_device(struct pci_dev * dev) | |
717 | { | |
718 | u32 class; | |
719 | ||
eebfcfb5 GKH |
720 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
721 | dev->bus->number, PCI_SLOT(dev->devfn), | |
722 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
723 | |
724 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 725 | dev->revision = class & 0xff; |
1da177e4 LT |
726 | class >>= 8; /* upper 3 bytes */ |
727 | dev->class = class; | |
728 | class >>= 8; | |
729 | ||
80ccba11 | 730 | dev_dbg(&dev->dev, "found [%04x/%04x] class %06x header type %02x\n", |
1da177e4 LT |
731 | dev->vendor, dev->device, class, dev->hdr_type); |
732 | ||
733 | /* "Unknown power state" */ | |
3fe9d19f | 734 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
735 | |
736 | /* Early fixups, before probing the BARs */ | |
737 | pci_fixup_device(pci_fixup_early, dev); | |
738 | class = dev->class >> 8; | |
739 | ||
740 | switch (dev->hdr_type) { /* header type */ | |
741 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
742 | if (class == PCI_CLASS_BRIDGE_PCI) | |
743 | goto bad; | |
744 | pci_read_irq(dev); | |
745 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
746 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
747 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
748 | |
749 | /* | |
750 | * Do the ugly legacy mode stuff here rather than broken chip | |
751 | * quirk code. Legacy mode ATA controllers have fixed | |
752 | * addresses. These are not always echoed in BAR0-3, and | |
753 | * BAR0-3 in a few cases contain junk! | |
754 | */ | |
755 | if (class == PCI_CLASS_STORAGE_IDE) { | |
756 | u8 progif; | |
757 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
758 | if ((progif & 1) == 0) { | |
af1bff4f LT |
759 | dev->resource[0].start = 0x1F0; |
760 | dev->resource[0].end = 0x1F7; | |
761 | dev->resource[0].flags = LEGACY_IO_RESOURCE; | |
762 | dev->resource[1].start = 0x3F6; | |
763 | dev->resource[1].end = 0x3F6; | |
764 | dev->resource[1].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
765 | } |
766 | if ((progif & 4) == 0) { | |
af1bff4f LT |
767 | dev->resource[2].start = 0x170; |
768 | dev->resource[2].end = 0x177; | |
769 | dev->resource[2].flags = LEGACY_IO_RESOURCE; | |
770 | dev->resource[3].start = 0x376; | |
771 | dev->resource[3].end = 0x376; | |
772 | dev->resource[3].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
773 | } |
774 | } | |
1da177e4 LT |
775 | break; |
776 | ||
777 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
778 | if (class != PCI_CLASS_BRIDGE_PCI) | |
779 | goto bad; | |
780 | /* The PCI-to-PCI bridge spec requires that subtractive | |
781 | decoding (i.e. transparent) bridge must have programming | |
782 | interface code of 0x01. */ | |
3efd273b | 783 | pci_read_irq(dev); |
1da177e4 LT |
784 | dev->transparent = ((dev->class & 0xff) == 1); |
785 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
786 | break; | |
787 | ||
788 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
789 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
790 | goto bad; | |
791 | pci_read_irq(dev); | |
792 | pci_read_bases(dev, 1, 0); | |
793 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
794 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
795 | break; | |
796 | ||
797 | default: /* unknown header */ | |
80ccba11 BH |
798 | dev_err(&dev->dev, "unknown header type %02x, " |
799 | "ignoring device\n", dev->hdr_type); | |
1da177e4 LT |
800 | return -1; |
801 | ||
802 | bad: | |
80ccba11 BH |
803 | dev_err(&dev->dev, "ignoring class %02x (doesn't match header " |
804 | "type %02x)\n", class, dev->hdr_type); | |
1da177e4 LT |
805 | dev->class = PCI_CLASS_NOT_DEFINED; |
806 | } | |
807 | ||
808 | /* We found a fine healthy device, go go go... */ | |
809 | return 0; | |
810 | } | |
811 | ||
812 | /** | |
813 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
814 | * @dev: device that's been disconnected | |
815 | * | |
816 | * Will be called only by the device core when all users of this pci device are | |
817 | * done. | |
818 | */ | |
819 | static void pci_release_dev(struct device *dev) | |
820 | { | |
821 | struct pci_dev *pci_dev; | |
822 | ||
823 | pci_dev = to_pci_dev(dev); | |
94e61088 | 824 | pci_vpd_release(pci_dev); |
1da177e4 LT |
825 | kfree(pci_dev); |
826 | } | |
827 | ||
994a65e2 KA |
828 | static void set_pcie_port_type(struct pci_dev *pdev) |
829 | { | |
830 | int pos; | |
831 | u16 reg16; | |
832 | ||
833 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
834 | if (!pos) | |
835 | return; | |
836 | pdev->is_pcie = 1; | |
837 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
838 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; | |
839 | } | |
840 | ||
1da177e4 LT |
841 | /** |
842 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
8f7020d3 | 843 | * @dev: PCI device |
1da177e4 LT |
844 | * |
845 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
846 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
847 | * access it. Maybe we don't have a way to generate extended config space | |
848 | * accesses, or the device is behind a reverse Express bridge. So we try | |
849 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
850 | * capability header. | |
851 | */ | |
70b9f7dc | 852 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
1da177e4 | 853 | { |
1da177e4 LT |
854 | u32 status; |
855 | ||
70b9f7dc YL |
856 | if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL) |
857 | goto fail; | |
858 | if (status == 0xffffffff) | |
859 | goto fail; | |
860 | ||
861 | return PCI_CFG_SPACE_EXP_SIZE; | |
862 | ||
863 | fail: | |
864 | return PCI_CFG_SPACE_SIZE; | |
865 | } | |
866 | ||
867 | int pci_cfg_space_size(struct pci_dev *dev) | |
868 | { | |
869 | int pos; | |
870 | u32 status; | |
57741a77 | 871 | |
1da177e4 LT |
872 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
873 | if (!pos) { | |
874 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
875 | if (!pos) | |
876 | goto fail; | |
877 | ||
878 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
879 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
880 | goto fail; | |
881 | } | |
882 | ||
70b9f7dc | 883 | return pci_cfg_space_size_ext(dev); |
1da177e4 LT |
884 | |
885 | fail: | |
886 | return PCI_CFG_SPACE_SIZE; | |
887 | } | |
888 | ||
889 | static void pci_release_bus_bridge_dev(struct device *dev) | |
890 | { | |
891 | kfree(dev); | |
892 | } | |
893 | ||
65891215 ME |
894 | struct pci_dev *alloc_pci_dev(void) |
895 | { | |
896 | struct pci_dev *dev; | |
897 | ||
898 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
899 | if (!dev) | |
900 | return NULL; | |
901 | ||
65891215 ME |
902 | INIT_LIST_HEAD(&dev->bus_list); |
903 | ||
4aa9bc95 ME |
904 | pci_msi_init_pci_dev(dev); |
905 | ||
65891215 ME |
906 | return dev; |
907 | } | |
908 | EXPORT_SYMBOL(alloc_pci_dev); | |
909 | ||
1da177e4 LT |
910 | /* |
911 | * Read the config data for a PCI device, sanity-check it | |
912 | * and fill in the dev structure... | |
913 | */ | |
7f7b5de2 | 914 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) |
1da177e4 LT |
915 | { |
916 | struct pci_dev *dev; | |
917 | u32 l; | |
918 | u8 hdr_type; | |
919 | int delay = 1; | |
920 | ||
921 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
922 | return NULL; | |
923 | ||
924 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
925 | if (l == 0xffffffff || l == 0x00000000 || | |
926 | l == 0x0000ffff || l == 0xffff0000) | |
927 | return NULL; | |
928 | ||
929 | /* Configuration request Retry Status */ | |
930 | while (l == 0xffff0001) { | |
931 | msleep(delay); | |
932 | delay *= 2; | |
933 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
934 | return NULL; | |
935 | /* Card hasn't responded in 60 seconds? Must be stuck. */ | |
936 | if (delay > 60 * 1000) { | |
80ccba11 | 937 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
1da177e4 LT |
938 | "responding\n", pci_domain_nr(bus), |
939 | bus->number, PCI_SLOT(devfn), | |
940 | PCI_FUNC(devfn)); | |
941 | return NULL; | |
942 | } | |
943 | } | |
944 | ||
945 | if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type)) | |
946 | return NULL; | |
947 | ||
bab41e9b | 948 | dev = alloc_pci_dev(); |
1da177e4 LT |
949 | if (!dev) |
950 | return NULL; | |
951 | ||
1da177e4 LT |
952 | dev->bus = bus; |
953 | dev->sysdata = bus->sysdata; | |
954 | dev->dev.parent = bus->bridge; | |
955 | dev->dev.bus = &pci_bus_type; | |
956 | dev->devfn = devfn; | |
957 | dev->hdr_type = hdr_type & 0x7f; | |
958 | dev->multifunction = !!(hdr_type & 0x80); | |
959 | dev->vendor = l & 0xffff; | |
960 | dev->device = (l >> 16) & 0xffff; | |
961 | dev->cfg_size = pci_cfg_space_size(dev); | |
82081797 | 962 | dev->error_state = pci_channel_io_normal; |
994a65e2 | 963 | set_pcie_port_type(dev); |
1da177e4 LT |
964 | |
965 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
966 | set this higher, assuming the system even supports it. */ | |
967 | dev->dma_mask = 0xffffffff; | |
968 | if (pci_setup_device(dev) < 0) { | |
969 | kfree(dev); | |
970 | return NULL; | |
971 | } | |
1da177e4 | 972 | |
94e61088 BH |
973 | pci_vpd_pci22_init(dev); |
974 | ||
1da177e4 LT |
975 | return dev; |
976 | } | |
977 | ||
96bde06a | 978 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 979 | { |
cdb9b9f7 PM |
980 | device_initialize(&dev->dev); |
981 | dev->dev.release = pci_release_dev; | |
982 | pci_dev_get(dev); | |
1da177e4 | 983 | |
cdb9b9f7 | 984 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 985 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 986 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 987 | |
4d57cdfa | 988 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 989 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 990 | |
1da177e4 LT |
991 | /* Fix up broken headers */ |
992 | pci_fixup_device(pci_fixup_header, dev); | |
993 | ||
eb9d0fe4 RW |
994 | /* Initialize power management of the device */ |
995 | pci_pm_init(dev); | |
996 | ||
1da177e4 LT |
997 | /* |
998 | * Add the device to our list of discovered devices | |
999 | * and the bus list for fixup functions, etc. | |
1000 | */ | |
d71374da | 1001 | down_write(&pci_bus_sem); |
1da177e4 | 1002 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1003 | up_write(&pci_bus_sem); |
cdb9b9f7 PM |
1004 | } |
1005 | ||
451124a7 | 1006 | struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1007 | { |
1008 | struct pci_dev *dev; | |
1009 | ||
1010 | dev = pci_scan_device(bus, devfn); | |
1011 | if (!dev) | |
1012 | return NULL; | |
1013 | ||
1014 | pci_device_add(dev, bus); | |
1da177e4 LT |
1015 | |
1016 | return dev; | |
1017 | } | |
b73e9687 | 1018 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 LT |
1019 | |
1020 | /** | |
1021 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1022 | * @bus: PCI bus to scan | |
1023 | * @devfn: slot number to scan (must have zero function.) | |
1024 | * | |
1025 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1026 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1027 | * will not have is_added set. |
1da177e4 | 1028 | */ |
96bde06a | 1029 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 LT |
1030 | { |
1031 | int func, nr = 0; | |
1032 | int scan_all_fns; | |
1033 | ||
1034 | scan_all_fns = pcibios_scan_all_fns(bus, devfn); | |
1035 | ||
1036 | for (func = 0; func < 8; func++, devfn++) { | |
1037 | struct pci_dev *dev; | |
1038 | ||
1039 | dev = pci_scan_single_device(bus, devfn); | |
1040 | if (dev) { | |
1041 | nr++; | |
1042 | ||
1043 | /* | |
1044 | * If this is a single function device, | |
1045 | * don't scan past the first function. | |
1046 | */ | |
1047 | if (!dev->multifunction) { | |
1048 | if (func > 0) { | |
1049 | dev->multifunction = 1; | |
1050 | } else { | |
1051 | break; | |
1052 | } | |
1053 | } | |
1054 | } else { | |
1055 | if (func == 0 && !scan_all_fns) | |
1056 | break; | |
1057 | } | |
1058 | } | |
7d715a6c | 1059 | |
149e1637 SL |
1060 | /* only one slot has pcie device */ |
1061 | if (bus->self && nr) | |
7d715a6c SL |
1062 | pcie_aspm_init_link_state(bus->self); |
1063 | ||
1da177e4 LT |
1064 | return nr; |
1065 | } | |
1066 | ||
0ab2b57f | 1067 | unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 LT |
1068 | { |
1069 | unsigned int devfn, pass, max = bus->secondary; | |
1070 | struct pci_dev *dev; | |
1071 | ||
1072 | pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number); | |
1073 | ||
1074 | /* Go find them, Rover! */ | |
1075 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1076 | pci_scan_slot(bus, devfn); | |
1077 | ||
1078 | /* | |
1079 | * After performing arch-dependent fixup of the bus, look behind | |
1080 | * all PCI-to-PCI bridges on this bus. | |
1081 | */ | |
1082 | pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number); | |
1083 | pcibios_fixup_bus(bus); | |
1084 | for (pass=0; pass < 2; pass++) | |
1085 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1086 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1087 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1088 | max = pci_scan_bridge(bus, dev, max, pass); | |
1089 | } | |
1090 | ||
1091 | /* | |
1092 | * We've scanned the bus and so we know all about what's on | |
1093 | * the other side of any bridges that may be on this bus plus | |
1094 | * any devices. | |
1095 | * | |
1096 | * Return how far we've got finding sub-buses. | |
1097 | */ | |
1098 | pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n", | |
1099 | pci_domain_nr(bus), bus->number, max); | |
1100 | return max; | |
1101 | } | |
1102 | ||
30a18d6c YL |
1103 | void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b) |
1104 | { | |
1105 | } | |
1106 | ||
96bde06a | 1107 | struct pci_bus * pci_create_bus(struct device *parent, |
cdb9b9f7 | 1108 | int bus, struct pci_ops *ops, void *sysdata) |
1da177e4 LT |
1109 | { |
1110 | int error; | |
1111 | struct pci_bus *b; | |
1112 | struct device *dev; | |
1113 | ||
1114 | b = pci_alloc_bus(); | |
1115 | if (!b) | |
1116 | return NULL; | |
1117 | ||
1118 | dev = kmalloc(sizeof(*dev), GFP_KERNEL); | |
1119 | if (!dev){ | |
1120 | kfree(b); | |
1121 | return NULL; | |
1122 | } | |
1123 | ||
1124 | b->sysdata = sysdata; | |
1125 | b->ops = ops; | |
1126 | ||
1127 | if (pci_find_bus(pci_domain_nr(b), bus)) { | |
1128 | /* If we already got to this bus through a different bridge, ignore it */ | |
1129 | pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); | |
1130 | goto err_out; | |
1131 | } | |
d71374da ZY |
1132 | |
1133 | down_write(&pci_bus_sem); | |
1da177e4 | 1134 | list_add_tail(&b->node, &pci_root_buses); |
d71374da | 1135 | up_write(&pci_bus_sem); |
1da177e4 LT |
1136 | |
1137 | memset(dev, 0, sizeof(*dev)); | |
1138 | dev->parent = parent; | |
1139 | dev->release = pci_release_bus_bridge_dev; | |
1140 | sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus); | |
1141 | error = device_register(dev); | |
1142 | if (error) | |
1143 | goto dev_reg_err; | |
1144 | b->bridge = get_device(dev); | |
1145 | ||
0d358f22 YL |
1146 | if (!parent) |
1147 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
1148 | ||
fd7d1ced GKH |
1149 | b->dev.class = &pcibus_class; |
1150 | b->dev.parent = b->bridge; | |
1151 | sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus); | |
1152 | error = device_register(&b->dev); | |
1da177e4 LT |
1153 | if (error) |
1154 | goto class_dev_reg_err; | |
fd7d1ced | 1155 | error = device_create_file(&b->dev, &dev_attr_cpuaffinity); |
1da177e4 | 1156 | if (error) |
fd7d1ced | 1157 | goto dev_create_file_err; |
1da177e4 LT |
1158 | |
1159 | /* Create legacy_io and legacy_mem files for this bus */ | |
1160 | pci_create_legacy_files(b); | |
1161 | ||
1da177e4 LT |
1162 | b->number = b->secondary = bus; |
1163 | b->resource[0] = &ioport_resource; | |
1164 | b->resource[1] = &iomem_resource; | |
1165 | ||
30a18d6c YL |
1166 | set_pci_bus_resources_arch_default(b); |
1167 | ||
1da177e4 LT |
1168 | return b; |
1169 | ||
fd7d1ced GKH |
1170 | dev_create_file_err: |
1171 | device_unregister(&b->dev); | |
1da177e4 LT |
1172 | class_dev_reg_err: |
1173 | device_unregister(dev); | |
1174 | dev_reg_err: | |
d71374da | 1175 | down_write(&pci_bus_sem); |
1da177e4 | 1176 | list_del(&b->node); |
d71374da | 1177 | up_write(&pci_bus_sem); |
1da177e4 LT |
1178 | err_out: |
1179 | kfree(dev); | |
1180 | kfree(b); | |
1181 | return NULL; | |
1182 | } | |
cdb9b9f7 | 1183 | |
0ab2b57f | 1184 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
1185 | int bus, struct pci_ops *ops, void *sysdata) |
1186 | { | |
1187 | struct pci_bus *b; | |
1188 | ||
1189 | b = pci_create_bus(parent, bus, ops, sysdata); | |
1190 | if (b) | |
1191 | b->subordinate = pci_scan_child_bus(b); | |
1192 | return b; | |
1193 | } | |
1da177e4 LT |
1194 | EXPORT_SYMBOL(pci_scan_bus_parented); |
1195 | ||
1196 | #ifdef CONFIG_HOTPLUG | |
1197 | EXPORT_SYMBOL(pci_add_new_bus); | |
1da177e4 LT |
1198 | EXPORT_SYMBOL(pci_scan_slot); |
1199 | EXPORT_SYMBOL(pci_scan_bridge); | |
1da177e4 LT |
1200 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1201 | #endif | |
6b4b78fe MD |
1202 | |
1203 | static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b) | |
1204 | { | |
1205 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; | |
1206 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
1207 | ||
1208 | if (a->bus->number < b->bus->number) return -1; | |
1209 | else if (a->bus->number > b->bus->number) return 1; | |
1210 | ||
1211 | if (a->devfn < b->devfn) return -1; | |
1212 | else if (a->devfn > b->devfn) return 1; | |
1213 | ||
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | /* | |
1218 | * Yes, this forcably breaks the klist abstraction temporarily. It | |
1219 | * just wants to sort the klist, not change reference counts and | |
1220 | * take/drop locks rapidly in the process. It does all this while | |
1221 | * holding the lock for the list, so objects can't otherwise be | |
1222 | * added/removed while we're swizzling. | |
1223 | */ | |
1224 | static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list) | |
1225 | { | |
1226 | struct list_head *pos; | |
1227 | struct klist_node *n; | |
1228 | struct device *dev; | |
1229 | struct pci_dev *b; | |
1230 | ||
1231 | list_for_each(pos, list) { | |
1232 | n = container_of(pos, struct klist_node, n_node); | |
1233 | dev = container_of(n, struct device, knode_bus); | |
1234 | b = to_pci_dev(dev); | |
1235 | if (pci_sort_bf_cmp(a, b) <= 0) { | |
1236 | list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node); | |
1237 | return; | |
1238 | } | |
1239 | } | |
1240 | list_move_tail(&a->dev.knode_bus.n_node, list); | |
1241 | } | |
1242 | ||
5ff580c1 | 1243 | void __init pci_sort_breadthfirst(void) |
6b4b78fe MD |
1244 | { |
1245 | LIST_HEAD(sorted_devices); | |
1246 | struct list_head *pos, *tmp; | |
1247 | struct klist_node *n; | |
1248 | struct device *dev; | |
1249 | struct pci_dev *pdev; | |
b249072e | 1250 | struct klist *device_klist; |
6b4b78fe | 1251 | |
b249072e GKH |
1252 | device_klist = bus_get_device_klist(&pci_bus_type); |
1253 | ||
1254 | spin_lock(&device_klist->k_lock); | |
1255 | list_for_each_safe(pos, tmp, &device_klist->k_list) { | |
6b4b78fe MD |
1256 | n = container_of(pos, struct klist_node, n_node); |
1257 | dev = container_of(n, struct device, knode_bus); | |
1258 | pdev = to_pci_dev(dev); | |
1259 | pci_insertion_sort_klist(pdev, &sorted_devices); | |
1260 | } | |
b249072e GKH |
1261 | list_splice(&sorted_devices, &device_klist->k_list); |
1262 | spin_unlock(&device_klist->k_lock); | |
6b4b78fe | 1263 | } |