Commit | Line | Data |
---|---|---|
7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI detection and setup code |
1da177e4 LT |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/delay.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/pci.h> | |
bbd8810d | 10 | #include <linux/msi.h> |
50230713 | 11 | #include <linux/of_device.h> |
de335bb4 | 12 | #include <linux/of_pci.h> |
589fcc23 | 13 | #include <linux/pci_hotplug.h> |
1da177e4 LT |
14 | #include <linux/slab.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/cpumask.h> | |
b07461a8 | 17 | #include <linux/aer.h> |
29dbe1f0 | 18 | #include <linux/acpi.h> |
690f4304 | 19 | #include <linux/hypervisor.h> |
788858eb | 20 | #include <linux/irqdomain.h> |
d963f651 | 21 | #include <linux/pm_runtime.h> |
69139244 | 22 | #include <linux/bitfield.h> |
bc56b9e0 | 23 | #include "pci.h" |
1da177e4 LT |
24 | |
25 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
26 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 | 27 | |
0b950f0f | 28 | static struct resource busn_resource = { |
67cdc827 YL |
29 | .name = "PCI busn", |
30 | .start = 0, | |
31 | .end = 255, | |
32 | .flags = IORESOURCE_BUS, | |
33 | }; | |
34 | ||
1da177e4 LT |
35 | /* Ugh. Need to stop exporting this to modules. */ |
36 | LIST_HEAD(pci_root_buses); | |
37 | EXPORT_SYMBOL(pci_root_buses); | |
38 | ||
5cc62c20 YL |
39 | static LIST_HEAD(pci_domain_busn_res_list); |
40 | ||
41 | struct pci_domain_busn_res { | |
42 | struct list_head list; | |
43 | struct resource res; | |
44 | int domain_nr; | |
45 | }; | |
46 | ||
47 | static struct resource *get_pci_domain_busn_res(int domain_nr) | |
48 | { | |
49 | struct pci_domain_busn_res *r; | |
50 | ||
51 | list_for_each_entry(r, &pci_domain_busn_res_list, list) | |
52 | if (r->domain_nr == domain_nr) | |
53 | return &r->res; | |
54 | ||
55 | r = kzalloc(sizeof(*r), GFP_KERNEL); | |
56 | if (!r) | |
57 | return NULL; | |
58 | ||
59 | r->domain_nr = domain_nr; | |
60 | r->res.start = 0; | |
61 | r->res.end = 0xff; | |
62 | r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; | |
63 | ||
64 | list_add_tail(&r->list, &pci_domain_busn_res_list); | |
65 | ||
66 | return &r->res; | |
67 | } | |
68 | ||
ed4aaadb | 69 | /* |
3e466e2d BH |
70 | * Some device drivers need know if PCI is initiated. |
71 | * Basically, we think PCI is not initiated when there | |
70308923 | 72 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
73 | */ |
74 | int no_pci_devices(void) | |
75 | { | |
70308923 GKH |
76 | struct device *dev; |
77 | int no_devices; | |
ed4aaadb | 78 | |
6bf85ba9 | 79 | dev = bus_find_next_device(&pci_bus_type, NULL); |
70308923 GKH |
80 | no_devices = (dev == NULL); |
81 | put_device(dev); | |
82 | return no_devices; | |
83 | } | |
ed4aaadb ZY |
84 | EXPORT_SYMBOL(no_pci_devices); |
85 | ||
1da177e4 LT |
86 | /* |
87 | * PCI Bus Class | |
88 | */ | |
fd7d1ced | 89 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 90 | { |
fd7d1ced | 91 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 | 92 | |
ff0387c3 | 93 | put_device(pci_bus->bridge); |
2fe2abf8 | 94 | pci_bus_remove_resources(pci_bus); |
98d9f30c | 95 | pci_release_bus_of_node(pci_bus); |
1da177e4 LT |
96 | kfree(pci_bus); |
97 | } | |
98 | ||
99 | static struct class pcibus_class = { | |
100 | .name = "pci_bus", | |
fd7d1ced | 101 | .dev_release = &release_pcibus_dev, |
56039e65 | 102 | .dev_groups = pcibus_groups, |
1da177e4 LT |
103 | }; |
104 | ||
105 | static int __init pcibus_class_init(void) | |
106 | { | |
107 | return class_register(&pcibus_class); | |
108 | } | |
109 | postcore_initcall(pcibus_class_init); | |
110 | ||
6ac665c6 | 111 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 112 | { |
6ac665c6 | 113 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
114 | if (!size) |
115 | return 0; | |
116 | ||
3e466e2d BH |
117 | /* |
118 | * Get the lowest of them to find the decode size, and from that | |
119 | * the extent. | |
120 | */ | |
01b37f85 | 121 | size = size & ~(size-1); |
1da177e4 | 122 | |
3e466e2d BH |
123 | /* |
124 | * base == maxbase can be valid only if the BAR has already been | |
125 | * programmed with all 1s. | |
126 | */ | |
01b37f85 | 127 | if (base == maxbase && ((base | (size - 1)) & mask) != mask) |
1da177e4 LT |
128 | return 0; |
129 | ||
130 | return size; | |
131 | } | |
132 | ||
28c6821a | 133 | static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) |
6ac665c6 | 134 | { |
8d6a6a47 | 135 | u32 mem_type; |
28c6821a | 136 | unsigned long flags; |
8d6a6a47 | 137 | |
6ac665c6 | 138 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
28c6821a BH |
139 | flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
140 | flags |= IORESOURCE_IO; | |
141 | return flags; | |
6ac665c6 | 142 | } |
07eddf3d | 143 | |
28c6821a BH |
144 | flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
145 | flags |= IORESOURCE_MEM; | |
146 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
147 | flags |= IORESOURCE_PREFETCH; | |
07eddf3d | 148 | |
8d6a6a47 BH |
149 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
150 | switch (mem_type) { | |
151 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
152 | break; | |
153 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
0ff9514b | 154 | /* 1M mem BAR treated as 32-bit BAR */ |
8d6a6a47 BH |
155 | break; |
156 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
28c6821a BH |
157 | flags |= IORESOURCE_MEM_64; |
158 | break; | |
8d6a6a47 | 159 | default: |
0ff9514b | 160 | /* mem unknown type treated as 32-bit BAR */ |
8d6a6a47 BH |
161 | break; |
162 | } | |
28c6821a | 163 | return flags; |
07eddf3d YL |
164 | } |
165 | ||
808e34e2 ZK |
166 | #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) |
167 | ||
0b400c7e | 168 | /** |
2f0cd59c | 169 | * __pci_read_base - Read a PCI BAR |
0b400c7e YZ |
170 | * @dev: the PCI device |
171 | * @type: type of the BAR | |
172 | * @res: resource buffer to be filled in | |
173 | * @pos: BAR position in the config space | |
174 | * | |
175 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 176 | */ |
0b400c7e | 177 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
3c78bc61 | 178 | struct resource *res, unsigned int pos) |
07eddf3d | 179 | { |
dc5205ef | 180 | u32 l = 0, sz = 0, mask; |
23b13bc7 | 181 | u64 l64, sz64, mask64; |
253d2e54 | 182 | u16 orig_cmd; |
cf4d1cf5 | 183 | struct pci_bus_region region, inverted_region; |
6ac665c6 | 184 | |
1ed67439 | 185 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
6ac665c6 | 186 | |
0ff9514b | 187 | /* No printks while decoding is disabled! */ |
253d2e54 JP |
188 | if (!dev->mmio_always_on) { |
189 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); | |
808e34e2 ZK |
190 | if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { |
191 | pci_write_config_word(dev, PCI_COMMAND, | |
192 | orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); | |
193 | } | |
253d2e54 JP |
194 | } |
195 | ||
6ac665c6 MW |
196 | res->name = pci_name(dev); |
197 | ||
198 | pci_read_config_dword(dev, pos, &l); | |
1ed67439 | 199 | pci_write_config_dword(dev, pos, l | mask); |
6ac665c6 MW |
200 | pci_read_config_dword(dev, pos, &sz); |
201 | pci_write_config_dword(dev, pos, l); | |
202 | ||
203 | /* | |
204 | * All bits set in sz means the device isn't working properly. | |
45aa23b4 BH |
205 | * If the BAR isn't implemented, all bits must be 0. If it's a |
206 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
207 | * 1 must be clear. | |
6ac665c6 | 208 | */ |
fa52b644 | 209 | if (PCI_POSSIBLE_ERROR(sz)) |
f795d86a | 210 | sz = 0; |
6ac665c6 MW |
211 | |
212 | /* | |
213 | * I don't know how l can have all bits set. Copied from old code. | |
214 | * Maybe it fixes a bug on some ancient platform. | |
215 | */ | |
fa52b644 | 216 | if (PCI_POSSIBLE_ERROR(l)) |
6ac665c6 MW |
217 | l = 0; |
218 | ||
219 | if (type == pci_bar_unknown) { | |
28c6821a BH |
220 | res->flags = decode_bar(dev, l); |
221 | res->flags |= IORESOURCE_SIZEALIGN; | |
222 | if (res->flags & IORESOURCE_IO) { | |
f795d86a MS |
223 | l64 = l & PCI_BASE_ADDRESS_IO_MASK; |
224 | sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; | |
225 | mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; | |
6ac665c6 | 226 | } else { |
f795d86a MS |
227 | l64 = l & PCI_BASE_ADDRESS_MEM_MASK; |
228 | sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; | |
229 | mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
6ac665c6 MW |
230 | } |
231 | } else { | |
7a6d312b BH |
232 | if (l & PCI_ROM_ADDRESS_ENABLE) |
233 | res->flags |= IORESOURCE_ROM_ENABLE; | |
f795d86a MS |
234 | l64 = l & PCI_ROM_ADDRESS_MASK; |
235 | sz64 = sz & PCI_ROM_ADDRESS_MASK; | |
76dc5268 | 236 | mask64 = PCI_ROM_ADDRESS_MASK; |
6ac665c6 MW |
237 | } |
238 | ||
28c6821a | 239 | if (res->flags & IORESOURCE_MEM_64) { |
6ac665c6 MW |
240 | pci_read_config_dword(dev, pos + 4, &l); |
241 | pci_write_config_dword(dev, pos + 4, ~0); | |
242 | pci_read_config_dword(dev, pos + 4, &sz); | |
243 | pci_write_config_dword(dev, pos + 4, l); | |
244 | ||
245 | l64 |= ((u64)l << 32); | |
246 | sz64 |= ((u64)sz << 32); | |
f795d86a MS |
247 | mask64 |= ((u64)~0 << 32); |
248 | } | |
6ac665c6 | 249 | |
f795d86a MS |
250 | if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) |
251 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); | |
6ac665c6 | 252 | |
f795d86a MS |
253 | if (!sz64) |
254 | goto fail; | |
6ac665c6 | 255 | |
f795d86a | 256 | sz64 = pci_size(l64, sz64, mask64); |
7e79c5f8 | 257 | if (!sz64) { |
7506dc79 | 258 | pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", |
7e79c5f8 | 259 | pos); |
f795d86a | 260 | goto fail; |
7e79c5f8 | 261 | } |
f795d86a MS |
262 | |
263 | if (res->flags & IORESOURCE_MEM_64) { | |
3a9ad0b4 YL |
264 | if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) |
265 | && sz64 > 0x100000000ULL) { | |
23b13bc7 BH |
266 | res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; |
267 | res->start = 0; | |
268 | res->end = 0; | |
7506dc79 | 269 | pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", |
f795d86a | 270 | pos, (unsigned long long)sz64); |
23b13bc7 | 271 | goto out; |
c7dabef8 BH |
272 | } |
273 | ||
3a9ad0b4 | 274 | if ((sizeof(pci_bus_addr_t) < 8) && l) { |
31e9dd25 | 275 | /* Above 32-bit boundary; try to reallocate */ |
c83bd900 | 276 | res->flags |= IORESOURCE_UNSET; |
72dc5601 | 277 | res->start = 0; |
01b37f85 | 278 | res->end = sz64 - 1; |
7506dc79 | 279 | pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", |
f795d86a | 280 | pos, (unsigned long long)l64); |
72dc5601 | 281 | goto out; |
6ac665c6 | 282 | } |
6ac665c6 MW |
283 | } |
284 | ||
f795d86a | 285 | region.start = l64; |
01b37f85 | 286 | region.end = l64 + sz64 - 1; |
f795d86a | 287 | |
fc279850 YL |
288 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
289 | pcibios_resource_to_bus(dev->bus, &inverted_region, res); | |
cf4d1cf5 KH |
290 | |
291 | /* | |
292 | * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is | |
293 | * the corresponding resource address (the physical address used by | |
294 | * the CPU. Converting that resource address back to a bus address | |
295 | * should yield the original BAR value: | |
296 | * | |
297 | * resource_to_bus(bus_to_resource(A)) == A | |
298 | * | |
299 | * If it doesn't, CPU accesses to "bus_to_resource(A)" will not | |
300 | * be claimed by the device. | |
301 | */ | |
302 | if (inverted_region.start != region.start) { | |
cf4d1cf5 | 303 | res->flags |= IORESOURCE_UNSET; |
cf4d1cf5 | 304 | res->start = 0; |
26370fc6 | 305 | res->end = region.end - region.start; |
7506dc79 | 306 | pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", |
f795d86a | 307 | pos, (unsigned long long)region.start); |
cf4d1cf5 | 308 | } |
96ddef25 | 309 | |
0ff9514b BH |
310 | goto out; |
311 | ||
312 | ||
313 | fail: | |
314 | res->flags = 0; | |
315 | out: | |
31e9dd25 | 316 | if (res->flags) |
34c6b710 | 317 | pci_info(dev, "reg 0x%x: %pR\n", pos, res); |
0ff9514b | 318 | |
28c6821a | 319 | return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; |
07eddf3d YL |
320 | } |
321 | ||
1da177e4 LT |
322 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
323 | { | |
6ac665c6 | 324 | unsigned int pos, reg; |
07eddf3d | 325 | |
ad67b437 PB |
326 | if (dev->non_compliant_bars) |
327 | return; | |
328 | ||
bf4447fd KA |
329 | /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ |
330 | if (dev->is_virtfn) | |
331 | return; | |
332 | ||
6ac665c6 MW |
333 | for (pos = 0; pos < howmany; pos++) { |
334 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 335 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 336 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 337 | } |
6ac665c6 | 338 | |
1da177e4 | 339 | if (rom) { |
6ac665c6 | 340 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 341 | dev->rom_base_reg = rom; |
6ac665c6 | 342 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
92b19ff5 | 343 | IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; |
6ac665c6 | 344 | __pci_read_base(dev, pci_bar_mem32, res, rom); |
1da177e4 LT |
345 | } |
346 | } | |
347 | ||
51c48b31 BH |
348 | static void pci_read_bridge_windows(struct pci_dev *bridge) |
349 | { | |
350 | u16 io; | |
351 | u32 pmem, tmp; | |
352 | ||
353 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
354 | if (!io) { | |
355 | pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); | |
356 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
357 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
358 | } | |
359 | if (io) | |
360 | bridge->io_window = 1; | |
361 | ||
362 | /* | |
363 | * DECchip 21050 pass 2 errata: the bridge may miss an address | |
364 | * disconnect boundary by one PCI data phase. Workaround: do not | |
365 | * use prefetching on this device. | |
366 | */ | |
367 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
368 | return; | |
369 | ||
370 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
371 | if (!pmem) { | |
372 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
373 | 0xffe0fff0); | |
374 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
375 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
376 | } | |
377 | if (!pmem) | |
378 | return; | |
379 | ||
380 | bridge->pref_window = 1; | |
381 | ||
382 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
383 | ||
384 | /* | |
385 | * Bridge claims to have a 64-bit prefetchable memory | |
386 | * window; verify that the upper bits are actually | |
387 | * writable. | |
388 | */ | |
389 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); | |
390 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
391 | 0xffffffff); | |
392 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
393 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); | |
394 | if (tmp) | |
395 | bridge->pref_64_window = 1; | |
396 | } | |
397 | } | |
398 | ||
15856ad5 | 399 | static void pci_read_bridge_io(struct pci_bus *child) |
1da177e4 LT |
400 | { |
401 | struct pci_dev *dev = child->self; | |
402 | u8 io_base_lo, io_limit_lo; | |
2b28ae19 | 403 | unsigned long io_mask, io_granularity, base, limit; |
5bfa14ed | 404 | struct pci_bus_region region; |
2b28ae19 BH |
405 | struct resource *res; |
406 | ||
407 | io_mask = PCI_IO_RANGE_MASK; | |
408 | io_granularity = 0x1000; | |
409 | if (dev->io_window_1k) { | |
410 | /* Support 1K I/O space granularity */ | |
411 | io_mask = PCI_IO_1K_RANGE_MASK; | |
412 | io_granularity = 0x400; | |
413 | } | |
1da177e4 | 414 | |
1da177e4 LT |
415 | res = child->resource[0]; |
416 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
417 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
2b28ae19 BH |
418 | base = (io_base_lo & io_mask) << 8; |
419 | limit = (io_limit_lo & io_mask) << 8; | |
1da177e4 LT |
420 | |
421 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
422 | u16 io_base_hi, io_limit_hi; | |
8f38eaca | 423 | |
1da177e4 LT |
424 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); |
425 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
8f38eaca BH |
426 | base |= ((unsigned long) io_base_hi << 16); |
427 | limit |= ((unsigned long) io_limit_hi << 16); | |
1da177e4 LT |
428 | } |
429 | ||
5dde383e | 430 | if (base <= limit) { |
1da177e4 | 431 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
5bfa14ed | 432 | region.start = base; |
2b28ae19 | 433 | region.end = limit + io_granularity - 1; |
fc279850 | 434 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
34c6b710 | 435 | pci_info(dev, " bridge window %pR\n", res); |
1da177e4 | 436 | } |
fa27b2d1 BH |
437 | } |
438 | ||
15856ad5 | 439 | static void pci_read_bridge_mmio(struct pci_bus *child) |
fa27b2d1 BH |
440 | { |
441 | struct pci_dev *dev = child->self; | |
442 | u16 mem_base_lo, mem_limit_lo; | |
443 | unsigned long base, limit; | |
5bfa14ed | 444 | struct pci_bus_region region; |
fa27b2d1 | 445 | struct resource *res; |
1da177e4 LT |
446 | |
447 | res = child->resource[1]; | |
448 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
449 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
8f38eaca BH |
450 | base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; |
451 | limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
5dde383e | 452 | if (base <= limit) { |
1da177e4 | 453 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
5bfa14ed BH |
454 | region.start = base; |
455 | region.end = limit + 0xfffff; | |
fc279850 | 456 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
34c6b710 | 457 | pci_info(dev, " bridge window %pR\n", res); |
1da177e4 | 458 | } |
fa27b2d1 BH |
459 | } |
460 | ||
15856ad5 | 461 | static void pci_read_bridge_mmio_pref(struct pci_bus *child) |
fa27b2d1 BH |
462 | { |
463 | struct pci_dev *dev = child->self; | |
464 | u16 mem_base_lo, mem_limit_lo; | |
7fc986d8 | 465 | u64 base64, limit64; |
3a9ad0b4 | 466 | pci_bus_addr_t base, limit; |
5bfa14ed | 467 | struct pci_bus_region region; |
fa27b2d1 | 468 | struct resource *res; |
1da177e4 LT |
469 | |
470 | res = child->resource[2]; | |
471 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
472 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
7fc986d8 YL |
473 | base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; |
474 | limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
1da177e4 LT |
475 | |
476 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
477 | u32 mem_base_hi, mem_limit_hi; | |
8f38eaca | 478 | |
1da177e4 LT |
479 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); |
480 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
481 | ||
482 | /* | |
483 | * Some bridges set the base > limit by default, and some | |
484 | * (broken) BIOSes do not initialize them. If we find | |
485 | * this, just assume they are not being used. | |
486 | */ | |
487 | if (mem_base_hi <= mem_limit_hi) { | |
7fc986d8 YL |
488 | base64 |= (u64) mem_base_hi << 32; |
489 | limit64 |= (u64) mem_limit_hi << 32; | |
1da177e4 LT |
490 | } |
491 | } | |
7fc986d8 | 492 | |
3a9ad0b4 YL |
493 | base = (pci_bus_addr_t) base64; |
494 | limit = (pci_bus_addr_t) limit64; | |
7fc986d8 YL |
495 | |
496 | if (base != base64) { | |
7506dc79 | 497 | pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", |
7fc986d8 YL |
498 | (unsigned long long) base64); |
499 | return; | |
500 | } | |
501 | ||
5dde383e | 502 | if (base <= limit) { |
1f82de10 YL |
503 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
504 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
505 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
506 | res->flags |= IORESOURCE_MEM_64; | |
5bfa14ed BH |
507 | region.start = base; |
508 | region.end = limit + 0xfffff; | |
fc279850 | 509 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
34c6b710 | 510 | pci_info(dev, " bridge window %pR\n", res); |
1da177e4 LT |
511 | } |
512 | } | |
513 | ||
15856ad5 | 514 | void pci_read_bridge_bases(struct pci_bus *child) |
fa27b2d1 BH |
515 | { |
516 | struct pci_dev *dev = child->self; | |
2fe2abf8 | 517 | struct resource *res; |
fa27b2d1 BH |
518 | int i; |
519 | ||
520 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ | |
521 | return; | |
522 | ||
7506dc79 | 523 | pci_info(dev, "PCI bridge to %pR%s\n", |
b918c62e | 524 | &child->busn_res, |
fa27b2d1 BH |
525 | dev->transparent ? " (subtractive decode)" : ""); |
526 | ||
2fe2abf8 BH |
527 | pci_bus_remove_resources(child); |
528 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
529 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
530 | ||
fa27b2d1 BH |
531 | pci_read_bridge_io(child); |
532 | pci_read_bridge_mmio(child); | |
533 | pci_read_bridge_mmio_pref(child); | |
2adf7516 BH |
534 | |
535 | if (dev->transparent) { | |
2fe2abf8 | 536 | pci_bus_for_each_resource(child->parent, res, i) { |
d739a099 | 537 | if (res && res->flags) { |
2fe2abf8 BH |
538 | pci_bus_add_resource(child, res, |
539 | PCI_SUBTRACTIVE_DECODE); | |
34c6b710 | 540 | pci_info(dev, " bridge window %pR (subtractive decode)\n", |
2fe2abf8 BH |
541 | res); |
542 | } | |
2adf7516 BH |
543 | } |
544 | } | |
fa27b2d1 BH |
545 | } |
546 | ||
670ba0c8 | 547 | static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) |
1da177e4 LT |
548 | { |
549 | struct pci_bus *b; | |
550 | ||
f5afe806 | 551 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
05013486 BH |
552 | if (!b) |
553 | return NULL; | |
554 | ||
555 | INIT_LIST_HEAD(&b->node); | |
556 | INIT_LIST_HEAD(&b->children); | |
557 | INIT_LIST_HEAD(&b->devices); | |
558 | INIT_LIST_HEAD(&b->slots); | |
559 | INIT_LIST_HEAD(&b->resources); | |
560 | b->max_bus_speed = PCI_SPEED_UNKNOWN; | |
561 | b->cur_bus_speed = PCI_SPEED_UNKNOWN; | |
670ba0c8 CM |
562 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
563 | if (parent) | |
564 | b->domain_nr = parent->domain_nr; | |
565 | #endif | |
1da177e4 LT |
566 | return b; |
567 | } | |
568 | ||
9885440b | 569 | static void pci_release_host_bridge_dev(struct device *dev) |
70efde2a JL |
570 | { |
571 | struct pci_host_bridge *bridge = to_pci_host_bridge(dev); | |
572 | ||
573 | if (bridge->release_fn) | |
574 | bridge->release_fn(bridge); | |
3bbce531 JK |
575 | |
576 | pci_free_resource_list(&bridge->windows); | |
7608158d | 577 | pci_free_resource_list(&bridge->dma_ranges); |
9885440b | 578 | kfree(bridge); |
70efde2a JL |
579 | } |
580 | ||
6302bf3e | 581 | static void pci_init_host_bridge(struct pci_host_bridge *bridge) |
7b543663 | 582 | { |
05013486 | 583 | INIT_LIST_HEAD(&bridge->windows); |
e80a91ad | 584 | INIT_LIST_HEAD(&bridge->dma_ranges); |
37d6a0a6 | 585 | |
02bfeb48 BH |
586 | /* |
587 | * We assume we can manage these PCIe features. Some systems may | |
588 | * reserve these for use by the platform itself, e.g., an ACPI BIOS | |
589 | * may implement its own AER handling and use _OSC to prevent the | |
590 | * OS from interfering. | |
591 | */ | |
592 | bridge->native_aer = 1; | |
9310f0dc | 593 | bridge->native_pcie_hotplug = 1; |
1df81a6d | 594 | bridge->native_shpc_hotplug = 1; |
02bfeb48 | 595 | bridge->native_pme = 1; |
af8bb9f8 | 596 | bridge->native_ltr = 1; |
ac1c8e35 | 597 | bridge->native_dpc = 1; |
15d82ca2 | 598 | bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; |
9885440b RH |
599 | |
600 | device_initialize(&bridge->dev); | |
6302bf3e JPB |
601 | } |
602 | ||
603 | struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) | |
604 | { | |
605 | struct pci_host_bridge *bridge; | |
606 | ||
607 | bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); | |
608 | if (!bridge) | |
609 | return NULL; | |
610 | ||
611 | pci_init_host_bridge(bridge); | |
612 | bridge->dev.release = pci_release_host_bridge_dev; | |
02bfeb48 | 613 | |
7b543663 YL |
614 | return bridge; |
615 | } | |
a52d1443 | 616 | EXPORT_SYMBOL(pci_alloc_host_bridge); |
7b543663 | 617 | |
9885440b RH |
618 | static void devm_pci_alloc_host_bridge_release(void *data) |
619 | { | |
620 | pci_free_host_bridge(data); | |
621 | } | |
622 | ||
5c3f18cc LP |
623 | struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, |
624 | size_t priv) | |
625 | { | |
9885440b | 626 | int ret; |
5c3f18cc LP |
627 | struct pci_host_bridge *bridge; |
628 | ||
9885440b | 629 | bridge = pci_alloc_host_bridge(priv); |
5c3f18cc LP |
630 | if (!bridge) |
631 | return NULL; | |
632 | ||
6a589900 RH |
633 | bridge->dev.parent = dev; |
634 | ||
9885440b RH |
635 | ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, |
636 | bridge); | |
637 | if (ret) | |
638 | return NULL; | |
5c3f18cc | 639 | |
669cbc70 RH |
640 | ret = devm_of_pci_bridge_init(dev, bridge); |
641 | if (ret) | |
642 | return NULL; | |
643 | ||
5c3f18cc LP |
644 | return bridge; |
645 | } | |
646 | EXPORT_SYMBOL(devm_pci_alloc_host_bridge); | |
647 | ||
dff79b91 LP |
648 | void pci_free_host_bridge(struct pci_host_bridge *bridge) |
649 | { | |
9885440b | 650 | put_device(&bridge->dev); |
dff79b91 LP |
651 | } |
652 | EXPORT_SYMBOL(pci_free_host_bridge); | |
653 | ||
e56faff5 | 654 | /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ |
0b950f0f | 655 | static const unsigned char pcix_bus_speed[] = { |
9be60ca0 MW |
656 | PCI_SPEED_UNKNOWN, /* 0 */ |
657 | PCI_SPEED_66MHz_PCIX, /* 1 */ | |
658 | PCI_SPEED_100MHz_PCIX, /* 2 */ | |
659 | PCI_SPEED_133MHz_PCIX, /* 3 */ | |
660 | PCI_SPEED_UNKNOWN, /* 4 */ | |
661 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ | |
662 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ | |
663 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ | |
664 | PCI_SPEED_UNKNOWN, /* 8 */ | |
665 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ | |
666 | PCI_SPEED_100MHz_PCIX_266, /* A */ | |
667 | PCI_SPEED_133MHz_PCIX_266, /* B */ | |
668 | PCI_SPEED_UNKNOWN, /* C */ | |
669 | PCI_SPEED_66MHz_PCIX_533, /* D */ | |
670 | PCI_SPEED_100MHz_PCIX_533, /* E */ | |
671 | PCI_SPEED_133MHz_PCIX_533 /* F */ | |
672 | }; | |
673 | ||
e56faff5 | 674 | /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ |
343e51ae | 675 | const unsigned char pcie_link_speed[] = { |
3749c51a MW |
676 | PCI_SPEED_UNKNOWN, /* 0 */ |
677 | PCIE_SPEED_2_5GT, /* 1 */ | |
678 | PCIE_SPEED_5_0GT, /* 2 */ | |
9dfd97fe | 679 | PCIE_SPEED_8_0GT, /* 3 */ |
1acfb9b7 | 680 | PCIE_SPEED_16_0GT, /* 4 */ |
de76cda2 | 681 | PCIE_SPEED_32_0GT, /* 5 */ |
34191749 | 682 | PCIE_SPEED_64_0GT, /* 6 */ |
3749c51a MW |
683 | PCI_SPEED_UNKNOWN, /* 7 */ |
684 | PCI_SPEED_UNKNOWN, /* 8 */ | |
685 | PCI_SPEED_UNKNOWN, /* 9 */ | |
686 | PCI_SPEED_UNKNOWN, /* A */ | |
687 | PCI_SPEED_UNKNOWN, /* B */ | |
688 | PCI_SPEED_UNKNOWN, /* C */ | |
689 | PCI_SPEED_UNKNOWN, /* D */ | |
690 | PCI_SPEED_UNKNOWN, /* E */ | |
691 | PCI_SPEED_UNKNOWN /* F */ | |
692 | }; | |
e56faff5 BH |
693 | EXPORT_SYMBOL_GPL(pcie_link_speed); |
694 | ||
695 | const char *pci_speed_string(enum pci_bus_speed speed) | |
696 | { | |
697 | /* Indexed by the pci_bus_speed enum */ | |
698 | static const char *speed_strings[] = { | |
699 | "33 MHz PCI", /* 0x00 */ | |
700 | "66 MHz PCI", /* 0x01 */ | |
701 | "66 MHz PCI-X", /* 0x02 */ | |
702 | "100 MHz PCI-X", /* 0x03 */ | |
703 | "133 MHz PCI-X", /* 0x04 */ | |
704 | NULL, /* 0x05 */ | |
705 | NULL, /* 0x06 */ | |
706 | NULL, /* 0x07 */ | |
707 | NULL, /* 0x08 */ | |
708 | "66 MHz PCI-X 266", /* 0x09 */ | |
709 | "100 MHz PCI-X 266", /* 0x0a */ | |
710 | "133 MHz PCI-X 266", /* 0x0b */ | |
711 | "Unknown AGP", /* 0x0c */ | |
712 | "1x AGP", /* 0x0d */ | |
713 | "2x AGP", /* 0x0e */ | |
714 | "4x AGP", /* 0x0f */ | |
715 | "8x AGP", /* 0x10 */ | |
716 | "66 MHz PCI-X 533", /* 0x11 */ | |
717 | "100 MHz PCI-X 533", /* 0x12 */ | |
718 | "133 MHz PCI-X 533", /* 0x13 */ | |
719 | "2.5 GT/s PCIe", /* 0x14 */ | |
720 | "5.0 GT/s PCIe", /* 0x15 */ | |
721 | "8.0 GT/s PCIe", /* 0x16 */ | |
722 | "16.0 GT/s PCIe", /* 0x17 */ | |
723 | "32.0 GT/s PCIe", /* 0x18 */ | |
34191749 | 724 | "64.0 GT/s PCIe", /* 0x19 */ |
e56faff5 BH |
725 | }; |
726 | ||
727 | if (speed < ARRAY_SIZE(speed_strings)) | |
728 | return speed_strings[speed]; | |
729 | return "Unknown"; | |
730 | } | |
731 | EXPORT_SYMBOL_GPL(pci_speed_string); | |
3749c51a MW |
732 | |
733 | void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) | |
734 | { | |
231afea1 | 735 | bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; |
3749c51a MW |
736 | } |
737 | EXPORT_SYMBOL_GPL(pcie_update_link_speed); | |
738 | ||
45b4cdd5 MW |
739 | static unsigned char agp_speeds[] = { |
740 | AGP_UNKNOWN, | |
741 | AGP_1X, | |
742 | AGP_2X, | |
743 | AGP_4X, | |
744 | AGP_8X | |
745 | }; | |
746 | ||
747 | static enum pci_bus_speed agp_speed(int agp3, int agpstat) | |
748 | { | |
749 | int index = 0; | |
750 | ||
751 | if (agpstat & 4) | |
752 | index = 3; | |
753 | else if (agpstat & 2) | |
754 | index = 2; | |
755 | else if (agpstat & 1) | |
756 | index = 1; | |
757 | else | |
758 | goto out; | |
f7625980 | 759 | |
45b4cdd5 MW |
760 | if (agp3) { |
761 | index += 2; | |
762 | if (index == 5) | |
763 | index = 0; | |
764 | } | |
765 | ||
766 | out: | |
767 | return agp_speeds[index]; | |
768 | } | |
769 | ||
9be60ca0 MW |
770 | static void pci_set_bus_speed(struct pci_bus *bus) |
771 | { | |
772 | struct pci_dev *bridge = bus->self; | |
773 | int pos; | |
774 | ||
45b4cdd5 MW |
775 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
776 | if (!pos) | |
777 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); | |
778 | if (pos) { | |
779 | u32 agpstat, agpcmd; | |
780 | ||
781 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); | |
782 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); | |
783 | ||
784 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); | |
785 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); | |
786 | } | |
787 | ||
9be60ca0 MW |
788 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
789 | if (pos) { | |
790 | u16 status; | |
791 | enum pci_bus_speed max; | |
9be60ca0 | 792 | |
7793eeab BH |
793 | pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, |
794 | &status); | |
795 | ||
796 | if (status & PCI_X_SSTATUS_533MHZ) { | |
9be60ca0 | 797 | max = PCI_SPEED_133MHz_PCIX_533; |
7793eeab | 798 | } else if (status & PCI_X_SSTATUS_266MHZ) { |
9be60ca0 | 799 | max = PCI_SPEED_133MHz_PCIX_266; |
7793eeab | 800 | } else if (status & PCI_X_SSTATUS_133MHZ) { |
3c78bc61 | 801 | if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) |
9be60ca0 | 802 | max = PCI_SPEED_133MHz_PCIX_ECC; |
3c78bc61 | 803 | else |
9be60ca0 | 804 | max = PCI_SPEED_133MHz_PCIX; |
9be60ca0 MW |
805 | } else { |
806 | max = PCI_SPEED_66MHz_PCIX; | |
807 | } | |
808 | ||
809 | bus->max_bus_speed = max; | |
7793eeab BH |
810 | bus->cur_bus_speed = pcix_bus_speed[ |
811 | (status & PCI_X_SSTATUS_FREQ) >> 6]; | |
9be60ca0 MW |
812 | |
813 | return; | |
814 | } | |
815 | ||
fdfe1511 | 816 | if (pci_is_pcie(bridge)) { |
9be60ca0 MW |
817 | u32 linkcap; |
818 | u16 linksta; | |
819 | ||
59875ae4 | 820 | pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); |
231afea1 | 821 | bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; |
f0157160 | 822 | bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); |
9be60ca0 | 823 | |
59875ae4 | 824 | pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); |
9be60ca0 MW |
825 | pcie_update_link_speed(bus, linksta); |
826 | } | |
827 | } | |
828 | ||
44aa0c65 MZ |
829 | static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) |
830 | { | |
b165e2b6 MZ |
831 | struct irq_domain *d; |
832 | ||
41dd40fd BF |
833 | /* If the host bridge driver sets a MSI domain of the bridge, use it */ |
834 | d = dev_get_msi_domain(bus->bridge); | |
835 | ||
44aa0c65 MZ |
836 | /* |
837 | * Any firmware interface that can resolve the msi_domain | |
838 | * should be called from here. | |
839 | */ | |
41dd40fd BF |
840 | if (!d) |
841 | d = pci_host_bridge_of_msi_domain(bus); | |
471036b2 SS |
842 | if (!d) |
843 | d = pci_host_bridge_acpi_msi_domain(bus); | |
44aa0c65 | 844 | |
788858eb JO |
845 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
846 | /* | |
847 | * If no IRQ domain was found via the OF tree, try looking it up | |
848 | * directly through the fwnode_handle. | |
849 | */ | |
850 | if (!d) { | |
851 | struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); | |
852 | ||
853 | if (fwnode) | |
854 | d = irq_find_matching_fwnode(fwnode, | |
855 | DOMAIN_BUS_PCI_MSI); | |
856 | } | |
857 | #endif | |
858 | ||
b165e2b6 | 859 | return d; |
44aa0c65 MZ |
860 | } |
861 | ||
862 | static void pci_set_bus_msi_domain(struct pci_bus *bus) | |
863 | { | |
864 | struct irq_domain *d; | |
38ea72bd | 865 | struct pci_bus *b; |
44aa0c65 MZ |
866 | |
867 | /* | |
38ea72bd AW |
868 | * The bus can be a root bus, a subordinate bus, or a virtual bus |
869 | * created by an SR-IOV device. Walk up to the first bridge device | |
870 | * found or derive the domain from the host bridge. | |
44aa0c65 | 871 | */ |
38ea72bd AW |
872 | for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { |
873 | if (b->self) | |
874 | d = dev_get_msi_domain(&b->self->dev); | |
875 | } | |
876 | ||
877 | if (!d) | |
878 | d = pci_host_bridge_msi_domain(b); | |
44aa0c65 MZ |
879 | |
880 | dev_set_msi_domain(&bus->dev, d); | |
881 | } | |
882 | ||
cea9bc0b | 883 | static int pci_register_host_bridge(struct pci_host_bridge *bridge) |
37d6a0a6 AB |
884 | { |
885 | struct device *parent = bridge->dev.parent; | |
7c3855c4 | 886 | struct resource_entry *window, *next, *n; |
37d6a0a6 | 887 | struct pci_bus *bus, *b; |
7c3855c4 | 888 | resource_size_t offset, next_offset; |
37d6a0a6 | 889 | LIST_HEAD(resources); |
7c3855c4 | 890 | struct resource *res, *next_res; |
37d6a0a6 AB |
891 | char addr[64], *fmt; |
892 | const char *name; | |
893 | int err; | |
894 | ||
895 | bus = pci_alloc_bus(NULL); | |
896 | if (!bus) | |
897 | return -ENOMEM; | |
898 | ||
899 | bridge->bus = bus; | |
900 | ||
37d6a0a6 | 901 | bus->sysdata = bridge->sysdata; |
37d6a0a6 AB |
902 | bus->ops = bridge->ops; |
903 | bus->number = bus->busn_res.start = bridge->busnr; | |
904 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
15d82ca2 BF |
905 | if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) |
906 | bus->domain_nr = pci_bus_find_domain_nr(bus, parent); | |
907 | else | |
908 | bus->domain_nr = bridge->domain_nr; | |
37d6a0a6 AB |
909 | #endif |
910 | ||
911 | b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); | |
912 | if (b) { | |
3e466e2d | 913 | /* Ignore it if we already got here via a different bridge */ |
37d6a0a6 AB |
914 | dev_dbg(&b->dev, "bus already known\n"); |
915 | err = -EEXIST; | |
916 | goto free; | |
917 | } | |
918 | ||
919 | dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), | |
920 | bridge->busnr); | |
921 | ||
922 | err = pcibios_root_bridge_prepare(bridge); | |
923 | if (err) | |
924 | goto free; | |
925 | ||
661c4c4f SP |
926 | /* Temporarily move resources off the list */ |
927 | list_splice_init(&bridge->windows, &resources); | |
9885440b | 928 | err = device_add(&bridge->dev); |
1b54ae83 | 929 | if (err) { |
37d6a0a6 | 930 | put_device(&bridge->dev); |
1b54ae83 RH |
931 | goto free; |
932 | } | |
37d6a0a6 AB |
933 | bus->bridge = get_device(&bridge->dev); |
934 | device_enable_async_suspend(bus->bridge); | |
935 | pci_set_bus_of_node(bus); | |
936 | pci_set_bus_msi_domain(bus); | |
85aabbd7 JPB |
937 | if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && |
938 | !pci_host_of_has_msi_map(parent)) | |
94e89b14 | 939 | bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
37d6a0a6 AB |
940 | |
941 | if (!parent) | |
942 | set_dev_node(bus->bridge, pcibus_to_node(bus)); | |
943 | ||
944 | bus->dev.class = &pcibus_class; | |
945 | bus->dev.parent = bus->bridge; | |
946 | ||
947 | dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); | |
948 | name = dev_name(&bus->dev); | |
949 | ||
950 | err = device_register(&bus->dev); | |
951 | if (err) | |
952 | goto unregister; | |
953 | ||
954 | pcibios_add_bus(bus); | |
955 | ||
6e8e104d RH |
956 | if (bus->ops->add_bus) { |
957 | err = bus->ops->add_bus(bus); | |
958 | if (WARN_ON(err < 0)) | |
959 | dev_err(&bus->dev, "failed to add bus: %d\n", err); | |
960 | } | |
961 | ||
37d6a0a6 AB |
962 | /* Create legacy_io and legacy_mem files for this bus */ |
963 | pci_create_legacy_files(bus); | |
964 | ||
965 | if (parent) | |
966 | dev_info(parent, "PCI host bridge to bus %s\n", name); | |
967 | else | |
968 | pr_info("PCI host bridge to bus %s\n", name); | |
969 | ||
ad508610 YL |
970 | if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) |
971 | dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); | |
972 | ||
7c3855c4 KHF |
973 | /* Coalesce contiguous windows */ |
974 | resource_list_for_each_entry_safe(window, n, &resources) { | |
975 | if (list_is_last(&window->node, &resources)) | |
976 | break; | |
977 | ||
978 | next = list_next_entry(window, node); | |
979 | offset = window->offset; | |
980 | res = window->res; | |
981 | next_offset = next->offset; | |
982 | next_res = next->res; | |
983 | ||
984 | if (res->flags != next_res->flags || offset != next_offset) | |
985 | continue; | |
986 | ||
987 | if (res->end + 1 == next_res->start) { | |
988 | next_res->start = res->start; | |
989 | res->flags = res->start = res->end = 0; | |
990 | } | |
991 | } | |
992 | ||
37d6a0a6 AB |
993 | /* Add initial resources to the bus */ |
994 | resource_list_for_each_entry_safe(window, n, &resources) { | |
37d6a0a6 AB |
995 | offset = window->offset; |
996 | res = window->res; | |
7c3855c4 KHF |
997 | if (!res->end) |
998 | continue; | |
999 | ||
1000 | list_move_tail(&window->node, &bridge->windows); | |
37d6a0a6 AB |
1001 | |
1002 | if (res->flags & IORESOURCE_BUS) | |
1003 | pci_bus_insert_busn_res(bus, bus->number, res->end); | |
1004 | else | |
1005 | pci_bus_add_resource(bus, res, 0); | |
1006 | ||
1007 | if (offset) { | |
1008 | if (resource_type(res) == IORESOURCE_IO) | |
1009 | fmt = " (bus address [%#06llx-%#06llx])"; | |
1010 | else | |
1011 | fmt = " (bus address [%#010llx-%#010llx])"; | |
1012 | ||
1013 | snprintf(addr, sizeof(addr), fmt, | |
1014 | (unsigned long long)(res->start - offset), | |
1015 | (unsigned long long)(res->end - offset)); | |
1016 | } else | |
1017 | addr[0] = '\0'; | |
1018 | ||
1019 | dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); | |
1020 | } | |
1021 | ||
1022 | down_write(&pci_bus_sem); | |
1023 | list_add_tail(&bus->node, &pci_root_buses); | |
1024 | up_write(&pci_bus_sem); | |
1025 | ||
1026 | return 0; | |
1027 | ||
1028 | unregister: | |
1029 | put_device(&bridge->dev); | |
9885440b | 1030 | device_del(&bridge->dev); |
37d6a0a6 AB |
1031 | |
1032 | free: | |
1033 | kfree(bus); | |
1034 | return err; | |
1035 | } | |
1036 | ||
17e8f0d4 GB |
1037 | static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) |
1038 | { | |
1039 | int pos; | |
1040 | u32 status; | |
1041 | ||
1042 | /* | |
1043 | * If extended config space isn't accessible on a bridge's primary | |
1044 | * bus, we certainly can't access it on the secondary bus. | |
1045 | */ | |
1046 | if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) | |
1047 | return false; | |
1048 | ||
1049 | /* | |
1050 | * PCIe Root Ports and switch ports are PCIe on both sides, so if | |
1051 | * extended config space is accessible on the primary, it's also | |
1052 | * accessible on the secondary. | |
1053 | */ | |
1054 | if (pci_is_pcie(bridge) && | |
1055 | (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || | |
1056 | pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || | |
1057 | pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) | |
1058 | return true; | |
1059 | ||
1060 | /* | |
1061 | * For the other bridge types: | |
1062 | * - PCI-to-PCI bridges | |
1063 | * - PCIe-to-PCI/PCI-X forward bridges | |
1064 | * - PCI/PCI-X-to-PCIe reverse bridges | |
1065 | * extended config space on the secondary side is only accessible | |
1066 | * if the bridge supports PCI-X Mode 2. | |
1067 | */ | |
1068 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); | |
1069 | if (!pos) | |
1070 | return false; | |
1071 | ||
1072 | pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); | |
1073 | return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); | |
1074 | } | |
1075 | ||
cbd4e055 AB |
1076 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
1077 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
1078 | { |
1079 | struct pci_bus *child; | |
07e29295 | 1080 | struct pci_host_bridge *host; |
1da177e4 | 1081 | int i; |
4f535093 | 1082 | int ret; |
1da177e4 | 1083 | |
3e466e2d | 1084 | /* Allocate a new bus and inherit stuff from the parent */ |
670ba0c8 | 1085 | child = pci_alloc_bus(parent); |
1da177e4 LT |
1086 | if (!child) |
1087 | return NULL; | |
1088 | ||
1da177e4 | 1089 | child->parent = parent; |
1da177e4 | 1090 | child->sysdata = parent->sysdata; |
6e325a62 | 1091 | child->bus_flags = parent->bus_flags; |
1da177e4 | 1092 | |
07e29295 RH |
1093 | host = pci_find_host_bridge(parent); |
1094 | if (host->child_ops) | |
1095 | child->ops = host->child_ops; | |
1096 | else | |
1097 | child->ops = parent->ops; | |
1098 | ||
3e466e2d BH |
1099 | /* |
1100 | * Initialize some portions of the bus device, but don't register | |
1101 | * it now as the parent is not properly set up yet. | |
fd7d1ced GKH |
1102 | */ |
1103 | child->dev.class = &pcibus_class; | |
1a927133 | 1104 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 | 1105 | |
3e466e2d | 1106 | /* Set up the primary, secondary and subordinate bus numbers */ |
b918c62e YL |
1107 | child->number = child->busn_res.start = busnr; |
1108 | child->primary = parent->busn_res.start; | |
1109 | child->busn_res.end = 0xff; | |
1da177e4 | 1110 | |
4f535093 YL |
1111 | if (!bridge) { |
1112 | child->dev.parent = parent->bridge; | |
1113 | goto add_dev; | |
1114 | } | |
3789fa8a YZ |
1115 | |
1116 | child->self = bridge; | |
1117 | child->bridge = get_device(&bridge->dev); | |
4f535093 | 1118 | child->dev.parent = child->bridge; |
98d9f30c | 1119 | pci_set_bus_of_node(child); |
9be60ca0 MW |
1120 | pci_set_bus_speed(child); |
1121 | ||
17e8f0d4 GB |
1122 | /* |
1123 | * Check whether extended config space is accessible on the child | |
1124 | * bus. Note that we currently assume it is always accessible on | |
1125 | * the root bus. | |
1126 | */ | |
1127 | if (!pci_bridge_child_ext_cfg_accessible(bridge)) { | |
1128 | child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; | |
1129 | pci_info(child, "extended config space not accessible\n"); | |
1130 | } | |
1131 | ||
3e466e2d | 1132 | /* Set up default resource pointers and names */ |
fde09c6d | 1133 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
1134 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
1135 | child->resource[i]->name = child->name; | |
1136 | } | |
1137 | bridge->subordinate = child; | |
1138 | ||
4f535093 | 1139 | add_dev: |
44aa0c65 | 1140 | pci_set_bus_msi_domain(child); |
4f535093 YL |
1141 | ret = device_register(&child->dev); |
1142 | WARN_ON(ret < 0); | |
1143 | ||
10a95747 JL |
1144 | pcibios_add_bus(child); |
1145 | ||
057bd2e0 TR |
1146 | if (child->ops->add_bus) { |
1147 | ret = child->ops->add_bus(child); | |
1148 | if (WARN_ON(ret < 0)) | |
1149 | dev_err(&child->dev, "failed to add bus: %d\n", ret); | |
1150 | } | |
1151 | ||
4f535093 YL |
1152 | /* Create legacy_io and legacy_mem files for this bus */ |
1153 | pci_create_legacy_files(child); | |
1154 | ||
1da177e4 LT |
1155 | return child; |
1156 | } | |
1157 | ||
3c78bc61 RD |
1158 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
1159 | int busnr) | |
1da177e4 LT |
1160 | { |
1161 | struct pci_bus *child; | |
1162 | ||
1163 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 1164 | if (child) { |
d71374da | 1165 | down_write(&pci_bus_sem); |
1da177e4 | 1166 | list_add_tail(&child->node, &parent->children); |
d71374da | 1167 | up_write(&pci_bus_sem); |
e4ea9bb7 | 1168 | } |
1da177e4 LT |
1169 | return child; |
1170 | } | |
b7fe9434 | 1171 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 | 1172 | |
f3dbd802 RJ |
1173 | static void pci_enable_crs(struct pci_dev *pdev) |
1174 | { | |
1175 | u16 root_cap = 0; | |
1176 | ||
1177 | /* Enable CRS Software Visibility if supported */ | |
1178 | pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); | |
1179 | if (root_cap & PCI_EXP_RTCAP_CRSVIS) | |
1180 | pcie_capability_set_word(pdev, PCI_EXP_RTCTL, | |
1181 | PCI_EXP_RTCTL_CRSSVE); | |
1182 | } | |
1183 | ||
1c02ea81 MW |
1184 | static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, |
1185 | unsigned int available_buses); | |
2dbce590 SS |
1186 | /** |
1187 | * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus | |
1188 | * numbers from EA capability. | |
1189 | * @dev: Bridge | |
1190 | * @sec: updated with secondary bus number from EA | |
1191 | * @sub: updated with subordinate bus number from EA | |
1192 | * | |
73884a70 SS |
1193 | * If @dev is a bridge with EA capability that specifies valid secondary |
1194 | * and subordinate bus numbers, return true with the bus numbers in @sec | |
1195 | * and @sub. Otherwise return false. | |
2dbce590 SS |
1196 | */ |
1197 | static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) | |
1198 | { | |
1199 | int ea, offset; | |
1200 | u32 dw; | |
73884a70 | 1201 | u8 ea_sec, ea_sub; |
2dbce590 SS |
1202 | |
1203 | if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) | |
1204 | return false; | |
1205 | ||
1206 | /* find PCI EA capability in list */ | |
1207 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
1208 | if (!ea) | |
1209 | return false; | |
1210 | ||
1211 | offset = ea + PCI_EA_FIRST_ENT; | |
1212 | pci_read_config_dword(dev, offset, &dw); | |
73884a70 SS |
1213 | ea_sec = dw & PCI_EA_SEC_BUS_MASK; |
1214 | ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; | |
1215 | if (ea_sec == 0 || ea_sub < ea_sec) | |
1216 | return false; | |
1217 | ||
1218 | *sec = ea_sec; | |
1219 | *sub = ea_sub; | |
2dbce590 SS |
1220 | return true; |
1221 | } | |
1c02ea81 | 1222 | |
1da177e4 | 1223 | /* |
1c02ea81 MW |
1224 | * pci_scan_bridge_extend() - Scan buses behind a bridge |
1225 | * @bus: Parent bus the bridge is on | |
1226 | * @dev: Bridge itself | |
1227 | * @max: Starting subordinate number of buses behind this bridge | |
1228 | * @available_buses: Total number of buses available for this bridge and | |
1229 | * the devices below. After the minimal bus space has | |
1230 | * been allocated the remaining buses will be | |
1231 | * distributed equally between hotplug-capable bridges. | |
1232 | * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges | |
1233 | * that need to be reconfigured. | |
1234 | * | |
1da177e4 LT |
1235 | * If it's a bridge, configure it and scan the bus behind it. |
1236 | * For CardBus bridges, we don't scan behind as the devices will | |
1237 | * be handled by the bridge driver itself. | |
1238 | * | |
1239 | * We need to process bridges in two passes -- first we scan those | |
1240 | * already configured by the BIOS and after we are done with all of | |
1241 | * them, we proceed to assigning numbers to the remaining buses in | |
1242 | * order to avoid overlaps between old and new bus numbers. | |
70f7880d MW |
1243 | * |
1244 | * Return: New subordinate number covering all buses behind this bridge. | |
1da177e4 | 1245 | */ |
1c02ea81 MW |
1246 | static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, |
1247 | int max, unsigned int available_buses, | |
1248 | int pass) | |
1da177e4 LT |
1249 | { |
1250 | struct pci_bus *child; | |
1251 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 1252 | u32 buses, i, j = 0; |
1da177e4 | 1253 | u16 bctl; |
99ddd552 | 1254 | u8 primary, secondary, subordinate; |
a1c19894 | 1255 | int broken = 0; |
2dbce590 SS |
1256 | bool fixed_buses; |
1257 | u8 fixed_sec, fixed_sub; | |
1258 | int next_busnr; | |
1da177e4 | 1259 | |
d963f651 MW |
1260 | /* |
1261 | * Make sure the bridge is powered on to be able to access config | |
1262 | * space of devices below it. | |
1263 | */ | |
1264 | pm_runtime_get_sync(&dev->dev); | |
1265 | ||
1da177e4 | 1266 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
99ddd552 BH |
1267 | primary = buses & 0xFF; |
1268 | secondary = (buses >> 8) & 0xFF; | |
1269 | subordinate = (buses >> 16) & 0xFF; | |
1da177e4 | 1270 | |
7506dc79 | 1271 | pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", |
99ddd552 | 1272 | secondary, subordinate, pass); |
1da177e4 | 1273 | |
71f6bd4a | 1274 | if (!primary && (primary != bus->number) && secondary && subordinate) { |
7506dc79 | 1275 | pci_warn(dev, "Primary bus is hard wired to 0\n"); |
71f6bd4a YL |
1276 | primary = bus->number; |
1277 | } | |
1278 | ||
a1c19894 BH |
1279 | /* Check if setup is sensible at all */ |
1280 | if (!pass && | |
1965f66e | 1281 | (primary != bus->number || secondary <= bus->number || |
12d87069 | 1282 | secondary > subordinate)) { |
7506dc79 | 1283 | pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", |
1965f66e | 1284 | secondary, subordinate); |
a1c19894 BH |
1285 | broken = 1; |
1286 | } | |
1287 | ||
3e466e2d BH |
1288 | /* |
1289 | * Disable Master-Abort Mode during probing to avoid reporting of | |
1290 | * bus errors in some architectures. | |
1291 | */ | |
1da177e4 LT |
1292 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
1293 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
1294 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
1295 | ||
f3dbd802 RJ |
1296 | pci_enable_crs(dev); |
1297 | ||
99ddd552 BH |
1298 | if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
1299 | !is_cardbus && !broken) { | |
1300 | unsigned int cmax; | |
3e466e2d | 1301 | |
1da177e4 | 1302 | /* |
3e466e2d BH |
1303 | * Bus already configured by firmware, process it in the |
1304 | * first pass and just note the configuration. | |
1da177e4 LT |
1305 | */ |
1306 | if (pass) | |
bbe8f9a3 | 1307 | goto out; |
1da177e4 LT |
1308 | |
1309 | /* | |
3e466e2d BH |
1310 | * The bus might already exist for two reasons: Either we |
1311 | * are rescanning the bus or the bus is reachable through | |
1312 | * more than one bridge. The second case can happen with | |
1313 | * the i450NX chipset. | |
1da177e4 | 1314 | */ |
99ddd552 | 1315 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
74710ded | 1316 | if (!child) { |
99ddd552 | 1317 | child = pci_add_new_bus(bus, dev, secondary); |
74710ded AC |
1318 | if (!child) |
1319 | goto out; | |
99ddd552 | 1320 | child->primary = primary; |
bc76b731 | 1321 | pci_bus_insert_busn_res(child, secondary, subordinate); |
74710ded | 1322 | child->bridge_ctl = bctl; |
1da177e4 LT |
1323 | } |
1324 | ||
1da177e4 | 1325 | cmax = pci_scan_child_bus(child); |
c95b0bd6 | 1326 | if (cmax > subordinate) |
7506dc79 | 1327 | pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", |
c95b0bd6 | 1328 | subordinate, cmax); |
3e466e2d BH |
1329 | |
1330 | /* Subordinate should equal child->busn_res.end */ | |
c95b0bd6 AN |
1331 | if (subordinate > max) |
1332 | max = subordinate; | |
1da177e4 | 1333 | } else { |
3e466e2d | 1334 | |
1da177e4 LT |
1335 | /* |
1336 | * We need to assign a number to this bus which we always | |
1337 | * do in the second pass. | |
1338 | */ | |
12f44f46 | 1339 | if (!pass) { |
619c8c31 | 1340 | if (pcibios_assign_all_busses() || broken || is_cardbus) |
3e466e2d BH |
1341 | |
1342 | /* | |
1343 | * Temporarily disable forwarding of the | |
1344 | * configuration cycles on all bridges in | |
1345 | * this bus segment to avoid possible | |
1346 | * conflicts in the second pass between two | |
1347 | * bridges programmed with overlapping bus | |
1348 | * ranges. | |
1349 | */ | |
12f44f46 IK |
1350 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, |
1351 | buses & ~0xffffff); | |
bbe8f9a3 | 1352 | goto out; |
12f44f46 | 1353 | } |
1da177e4 LT |
1354 | |
1355 | /* Clear errors */ | |
1356 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
1357 | ||
2dbce590 SS |
1358 | /* Read bus numbers from EA Capability (if present) */ |
1359 | fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); | |
1360 | if (fixed_buses) | |
1361 | next_busnr = fixed_sec; | |
1362 | else | |
1363 | next_busnr = max + 1; | |
1364 | ||
3e466e2d BH |
1365 | /* |
1366 | * Prevent assigning a bus number that already exists. | |
1367 | * This can happen when a bridge is hot-plugged, so in this | |
1368 | * case we only re-scan this bus. | |
1369 | */ | |
2dbce590 | 1370 | child = pci_find_bus(pci_domain_nr(bus), next_busnr); |
b1a98b69 | 1371 | if (!child) { |
2dbce590 | 1372 | child = pci_add_new_bus(bus, dev, next_busnr); |
b1a98b69 TC |
1373 | if (!child) |
1374 | goto out; | |
2dbce590 | 1375 | pci_bus_insert_busn_res(child, next_busnr, |
a20c7f36 | 1376 | bus->busn_res.end); |
b1a98b69 | 1377 | } |
9a4d7d87 | 1378 | max++; |
1c02ea81 MW |
1379 | if (available_buses) |
1380 | available_buses--; | |
1381 | ||
1da177e4 LT |
1382 | buses = (buses & 0xff000000) |
1383 | | ((unsigned int)(child->primary) << 0) | |
b918c62e YL |
1384 | | ((unsigned int)(child->busn_res.start) << 8) |
1385 | | ((unsigned int)(child->busn_res.end) << 16); | |
1da177e4 LT |
1386 | |
1387 | /* | |
1388 | * yenta.c forces a secondary latency timer of 176. | |
1389 | * Copy that behaviour here. | |
1390 | */ | |
1391 | if (is_cardbus) { | |
1392 | buses &= ~0xff000000; | |
1393 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
1394 | } | |
7c867c88 | 1395 | |
3e466e2d | 1396 | /* We need to blast all three values with a single write */ |
1da177e4 LT |
1397 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); |
1398 | ||
1399 | if (!is_cardbus) { | |
11949255 | 1400 | child->bridge_ctl = bctl; |
1c02ea81 | 1401 | max = pci_scan_child_bus_extend(child, available_buses); |
1da177e4 | 1402 | } else { |
3e466e2d | 1403 | |
1da177e4 | 1404 | /* |
3e466e2d BH |
1405 | * For CardBus bridges, we leave 4 bus numbers as |
1406 | * cards with a PCI-to-PCI bridge can be inserted | |
1407 | * later. | |
1da177e4 | 1408 | */ |
3c78bc61 | 1409 | for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { |
49887941 | 1410 | struct pci_bus *parent = bus; |
cc57450f RS |
1411 | if (pci_find_bus(pci_domain_nr(bus), |
1412 | max+i+1)) | |
1413 | break; | |
49887941 DB |
1414 | while (parent->parent) { |
1415 | if ((!pcibios_assign_all_busses()) && | |
b918c62e YL |
1416 | (parent->busn_res.end > max) && |
1417 | (parent->busn_res.end <= max+i)) { | |
49887941 DB |
1418 | j = 1; |
1419 | } | |
1420 | parent = parent->parent; | |
1421 | } | |
1422 | if (j) { | |
3e466e2d | 1423 | |
49887941 | 1424 | /* |
3e466e2d BH |
1425 | * Often, there are two CardBus |
1426 | * bridges -- try to leave one | |
1427 | * valid bus number for each one. | |
49887941 DB |
1428 | */ |
1429 | i /= 2; | |
1430 | break; | |
1431 | } | |
1432 | } | |
cc57450f | 1433 | max += i; |
1da177e4 | 1434 | } |
3e466e2d | 1435 | |
2dbce590 SS |
1436 | /* |
1437 | * Set subordinate bus number to its real value. | |
1438 | * If fixed subordinate bus number exists from EA | |
1439 | * capability then use it. | |
1440 | */ | |
1441 | if (fixed_buses) | |
1442 | max = fixed_sub; | |
bc76b731 | 1443 | pci_bus_update_busn_res_end(child, max); |
1da177e4 LT |
1444 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
1445 | } | |
1446 | ||
cb3576fa GH |
1447 | sprintf(child->name, |
1448 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
1449 | pci_domain_nr(bus), child->number); | |
1da177e4 | 1450 | |
e412d63d | 1451 | /* Check that all devices are accessible */ |
49887941 | 1452 | while (bus->parent) { |
b918c62e YL |
1453 | if ((child->busn_res.end > bus->busn_res.end) || |
1454 | (child->number > bus->busn_res.end) || | |
49887941 | 1455 | (child->number < bus->number) || |
b918c62e | 1456 | (child->busn_res.end < bus->number)) { |
e412d63d MW |
1457 | dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", |
1458 | &child->busn_res); | |
1459 | break; | |
49887941 DB |
1460 | } |
1461 | bus = bus->parent; | |
1462 | } | |
1463 | ||
bbe8f9a3 RB |
1464 | out: |
1465 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
1466 | ||
d963f651 MW |
1467 | pm_runtime_put(&dev->dev); |
1468 | ||
1da177e4 LT |
1469 | return max; |
1470 | } | |
1c02ea81 MW |
1471 | |
1472 | /* | |
1473 | * pci_scan_bridge() - Scan buses behind a bridge | |
1474 | * @bus: Parent bus the bridge is on | |
1475 | * @dev: Bridge itself | |
1476 | * @max: Starting subordinate number of buses behind this bridge | |
1477 | * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges | |
1478 | * that need to be reconfigured. | |
1479 | * | |
1480 | * If it's a bridge, configure it and scan the bus behind it. | |
1481 | * For CardBus bridges, we don't scan behind as the devices will | |
1482 | * be handled by the bridge driver itself. | |
1483 | * | |
1484 | * We need to process bridges in two passes -- first we scan those | |
1485 | * already configured by the BIOS and after we are done with all of | |
1486 | * them, we proceed to assigning numbers to the remaining buses in | |
1487 | * order to avoid overlaps between old and new bus numbers. | |
70f7880d MW |
1488 | * |
1489 | * Return: New subordinate number covering all buses behind this bridge. | |
1c02ea81 MW |
1490 | */ |
1491 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) | |
1492 | { | |
1493 | return pci_scan_bridge_extend(bus, dev, max, 0, pass); | |
1494 | } | |
b7fe9434 | 1495 | EXPORT_SYMBOL(pci_scan_bridge); |
1da177e4 LT |
1496 | |
1497 | /* | |
1498 | * Read interrupt line and base address registers. | |
1499 | * The architecture-dependent code can tweak these, of course. | |
1500 | */ | |
1501 | static void pci_read_irq(struct pci_dev *dev) | |
1502 | { | |
1503 | unsigned char irq; | |
1504 | ||
be20f6b0 KA |
1505 | /* VFs are not allowed to use INTx, so skip the config reads */ |
1506 | if (dev->is_virtfn) { | |
1507 | dev->pin = 0; | |
1508 | dev->irq = 0; | |
1509 | return; | |
1510 | } | |
1511 | ||
1da177e4 | 1512 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); |
ffeff788 | 1513 | dev->pin = irq; |
1da177e4 LT |
1514 | if (irq) |
1515 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
1516 | dev->irq = irq; | |
1517 | } | |
1518 | ||
bb209c82 | 1519 | void set_pcie_port_type(struct pci_dev *pdev) |
480b93b7 YZ |
1520 | { |
1521 | int pos; | |
1522 | u16 reg16; | |
d0751b98 YW |
1523 | int type; |
1524 | struct pci_dev *parent; | |
480b93b7 YZ |
1525 | |
1526 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
1527 | if (!pos) | |
1528 | return; | |
51ebfc92 | 1529 | |
0efea000 | 1530 | pdev->pcie_cap = pos; |
480b93b7 | 1531 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
786e2288 | 1532 | pdev->pcie_flags_reg = reg16; |
69139244 AN |
1533 | pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); |
1534 | pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); | |
d0751b98 | 1535 | |
ca784104 MW |
1536 | parent = pci_upstream_bridge(pdev); |
1537 | if (!parent) | |
1538 | return; | |
1539 | ||
d0751b98 | 1540 | /* |
ca784104 MW |
1541 | * Some systems do not identify their upstream/downstream ports |
1542 | * correctly so detect impossible configurations here and correct | |
1543 | * the port type accordingly. | |
d0751b98 YW |
1544 | */ |
1545 | type = pci_pcie_type(pdev); | |
ca784104 | 1546 | if (type == PCI_EXP_TYPE_DOWNSTREAM) { |
b35b1df5 | 1547 | /* |
ca784104 MW |
1548 | * If pdev claims to be downstream port but the parent |
1549 | * device is also downstream port assume pdev is actually | |
1550 | * upstream port. | |
b35b1df5 | 1551 | */ |
ca784104 MW |
1552 | if (pcie_downstream_port(parent)) { |
1553 | pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); | |
1554 | pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; | |
1555 | pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; | |
1556 | } | |
1557 | } else if (type == PCI_EXP_TYPE_UPSTREAM) { | |
1558 | /* | |
1559 | * If pdev claims to be upstream port but the parent | |
1560 | * device is also upstream port assume pdev is actually | |
1561 | * downstream port. | |
1562 | */ | |
1563 | if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { | |
1564 | pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); | |
1565 | pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; | |
1566 | pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; | |
1567 | } | |
d0751b98 | 1568 | } |
480b93b7 YZ |
1569 | } |
1570 | ||
bb209c82 | 1571 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
28760489 | 1572 | { |
28760489 EB |
1573 | u32 reg32; |
1574 | ||
59875ae4 | 1575 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); |
28760489 EB |
1576 | if (reg32 & PCI_EXP_SLTCAP_HPC) |
1577 | pdev->is_hotplug_bridge = 1; | |
1578 | } | |
1579 | ||
8531e283 LW |
1580 | static void set_pcie_thunderbolt(struct pci_dev *dev) |
1581 | { | |
d2c64f98 | 1582 | u16 vsec; |
8531e283 | 1583 | |
d2c64f98 AS |
1584 | /* Is the device part of a Thunderbolt controller? */ |
1585 | vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); | |
1586 | if (vsec) | |
1587 | dev->is_thunderbolt = 1; | |
8531e283 LW |
1588 | } |
1589 | ||
617654aa MW |
1590 | static void set_pcie_untrusted(struct pci_dev *dev) |
1591 | { | |
1592 | struct pci_dev *parent; | |
1593 | ||
1594 | /* | |
1595 | * If the upstream bridge is untrusted we treat this device | |
1596 | * untrusted as well. | |
1597 | */ | |
1598 | parent = pci_upstream_bridge(dev); | |
99b50be9 | 1599 | if (parent && (parent->untrusted || parent->external_facing)) |
617654aa MW |
1600 | dev->untrusted = true; |
1601 | } | |
1602 | ||
c037b6c8 RJ |
1603 | static void pci_set_removable(struct pci_dev *dev) |
1604 | { | |
1605 | struct pci_dev *parent = pci_upstream_bridge(dev); | |
1606 | ||
1607 | /* | |
1608 | * We (only) consider everything downstream from an external_facing | |
1609 | * device to be removable by the user. We're mainly concerned with | |
1610 | * consumer platforms with user accessible thunderbolt ports that are | |
1611 | * vulnerable to DMA attacks, and we expect those ports to be marked by | |
1612 | * the firmware as external_facing. Devices in traditional hotplug | |
1613 | * slots can technically be removed, but the expectation is that unless | |
1614 | * the port is marked with external_facing, such devices are less | |
1615 | * accessible to user / may not be removed by end user, and thus not | |
1616 | * exposed as "removable" to userspace. | |
1617 | */ | |
1618 | if (parent && | |
1619 | (parent->external_facing || dev_is_removable(&parent->dev))) | |
1620 | dev_set_removable(&dev->dev, DEVICE_REMOVABLE); | |
1621 | } | |
1622 | ||
78916b00 | 1623 | /** |
3e466e2d | 1624 | * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? |
78916b00 AW |
1625 | * @dev: PCI device |
1626 | * | |
1627 | * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that | |
1628 | * when forwarding a type1 configuration request the bridge must check that | |
1629 | * the extended register address field is zero. The bridge is not permitted | |
1630 | * to forward the transactions and must handle it as an Unsupported Request. | |
1631 | * Some bridges do not follow this rule and simply drop the extended register | |
1632 | * bits, resulting in the standard config space being aliased, every 256 | |
1633 | * bytes across the entire configuration space. Test for this condition by | |
1634 | * comparing the first dword of each potential alias to the vendor/device ID. | |
1635 | * Known offenders: | |
1636 | * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) | |
1637 | * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) | |
1638 | */ | |
1639 | static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) | |
1640 | { | |
1641 | #ifdef CONFIG_PCI_QUIRKS | |
1642 | int pos; | |
1643 | u32 header, tmp; | |
1644 | ||
1645 | pci_read_config_dword(dev, PCI_VENDOR_ID, &header); | |
1646 | ||
1647 | for (pos = PCI_CFG_SPACE_SIZE; | |
1648 | pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { | |
1649 | if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL | |
1650 | || header != tmp) | |
1651 | return false; | |
1652 | } | |
1653 | ||
1654 | return true; | |
1655 | #else | |
1656 | return false; | |
1657 | #endif | |
1658 | } | |
1659 | ||
0b950f0f | 1660 | /** |
2f0cd59c | 1661 | * pci_cfg_space_size_ext - Get the configuration space size of the PCI device |
0b950f0f SH |
1662 | * @dev: PCI device |
1663 | * | |
1664 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
1665 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
1666 | * access it. Maybe we don't have a way to generate extended config space | |
1667 | * accesses, or the device is behind a reverse Express bridge. So we try | |
1668 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
1669 | * capability header. | |
1670 | */ | |
1671 | static int pci_cfg_space_size_ext(struct pci_dev *dev) | |
1672 | { | |
1673 | u32 status; | |
1674 | int pos = PCI_CFG_SPACE_SIZE; | |
1675 | ||
1676 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) | |
8e5a395a | 1677 | return PCI_CFG_SPACE_SIZE; |
fa52b644 | 1678 | if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) |
8e5a395a | 1679 | return PCI_CFG_SPACE_SIZE; |
0b950f0f SH |
1680 | |
1681 | return PCI_CFG_SPACE_EXP_SIZE; | |
0b950f0f SH |
1682 | } |
1683 | ||
1684 | int pci_cfg_space_size(struct pci_dev *dev) | |
1685 | { | |
1686 | int pos; | |
1687 | u32 status; | |
1688 | u16 class; | |
1689 | ||
975bb8b4 | 1690 | #ifdef CONFIG_PCI_IOV |
06013b64 AW |
1691 | /* |
1692 | * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to | |
1693 | * implement a PCIe capability and therefore must implement extended | |
1694 | * config space. We can skip the NO_EXTCFG test below and the | |
1695 | * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of | |
1696 | * the fact that the SR-IOV capability on the PF resides in extended | |
1697 | * config space and must be accessible and non-aliased to have enabled | |
1698 | * support for this VF. This is a micro performance optimization for | |
1699 | * systems supporting many VFs. | |
1700 | */ | |
1701 | if (dev->is_virtfn) | |
1702 | return PCI_CFG_SPACE_EXP_SIZE; | |
975bb8b4 KA |
1703 | #endif |
1704 | ||
17e8f0d4 GB |
1705 | if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) |
1706 | return PCI_CFG_SPACE_SIZE; | |
1707 | ||
0b950f0f SH |
1708 | class = dev->class >> 8; |
1709 | if (class == PCI_CLASS_BRIDGE_HOST) | |
1710 | return pci_cfg_space_size_ext(dev); | |
1711 | ||
8e5a395a BH |
1712 | if (pci_is_pcie(dev)) |
1713 | return pci_cfg_space_size_ext(dev); | |
0b950f0f | 1714 | |
8e5a395a BH |
1715 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
1716 | if (!pos) | |
1717 | return PCI_CFG_SPACE_SIZE; | |
0b950f0f | 1718 | |
8e5a395a BH |
1719 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); |
1720 | if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) | |
1721 | return pci_cfg_space_size_ext(dev); | |
0b950f0f | 1722 | |
0b950f0f SH |
1723 | return PCI_CFG_SPACE_SIZE; |
1724 | } | |
1725 | ||
cf0921be KA |
1726 | static u32 pci_class(struct pci_dev *dev) |
1727 | { | |
1728 | u32 class; | |
1729 | ||
1730 | #ifdef CONFIG_PCI_IOV | |
1731 | if (dev->is_virtfn) | |
1732 | return dev->physfn->sriov->class; | |
1733 | #endif | |
1734 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
1735 | return class; | |
1736 | } | |
1737 | ||
1738 | static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) | |
1739 | { | |
1740 | #ifdef CONFIG_PCI_IOV | |
1741 | if (dev->is_virtfn) { | |
1742 | *vendor = dev->physfn->sriov->subsystem_vendor; | |
1743 | *device = dev->physfn->sriov->subsystem_device; | |
1744 | return; | |
1745 | } | |
1746 | #endif | |
1747 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); | |
1748 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); | |
1749 | } | |
1750 | ||
1751 | static u8 pci_hdr_type(struct pci_dev *dev) | |
1752 | { | |
1753 | u8 hdr_type; | |
1754 | ||
1755 | #ifdef CONFIG_PCI_IOV | |
1756 | if (dev->is_virtfn) | |
1757 | return dev->physfn->sriov->hdr_type; | |
1758 | #endif | |
1759 | pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); | |
1760 | return hdr_type; | |
1761 | } | |
1762 | ||
01abc2aa | 1763 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 1764 | |
99b3c58f | 1765 | /** |
3e466e2d | 1766 | * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability |
99b3c58f PG |
1767 | * @dev: PCI device |
1768 | * | |
1769 | * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this | |
1770 | * at enumeration-time to avoid modifying PCI_COMMAND at run-time. | |
1771 | */ | |
1772 | static int pci_intx_mask_broken(struct pci_dev *dev) | |
1773 | { | |
1774 | u16 orig, toggle, new; | |
1775 | ||
1776 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
1777 | toggle = orig ^ PCI_COMMAND_INTX_DISABLE; | |
1778 | pci_write_config_word(dev, PCI_COMMAND, toggle); | |
1779 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
1780 | ||
1781 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
1782 | ||
1783 | /* | |
1784 | * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI | |
1785 | * r2.3, so strictly speaking, a device is not *broken* if it's not | |
1786 | * writable. But we'll live with the misnomer for now. | |
1787 | */ | |
1788 | if (new != toggle) | |
1789 | return 1; | |
1790 | return 0; | |
1791 | } | |
1792 | ||
11eb0e0e SK |
1793 | static void early_dump_pci_device(struct pci_dev *pdev) |
1794 | { | |
1795 | u32 value[256 / 4]; | |
1796 | int i; | |
1797 | ||
1798 | pci_info(pdev, "config space:\n"); | |
1799 | ||
1800 | for (i = 0; i < 256; i += 4) | |
1801 | pci_read_config_dword(pdev, i, &value[i / 4]); | |
1802 | ||
1803 | print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, | |
1804 | value, 256, false); | |
1805 | } | |
1806 | ||
1da177e4 | 1807 | /** |
3e466e2d | 1808 | * pci_setup_device - Fill in class and map information of a device |
1da177e4 LT |
1809 | * @dev: the device structure to fill |
1810 | * | |
f7625980 | 1811 | * Initialize the device structure with information about the device's |
3e466e2d | 1812 | * vendor,class,memory and IO-space addresses, IRQ lines etc. |
1da177e4 | 1813 | * Called at initialisation of the PCI subsystem and by CardBus services. |
480b93b7 YZ |
1814 | * Returns 0 on success and negative if unknown type of device (not normal, |
1815 | * bridge or CardBus). | |
1da177e4 | 1816 | */ |
480b93b7 | 1817 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
1818 | { |
1819 | u32 class; | |
b84106b4 | 1820 | u16 cmd; |
480b93b7 | 1821 | u8 hdr_type; |
bc577d2b | 1822 | int pos = 0; |
5bfa14ed BH |
1823 | struct pci_bus_region region; |
1824 | struct resource *res; | |
480b93b7 | 1825 | |
cf0921be | 1826 | hdr_type = pci_hdr_type(dev); |
480b93b7 YZ |
1827 | |
1828 | dev->sysdata = dev->bus->sysdata; | |
1829 | dev->dev.parent = dev->bus->bridge; | |
1830 | dev->dev.bus = &pci_bus_type; | |
1831 | dev->hdr_type = hdr_type & 0x7f; | |
1832 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
1833 | dev->error_state = pci_channel_io_normal; |
1834 | set_pcie_port_type(dev); | |
1835 | ||
375553a9 SD |
1836 | pci_set_of_node(dev); |
1837 | pci_set_acpi_fwnode(dev); | |
1838 | ||
017ffe64 | 1839 | pci_dev_assign_slot(dev); |
3e466e2d BH |
1840 | |
1841 | /* | |
1842 | * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
1843 | * set this higher, assuming the system even supports it. | |
1844 | */ | |
480b93b7 | 1845 | dev->dma_mask = 0xffffffff; |
1da177e4 | 1846 | |
eebfcfb5 GKH |
1847 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
1848 | dev->bus->number, PCI_SLOT(dev->devfn), | |
1849 | PCI_FUNC(dev->devfn)); | |
1da177e4 | 1850 | |
cf0921be KA |
1851 | class = pci_class(dev); |
1852 | ||
b8a3a521 | 1853 | dev->revision = class & 0xff; |
2dd8ba92 | 1854 | dev->class = class >> 8; /* upper 3 bytes */ |
1da177e4 | 1855 | |
11eb0e0e SK |
1856 | if (pci_early_dump) |
1857 | early_dump_pci_device(dev); | |
1858 | ||
3e466e2d | 1859 | /* Need to have dev->class ready */ |
853346e4 YZ |
1860 | dev->cfg_size = pci_cfg_space_size(dev); |
1861 | ||
3e466e2d | 1862 | /* Need to have dev->cfg_size ready */ |
8531e283 LW |
1863 | set_pcie_thunderbolt(dev); |
1864 | ||
617654aa MW |
1865 | set_pcie_untrusted(dev); |
1866 | ||
1da177e4 | 1867 | /* "Unknown power state" */ |
3fe9d19f | 1868 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
1869 | |
1870 | /* Early fixups, before probing the BARs */ | |
1871 | pci_fixup_device(pci_fixup_early, dev); | |
3e466e2d | 1872 | |
c037b6c8 RJ |
1873 | pci_set_removable(dev); |
1874 | ||
b7360f60 TY |
1875 | pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", |
1876 | dev->vendor, dev->device, dev->hdr_type, dev->class); | |
1877 | ||
3e466e2d | 1878 | /* Device class may be changed after fixup */ |
f79b1b14 | 1879 | class = dev->class >> 8; |
1da177e4 | 1880 | |
b6caa1d8 | 1881 | if (dev->non_compliant_bars && !dev->mmio_always_on) { |
b84106b4 BH |
1882 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
1883 | if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { | |
7506dc79 | 1884 | pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); |
b84106b4 BH |
1885 | cmd &= ~PCI_COMMAND_IO; |
1886 | cmd &= ~PCI_COMMAND_MEMORY; | |
1887 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1888 | } | |
1889 | } | |
1890 | ||
99b3c58f PG |
1891 | dev->broken_intx_masking = pci_intx_mask_broken(dev); |
1892 | ||
1da177e4 LT |
1893 | switch (dev->hdr_type) { /* header type */ |
1894 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
1895 | if (class == PCI_CLASS_BRIDGE_PCI) | |
1896 | goto bad; | |
1897 | pci_read_irq(dev); | |
1898 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
cf0921be KA |
1899 | |
1900 | pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); | |
368c73d4 AC |
1901 | |
1902 | /* | |
075eb9e3 BH |
1903 | * Do the ugly legacy mode stuff here rather than broken chip |
1904 | * quirk code. Legacy mode ATA controllers have fixed | |
1905 | * addresses. These are not always echoed in BAR0-3, and | |
1906 | * BAR0-3 in a few cases contain junk! | |
368c73d4 AC |
1907 | */ |
1908 | if (class == PCI_CLASS_STORAGE_IDE) { | |
1909 | u8 progif; | |
1910 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1911 | if ((progif & 1) == 0) { | |
5bfa14ed BH |
1912 | region.start = 0x1F0; |
1913 | region.end = 0x1F7; | |
1914 | res = &dev->resource[0]; | |
1915 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1916 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc79 | 1917 | pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", |
075eb9e3 | 1918 | res); |
5bfa14ed BH |
1919 | region.start = 0x3F6; |
1920 | region.end = 0x3F6; | |
1921 | res = &dev->resource[1]; | |
1922 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1923 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc79 | 1924 | pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", |
075eb9e3 | 1925 | res); |
368c73d4 AC |
1926 | } |
1927 | if ((progif & 4) == 0) { | |
5bfa14ed BH |
1928 | region.start = 0x170; |
1929 | region.end = 0x177; | |
1930 | res = &dev->resource[2]; | |
1931 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1932 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc79 | 1933 | pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", |
075eb9e3 | 1934 | res); |
5bfa14ed BH |
1935 | region.start = 0x376; |
1936 | region.end = 0x376; | |
1937 | res = &dev->resource[3]; | |
1938 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1939 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc79 | 1940 | pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", |
075eb9e3 | 1941 | res); |
368c73d4 AC |
1942 | } |
1943 | } | |
1da177e4 LT |
1944 | break; |
1945 | ||
1946 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
3e466e2d BH |
1947 | /* |
1948 | * The PCI-to-PCI bridge spec requires that subtractive | |
1949 | * decoding (i.e. transparent) bridge must have programming | |
1950 | * interface code of 0x01. | |
1951 | */ | |
3efd273b | 1952 | pci_read_irq(dev); |
1da177e4 LT |
1953 | dev->transparent = ((dev->class & 0xff) == 1); |
1954 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
51c48b31 | 1955 | pci_read_bridge_windows(dev); |
28760489 | 1956 | set_pcie_hotplug_bridge(dev); |
bc577d2b GB |
1957 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
1958 | if (pos) { | |
1959 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); | |
1960 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); | |
1961 | } | |
1da177e4 LT |
1962 | break; |
1963 | ||
1964 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
1965 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
1966 | goto bad; | |
1967 | pci_read_irq(dev); | |
1968 | pci_read_bases(dev, 1, 0); | |
1969 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1970 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
1971 | break; | |
1972 | ||
1973 | default: /* unknown header */ | |
7506dc79 | 1974 | pci_err(dev, "unknown header type %02x, ignoring device\n", |
227f0647 | 1975 | dev->hdr_type); |
375553a9 | 1976 | pci_release_of_node(dev); |
480b93b7 | 1977 | return -EIO; |
1da177e4 LT |
1978 | |
1979 | bad: | |
7506dc79 | 1980 | pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", |
227f0647 | 1981 | dev->class, dev->hdr_type); |
2b4aed1d | 1982 | dev->class = PCI_CLASS_NOT_DEFINED << 8; |
1da177e4 LT |
1983 | } |
1984 | ||
1985 | /* We found a fine healthy device, go go go... */ | |
1986 | return 0; | |
1987 | } | |
1988 | ||
9dae3a97 BH |
1989 | static void pci_configure_mps(struct pci_dev *dev) |
1990 | { | |
1991 | struct pci_dev *bridge = pci_upstream_bridge(dev); | |
9f0e8935 | 1992 | int mps, mpss, p_mps, rc; |
9dae3a97 | 1993 | |
aa0ce96d | 1994 | if (!pci_is_pcie(dev)) |
9dae3a97 BH |
1995 | return; |
1996 | ||
3dbe97ef MS |
1997 | /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ |
1998 | if (dev->is_virtfn) | |
1999 | return; | |
2000 | ||
aa0ce96d AR |
2001 | /* |
2002 | * For Root Complex Integrated Endpoints, program the maximum | |
2003 | * supported value unless limited by the PCIE_BUS_PEER2PEER case. | |
2004 | */ | |
2005 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { | |
2006 | if (pcie_bus_config == PCIE_BUS_PEER2PEER) | |
2007 | mps = 128; | |
2008 | else | |
2009 | mps = 128 << dev->pcie_mpss; | |
2010 | rc = pcie_set_mps(dev, mps); | |
2011 | if (rc) { | |
2012 | pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", | |
2013 | mps); | |
2014 | } | |
2015 | return; | |
2016 | } | |
2017 | ||
2018 | if (!bridge || !pci_is_pcie(bridge)) | |
2019 | return; | |
2020 | ||
9dae3a97 BH |
2021 | mps = pcie_get_mps(dev); |
2022 | p_mps = pcie_get_mps(bridge); | |
2023 | ||
2024 | if (mps == p_mps) | |
2025 | return; | |
2026 | ||
2027 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { | |
7506dc79 | 2028 | pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", |
9dae3a97 BH |
2029 | mps, pci_name(bridge), p_mps); |
2030 | return; | |
2031 | } | |
27d868b5 KB |
2032 | |
2033 | /* | |
2034 | * Fancier MPS configuration is done later by | |
2035 | * pcie_bus_configure_settings() | |
2036 | */ | |
2037 | if (pcie_bus_config != PCIE_BUS_DEFAULT) | |
2038 | return; | |
2039 | ||
9f0e8935 MS |
2040 | mpss = 128 << dev->pcie_mpss; |
2041 | if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { | |
2042 | pcie_set_mps(bridge, mpss); | |
2043 | pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", | |
2044 | mpss, p_mps, 128 << bridge->pcie_mpss); | |
2045 | p_mps = pcie_get_mps(bridge); | |
2046 | } | |
2047 | ||
27d868b5 KB |
2048 | rc = pcie_set_mps(dev, p_mps); |
2049 | if (rc) { | |
7506dc79 | 2050 | pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", |
27d868b5 KB |
2051 | p_mps); |
2052 | return; | |
2053 | } | |
2054 | ||
7506dc79 | 2055 | pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", |
9f0e8935 | 2056 | p_mps, mps, mpss); |
9dae3a97 BH |
2057 | } |
2058 | ||
62ce94a7 | 2059 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign) |
60db3a4d | 2060 | { |
62ce94a7 SK |
2061 | struct pci_host_bridge *host; |
2062 | u32 cap; | |
2063 | u16 ctl; | |
60db3a4d SK |
2064 | int ret; |
2065 | ||
2066 | if (!pci_is_pcie(dev)) | |
62ce94a7 | 2067 | return 0; |
60db3a4d | 2068 | |
62ce94a7 | 2069 | ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
60db3a4d | 2070 | if (ret) |
62ce94a7 SK |
2071 | return 0; |
2072 | ||
2073 | if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) | |
2074 | return 0; | |
60db3a4d | 2075 | |
62ce94a7 SK |
2076 | ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
2077 | if (ret) | |
2078 | return 0; | |
2079 | ||
2080 | host = pci_find_host_bridge(dev->bus); | |
2081 | if (!host) | |
2082 | return 0; | |
60db3a4d | 2083 | |
62ce94a7 SK |
2084 | /* |
2085 | * If some device in the hierarchy doesn't handle Extended Tags | |
2086 | * correctly, make sure they're disabled. | |
2087 | */ | |
2088 | if (host->no_ext_tags) { | |
2089 | if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { | |
7506dc79 | 2090 | pci_info(dev, "disabling Extended Tags\n"); |
62ce94a7 SK |
2091 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, |
2092 | PCI_EXP_DEVCTL_EXT_TAG); | |
2093 | } | |
2094 | return 0; | |
2095 | } | |
2096 | ||
2097 | if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { | |
7506dc79 | 2098 | pci_info(dev, "enabling Extended Tags\n"); |
60db3a4d SK |
2099 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, |
2100 | PCI_EXP_DEVCTL_EXT_TAG); | |
62ce94a7 SK |
2101 | } |
2102 | return 0; | |
60db3a4d SK |
2103 | } |
2104 | ||
a99b646a | 2105 | /** |
2106 | * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable | |
2107 | * @dev: PCI device to query | |
2108 | * | |
2109 | * Returns true if the device has enabled relaxed ordering attribute. | |
2110 | */ | |
2111 | bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) | |
2112 | { | |
2113 | u16 v; | |
2114 | ||
2115 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); | |
2116 | ||
2117 | return !!(v & PCI_EXP_DEVCTL_RELAX_EN); | |
2118 | } | |
2119 | EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); | |
2120 | ||
2121 | static void pci_configure_relaxed_ordering(struct pci_dev *dev) | |
2122 | { | |
2123 | struct pci_dev *root; | |
2124 | ||
2125 | /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ | |
2126 | if (dev->is_virtfn) | |
2127 | return; | |
2128 | ||
2129 | if (!pcie_relaxed_ordering_enabled(dev)) | |
2130 | return; | |
2131 | ||
2132 | /* | |
2133 | * For now, we only deal with Relaxed Ordering issues with Root | |
2134 | * Ports. Peer-to-Peer DMA is another can of worms. | |
2135 | */ | |
6ae72bfa | 2136 | root = pcie_find_root_port(dev); |
a99b646a | 2137 | if (!root) |
2138 | return; | |
2139 | ||
2140 | if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { | |
2141 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, | |
2142 | PCI_EXP_DEVCTL_RELAX_EN); | |
7506dc79 | 2143 | pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); |
a99b646a | 2144 | } |
2145 | } | |
2146 | ||
c46fd358 BH |
2147 | static void pci_configure_ltr(struct pci_dev *dev) |
2148 | { | |
2149 | #ifdef CONFIG_PCIEASPM | |
af8bb9f8 | 2150 | struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); |
c46fd358 | 2151 | struct pci_dev *bridge; |
10ecc818 | 2152 | u32 cap, ctl; |
af8bb9f8 | 2153 | |
c46fd358 BH |
2154 | if (!pci_is_pcie(dev)) |
2155 | return; | |
2156 | ||
ecdf57b4 SB |
2157 | /* Read L1 PM substate capabilities */ |
2158 | dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); | |
2159 | ||
c46fd358 BH |
2160 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); |
2161 | if (!(cap & PCI_EXP_DEVCAP2_LTR)) | |
2162 | return; | |
2163 | ||
10ecc818 BH |
2164 | pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); |
2165 | if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { | |
2166 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { | |
2167 | dev->ltr_path = 1; | |
2168 | return; | |
2169 | } | |
2170 | ||
c46fd358 BH |
2171 | bridge = pci_upstream_bridge(dev); |
2172 | if (bridge && bridge->ltr_path) | |
2173 | dev->ltr_path = 1; | |
10ecc818 BH |
2174 | |
2175 | return; | |
c46fd358 BH |
2176 | } |
2177 | ||
10ecc818 BH |
2178 | if (!host->native_ltr) |
2179 | return; | |
2180 | ||
2181 | /* | |
2182 | * Software must not enable LTR in an Endpoint unless the Root | |
2183 | * Complex and all intermediate Switches indicate support for LTR. | |
2184 | * PCIe r4.0, sec 6.18. | |
2185 | */ | |
e1b0d0bb MQ |
2186 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { |
2187 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, | |
2188 | PCI_EXP_DEVCTL2_LTR_EN); | |
2189 | dev->ltr_path = 1; | |
2190 | return; | |
2191 | } | |
2192 | ||
2193 | /* | |
2194 | * If we're configuring a hot-added device, LTR was likely | |
2195 | * disabled in the upstream bridge, so re-enable it before enabling | |
2196 | * it in the new device. | |
2197 | */ | |
2198 | bridge = pci_upstream_bridge(dev); | |
2199 | if (bridge && bridge->ltr_path) { | |
2200 | pci_bridge_reconfigure_ltr(dev); | |
c46fd358 BH |
2201 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, |
2202 | PCI_EXP_DEVCTL2_LTR_EN); | |
10ecc818 BH |
2203 | dev->ltr_path = 1; |
2204 | } | |
c46fd358 BH |
2205 | #endif |
2206 | } | |
2207 | ||
7ce3f912 SK |
2208 | static void pci_configure_eetlp_prefix(struct pci_dev *dev) |
2209 | { | |
2210 | #ifdef CONFIG_PCI_PASID | |
2211 | struct pci_dev *bridge; | |
9d27e39d | 2212 | int pcie_type; |
7ce3f912 SK |
2213 | u32 cap; |
2214 | ||
2215 | if (!pci_is_pcie(dev)) | |
2216 | return; | |
2217 | ||
2218 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); | |
2219 | if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) | |
2220 | return; | |
2221 | ||
9d27e39d FK |
2222 | pcie_type = pci_pcie_type(dev); |
2223 | if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
2224 | pcie_type == PCI_EXP_TYPE_RC_END) | |
7ce3f912 SK |
2225 | dev->eetlp_prefix_path = 1; |
2226 | else { | |
2227 | bridge = pci_upstream_bridge(dev); | |
2228 | if (bridge && bridge->eetlp_prefix_path) | |
2229 | dev->eetlp_prefix_path = 1; | |
2230 | } | |
2231 | #endif | |
2232 | } | |
2233 | ||
b4f6dcb9 BKG |
2234 | static void pci_configure_serr(struct pci_dev *dev) |
2235 | { | |
2236 | u16 control; | |
2237 | ||
2238 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
2239 | ||
2240 | /* | |
2241 | * A bridge will not forward ERR_ messages coming from an | |
2242 | * endpoint unless SERR# forwarding is enabled. | |
2243 | */ | |
2244 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); | |
2245 | if (!(control & PCI_BRIDGE_CTL_SERR)) { | |
2246 | control |= PCI_BRIDGE_CTL_SERR; | |
2247 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); | |
2248 | } | |
2249 | } | |
2250 | } | |
2251 | ||
6cd33649 BH |
2252 | static void pci_configure_device(struct pci_dev *dev) |
2253 | { | |
9dae3a97 | 2254 | pci_configure_mps(dev); |
62ce94a7 | 2255 | pci_configure_extended_tags(dev, NULL); |
a99b646a | 2256 | pci_configure_relaxed_ordering(dev); |
c46fd358 | 2257 | pci_configure_ltr(dev); |
7ce3f912 | 2258 | pci_configure_eetlp_prefix(dev); |
b4f6dcb9 | 2259 | pci_configure_serr(dev); |
9dae3a97 | 2260 | |
4a2dbedd | 2261 | pci_acpi_program_hp_params(dev); |
6cd33649 BH |
2262 | } |
2263 | ||
201de56e ZY |
2264 | static void pci_release_capabilities(struct pci_dev *dev) |
2265 | { | |
db89ccbe | 2266 | pci_aer_exit(dev); |
90655631 | 2267 | pci_rcec_exit(dev); |
d1b054da | 2268 | pci_iov_release(dev); |
f796841e | 2269 | pci_free_cap_save_buffers(dev); |
201de56e ZY |
2270 | } |
2271 | ||
1da177e4 | 2272 | /** |
3e466e2d BH |
2273 | * pci_release_dev - Free a PCI device structure when all users of it are |
2274 | * finished | |
1da177e4 LT |
2275 | * @dev: device that's been disconnected |
2276 | * | |
3e466e2d | 2277 | * Will be called only by the device core when all users of this PCI device are |
1da177e4 LT |
2278 | * done. |
2279 | */ | |
2280 | static void pci_release_dev(struct device *dev) | |
2281 | { | |
04480094 | 2282 | struct pci_dev *pci_dev; |
1da177e4 | 2283 | |
04480094 | 2284 | pci_dev = to_pci_dev(dev); |
201de56e | 2285 | pci_release_capabilities(pci_dev); |
98d9f30c | 2286 | pci_release_of_node(pci_dev); |
6ae32c53 | 2287 | pcibios_release_device(pci_dev); |
8b1fce04 | 2288 | pci_bus_put(pci_dev->bus); |
782a985d | 2289 | kfree(pci_dev->driver_override); |
c6635792 | 2290 | bitmap_free(pci_dev->dma_alias_mask); |
ea4aae05 | 2291 | dev_dbg(dev, "device released\n"); |
1da177e4 LT |
2292 | kfree(pci_dev); |
2293 | } | |
2294 | ||
3c6e6ae7 | 2295 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus) |
65891215 ME |
2296 | { |
2297 | struct pci_dev *dev; | |
2298 | ||
2299 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
2300 | if (!dev) | |
2301 | return NULL; | |
2302 | ||
65891215 | 2303 | INIT_LIST_HEAD(&dev->bus_list); |
88e7b167 | 2304 | dev->dev.type = &pci_dev_type; |
3c6e6ae7 | 2305 | dev->bus = pci_bus_get(bus); |
cd119b09 TG |
2306 | #ifdef CONFIG_PCI_MSI |
2307 | raw_spin_lock_init(&dev->msi_lock); | |
2308 | #endif | |
65891215 ME |
2309 | return dev; |
2310 | } | |
3c6e6ae7 GZ |
2311 | EXPORT_SYMBOL(pci_alloc_dev); |
2312 | ||
62bc6a6f SK |
2313 | static bool pci_bus_crs_vendor_id(u32 l) |
2314 | { | |
2315 | return (l & 0xffff) == 0x0001; | |
2316 | } | |
2317 | ||
6a802ef0 SK |
2318 | static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, |
2319 | int timeout) | |
1da177e4 | 2320 | { |
1da177e4 LT |
2321 | int delay = 1; |
2322 | ||
6a802ef0 SK |
2323 | if (!pci_bus_crs_vendor_id(*l)) |
2324 | return true; /* not a CRS completion */ | |
1da177e4 | 2325 | |
6a802ef0 SK |
2326 | if (!timeout) |
2327 | return false; /* CRS, but caller doesn't want to wait */ | |
1da177e4 | 2328 | |
89665a6a | 2329 | /* |
6a802ef0 SK |
2330 | * We got the reserved Vendor ID that indicates a completion with |
2331 | * Configuration Request Retry Status (CRS). Retry until we get a | |
2332 | * valid Vendor ID or we time out. | |
89665a6a | 2333 | */ |
62bc6a6f | 2334 | while (pci_bus_crs_vendor_id(*l)) { |
6a802ef0 | 2335 | if (delay > timeout) { |
e78e661f SK |
2336 | pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", |
2337 | pci_domain_nr(bus), bus->number, | |
2338 | PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); | |
2339 | ||
efdc87da | 2340 | return false; |
1da177e4 | 2341 | } |
e78e661f SK |
2342 | if (delay >= 1000) |
2343 | pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", | |
2344 | pci_domain_nr(bus), bus->number, | |
2345 | PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); | |
efdc87da | 2346 | |
1da177e4 LT |
2347 | msleep(delay); |
2348 | delay *= 2; | |
9f982756 | 2349 | |
efdc87da YL |
2350 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
2351 | return false; | |
1da177e4 LT |
2352 | } |
2353 | ||
e78e661f SK |
2354 | if (delay >= 1000) |
2355 | pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", | |
2356 | pci_domain_nr(bus), bus->number, | |
2357 | PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); | |
2358 | ||
efdc87da YL |
2359 | return true; |
2360 | } | |
6a802ef0 | 2361 | |
aa667c64 JP |
2362 | bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, |
2363 | int timeout) | |
6a802ef0 SK |
2364 | { |
2365 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) | |
2366 | return false; | |
2367 | ||
fa52b644 NN |
2368 | /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ |
2369 | if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 || | |
6a802ef0 SK |
2370 | *l == 0x0000ffff || *l == 0xffff0000) |
2371 | return false; | |
2372 | ||
2373 | if (pci_bus_crs_vendor_id(*l)) | |
2374 | return pci_bus_wait_crs(bus, devfn, l, timeout); | |
2375 | ||
efdc87da YL |
2376 | return true; |
2377 | } | |
aa667c64 JP |
2378 | |
2379 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, | |
2380 | int timeout) | |
2381 | { | |
2382 | #ifdef CONFIG_PCI_QUIRKS | |
2383 | struct pci_dev *bridge = bus->self; | |
2384 | ||
2385 | /* | |
2386 | * Certain IDT switches have an issue where they improperly trigger | |
2387 | * ACS Source Validation errors on completions for config reads. | |
2388 | */ | |
2389 | if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && | |
2390 | bridge->device == 0x80b5) | |
2391 | return pci_idt_bus_quirk(bus, devfn, l, timeout); | |
2392 | #endif | |
2393 | ||
2394 | return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); | |
2395 | } | |
efdc87da YL |
2396 | EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); |
2397 | ||
2398 | /* | |
3e466e2d BH |
2399 | * Read the config data for a PCI device, sanity-check it, |
2400 | * and fill in the dev structure. | |
efdc87da YL |
2401 | */ |
2402 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) | |
2403 | { | |
2404 | struct pci_dev *dev; | |
2405 | u32 l; | |
2406 | ||
2407 | if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) | |
2408 | return NULL; | |
2409 | ||
8b1fce04 | 2410 | dev = pci_alloc_dev(bus); |
1da177e4 LT |
2411 | if (!dev) |
2412 | return NULL; | |
2413 | ||
1da177e4 | 2414 | dev->devfn = devfn; |
1da177e4 LT |
2415 | dev->vendor = l & 0xffff; |
2416 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 2417 | |
480b93b7 | 2418 | if (pci_setup_device(dev)) { |
8b1fce04 | 2419 | pci_bus_put(dev->bus); |
1da177e4 LT |
2420 | kfree(dev); |
2421 | return NULL; | |
2422 | } | |
1da177e4 LT |
2423 | |
2424 | return dev; | |
2425 | } | |
2426 | ||
0fa635ae | 2427 | void pcie_report_downtraining(struct pci_dev *dev) |
2d1ce5ec AG |
2428 | { |
2429 | if (!pci_is_pcie(dev)) | |
2430 | return; | |
2431 | ||
2432 | /* Look from the device up to avoid downstream ports with no devices */ | |
2433 | if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && | |
2434 | (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && | |
2435 | (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) | |
2436 | return; | |
2437 | ||
2438 | /* Multi-function PCIe devices share the same link/status */ | |
2439 | if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) | |
2440 | return; | |
2441 | ||
2442 | /* Print link status only if the device is constrained by the fabric */ | |
2443 | __pcie_print_link_status(dev, false); | |
2444 | } | |
2445 | ||
201de56e ZY |
2446 | static void pci_init_capabilities(struct pci_dev *dev) |
2447 | { | |
9d8b738b | 2448 | pci_ea_init(dev); /* Enhanced Allocation */ |
cbc40d5c BH |
2449 | pci_msi_init(dev); /* Disable MSI */ |
2450 | pci_msix_init(dev); /* Disable MSI-X */ | |
201de56e | 2451 | |
63f4898a RW |
2452 | /* Buffers for saving PCIe and PCI-X capabilities */ |
2453 | pci_allocate_cap_save_buffers(dev); | |
2454 | ||
9d8b738b BH |
2455 | pci_pm_init(dev); /* Power Management */ |
2456 | pci_vpd_init(dev); /* Vital Product Data */ | |
2457 | pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ | |
2458 | pci_iov_init(dev); /* Single Root I/O Virtualization */ | |
2459 | pci_ats_init(dev); /* Address Translation Services */ | |
7e124c40 BH |
2460 | pci_pri_init(dev); /* Page Request Interface */ |
2461 | pci_pasid_init(dev); /* Process Address Space ID */ | |
52fbf5bd | 2462 | pci_acs_init(dev); /* Access Control Services */ |
9d8b738b BH |
2463 | pci_ptm_init(dev); /* Precision Time Measurement */ |
2464 | pci_aer_init(dev); /* Advanced Error Reporting */ | |
27005618 | 2465 | pci_dpc_init(dev); /* Downstream Port Containment */ |
90655631 | 2466 | pci_rcec_init(dev); /* Root Complex Event Collector */ |
5b0764ca | 2467 | |
2d1ce5ec | 2468 | pcie_report_downtraining(dev); |
e20afa06 | 2469 | pci_init_reset_methods(dev); |
201de56e ZY |
2470 | } |
2471 | ||
098259eb | 2472 | /* |
3e466e2d | 2473 | * This is the equivalent of pci_host_bridge_msi_domain() that acts on |
098259eb MZ |
2474 | * devices. Firmware interfaces that can select the MSI domain on a |
2475 | * per-device basis should be called from here. | |
2476 | */ | |
2477 | static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) | |
2478 | { | |
2479 | struct irq_domain *d; | |
2480 | ||
2481 | /* | |
06dc660e | 2482 | * If a domain has been set through the pcibios_device_add() |
098259eb MZ |
2483 | * callback, then this is the one (platform code knows best). |
2484 | */ | |
2485 | d = dev_get_msi_domain(&dev->dev); | |
2486 | if (d) | |
2487 | return d; | |
2488 | ||
54fa97ee MZ |
2489 | /* |
2490 | * Let's see if we have a firmware interface able to provide | |
2491 | * the domain. | |
2492 | */ | |
2493 | d = pci_msi_get_device_domain(dev); | |
2494 | if (d) | |
2495 | return d; | |
2496 | ||
098259eb MZ |
2497 | return NULL; |
2498 | } | |
2499 | ||
44aa0c65 MZ |
2500 | static void pci_set_msi_domain(struct pci_dev *dev) |
2501 | { | |
098259eb MZ |
2502 | struct irq_domain *d; |
2503 | ||
44aa0c65 | 2504 | /* |
098259eb MZ |
2505 | * If the platform or firmware interfaces cannot supply a |
2506 | * device-specific MSI domain, then inherit the default domain | |
2507 | * from the host bridge itself. | |
44aa0c65 | 2508 | */ |
098259eb MZ |
2509 | d = pci_dev_msi_domain(dev); |
2510 | if (!d) | |
2511 | d = dev_get_msi_domain(&dev->bus->dev); | |
2512 | ||
2513 | dev_set_msi_domain(&dev->dev, d); | |
44aa0c65 MZ |
2514 | } |
2515 | ||
96bde06a | 2516 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 2517 | { |
4f535093 YL |
2518 | int ret; |
2519 | ||
6cd33649 BH |
2520 | pci_configure_device(dev); |
2521 | ||
cdb9b9f7 PM |
2522 | device_initialize(&dev->dev); |
2523 | dev->dev.release = pci_release_dev; | |
1da177e4 | 2524 | |
7629d19a | 2525 | set_dev_node(&dev->dev, pcibus_to_node(bus)); |
cdb9b9f7 | 2526 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 2527 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 2528 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 2529 | |
b0da3498 | 2530 | dma_set_max_seg_size(&dev->dev, 65536); |
a6f44cf9 | 2531 | dma_set_seg_boundary(&dev->dev, 0xffffffff); |
4d57cdfa | 2532 | |
1da177e4 LT |
2533 | /* Fix up broken headers */ |
2534 | pci_fixup_device(pci_fixup_header, dev); | |
2535 | ||
2069ecfb YL |
2536 | pci_reassigndev_resource_alignment(dev); |
2537 | ||
4b77b0a2 RW |
2538 | dev->state_saved = false; |
2539 | ||
201de56e | 2540 | pci_init_capabilities(dev); |
eb9d0fe4 | 2541 | |
1da177e4 LT |
2542 | /* |
2543 | * Add the device to our list of discovered devices | |
2544 | * and the bus list for fixup functions, etc. | |
2545 | */ | |
d71374da | 2546 | down_write(&pci_bus_sem); |
1da177e4 | 2547 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 2548 | up_write(&pci_bus_sem); |
4f535093 | 2549 | |
06dc660e | 2550 | ret = pcibios_device_add(dev); |
4f535093 YL |
2551 | WARN_ON(ret < 0); |
2552 | ||
3e466e2d | 2553 | /* Set up MSI IRQ domain */ |
44aa0c65 MZ |
2554 | pci_set_msi_domain(dev); |
2555 | ||
4f535093 YL |
2556 | /* Notifier could use PCI capabilities */ |
2557 | dev->match_driver = false; | |
2558 | ret = device_add(&dev->dev); | |
2559 | WARN_ON(ret < 0); | |
cdb9b9f7 PM |
2560 | } |
2561 | ||
10874f5a | 2562 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
2563 | { |
2564 | struct pci_dev *dev; | |
2565 | ||
90bdb311 TP |
2566 | dev = pci_get_slot(bus, devfn); |
2567 | if (dev) { | |
2568 | pci_dev_put(dev); | |
2569 | return dev; | |
2570 | } | |
2571 | ||
cdb9b9f7 PM |
2572 | dev = pci_scan_device(bus, devfn); |
2573 | if (!dev) | |
2574 | return NULL; | |
2575 | ||
2576 | pci_device_add(dev, bus); | |
1da177e4 LT |
2577 | |
2578 | return dev; | |
2579 | } | |
b73e9687 | 2580 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 | 2581 | |
fd1ae23b KW |
2582 | static unsigned int next_fn(struct pci_bus *bus, struct pci_dev *dev, |
2583 | unsigned int fn) | |
f07852d6 | 2584 | { |
b1bd58e4 YW |
2585 | int pos; |
2586 | u16 cap = 0; | |
fd1ae23b | 2587 | unsigned int next_fn; |
4fb88c1a | 2588 | |
b1bd58e4 YW |
2589 | if (pci_ari_enabled(bus)) { |
2590 | if (!dev) | |
2591 | return 0; | |
2592 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); | |
2593 | if (!pos) | |
2594 | return 0; | |
4fb88c1a | 2595 | |
b1bd58e4 YW |
2596 | pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); |
2597 | next_fn = PCI_ARI_CAP_NFN(cap); | |
2598 | if (next_fn <= fn) | |
2599 | return 0; /* protect against malformed list */ | |
f07852d6 | 2600 | |
b1bd58e4 YW |
2601 | return next_fn; |
2602 | } | |
2603 | ||
2604 | /* dev may be NULL for non-contiguous multifunction devices */ | |
2605 | if (!dev || dev->multifunction) | |
2606 | return (fn + 1) % 8; | |
f07852d6 | 2607 | |
f07852d6 MW |
2608 | return 0; |
2609 | } | |
2610 | ||
2611 | static int only_one_child(struct pci_bus *bus) | |
2612 | { | |
d57f0b8c | 2613 | struct pci_dev *bridge = bus->self; |
284f5f9d | 2614 | |
d57f0b8c BH |
2615 | /* |
2616 | * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so | |
2617 | * we scan for all possible devices, not just Device 0. | |
2618 | */ | |
2619 | if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) | |
f07852d6 | 2620 | return 0; |
5bbe029f BH |
2621 | |
2622 | /* | |
d57f0b8c BH |
2623 | * A PCIe Downstream Port normally leads to a Link with only Device |
2624 | * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan | |
2625 | * only for Device 0 in that situation. | |
5bbe029f | 2626 | */ |
ca784104 | 2627 | if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) |
f07852d6 | 2628 | return 1; |
d57f0b8c | 2629 | |
f07852d6 MW |
2630 | return 0; |
2631 | } | |
2632 | ||
1da177e4 | 2633 | /** |
3e466e2d | 2634 | * pci_scan_slot - Scan a PCI slot on a bus for devices |
1da177e4 | 2635 | * @bus: PCI bus to scan |
3e466e2d | 2636 | * @devfn: slot number to scan (must have zero function) |
1da177e4 LT |
2637 | * |
2638 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
2639 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 2640 | * will not have is_added set. |
1b69dfc6 TP |
2641 | * |
2642 | * Returns the number of new devices found. | |
1da177e4 | 2643 | */ |
96bde06a | 2644 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 2645 | { |
fd1ae23b | 2646 | unsigned int fn, nr = 0; |
1b69dfc6 | 2647 | struct pci_dev *dev; |
f07852d6 MW |
2648 | |
2649 | if (only_one_child(bus) && (devfn > 0)) | |
2650 | return 0; /* Already scanned the entire slot */ | |
1da177e4 | 2651 | |
1b69dfc6 | 2652 | dev = pci_scan_single_device(bus, devfn); |
4fb88c1a MW |
2653 | if (!dev) |
2654 | return 0; | |
44bda4b7 | 2655 | if (!pci_dev_is_added(dev)) |
1b69dfc6 TP |
2656 | nr++; |
2657 | ||
b1bd58e4 | 2658 | for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { |
f07852d6 MW |
2659 | dev = pci_scan_single_device(bus, devfn + fn); |
2660 | if (dev) { | |
44bda4b7 | 2661 | if (!pci_dev_is_added(dev)) |
f07852d6 MW |
2662 | nr++; |
2663 | dev->multifunction = 1; | |
1da177e4 LT |
2664 | } |
2665 | } | |
7d715a6c | 2666 | |
3e466e2d | 2667 | /* Only one slot has PCIe device */ |
149e1637 | 2668 | if (bus->self && nr) |
7d715a6c SL |
2669 | pcie_aspm_init_link_state(bus->self); |
2670 | ||
1da177e4 LT |
2671 | return nr; |
2672 | } | |
b7fe9434 | 2673 | EXPORT_SYMBOL(pci_scan_slot); |
1da177e4 | 2674 | |
b03e7495 JM |
2675 | static int pcie_find_smpss(struct pci_dev *dev, void *data) |
2676 | { | |
2677 | u8 *smpss = data; | |
2678 | ||
2679 | if (!pci_is_pcie(dev)) | |
2680 | return 0; | |
2681 | ||
d4aa68f6 YW |
2682 | /* |
2683 | * We don't have a way to change MPS settings on devices that have | |
2684 | * drivers attached. A hot-added device might support only the minimum | |
2685 | * MPS setting (MPS=128). Therefore, if the fabric contains a bridge | |
2686 | * where devices may be hot-added, we limit the fabric MPS to 128 so | |
2687 | * hot-added devices will work correctly. | |
2688 | * | |
2689 | * However, if we hot-add a device to a slot directly below a Root | |
2690 | * Port, it's impossible for there to be other existing devices below | |
2691 | * the port. We don't limit the MPS in this case because we can | |
2692 | * reconfigure MPS on both the Root Port and the hot-added device, | |
2693 | * and there are no other devices involved. | |
2694 | * | |
2695 | * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. | |
b03e7495 | 2696 | */ |
d4aa68f6 YW |
2697 | if (dev->is_hotplug_bridge && |
2698 | pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) | |
b03e7495 JM |
2699 | *smpss = 0; |
2700 | ||
2701 | if (*smpss > dev->pcie_mpss) | |
2702 | *smpss = dev->pcie_mpss; | |
2703 | ||
2704 | return 0; | |
2705 | } | |
2706 | ||
2707 | static void pcie_write_mps(struct pci_dev *dev, int mps) | |
2708 | { | |
62f392ea | 2709 | int rc; |
b03e7495 JM |
2710 | |
2711 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
62f392ea | 2712 | mps = 128 << dev->pcie_mpss; |
b03e7495 | 2713 | |
62f87c0e YW |
2714 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && |
2715 | dev->bus->self) | |
3e466e2d BH |
2716 | |
2717 | /* | |
2718 | * For "Performance", the assumption is made that | |
b03e7495 JM |
2719 | * downstream communication will never be larger than |
2720 | * the MRRS. So, the MPS only needs to be configured | |
2721 | * for the upstream communication. This being the case, | |
2722 | * walk from the top down and set the MPS of the child | |
2723 | * to that of the parent bus. | |
62f392ea JM |
2724 | * |
2725 | * Configure the device MPS with the smaller of the | |
2726 | * device MPSS or the bridge MPS (which is assumed to be | |
2727 | * properly configured at this point to the largest | |
2728 | * allowable MPS based on its parent bus). | |
b03e7495 | 2729 | */ |
62f392ea | 2730 | mps = min(mps, pcie_get_mps(dev->bus->self)); |
b03e7495 JM |
2731 | } |
2732 | ||
2733 | rc = pcie_set_mps(dev, mps); | |
2734 | if (rc) | |
7506dc79 | 2735 | pci_err(dev, "Failed attempting to set the MPS\n"); |
b03e7495 JM |
2736 | } |
2737 | ||
62f392ea | 2738 | static void pcie_write_mrrs(struct pci_dev *dev) |
b03e7495 | 2739 | { |
62f392ea | 2740 | int rc, mrrs; |
b03e7495 | 2741 | |
3e466e2d BH |
2742 | /* |
2743 | * In the "safe" case, do not configure the MRRS. There appear to be | |
ed2888e9 JM |
2744 | * issues with setting MRRS to 0 on a number of devices. |
2745 | */ | |
ed2888e9 JM |
2746 | if (pcie_bus_config != PCIE_BUS_PERFORMANCE) |
2747 | return; | |
2748 | ||
3e466e2d BH |
2749 | /* |
2750 | * For max performance, the MRRS must be set to the largest supported | |
ed2888e9 | 2751 | * value. However, it cannot be configured larger than the MPS the |
62f392ea | 2752 | * device or the bus can support. This should already be properly |
3e466e2d | 2753 | * configured by a prior call to pcie_write_mps(). |
ed2888e9 | 2754 | */ |
62f392ea | 2755 | mrrs = pcie_get_mps(dev); |
b03e7495 | 2756 | |
3e466e2d BH |
2757 | /* |
2758 | * MRRS is a R/W register. Invalid values can be written, but a | |
ed2888e9 | 2759 | * subsequent read will verify if the value is acceptable or not. |
b03e7495 JM |
2760 | * If the MRRS value provided is not acceptable (e.g., too large), |
2761 | * shrink the value until it is acceptable to the HW. | |
f7625980 | 2762 | */ |
b03e7495 JM |
2763 | while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { |
2764 | rc = pcie_set_readrq(dev, mrrs); | |
62f392ea JM |
2765 | if (!rc) |
2766 | break; | |
b03e7495 | 2767 | |
7506dc79 | 2768 | pci_warn(dev, "Failed attempting to set the MRRS\n"); |
b03e7495 JM |
2769 | mrrs /= 2; |
2770 | } | |
62f392ea JM |
2771 | |
2772 | if (mrrs < 128) | |
7506dc79 | 2773 | pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); |
b03e7495 JM |
2774 | } |
2775 | ||
2776 | static int pcie_bus_configure_set(struct pci_dev *dev, void *data) | |
2777 | { | |
a513a99a | 2778 | int mps, orig_mps; |
b03e7495 JM |
2779 | |
2780 | if (!pci_is_pcie(dev)) | |
2781 | return 0; | |
2782 | ||
27d868b5 KB |
2783 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF || |
2784 | pcie_bus_config == PCIE_BUS_DEFAULT) | |
5895af79 | 2785 | return 0; |
5895af79 | 2786 | |
a513a99a JM |
2787 | mps = 128 << *(u8 *)data; |
2788 | orig_mps = pcie_get_mps(dev); | |
b03e7495 JM |
2789 | |
2790 | pcie_write_mps(dev, mps); | |
62f392ea | 2791 | pcie_write_mrrs(dev); |
b03e7495 | 2792 | |
7506dc79 | 2793 | pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", |
227f0647 | 2794 | pcie_get_mps(dev), 128 << dev->pcie_mpss, |
a513a99a | 2795 | orig_mps, pcie_get_readrq(dev)); |
b03e7495 JM |
2796 | |
2797 | return 0; | |
2798 | } | |
2799 | ||
3e466e2d BH |
2800 | /* |
2801 | * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, | |
b03e7495 JM |
2802 | * parents then children fashion. If this changes, then this code will not |
2803 | * work as designed. | |
2804 | */ | |
a58674ff | 2805 | void pcie_bus_configure_settings(struct pci_bus *bus) |
b03e7495 | 2806 | { |
1e358f94 | 2807 | u8 smpss = 0; |
b03e7495 | 2808 | |
a58674ff | 2809 | if (!bus->self) |
b03e7495 JM |
2810 | return; |
2811 | ||
b03e7495 | 2812 | if (!pci_is_pcie(bus->self)) |
5f39e670 JM |
2813 | return; |
2814 | ||
3e466e2d BH |
2815 | /* |
2816 | * FIXME - Peer to peer DMA is possible, though the endpoint would need | |
3315472c | 2817 | * to be aware of the MPS of the destination. To work around this, |
5f39e670 JM |
2818 | * simply force the MPS of the entire system to the smallest possible. |
2819 | */ | |
2820 | if (pcie_bus_config == PCIE_BUS_PEER2PEER) | |
2821 | smpss = 0; | |
2822 | ||
b03e7495 | 2823 | if (pcie_bus_config == PCIE_BUS_SAFE) { |
a58674ff | 2824 | smpss = bus->self->pcie_mpss; |
5f39e670 | 2825 | |
b03e7495 JM |
2826 | pcie_find_smpss(bus->self, &smpss); |
2827 | pci_walk_bus(bus, pcie_find_smpss, &smpss); | |
2828 | } | |
2829 | ||
2830 | pcie_bus_configure_set(bus->self, &smpss); | |
2831 | pci_walk_bus(bus, pcie_bus_configure_set, &smpss); | |
2832 | } | |
debc3b77 | 2833 | EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); |
b03e7495 | 2834 | |
bccf90d6 PD |
2835 | /* |
2836 | * Called after each bus is probed, but before its children are examined. This | |
2837 | * is marked as __weak because multiple architectures define it. | |
2838 | */ | |
2839 | void __weak pcibios_fixup_bus(struct pci_bus *bus) | |
2840 | { | |
2841 | /* nothing to do, expected to be removed in the future */ | |
2842 | } | |
2843 | ||
1c02ea81 MW |
2844 | /** |
2845 | * pci_scan_child_bus_extend() - Scan devices below a bus | |
2846 | * @bus: Bus to scan for devices | |
2847 | * @available_buses: Total number of buses available (%0 does not try to | |
2848 | * extend beyond the minimal) | |
2849 | * | |
2850 | * Scans devices below @bus including subordinate buses. Returns new | |
2851 | * subordinate number including all the found devices. Passing | |
2852 | * @available_buses causes the remaining bus space to be distributed | |
2853 | * equally between hotplug-capable bridges to allow future extension of the | |
2854 | * hierarchy. | |
2855 | */ | |
2856 | static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, | |
2857 | unsigned int available_buses) | |
1da177e4 | 2858 | { |
1c02ea81 MW |
2859 | unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; |
2860 | unsigned int start = bus->busn_res.start; | |
690f4304 | 2861 | unsigned int devfn, fn, cmax, max = start; |
1da177e4 | 2862 | struct pci_dev *dev; |
690f4304 | 2863 | int nr_devs; |
1da177e4 | 2864 | |
0207c356 | 2865 | dev_dbg(&bus->dev, "scanning bus\n"); |
1da177e4 LT |
2866 | |
2867 | /* Go find them, Rover! */ | |
690f4304 JK |
2868 | for (devfn = 0; devfn < 256; devfn += 8) { |
2869 | nr_devs = pci_scan_slot(bus, devfn); | |
2870 | ||
2871 | /* | |
2872 | * The Jailhouse hypervisor may pass individual functions of a | |
2873 | * multi-function device to a guest without passing function 0. | |
2874 | * Look for them as well. | |
2875 | */ | |
2876 | if (jailhouse_paravirt() && nr_devs == 0) { | |
2877 | for (fn = 1; fn < 8; fn++) { | |
2878 | dev = pci_scan_single_device(bus, devfn + fn); | |
2879 | if (dev) | |
2880 | dev->multifunction = 1; | |
2881 | } | |
2882 | } | |
2883 | } | |
1da177e4 | 2884 | |
3e466e2d | 2885 | /* Reserve buses for SR-IOV capability */ |
1c02ea81 MW |
2886 | used_buses = pci_iov_bus_range(bus); |
2887 | max += used_buses; | |
a28724b0 | 2888 | |
1da177e4 LT |
2889 | /* |
2890 | * After performing arch-dependent fixup of the bus, look behind | |
2891 | * all PCI-to-PCI bridges on this bus. | |
2892 | */ | |
74710ded | 2893 | if (!bus->is_added) { |
0207c356 | 2894 | dev_dbg(&bus->dev, "fixups for bus\n"); |
74710ded | 2895 | pcibios_fixup_bus(bus); |
981cf9ea | 2896 | bus->is_added = 1; |
74710ded AC |
2897 | } |
2898 | ||
1c02ea81 MW |
2899 | /* |
2900 | * Calculate how many hotplug bridges and normal bridges there | |
2901 | * are on this bus. We will distribute the additional available | |
2902 | * buses between hotplug bridges. | |
2903 | */ | |
2904 | for_each_pci_bridge(dev, bus) { | |
2905 | if (dev->is_hotplug_bridge) | |
2906 | hotplug_bridges++; | |
2907 | else | |
2908 | normal_bridges++; | |
2909 | } | |
2910 | ||
4147c2fd MW |
2911 | /* |
2912 | * Scan bridges that are already configured. We don't touch them | |
2913 | * unless they are misconfigured (which will be done in the second | |
2914 | * scan below). | |
2915 | */ | |
1c02ea81 MW |
2916 | for_each_pci_bridge(dev, bus) { |
2917 | cmax = max; | |
2918 | max = pci_scan_bridge_extend(bus, dev, max, 0, 0); | |
3374c545 MW |
2919 | |
2920 | /* | |
2921 | * Reserve one bus for each bridge now to avoid extending | |
2922 | * hotplug bridges too much during the second scan below. | |
2923 | */ | |
2924 | used_buses++; | |
2925 | if (cmax - max > 1) | |
2926 | used_buses += cmax - max - 1; | |
1c02ea81 | 2927 | } |
4147c2fd MW |
2928 | |
2929 | /* Scan bridges that need to be reconfigured */ | |
1c02ea81 MW |
2930 | for_each_pci_bridge(dev, bus) { |
2931 | unsigned int buses = 0; | |
2932 | ||
2933 | if (!hotplug_bridges && normal_bridges == 1) { | |
3e466e2d | 2934 | |
1c02ea81 MW |
2935 | /* |
2936 | * There is only one bridge on the bus (upstream | |
2937 | * port) so it gets all available buses which it | |
2938 | * can then distribute to the possible hotplug | |
2939 | * bridges below. | |
2940 | */ | |
2941 | buses = available_buses; | |
2942 | } else if (dev->is_hotplug_bridge) { | |
3e466e2d | 2943 | |
1c02ea81 MW |
2944 | /* |
2945 | * Distribute the extra buses between hotplug | |
2946 | * bridges if any. | |
2947 | */ | |
2948 | buses = available_buses / hotplug_bridges; | |
3374c545 | 2949 | buses = min(buses, available_buses - used_buses + 1); |
1c02ea81 MW |
2950 | } |
2951 | ||
2952 | cmax = max; | |
2953 | max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); | |
3374c545 MW |
2954 | /* One bus is already accounted so don't add it again */ |
2955 | if (max - cmax > 1) | |
2956 | used_buses += max - cmax - 1; | |
1c02ea81 | 2957 | } |
1da177e4 | 2958 | |
e16b4660 KB |
2959 | /* |
2960 | * Make sure a hotplug bridge has at least the minimum requested | |
1c02ea81 MW |
2961 | * number of buses but allow it to grow up to the maximum available |
2962 | * bus number of there is room. | |
e16b4660 | 2963 | */ |
1c02ea81 MW |
2964 | if (bus->self && bus->self->is_hotplug_bridge) { |
2965 | used_buses = max_t(unsigned int, available_buses, | |
2966 | pci_hotplug_bus_size - 1); | |
2967 | if (max - start < used_buses) { | |
2968 | max = start + used_buses; | |
2969 | ||
2970 | /* Do not allocate more buses than we have room left */ | |
2971 | if (max > bus->busn_res.end) | |
2972 | max = bus->busn_res.end; | |
2973 | ||
2974 | dev_dbg(&bus->dev, "%pR extended by %#02x\n", | |
2975 | &bus->busn_res, max - start); | |
2976 | } | |
e16b4660 KB |
2977 | } |
2978 | ||
1da177e4 LT |
2979 | /* |
2980 | * We've scanned the bus and so we know all about what's on | |
2981 | * the other side of any bridges that may be on this bus plus | |
2982 | * any devices. | |
2983 | * | |
2984 | * Return how far we've got finding sub-buses. | |
2985 | */ | |
0207c356 | 2986 | dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); |
1da177e4 LT |
2987 | return max; |
2988 | } | |
1c02ea81 MW |
2989 | |
2990 | /** | |
2991 | * pci_scan_child_bus() - Scan devices below a bus | |
2992 | * @bus: Bus to scan for devices | |
2993 | * | |
2994 | * Scans devices below @bus including subordinate buses. Returns new | |
2995 | * subordinate number including all the found devices. | |
2996 | */ | |
2997 | unsigned int pci_scan_child_bus(struct pci_bus *bus) | |
2998 | { | |
2999 | return pci_scan_child_bus_extend(bus, 0); | |
3000 | } | |
b7fe9434 | 3001 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1da177e4 | 3002 | |
6c0cc950 | 3003 | /** |
3e466e2d BH |
3004 | * pcibios_root_bridge_prepare - Platform-specific host bridge setup |
3005 | * @bridge: Host bridge to set up | |
6c0cc950 RW |
3006 | * |
3007 | * Default empty implementation. Replace with an architecture-specific setup | |
3008 | * routine, if necessary. | |
3009 | */ | |
3010 | int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) | |
3011 | { | |
3012 | return 0; | |
3013 | } | |
3014 | ||
10a95747 JL |
3015 | void __weak pcibios_add_bus(struct pci_bus *bus) |
3016 | { | |
3017 | } | |
3018 | ||
3019 | void __weak pcibios_remove_bus(struct pci_bus *bus) | |
3020 | { | |
3021 | } | |
3022 | ||
9ee8a1c4 LP |
3023 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
3024 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
1da177e4 | 3025 | { |
0efd5aab | 3026 | int error; |
5a21d70d | 3027 | struct pci_host_bridge *bridge; |
1da177e4 | 3028 | |
59094065 | 3029 | bridge = pci_alloc_host_bridge(0); |
7b543663 | 3030 | if (!bridge) |
37d6a0a6 | 3031 | return NULL; |
7b543663 YL |
3032 | |
3033 | bridge->dev.parent = parent; | |
a9d9f527 | 3034 | |
37d6a0a6 AB |
3035 | list_splice_init(resources, &bridge->windows); |
3036 | bridge->sysdata = sysdata; | |
3037 | bridge->busnr = bus; | |
3038 | bridge->ops = ops; | |
a9d9f527 | 3039 | |
37d6a0a6 AB |
3040 | error = pci_register_host_bridge(bridge); |
3041 | if (error < 0) | |
3042 | goto err_out; | |
a5390aa6 | 3043 | |
37d6a0a6 | 3044 | return bridge->bus; |
1da177e4 | 3045 | |
1da177e4 | 3046 | err_out: |
9885440b | 3047 | put_device(&bridge->dev); |
1da177e4 LT |
3048 | return NULL; |
3049 | } | |
e6b29dea | 3050 | EXPORT_SYMBOL_GPL(pci_create_root_bus); |
cdb9b9f7 | 3051 | |
49b8e3f3 CP |
3052 | int pci_host_probe(struct pci_host_bridge *bridge) |
3053 | { | |
3054 | struct pci_bus *bus, *child; | |
3055 | int ret; | |
3056 | ||
3057 | ret = pci_scan_root_bus_bridge(bridge); | |
3058 | if (ret < 0) { | |
3059 | dev_err(bridge->dev.parent, "Scanning root bridge failed"); | |
3060 | return ret; | |
3061 | } | |
3062 | ||
3063 | bus = bridge->bus; | |
3064 | ||
3065 | /* | |
3066 | * We insert PCI resources into the iomem_resource and | |
3067 | * ioport_resource trees in either pci_bus_claim_resources() | |
3068 | * or pci_bus_assign_resources(). | |
3069 | */ | |
3070 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
3071 | pci_bus_claim_resources(bus); | |
3072 | } else { | |
3073 | pci_bus_size_bridges(bus); | |
3074 | pci_bus_assign_resources(bus); | |
3075 | ||
3076 | list_for_each_entry(child, &bus->children, node) | |
3077 | pcie_bus_configure_settings(child); | |
3078 | } | |
3079 | ||
3080 | pci_bus_add_devices(bus); | |
3081 | return 0; | |
3082 | } | |
3083 | EXPORT_SYMBOL_GPL(pci_host_probe); | |
3084 | ||
98a35831 YL |
3085 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) |
3086 | { | |
3087 | struct resource *res = &b->busn_res; | |
3088 | struct resource *parent_res, *conflict; | |
3089 | ||
3090 | res->start = bus; | |
3091 | res->end = bus_max; | |
3092 | res->flags = IORESOURCE_BUS; | |
3093 | ||
3094 | if (!pci_is_root_bus(b)) | |
3095 | parent_res = &b->parent->busn_res; | |
3096 | else { | |
3097 | parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); | |
3098 | res->flags |= IORESOURCE_PCI_FIXED; | |
3099 | } | |
3100 | ||
ced04d15 | 3101 | conflict = request_resource_conflict(parent_res, res); |
98a35831 YL |
3102 | |
3103 | if (conflict) | |
34c6b710 | 3104 | dev_info(&b->dev, |
98a35831 YL |
3105 | "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", |
3106 | res, pci_is_root_bus(b) ? "domain " : "", | |
3107 | parent_res, conflict->name, conflict); | |
98a35831 YL |
3108 | |
3109 | return conflict == NULL; | |
3110 | } | |
3111 | ||
3112 | int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) | |
3113 | { | |
3114 | struct resource *res = &b->busn_res; | |
3115 | struct resource old_res = *res; | |
3116 | resource_size_t size; | |
3117 | int ret; | |
3118 | ||
3119 | if (res->start > bus_max) | |
3120 | return -EINVAL; | |
3121 | ||
3122 | size = bus_max - res->start + 1; | |
3123 | ret = adjust_resource(res, res->start, size); | |
34c6b710 | 3124 | dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", |
98a35831 YL |
3125 | &old_res, ret ? "can not be" : "is", bus_max); |
3126 | ||
3127 | if (!ret && !res->parent) | |
3128 | pci_bus_insert_busn_res(b, res->start, res->end); | |
3129 | ||
3130 | return ret; | |
3131 | } | |
3132 | ||
3133 | void pci_bus_release_busn_res(struct pci_bus *b) | |
3134 | { | |
3135 | struct resource *res = &b->busn_res; | |
3136 | int ret; | |
3137 | ||
3138 | if (!res->flags || !res->parent) | |
3139 | return; | |
3140 | ||
3141 | ret = release_resource(res); | |
34c6b710 | 3142 | dev_info(&b->dev, "busn_res: %pR %s released\n", |
98a35831 YL |
3143 | res, ret ? "can not be" : "is"); |
3144 | } | |
3145 | ||
1228c4b6 | 3146 | int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) |
a2ebb827 | 3147 | { |
14d76b68 | 3148 | struct resource_entry *window; |
4d99f524 | 3149 | bool found = false; |
a2ebb827 | 3150 | struct pci_bus *b; |
1228c4b6 | 3151 | int max, bus, ret; |
4d99f524 | 3152 | |
1228c4b6 LP |
3153 | if (!bridge) |
3154 | return -EINVAL; | |
3155 | ||
3156 | resource_list_for_each_entry(window, &bridge->windows) | |
4d99f524 | 3157 | if (window->res->flags & IORESOURCE_BUS) { |
4f5c883d | 3158 | bridge->busnr = window->res->start; |
4d99f524 YL |
3159 | found = true; |
3160 | break; | |
3161 | } | |
a2ebb827 | 3162 | |
1228c4b6 LP |
3163 | ret = pci_register_host_bridge(bridge); |
3164 | if (ret < 0) | |
3165 | return ret; | |
3166 | ||
3167 | b = bridge->bus; | |
3168 | bus = bridge->busnr; | |
a2ebb827 | 3169 | |
4d99f524 YL |
3170 | if (!found) { |
3171 | dev_info(&b->dev, | |
3172 | "No busn resource found for root bus, will use [bus %02x-ff]\n", | |
3173 | bus); | |
3174 | pci_bus_insert_busn_res(b, bus, 255); | |
3175 | } | |
3176 | ||
3177 | max = pci_scan_child_bus(b); | |
3178 | ||
3179 | if (!found) | |
3180 | pci_bus_update_busn_res_end(b, max); | |
3181 | ||
1228c4b6 | 3182 | return 0; |
a2ebb827 | 3183 | } |
1228c4b6 | 3184 | EXPORT_SYMBOL(pci_scan_root_bus_bridge); |
d2a7926d LP |
3185 | |
3186 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, | |
3187 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
3188 | { | |
14d76b68 | 3189 | struct resource_entry *window; |
4d99f524 | 3190 | bool found = false; |
a2ebb827 | 3191 | struct pci_bus *b; |
4d99f524 YL |
3192 | int max; |
3193 | ||
14d76b68 | 3194 | resource_list_for_each_entry(window, resources) |
4d99f524 YL |
3195 | if (window->res->flags & IORESOURCE_BUS) { |
3196 | found = true; | |
3197 | break; | |
3198 | } | |
a2ebb827 | 3199 | |
9ee8a1c4 | 3200 | b = pci_create_root_bus(parent, bus, ops, sysdata, resources); |
a2ebb827 BH |
3201 | if (!b) |
3202 | return NULL; | |
3203 | ||
4d99f524 YL |
3204 | if (!found) { |
3205 | dev_info(&b->dev, | |
3206 | "No busn resource found for root bus, will use [bus %02x-ff]\n", | |
3207 | bus); | |
3208 | pci_bus_insert_busn_res(b, bus, 255); | |
3209 | } | |
3210 | ||
3211 | max = pci_scan_child_bus(b); | |
3212 | ||
3213 | if (!found) | |
3214 | pci_bus_update_busn_res_end(b, max); | |
3215 | ||
a2ebb827 | 3216 | return b; |
d2a7926d | 3217 | } |
a2ebb827 BH |
3218 | EXPORT_SYMBOL(pci_scan_root_bus); |
3219 | ||
15856ad5 | 3220 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, |
de4b2f76 BH |
3221 | void *sysdata) |
3222 | { | |
3223 | LIST_HEAD(resources); | |
3224 | struct pci_bus *b; | |
3225 | ||
3226 | pci_add_resource(&resources, &ioport_resource); | |
3227 | pci_add_resource(&resources, &iomem_resource); | |
857c3b66 | 3228 | pci_add_resource(&resources, &busn_resource); |
de4b2f76 BH |
3229 | b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); |
3230 | if (b) { | |
857c3b66 | 3231 | pci_scan_child_bus(b); |
de4b2f76 BH |
3232 | } else { |
3233 | pci_free_resource_list(&resources); | |
3234 | } | |
3235 | return b; | |
3236 | } | |
3237 | EXPORT_SYMBOL(pci_scan_bus); | |
3238 | ||
2f320521 | 3239 | /** |
3e466e2d | 3240 | * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices |
2f320521 YL |
3241 | * @bridge: PCI bridge for the bus to scan |
3242 | * | |
3243 | * Scan a PCI bus and child buses for new devices, add them, | |
3244 | * and enable them, resizing bridge mmio/io resource if necessary | |
3245 | * and possible. The caller must ensure the child devices are already | |
3246 | * removed for resizing to occur. | |
3247 | * | |
3248 | * Returns the max number of subordinate bus discovered. | |
3249 | */ | |
10874f5a | 3250 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) |
2f320521 YL |
3251 | { |
3252 | unsigned int max; | |
3253 | struct pci_bus *bus = bridge->subordinate; | |
3254 | ||
3255 | max = pci_scan_child_bus(bus); | |
3256 | ||
3257 | pci_assign_unassigned_bridge_resources(bridge); | |
3258 | ||
3259 | pci_bus_add_devices(bus); | |
3260 | ||
3261 | return max; | |
3262 | } | |
3263 | ||
a5213a31 | 3264 | /** |
3e466e2d | 3265 | * pci_rescan_bus - Scan a PCI bus for devices |
a5213a31 YL |
3266 | * @bus: PCI bus to scan |
3267 | * | |
3e466e2d BH |
3268 | * Scan a PCI bus and child buses for new devices, add them, |
3269 | * and enable them. | |
a5213a31 YL |
3270 | * |
3271 | * Returns the max number of subordinate bus discovered. | |
3272 | */ | |
10874f5a | 3273 | unsigned int pci_rescan_bus(struct pci_bus *bus) |
a5213a31 YL |
3274 | { |
3275 | unsigned int max; | |
3276 | ||
3277 | max = pci_scan_child_bus(bus); | |
3278 | pci_assign_unassigned_bus_resources(bus); | |
3279 | pci_bus_add_devices(bus); | |
3280 | ||
3281 | return max; | |
3282 | } | |
3283 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
3284 | ||
9d16947b RW |
3285 | /* |
3286 | * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal | |
3287 | * routines should always be executed under this mutex. | |
3288 | */ | |
3289 | static DEFINE_MUTEX(pci_rescan_remove_lock); | |
3290 | ||
3291 | void pci_lock_rescan_remove(void) | |
3292 | { | |
3293 | mutex_lock(&pci_rescan_remove_lock); | |
3294 | } | |
3295 | EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); | |
3296 | ||
3297 | void pci_unlock_rescan_remove(void) | |
3298 | { | |
3299 | mutex_unlock(&pci_rescan_remove_lock); | |
3300 | } | |
3301 | EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); | |
3302 | ||
3c78bc61 RD |
3303 | static int __init pci_sort_bf_cmp(const struct device *d_a, |
3304 | const struct device *d_b) | |
6b4b78fe | 3305 | { |
99178b03 GKH |
3306 | const struct pci_dev *a = to_pci_dev(d_a); |
3307 | const struct pci_dev *b = to_pci_dev(d_b); | |
3308 | ||
6b4b78fe MD |
3309 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
3310 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
3311 | ||
3312 | if (a->bus->number < b->bus->number) return -1; | |
3313 | else if (a->bus->number > b->bus->number) return 1; | |
3314 | ||
3315 | if (a->devfn < b->devfn) return -1; | |
3316 | else if (a->devfn > b->devfn) return 1; | |
3317 | ||
3318 | return 0; | |
3319 | } | |
3320 | ||
5ff580c1 | 3321 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 3322 | { |
99178b03 | 3323 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 3324 | } |
95e3ba97 MW |
3325 | |
3326 | int pci_hp_add_bridge(struct pci_dev *dev) | |
3327 | { | |
3328 | struct pci_bus *parent = dev->bus; | |
4147c2fd | 3329 | int busnr, start = parent->busn_res.start; |
1c02ea81 | 3330 | unsigned int available_buses = 0; |
95e3ba97 MW |
3331 | int end = parent->busn_res.end; |
3332 | ||
3333 | for (busnr = start; busnr <= end; busnr++) { | |
3334 | if (!pci_find_bus(pci_domain_nr(parent), busnr)) | |
3335 | break; | |
3336 | } | |
3337 | if (busnr-- > end) { | |
7506dc79 | 3338 | pci_err(dev, "No bus number available for hot-added bridge\n"); |
95e3ba97 MW |
3339 | return -1; |
3340 | } | |
4147c2fd MW |
3341 | |
3342 | /* Scan bridges that are already configured */ | |
3343 | busnr = pci_scan_bridge(parent, dev, busnr, 0); | |
3344 | ||
1c02ea81 MW |
3345 | /* |
3346 | * Distribute the available bus numbers between hotplug-capable | |
3347 | * bridges to make extending the chain later possible. | |
3348 | */ | |
3349 | available_buses = end - busnr; | |
3350 | ||
4147c2fd | 3351 | /* Scan bridges that need to be reconfigured */ |
1c02ea81 | 3352 | pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); |
4147c2fd | 3353 | |
95e3ba97 MW |
3354 | if (!dev->subordinate) |
3355 | return -1; | |
3356 | ||
3357 | return 0; | |
3358 | } | |
3359 | EXPORT_SYMBOL_GPL(pci_hp_add_bridge); |