Commit | Line | Data |
---|---|---|
7d715a6c SL |
1 | /* |
2 | * File: drivers/pci/pcie/aspm.c | |
3 | * Enabling PCIE link L0s/L1 state and Clock Power Management | |
4 | * | |
5 | * Copyright (C) 2007 Intel | |
6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | |
7 | * Copyright (C) Shaohua Li (shaohua.li@intel.com) | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/pci_regs.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/slab.h> | |
2a42d9db | 19 | #include <linux/jiffies.h> |
987a4c78 | 20 | #include <linux/delay.h> |
7d715a6c SL |
21 | #include <linux/pci-aspm.h> |
22 | #include "../pci.h" | |
23 | ||
24 | #ifdef MODULE_PARAM_PREFIX | |
25 | #undef MODULE_PARAM_PREFIX | |
26 | #endif | |
27 | #define MODULE_PARAM_PREFIX "pcie_aspm." | |
28 | ||
b6c2e54d KK |
29 | struct aspm_latency { |
30 | u32 l0s; /* L0s latency (nsec) */ | |
31 | u32 l1; /* L1 latency (nsec) */ | |
7d715a6c SL |
32 | }; |
33 | ||
34 | struct pcie_link_state { | |
5cde89d8 KK |
35 | struct pci_dev *pdev; /* Upstream component of the Link */ |
36 | struct pcie_link_state *parent; /* pointer to the parent Link state */ | |
37 | struct list_head sibling; /* node in link_list */ | |
38 | struct list_head children; /* list of child link states */ | |
39 | struct list_head link; /* node in parent's children list */ | |
7d715a6c SL |
40 | |
41 | /* ASPM state */ | |
80bfdbe3 KK |
42 | u32 aspm_support:2; /* Supported ASPM state */ |
43 | u32 aspm_enabled:2; /* Enabled ASPM state */ | |
44 | u32 aspm_default:2; /* Default ASPM state by BIOS */ | |
45 | ||
4d246e45 KK |
46 | /* Clock PM state */ |
47 | u32 clkpm_capable:1; /* Clock PM capable? */ | |
48 | u32 clkpm_enabled:1; /* Current Clock PM state */ | |
49 | u32 clkpm_default:1; /* Default Clock PM state by BIOS */ | |
50 | ||
b6c2e54d KK |
51 | /* Latencies */ |
52 | struct aspm_latency latency; /* Exit latency */ | |
7d715a6c | 53 | /* |
b6c2e54d KK |
54 | * Endpoint acceptable latencies. A pcie downstream port only |
55 | * has one slot under it, so at most there are 8 functions. | |
7d715a6c | 56 | */ |
b6c2e54d | 57 | struct aspm_latency acceptable[8]; |
7d715a6c SL |
58 | }; |
59 | ||
d6d38574 | 60 | static int aspm_disabled, aspm_force; |
7d715a6c SL |
61 | static DEFINE_MUTEX(aspm_lock); |
62 | static LIST_HEAD(link_list); | |
63 | ||
64 | #define POLICY_DEFAULT 0 /* BIOS default setting */ | |
65 | #define POLICY_PERFORMANCE 1 /* high performance */ | |
66 | #define POLICY_POWERSAVE 2 /* high power saving */ | |
67 | static int aspm_policy; | |
68 | static const char *policy_str[] = { | |
69 | [POLICY_DEFAULT] = "default", | |
70 | [POLICY_PERFORMANCE] = "performance", | |
71 | [POLICY_POWERSAVE] = "powersave" | |
72 | }; | |
73 | ||
987a4c78 AP |
74 | #define LINK_RETRAIN_TIMEOUT HZ |
75 | ||
5aa63583 | 76 | static int policy_to_aspm_state(struct pcie_link_state *link) |
7d715a6c | 77 | { |
7d715a6c SL |
78 | switch (aspm_policy) { |
79 | case POLICY_PERFORMANCE: | |
80 | /* Disable ASPM and Clock PM */ | |
81 | return 0; | |
82 | case POLICY_POWERSAVE: | |
83 | /* Enable ASPM L0s/L1 */ | |
80bfdbe3 | 84 | return PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1; |
7d715a6c | 85 | case POLICY_DEFAULT: |
5aa63583 | 86 | return link->aspm_default; |
7d715a6c SL |
87 | } |
88 | return 0; | |
89 | } | |
90 | ||
5aa63583 | 91 | static int policy_to_clkpm_state(struct pcie_link_state *link) |
7d715a6c | 92 | { |
7d715a6c SL |
93 | switch (aspm_policy) { |
94 | case POLICY_PERFORMANCE: | |
95 | /* Disable ASPM and Clock PM */ | |
96 | return 0; | |
97 | case POLICY_POWERSAVE: | |
98 | /* Disable Clock PM */ | |
99 | return 1; | |
100 | case POLICY_DEFAULT: | |
5aa63583 | 101 | return link->clkpm_default; |
7d715a6c SL |
102 | } |
103 | return 0; | |
104 | } | |
105 | ||
430842e2 | 106 | static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) |
7d715a6c | 107 | { |
7d715a6c SL |
108 | int pos; |
109 | u16 reg16; | |
5aa63583 KK |
110 | struct pci_dev *child; |
111 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c | 112 | |
5aa63583 KK |
113 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
114 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
7d715a6c SL |
115 | if (!pos) |
116 | return; | |
5aa63583 | 117 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
118 | if (enable) |
119 | reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
120 | else | |
121 | reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
5aa63583 | 122 | pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 123 | } |
5aa63583 | 124 | link->clkpm_enabled = !!enable; |
7d715a6c SL |
125 | } |
126 | ||
430842e2 KK |
127 | static void pcie_set_clkpm(struct pcie_link_state *link, int enable) |
128 | { | |
129 | /* Don't enable Clock PM if the link is not Clock PM capable */ | |
130 | if (!link->clkpm_capable && enable) | |
131 | return; | |
132 | /* Need nothing if the specified equals to current state */ | |
133 | if (link->clkpm_enabled == enable) | |
134 | return; | |
135 | pcie_set_clkpm_nocheck(link, enable); | |
136 | } | |
137 | ||
8d349ace | 138 | static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 139 | { |
5aa63583 | 140 | int pos, capable = 1, enabled = 1; |
7d715a6c SL |
141 | u32 reg32; |
142 | u16 reg16; | |
5aa63583 KK |
143 | struct pci_dev *child; |
144 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c SL |
145 | |
146 | /* All functions should have the same cap and state, take the worst */ | |
5aa63583 KK |
147 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
148 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
7d715a6c SL |
149 | if (!pos) |
150 | return; | |
5aa63583 | 151 | pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32); |
7d715a6c SL |
152 | if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { |
153 | capable = 0; | |
154 | enabled = 0; | |
155 | break; | |
156 | } | |
5aa63583 | 157 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
158 | if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) |
159 | enabled = 0; | |
160 | } | |
5aa63583 KK |
161 | link->clkpm_enabled = enabled; |
162 | link->clkpm_default = enabled; | |
8d349ace | 163 | link->clkpm_capable = (blacklist) ? 0 : capable; |
46bbdfa4 SL |
164 | } |
165 | ||
5aa63583 | 166 | static bool pcie_aspm_downstream_has_switch(struct pcie_link_state *link) |
46bbdfa4 | 167 | { |
5aa63583 KK |
168 | struct pci_dev *child; |
169 | struct pci_bus *linkbus = link->pdev->subordinate; | |
46bbdfa4 | 170 | |
5aa63583 KK |
171 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
172 | if (child->pcie_type == PCI_EXP_TYPE_UPSTREAM) | |
46bbdfa4 SL |
173 | return true; |
174 | } | |
175 | return false; | |
7d715a6c SL |
176 | } |
177 | ||
178 | /* | |
179 | * pcie_aspm_configure_common_clock: check if the 2 ends of a link | |
180 | * could use common clock. If they are, configure them to use the | |
181 | * common clock. That will reduce the ASPM state exit latency. | |
182 | */ | |
5aa63583 | 183 | static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) |
7d715a6c | 184 | { |
5aa63583 KK |
185 | int ppos, cpos, same_clock = 1; |
186 | u16 reg16, parent_reg, child_reg[8]; | |
2a42d9db | 187 | unsigned long start_jiffies; |
5aa63583 KK |
188 | struct pci_dev *child, *parent = link->pdev; |
189 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 190 | /* |
5aa63583 | 191 | * All functions of a slot should have the same Slot Clock |
7d715a6c | 192 | * Configuration, so just check one function |
5aa63583 KK |
193 | */ |
194 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); | |
195 | BUG_ON(!child->is_pcie); | |
7d715a6c SL |
196 | |
197 | /* Check downstream component if bit Slot Clock Configuration is 1 */ | |
5aa63583 KK |
198 | cpos = pci_find_capability(child, PCI_CAP_ID_EXP); |
199 | pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16); | |
7d715a6c SL |
200 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
201 | same_clock = 0; | |
202 | ||
203 | /* Check upstream component if bit Slot Clock Configuration is 1 */ | |
5aa63583 KK |
204 | ppos = pci_find_capability(parent, PCI_CAP_ID_EXP); |
205 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); | |
7d715a6c SL |
206 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
207 | same_clock = 0; | |
208 | ||
209 | /* Configure downstream component, all functions */ | |
5aa63583 KK |
210 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
211 | cpos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
212 | pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16); | |
213 | child_reg[PCI_FUNC(child->devfn)] = reg16; | |
7d715a6c SL |
214 | if (same_clock) |
215 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
216 | else | |
217 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 218 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16); |
7d715a6c SL |
219 | } |
220 | ||
221 | /* Configure upstream component */ | |
5aa63583 | 222 | pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16); |
2a42d9db | 223 | parent_reg = reg16; |
7d715a6c SL |
224 | if (same_clock) |
225 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
226 | else | |
227 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 228 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 229 | |
5aa63583 | 230 | /* Retrain link */ |
7d715a6c | 231 | reg16 |= PCI_EXP_LNKCTL_RL; |
5aa63583 | 232 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 233 | |
5aa63583 | 234 | /* Wait for link training end. Break out after waiting for timeout */ |
2a42d9db | 235 | start_jiffies = jiffies; |
987a4c78 | 236 | for (;;) { |
5aa63583 | 237 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
238 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
239 | break; | |
987a4c78 AP |
240 | if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
241 | break; | |
242 | msleep(1); | |
7d715a6c | 243 | } |
5aa63583 KK |
244 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
245 | return; | |
246 | ||
247 | /* Training failed. Restore common clock configurations */ | |
248 | dev_printk(KERN_ERR, &parent->dev, | |
249 | "ASPM: Could not configure common clock\n"); | |
250 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
251 | cpos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
252 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, | |
253 | child_reg[PCI_FUNC(child->devfn)]); | |
2a42d9db | 254 | } |
5aa63583 | 255 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg); |
7d715a6c SL |
256 | } |
257 | ||
5e0eaa7d KK |
258 | /* Convert L0s latency encoding to ns */ |
259 | static u32 calc_l0s_latency(u32 encoding) | |
7d715a6c | 260 | { |
5e0eaa7d KK |
261 | if (encoding == 0x7) |
262 | return (5 * 1000); /* > 4us */ | |
263 | return (64 << encoding); | |
264 | } | |
7d715a6c | 265 | |
5e0eaa7d KK |
266 | /* Convert L0s acceptable latency encoding to ns */ |
267 | static u32 calc_l0s_acceptable(u32 encoding) | |
268 | { | |
269 | if (encoding == 0x7) | |
270 | return -1U; | |
271 | return (64 << encoding); | |
7d715a6c SL |
272 | } |
273 | ||
5e0eaa7d KK |
274 | /* Convert L1 latency encoding to ns */ |
275 | static u32 calc_l1_latency(u32 encoding) | |
7d715a6c | 276 | { |
5e0eaa7d KK |
277 | if (encoding == 0x7) |
278 | return (65 * 1000); /* > 64us */ | |
279 | return (1000 << encoding); | |
280 | } | |
7d715a6c | 281 | |
5e0eaa7d KK |
282 | /* Convert L1 acceptable latency encoding to ns */ |
283 | static u32 calc_l1_acceptable(u32 encoding) | |
284 | { | |
285 | if (encoding == 0x7) | |
286 | return -1U; | |
287 | return (1000 << encoding); | |
7d715a6c SL |
288 | } |
289 | ||
290 | static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state, | |
7ab70991 | 291 | u32 *l0s, u32 *l1, u32 *enabled) |
7d715a6c SL |
292 | { |
293 | int pos; | |
294 | u16 reg16; | |
5e0eaa7d | 295 | u32 reg32, encoding; |
7d715a6c | 296 | |
80bfdbe3 | 297 | *l0s = *l1 = *enabled = 0; |
7d715a6c SL |
298 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
299 | pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); | |
300 | *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; | |
301 | if (*state != PCIE_LINK_STATE_L0S && | |
7ab70991 | 302 | *state != (PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_L0S)) |
7d715a6c SL |
303 | *state = 0; |
304 | if (*state == 0) | |
305 | return; | |
306 | ||
5e0eaa7d KK |
307 | encoding = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; |
308 | *l0s = calc_l0s_latency(encoding); | |
7d715a6c | 309 | if (*state & PCIE_LINK_STATE_L1) { |
5e0eaa7d KK |
310 | encoding = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; |
311 | *l1 = calc_l1_latency(encoding); | |
7d715a6c SL |
312 | } |
313 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
7ab70991 | 314 | *enabled = reg16 & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); |
7d715a6c SL |
315 | } |
316 | ||
8d349ace | 317 | static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 318 | { |
80bfdbe3 | 319 | u32 support, l0s, l1, enabled; |
5aa63583 KK |
320 | struct pci_dev *child, *parent = link->pdev; |
321 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 322 | |
8d349ace KK |
323 | if (blacklist) { |
324 | /* Set support state to 0, so we will disable ASPM later */ | |
325 | link->aspm_support = 0; | |
326 | link->aspm_default = 0; | |
327 | link->aspm_enabled = PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1; | |
328 | return; | |
329 | } | |
330 | ||
331 | /* Configure common clock before checking latencies */ | |
332 | pcie_aspm_configure_common_clock(link); | |
333 | ||
7d715a6c | 334 | /* upstream component states */ |
5aa63583 KK |
335 | pcie_aspm_get_cap_device(parent, &support, &l0s, &l1, &enabled); |
336 | link->aspm_support = support; | |
337 | link->latency.l0s = l0s; | |
338 | link->latency.l1 = l1; | |
339 | link->aspm_enabled = enabled; | |
80bfdbe3 | 340 | |
7d715a6c | 341 | /* downstream component states, all functions have the same setting */ |
5aa63583 KK |
342 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); |
343 | pcie_aspm_get_cap_device(child, &support, &l0s, &l1, &enabled); | |
344 | link->aspm_support &= support; | |
345 | link->latency.l0s = max_t(u32, link->latency.l0s, l0s); | |
346 | link->latency.l1 = max_t(u32, link->latency.l1, l1); | |
347 | ||
348 | if (!link->aspm_support) | |
7d715a6c | 349 | return; |
80bfdbe3 | 350 | |
5aa63583 KK |
351 | link->aspm_enabled &= link->aspm_support; |
352 | link->aspm_default = link->aspm_enabled; | |
7d715a6c SL |
353 | |
354 | /* ENDPOINT states*/ | |
5aa63583 | 355 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
7d715a6c | 356 | int pos; |
5e0eaa7d | 357 | u32 reg32, encoding; |
b6c2e54d | 358 | struct aspm_latency *acceptable = |
5aa63583 | 359 | &link->acceptable[PCI_FUNC(child->devfn)]; |
7d715a6c | 360 | |
5aa63583 KK |
361 | if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT && |
362 | child->pcie_type != PCI_EXP_TYPE_LEG_END) | |
7d715a6c SL |
363 | continue; |
364 | ||
5aa63583 KK |
365 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); |
366 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); | |
5e0eaa7d KK |
367 | encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; |
368 | acceptable->l0s = calc_l0s_acceptable(encoding); | |
5aa63583 | 369 | if (link->aspm_support & PCIE_LINK_STATE_L1) { |
5e0eaa7d KK |
370 | encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; |
371 | acceptable->l1 = calc_l1_acceptable(encoding); | |
7d715a6c SL |
372 | } |
373 | } | |
374 | } | |
375 | ||
f7ea3d7f KK |
376 | /** |
377 | * __pcie_aspm_check_state_one - check latency for endpoint device. | |
378 | * @endpoint: pointer to the struct pci_dev of endpoint device | |
379 | * | |
380 | * TBD: The latency from the endpoint to root complex vary per switch's | |
381 | * upstream link state above the device. Here we just do a simple check | |
382 | * which assumes all links above the device can be in L1 state, that | |
383 | * is we just consider the worst case. If switch's upstream link can't | |
384 | * be put into L0S/L1, then our check is too strictly. | |
385 | */ | |
386 | static u32 __pcie_aspm_check_state_one(struct pci_dev *endpoint, u32 state) | |
7d715a6c | 387 | { |
f7ea3d7f | 388 | u32 l1_switch_latency = 0; |
b6c2e54d | 389 | struct aspm_latency *acceptable; |
f7ea3d7f | 390 | struct pcie_link_state *link; |
7d715a6c | 391 | |
f7ea3d7f KK |
392 | link = endpoint->bus->self->link_state; |
393 | state &= link->aspm_support; | |
394 | acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; | |
7d715a6c | 395 | |
f7ea3d7f | 396 | while (link && state) { |
b6c2e54d | 397 | if ((state & PCIE_LINK_STATE_L0S) && |
f7ea3d7f | 398 | (link->latency.l0s > acceptable->l0s)) |
b6c2e54d | 399 | state &= ~PCIE_LINK_STATE_L0S; |
b6c2e54d | 400 | if ((state & PCIE_LINK_STATE_L1) && |
f7ea3d7f | 401 | (link->latency.l1 + l1_switch_latency > acceptable->l1)) |
b6c2e54d | 402 | state &= ~PCIE_LINK_STATE_L1; |
f7ea3d7f KK |
403 | link = link->parent; |
404 | /* | |
405 | * Every switch on the path to root complex need 1 | |
406 | * more microsecond for L1. Spec doesn't mention L0s. | |
407 | */ | |
408 | l1_switch_latency += 1000; | |
7d715a6c SL |
409 | } |
410 | return state; | |
411 | } | |
412 | ||
5aa63583 | 413 | static u32 pcie_aspm_check_state(struct pcie_link_state *link, u32 state) |
7d715a6c | 414 | { |
5aa63583 KK |
415 | pci_power_t power_state; |
416 | struct pci_dev *child; | |
417 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c | 418 | |
46bbdfa4 | 419 | /* If no child, ignore the link */ |
5aa63583 | 420 | if (list_empty(&linkbus->devices)) |
46bbdfa4 | 421 | return state; |
5aa63583 KK |
422 | |
423 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
424 | /* | |
425 | * If downstream component of a link is pci bridge, we | |
426 | * disable ASPM for now for the link | |
427 | */ | |
428 | if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) | |
429 | return 0; | |
430 | ||
431 | if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT && | |
432 | child->pcie_type != PCI_EXP_TYPE_LEG_END)) | |
7d715a6c SL |
433 | continue; |
434 | /* Device not in D0 doesn't need check latency */ | |
5aa63583 KK |
435 | power_state = child->current_state; |
436 | if (power_state == PCI_D1 || power_state == PCI_D2 || | |
437 | power_state == PCI_D3hot || power_state == PCI_D3cold) | |
7d715a6c | 438 | continue; |
5aa63583 | 439 | state = __pcie_aspm_check_state_one(child, state); |
7d715a6c SL |
440 | } |
441 | return state; | |
442 | } | |
443 | ||
444 | static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state) | |
445 | { | |
446 | u16 reg16; | |
447 | int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
448 | ||
449 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
450 | reg16 &= ~0x3; | |
451 | reg16 |= state; | |
452 | pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); | |
453 | } | |
454 | ||
5aa63583 | 455 | static void __pcie_aspm_config_link(struct pcie_link_state *link, u32 state) |
7d715a6c | 456 | { |
5aa63583 KK |
457 | struct pci_dev *child, *parent = link->pdev; |
458 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 459 | |
46bbdfa4 | 460 | /* If no child, disable the link */ |
5aa63583 | 461 | if (list_empty(&linkbus->devices)) |
46bbdfa4 | 462 | state = 0; |
7d715a6c | 463 | /* |
5aa63583 KK |
464 | * If the downstream component has pci bridge function, don't |
465 | * do ASPM now. | |
7d715a6c | 466 | */ |
5aa63583 KK |
467 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
468 | if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) | |
469 | return; | |
7d715a6c | 470 | } |
7d715a6c | 471 | /* |
5aa63583 KK |
472 | * Spec 2.0 suggests all functions should be configured the |
473 | * same setting for ASPM. Enabling ASPM L1 should be done in | |
474 | * upstream component first and then downstream, and vice | |
475 | * versa for disabling ASPM L1. Spec doesn't mention L0S. | |
7d715a6c SL |
476 | */ |
477 | if (state & PCIE_LINK_STATE_L1) | |
5aa63583 | 478 | __pcie_aspm_config_one_dev(parent, state); |
7d715a6c | 479 | |
5aa63583 KK |
480 | list_for_each_entry(child, &linkbus->devices, bus_list) |
481 | __pcie_aspm_config_one_dev(child, state); | |
7d715a6c SL |
482 | |
483 | if (!(state & PCIE_LINK_STATE_L1)) | |
5aa63583 | 484 | __pcie_aspm_config_one_dev(parent, state); |
7d715a6c | 485 | |
5aa63583 | 486 | link->aspm_enabled = state; |
7d715a6c SL |
487 | } |
488 | ||
46bbdfa4 SL |
489 | static struct pcie_link_state *get_root_port_link(struct pcie_link_state *link) |
490 | { | |
491 | struct pcie_link_state *root_port_link = link; | |
492 | while (root_port_link->parent) | |
493 | root_port_link = root_port_link->parent; | |
494 | return root_port_link; | |
495 | } | |
496 | ||
5aa63583 KK |
497 | /* Check the whole hierarchy, and configure each link in the hierarchy */ |
498 | static void __pcie_aspm_configure_link_state(struct pcie_link_state *link, | |
499 | u32 state) | |
7d715a6c | 500 | { |
5aa63583 | 501 | struct pcie_link_state *leaf, *root = get_root_port_link(link); |
7d715a6c | 502 | |
5aa63583 | 503 | state &= (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); |
7d715a6c | 504 | |
5aa63583 | 505 | /* Check all links who have specific root port link */ |
dc64cd11 | 506 | list_for_each_entry(leaf, &link_list, sibling) { |
46bbdfa4 | 507 | if (!list_empty(&leaf->children) || |
5aa63583 | 508 | get_root_port_link(leaf) != root) |
46bbdfa4 | 509 | continue; |
5aa63583 | 510 | state = pcie_aspm_check_state(leaf, state); |
46bbdfa4 | 511 | } |
5aa63583 KK |
512 | /* Check root port link too in case it hasn't children */ |
513 | state = pcie_aspm_check_state(root, state); | |
514 | if (link->aspm_enabled == state) | |
7d715a6c | 515 | return; |
46bbdfa4 | 516 | /* |
5aa63583 | 517 | * We must change the hierarchy. See comments in |
46bbdfa4 SL |
518 | * __pcie_aspm_config_link for the order |
519 | **/ | |
520 | if (state & PCIE_LINK_STATE_L1) { | |
dc64cd11 | 521 | list_for_each_entry(leaf, &link_list, sibling) { |
5aa63583 KK |
522 | if (get_root_port_link(leaf) == root) |
523 | __pcie_aspm_config_link(leaf, state); | |
46bbdfa4 SL |
524 | } |
525 | } else { | |
dc64cd11 | 526 | list_for_each_entry_reverse(leaf, &link_list, sibling) { |
5aa63583 KK |
527 | if (get_root_port_link(leaf) == root) |
528 | __pcie_aspm_config_link(leaf, state); | |
46bbdfa4 SL |
529 | } |
530 | } | |
7d715a6c SL |
531 | } |
532 | ||
533 | /* | |
534 | * pcie_aspm_configure_link_state: enable/disable PCI express link state | |
535 | * @pdev: the root port or switch downstream port | |
536 | */ | |
5aa63583 KK |
537 | static void pcie_aspm_configure_link_state(struct pcie_link_state *link, |
538 | u32 state) | |
7d715a6c SL |
539 | { |
540 | down_read(&pci_bus_sem); | |
541 | mutex_lock(&aspm_lock); | |
5aa63583 | 542 | __pcie_aspm_configure_link_state(link, state); |
7d715a6c SL |
543 | mutex_unlock(&aspm_lock); |
544 | up_read(&pci_bus_sem); | |
545 | } | |
546 | ||
5aa63583 | 547 | static void free_link_state(struct pcie_link_state *link) |
7d715a6c | 548 | { |
5aa63583 KK |
549 | link->pdev->link_state = NULL; |
550 | kfree(link); | |
7d715a6c SL |
551 | } |
552 | ||
ddc9753f SL |
553 | static int pcie_aspm_sanity_check(struct pci_dev *pdev) |
554 | { | |
3647584d KK |
555 | struct pci_dev *child; |
556 | int pos; | |
149e1637 | 557 | u32 reg32; |
ddc9753f | 558 | /* |
3647584d KK |
559 | * Some functions in a slot might not all be PCIE functions, |
560 | * very strange. Disable ASPM for the whole slot | |
ddc9753f | 561 | */ |
3647584d KK |
562 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
563 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
564 | if (!pos) | |
ddc9753f | 565 | return -EINVAL; |
149e1637 SL |
566 | /* |
567 | * Disable ASPM for pre-1.1 PCIe device, we follow MS to use | |
568 | * RBER bit to determine if a function is 1.1 version device | |
569 | */ | |
3647584d | 570 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); |
e1f4f59d | 571 | if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { |
3647584d | 572 | dev_printk(KERN_INFO, &child->dev, "disabling ASPM" |
f393d9b1 VL |
573 | " on pre-1.1 PCIe device. You can enable it" |
574 | " with 'pcie_aspm=force'\n"); | |
149e1637 SL |
575 | return -EINVAL; |
576 | } | |
ddc9753f SL |
577 | } |
578 | return 0; | |
579 | } | |
580 | ||
8d349ace KK |
581 | static struct pcie_link_state *pcie_aspm_setup_link_state(struct pci_dev *pdev) |
582 | { | |
583 | struct pcie_link_state *link; | |
584 | int blacklist = !!pcie_aspm_sanity_check(pdev); | |
585 | ||
586 | link = kzalloc(sizeof(*link), GFP_KERNEL); | |
587 | if (!link) | |
588 | return NULL; | |
589 | INIT_LIST_HEAD(&link->sibling); | |
590 | INIT_LIST_HEAD(&link->children); | |
591 | INIT_LIST_HEAD(&link->link); | |
592 | link->pdev = pdev; | |
8d349ace KK |
593 | if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) { |
594 | struct pcie_link_state *parent; | |
595 | parent = pdev->bus->parent->self->link_state; | |
596 | if (!parent) { | |
597 | kfree(link); | |
598 | return NULL; | |
599 | } | |
600 | link->parent = parent; | |
601 | list_add(&link->link, &parent->children); | |
602 | } | |
603 | list_add(&link->sibling, &link_list); | |
604 | ||
605 | pdev->link_state = link; | |
606 | ||
607 | /* Check ASPM capability */ | |
608 | pcie_aspm_cap_init(link, blacklist); | |
609 | ||
610 | /* Check Clock PM capability */ | |
611 | pcie_clkpm_cap_init(link, blacklist); | |
612 | ||
613 | return link; | |
614 | } | |
615 | ||
7d715a6c SL |
616 | /* |
617 | * pcie_aspm_init_link_state: Initiate PCI express link state. | |
618 | * It is called after the pcie and its children devices are scaned. | |
619 | * @pdev: the root port or switch downstream port | |
620 | */ | |
621 | void pcie_aspm_init_link_state(struct pci_dev *pdev) | |
622 | { | |
8d349ace KK |
623 | u32 state; |
624 | struct pcie_link_state *link; | |
7d715a6c SL |
625 | |
626 | if (aspm_disabled || !pdev->is_pcie || pdev->link_state) | |
627 | return; | |
628 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 629 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) |
7d715a6c | 630 | return; |
8d349ace | 631 | |
8e822df7 SL |
632 | /* VIA has a strange chipset, root port is under a bridge */ |
633 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 634 | pdev->bus->self) |
8e822df7 | 635 | return; |
8d349ace | 636 | |
7d715a6c SL |
637 | down_read(&pci_bus_sem); |
638 | if (list_empty(&pdev->subordinate->devices)) | |
639 | goto out; | |
640 | ||
641 | mutex_lock(&aspm_lock); | |
8d349ace KK |
642 | link = pcie_aspm_setup_link_state(pdev); |
643 | if (!link) | |
644 | goto unlock; | |
645 | /* | |
646 | * Setup initial ASPM state | |
647 | * | |
648 | * If link has switch, delay the link config. The leaf link | |
649 | * initialization will config the whole hierarchy. But we must | |
650 | * make sure BIOS doesn't set unsupported link state. | |
651 | */ | |
efdf8288 | 652 | if (pcie_aspm_downstream_has_switch(link)) { |
8d349ace KK |
653 | state = pcie_aspm_check_state(link, link->aspm_default); |
654 | __pcie_aspm_config_link(link, state); | |
46bbdfa4 | 655 | } else { |
8d349ace KK |
656 | state = policy_to_aspm_state(link); |
657 | __pcie_aspm_configure_link_state(link, state); | |
46bbdfa4 | 658 | } |
7d715a6c | 659 | |
8d349ace KK |
660 | /* Setup initial Clock PM state */ |
661 | state = (link->clkpm_capable) ? policy_to_clkpm_state(link) : 0; | |
430842e2 | 662 | pcie_set_clkpm(link, state); |
8d349ace | 663 | unlock: |
7d715a6c SL |
664 | mutex_unlock(&aspm_lock); |
665 | out: | |
666 | up_read(&pci_bus_sem); | |
667 | } | |
668 | ||
669 | /* @pdev: the endpoint device */ | |
670 | void pcie_aspm_exit_link_state(struct pci_dev *pdev) | |
671 | { | |
672 | struct pci_dev *parent = pdev->bus->self; | |
673 | struct pcie_link_state *link_state = parent->link_state; | |
674 | ||
675 | if (aspm_disabled || !pdev->is_pcie || !parent || !link_state) | |
676 | return; | |
677 | if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
678 | parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) | |
679 | return; | |
680 | down_read(&pci_bus_sem); | |
681 | mutex_lock(&aspm_lock); | |
682 | ||
683 | /* | |
684 | * All PCIe functions are in one slot, remove one function will remove | |
3419c75e | 685 | * the whole slot, so just wait until we are the last function left. |
7d715a6c | 686 | */ |
3419c75e | 687 | if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices)) |
7d715a6c SL |
688 | goto out; |
689 | ||
690 | /* All functions are removed, so just disable ASPM for the link */ | |
691 | __pcie_aspm_config_one_dev(parent, 0); | |
dc64cd11 | 692 | list_del(&link_state->sibling); |
46bbdfa4 | 693 | list_del(&link_state->link); |
7d715a6c SL |
694 | /* Clock PM is for endpoint device */ |
695 | ||
5aa63583 | 696 | free_link_state(link_state); |
7d715a6c SL |
697 | out: |
698 | mutex_unlock(&aspm_lock); | |
699 | up_read(&pci_bus_sem); | |
700 | } | |
701 | ||
702 | /* @pdev: the root port or switch downstream port */ | |
703 | void pcie_aspm_pm_state_change(struct pci_dev *pdev) | |
704 | { | |
705 | struct pcie_link_state *link_state = pdev->link_state; | |
706 | ||
707 | if (aspm_disabled || !pdev->is_pcie || !pdev->link_state) | |
708 | return; | |
709 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
710 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) | |
711 | return; | |
712 | /* | |
713 | * devices changed PM state, we should recheck if latency meets all | |
714 | * functions' requirement | |
715 | */ | |
5aa63583 | 716 | pcie_aspm_configure_link_state(link_state, link_state->aspm_enabled); |
7d715a6c SL |
717 | } |
718 | ||
719 | /* | |
720 | * pci_disable_link_state - disable pci device's link state, so the link will | |
721 | * never enter specific states | |
722 | */ | |
723 | void pci_disable_link_state(struct pci_dev *pdev, int state) | |
724 | { | |
725 | struct pci_dev *parent = pdev->bus->self; | |
726 | struct pcie_link_state *link_state; | |
727 | ||
728 | if (aspm_disabled || !pdev->is_pcie) | |
729 | return; | |
730 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
731 | pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) | |
732 | parent = pdev; | |
733 | if (!parent || !parent->link_state) | |
734 | return; | |
735 | ||
736 | down_read(&pci_bus_sem); | |
737 | mutex_lock(&aspm_lock); | |
738 | link_state = parent->link_state; | |
80bfdbe3 | 739 | link_state->aspm_support &= ~state; |
5aa63583 | 740 | __pcie_aspm_configure_link_state(link_state, link_state->aspm_enabled); |
430842e2 KK |
741 | if (state & PCIE_LINK_STATE_CLKPM) { |
742 | link_state->clkpm_capable = 0; | |
743 | pcie_set_clkpm(link_state, 0); | |
744 | } | |
7d715a6c SL |
745 | mutex_unlock(&aspm_lock); |
746 | up_read(&pci_bus_sem); | |
747 | } | |
748 | EXPORT_SYMBOL(pci_disable_link_state); | |
749 | ||
750 | static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) | |
751 | { | |
752 | int i; | |
7d715a6c SL |
753 | struct pcie_link_state *link_state; |
754 | ||
755 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
756 | if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) | |
757 | break; | |
758 | if (i >= ARRAY_SIZE(policy_str)) | |
759 | return -EINVAL; | |
760 | if (i == aspm_policy) | |
761 | return 0; | |
762 | ||
763 | down_read(&pci_bus_sem); | |
764 | mutex_lock(&aspm_lock); | |
765 | aspm_policy = i; | |
dc64cd11 | 766 | list_for_each_entry(link_state, &link_list, sibling) { |
5aa63583 KK |
767 | __pcie_aspm_configure_link_state(link_state, |
768 | policy_to_aspm_state(link_state)); | |
430842e2 | 769 | pcie_set_clkpm(link_state, policy_to_clkpm_state(link_state)); |
7d715a6c SL |
770 | } |
771 | mutex_unlock(&aspm_lock); | |
772 | up_read(&pci_bus_sem); | |
773 | return 0; | |
774 | } | |
775 | ||
776 | static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) | |
777 | { | |
778 | int i, cnt = 0; | |
779 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
780 | if (i == aspm_policy) | |
781 | cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); | |
782 | else | |
783 | cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); | |
784 | return cnt; | |
785 | } | |
786 | ||
787 | module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, | |
788 | NULL, 0644); | |
789 | ||
790 | #ifdef CONFIG_PCIEASPM_DEBUG | |
791 | static ssize_t link_state_show(struct device *dev, | |
792 | struct device_attribute *attr, | |
793 | char *buf) | |
794 | { | |
795 | struct pci_dev *pci_device = to_pci_dev(dev); | |
796 | struct pcie_link_state *link_state = pci_device->link_state; | |
797 | ||
80bfdbe3 | 798 | return sprintf(buf, "%d\n", link_state->aspm_enabled); |
7d715a6c SL |
799 | } |
800 | ||
801 | static ssize_t link_state_store(struct device *dev, | |
802 | struct device_attribute *attr, | |
803 | const char *buf, | |
804 | size_t n) | |
805 | { | |
5aa63583 | 806 | struct pci_dev *pdev = to_pci_dev(dev); |
7d715a6c SL |
807 | int state; |
808 | ||
809 | if (n < 1) | |
810 | return -EINVAL; | |
811 | state = buf[0]-'0'; | |
812 | if (state >= 0 && state <= 3) { | |
813 | /* setup link aspm state */ | |
5aa63583 | 814 | pcie_aspm_configure_link_state(pdev->link_state, state); |
7d715a6c SL |
815 | return n; |
816 | } | |
817 | ||
818 | return -EINVAL; | |
819 | } | |
820 | ||
821 | static ssize_t clk_ctl_show(struct device *dev, | |
822 | struct device_attribute *attr, | |
823 | char *buf) | |
824 | { | |
825 | struct pci_dev *pci_device = to_pci_dev(dev); | |
826 | struct pcie_link_state *link_state = pci_device->link_state; | |
827 | ||
4d246e45 | 828 | return sprintf(buf, "%d\n", link_state->clkpm_enabled); |
7d715a6c SL |
829 | } |
830 | ||
831 | static ssize_t clk_ctl_store(struct device *dev, | |
832 | struct device_attribute *attr, | |
833 | const char *buf, | |
834 | size_t n) | |
835 | { | |
430842e2 | 836 | struct pci_dev *pdev = to_pci_dev(dev); |
7d715a6c SL |
837 | int state; |
838 | ||
839 | if (n < 1) | |
840 | return -EINVAL; | |
841 | state = buf[0]-'0'; | |
842 | ||
843 | down_read(&pci_bus_sem); | |
844 | mutex_lock(&aspm_lock); | |
430842e2 | 845 | pcie_set_clkpm_nocheck(pdev->link_state, !!state); |
7d715a6c SL |
846 | mutex_unlock(&aspm_lock); |
847 | up_read(&pci_bus_sem); | |
848 | ||
849 | return n; | |
850 | } | |
851 | ||
852 | static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store); | |
853 | static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store); | |
854 | ||
855 | static char power_group[] = "power"; | |
856 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | |
857 | { | |
858 | struct pcie_link_state *link_state = pdev->link_state; | |
859 | ||
860 | if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
861 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
862 | return; | |
863 | ||
80bfdbe3 | 864 | if (link_state->aspm_support) |
7d715a6c SL |
865 | sysfs_add_file_to_group(&pdev->dev.kobj, |
866 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 867 | if (link_state->clkpm_capable) |
7d715a6c SL |
868 | sysfs_add_file_to_group(&pdev->dev.kobj, |
869 | &dev_attr_clk_ctl.attr, power_group); | |
870 | } | |
871 | ||
872 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | |
873 | { | |
874 | struct pcie_link_state *link_state = pdev->link_state; | |
875 | ||
876 | if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
877 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
878 | return; | |
879 | ||
80bfdbe3 | 880 | if (link_state->aspm_support) |
7d715a6c SL |
881 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
882 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 883 | if (link_state->clkpm_capable) |
7d715a6c SL |
884 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
885 | &dev_attr_clk_ctl.attr, power_group); | |
886 | } | |
887 | #endif | |
888 | ||
889 | static int __init pcie_aspm_disable(char *str) | |
890 | { | |
d6d38574 SL |
891 | if (!strcmp(str, "off")) { |
892 | aspm_disabled = 1; | |
893 | printk(KERN_INFO "PCIe ASPM is disabled\n"); | |
894 | } else if (!strcmp(str, "force")) { | |
895 | aspm_force = 1; | |
896 | printk(KERN_INFO "PCIe ASPM is forcedly enabled\n"); | |
897 | } | |
7d715a6c SL |
898 | return 1; |
899 | } | |
900 | ||
d6d38574 | 901 | __setup("pcie_aspm=", pcie_aspm_disable); |
7d715a6c | 902 | |
5fde244d SL |
903 | void pcie_no_aspm(void) |
904 | { | |
d6d38574 SL |
905 | if (!aspm_force) |
906 | aspm_disabled = 1; | |
5fde244d SL |
907 | } |
908 | ||
3e1b1600 AP |
909 | /** |
910 | * pcie_aspm_enabled - is PCIe ASPM enabled? | |
911 | * | |
912 | * Returns true if ASPM has not been disabled by the command-line option | |
913 | * pcie_aspm=off. | |
914 | **/ | |
915 | int pcie_aspm_enabled(void) | |
7d715a6c | 916 | { |
3e1b1600 | 917 | return !aspm_disabled; |
7d715a6c | 918 | } |
3e1b1600 | 919 | EXPORT_SYMBOL(pcie_aspm_enabled); |
7d715a6c | 920 |