Commit | Line | Data |
---|---|---|
7d715a6c SL |
1 | /* |
2 | * File: drivers/pci/pcie/aspm.c | |
45e829ea | 3 | * Enabling PCIe link L0s/L1 state and Clock Power Management |
7d715a6c SL |
4 | * |
5 | * Copyright (C) 2007 Intel | |
6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | |
7 | * Copyright (C) Shaohua Li (shaohua.li@intel.com) | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/pci_regs.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/slab.h> | |
2a42d9db | 19 | #include <linux/jiffies.h> |
987a4c78 | 20 | #include <linux/delay.h> |
7d715a6c SL |
21 | #include <linux/pci-aspm.h> |
22 | #include "../pci.h" | |
23 | ||
24 | #ifdef MODULE_PARAM_PREFIX | |
25 | #undef MODULE_PARAM_PREFIX | |
26 | #endif | |
27 | #define MODULE_PARAM_PREFIX "pcie_aspm." | |
28 | ||
ac18018a KK |
29 | /* Note: those are not register definitions */ |
30 | #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */ | |
31 | #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */ | |
32 | #define ASPM_STATE_L1 (4) /* L1 state */ | |
33 | #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW) | |
34 | #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1) | |
35 | ||
b6c2e54d KK |
36 | struct aspm_latency { |
37 | u32 l0s; /* L0s latency (nsec) */ | |
38 | u32 l1; /* L1 latency (nsec) */ | |
7d715a6c SL |
39 | }; |
40 | ||
41 | struct pcie_link_state { | |
5cde89d8 | 42 | struct pci_dev *pdev; /* Upstream component of the Link */ |
5c92ffb1 | 43 | struct pcie_link_state *root; /* pointer to the root port link */ |
5cde89d8 KK |
44 | struct pcie_link_state *parent; /* pointer to the parent Link state */ |
45 | struct list_head sibling; /* node in link_list */ | |
46 | struct list_head children; /* list of child link states */ | |
47 | struct list_head link; /* node in parent's children list */ | |
7d715a6c SL |
48 | |
49 | /* ASPM state */ | |
ac18018a KK |
50 | u32 aspm_support:3; /* Supported ASPM state */ |
51 | u32 aspm_enabled:3; /* Enabled ASPM state */ | |
52 | u32 aspm_capable:3; /* Capable ASPM state with latency */ | |
53 | u32 aspm_default:3; /* Default ASPM state by BIOS */ | |
54 | u32 aspm_disable:3; /* Disabled ASPM state */ | |
80bfdbe3 | 55 | |
4d246e45 KK |
56 | /* Clock PM state */ |
57 | u32 clkpm_capable:1; /* Clock PM capable? */ | |
58 | u32 clkpm_enabled:1; /* Current Clock PM state */ | |
59 | u32 clkpm_default:1; /* Default Clock PM state by BIOS */ | |
60 | ||
ac18018a KK |
61 | /* Exit latencies */ |
62 | struct aspm_latency latency_up; /* Upstream direction exit latency */ | |
63 | struct aspm_latency latency_dw; /* Downstream direction exit latency */ | |
7d715a6c | 64 | /* |
b6c2e54d KK |
65 | * Endpoint acceptable latencies. A pcie downstream port only |
66 | * has one slot under it, so at most there are 8 functions. | |
7d715a6c | 67 | */ |
b6c2e54d | 68 | struct aspm_latency acceptable[8]; |
7d715a6c SL |
69 | }; |
70 | ||
2f671e2d | 71 | static int aspm_disabled, aspm_force, aspm_clear_state; |
7d715a6c SL |
72 | static DEFINE_MUTEX(aspm_lock); |
73 | static LIST_HEAD(link_list); | |
74 | ||
75 | #define POLICY_DEFAULT 0 /* BIOS default setting */ | |
76 | #define POLICY_PERFORMANCE 1 /* high performance */ | |
77 | #define POLICY_POWERSAVE 2 /* high power saving */ | |
78 | static int aspm_policy; | |
79 | static const char *policy_str[] = { | |
80 | [POLICY_DEFAULT] = "default", | |
81 | [POLICY_PERFORMANCE] = "performance", | |
82 | [POLICY_POWERSAVE] = "powersave" | |
83 | }; | |
84 | ||
987a4c78 AP |
85 | #define LINK_RETRAIN_TIMEOUT HZ |
86 | ||
5aa63583 | 87 | static int policy_to_aspm_state(struct pcie_link_state *link) |
7d715a6c | 88 | { |
7d715a6c SL |
89 | switch (aspm_policy) { |
90 | case POLICY_PERFORMANCE: | |
91 | /* Disable ASPM and Clock PM */ | |
92 | return 0; | |
93 | case POLICY_POWERSAVE: | |
94 | /* Enable ASPM L0s/L1 */ | |
ac18018a | 95 | return ASPM_STATE_ALL; |
7d715a6c | 96 | case POLICY_DEFAULT: |
5aa63583 | 97 | return link->aspm_default; |
7d715a6c SL |
98 | } |
99 | return 0; | |
100 | } | |
101 | ||
5aa63583 | 102 | static int policy_to_clkpm_state(struct pcie_link_state *link) |
7d715a6c | 103 | { |
7d715a6c SL |
104 | switch (aspm_policy) { |
105 | case POLICY_PERFORMANCE: | |
106 | /* Disable ASPM and Clock PM */ | |
107 | return 0; | |
108 | case POLICY_POWERSAVE: | |
109 | /* Disable Clock PM */ | |
110 | return 1; | |
111 | case POLICY_DEFAULT: | |
5aa63583 | 112 | return link->clkpm_default; |
7d715a6c SL |
113 | } |
114 | return 0; | |
115 | } | |
116 | ||
430842e2 | 117 | static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) |
7d715a6c | 118 | { |
7d715a6c SL |
119 | int pos; |
120 | u16 reg16; | |
5aa63583 KK |
121 | struct pci_dev *child; |
122 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c | 123 | |
5aa63583 | 124 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
db9538a7 | 125 | pos = pci_pcie_cap(child); |
7d715a6c SL |
126 | if (!pos) |
127 | return; | |
5aa63583 | 128 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
129 | if (enable) |
130 | reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
131 | else | |
132 | reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
5aa63583 | 133 | pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 134 | } |
5aa63583 | 135 | link->clkpm_enabled = !!enable; |
7d715a6c SL |
136 | } |
137 | ||
430842e2 KK |
138 | static void pcie_set_clkpm(struct pcie_link_state *link, int enable) |
139 | { | |
140 | /* Don't enable Clock PM if the link is not Clock PM capable */ | |
141 | if (!link->clkpm_capable && enable) | |
2f671e2d | 142 | enable = 0; |
430842e2 KK |
143 | /* Need nothing if the specified equals to current state */ |
144 | if (link->clkpm_enabled == enable) | |
145 | return; | |
146 | pcie_set_clkpm_nocheck(link, enable); | |
147 | } | |
148 | ||
8d349ace | 149 | static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 150 | { |
5aa63583 | 151 | int pos, capable = 1, enabled = 1; |
7d715a6c SL |
152 | u32 reg32; |
153 | u16 reg16; | |
5aa63583 KK |
154 | struct pci_dev *child; |
155 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c SL |
156 | |
157 | /* All functions should have the same cap and state, take the worst */ | |
5aa63583 | 158 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
db9538a7 | 159 | pos = pci_pcie_cap(child); |
7d715a6c SL |
160 | if (!pos) |
161 | return; | |
5aa63583 | 162 | pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32); |
7d715a6c SL |
163 | if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { |
164 | capable = 0; | |
165 | enabled = 0; | |
166 | break; | |
167 | } | |
5aa63583 | 168 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
169 | if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) |
170 | enabled = 0; | |
171 | } | |
5aa63583 KK |
172 | link->clkpm_enabled = enabled; |
173 | link->clkpm_default = enabled; | |
8d349ace | 174 | link->clkpm_capable = (blacklist) ? 0 : capable; |
46bbdfa4 SL |
175 | } |
176 | ||
7d715a6c SL |
177 | /* |
178 | * pcie_aspm_configure_common_clock: check if the 2 ends of a link | |
179 | * could use common clock. If they are, configure them to use the | |
180 | * common clock. That will reduce the ASPM state exit latency. | |
181 | */ | |
5aa63583 | 182 | static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) |
7d715a6c | 183 | { |
5aa63583 KK |
184 | int ppos, cpos, same_clock = 1; |
185 | u16 reg16, parent_reg, child_reg[8]; | |
2a42d9db | 186 | unsigned long start_jiffies; |
5aa63583 KK |
187 | struct pci_dev *child, *parent = link->pdev; |
188 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 189 | /* |
5aa63583 | 190 | * All functions of a slot should have the same Slot Clock |
7d715a6c | 191 | * Configuration, so just check one function |
5aa63583 KK |
192 | */ |
193 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); | |
8b06477d | 194 | BUG_ON(!pci_is_pcie(child)); |
7d715a6c SL |
195 | |
196 | /* Check downstream component if bit Slot Clock Configuration is 1 */ | |
db9538a7 | 197 | cpos = pci_pcie_cap(child); |
5aa63583 | 198 | pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
199 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
200 | same_clock = 0; | |
201 | ||
202 | /* Check upstream component if bit Slot Clock Configuration is 1 */ | |
db9538a7 | 203 | ppos = pci_pcie_cap(parent); |
5aa63583 | 204 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
205 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
206 | same_clock = 0; | |
207 | ||
208 | /* Configure downstream component, all functions */ | |
5aa63583 | 209 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
db9538a7 | 210 | cpos = pci_pcie_cap(child); |
5aa63583 KK |
211 | pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16); |
212 | child_reg[PCI_FUNC(child->devfn)] = reg16; | |
7d715a6c SL |
213 | if (same_clock) |
214 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
215 | else | |
216 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 217 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16); |
7d715a6c SL |
218 | } |
219 | ||
220 | /* Configure upstream component */ | |
5aa63583 | 221 | pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16); |
2a42d9db | 222 | parent_reg = reg16; |
7d715a6c SL |
223 | if (same_clock) |
224 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
225 | else | |
226 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 227 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 228 | |
5aa63583 | 229 | /* Retrain link */ |
7d715a6c | 230 | reg16 |= PCI_EXP_LNKCTL_RL; |
5aa63583 | 231 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 232 | |
5aa63583 | 233 | /* Wait for link training end. Break out after waiting for timeout */ |
2a42d9db | 234 | start_jiffies = jiffies; |
987a4c78 | 235 | for (;;) { |
5aa63583 | 236 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
237 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
238 | break; | |
987a4c78 AP |
239 | if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
240 | break; | |
241 | msleep(1); | |
7d715a6c | 242 | } |
5aa63583 KK |
243 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
244 | return; | |
245 | ||
246 | /* Training failed. Restore common clock configurations */ | |
247 | dev_printk(KERN_ERR, &parent->dev, | |
248 | "ASPM: Could not configure common clock\n"); | |
249 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
db9538a7 | 250 | cpos = pci_pcie_cap(child); |
5aa63583 KK |
251 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, |
252 | child_reg[PCI_FUNC(child->devfn)]); | |
2a42d9db | 253 | } |
5aa63583 | 254 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg); |
7d715a6c SL |
255 | } |
256 | ||
5e0eaa7d KK |
257 | /* Convert L0s latency encoding to ns */ |
258 | static u32 calc_l0s_latency(u32 encoding) | |
7d715a6c | 259 | { |
5e0eaa7d KK |
260 | if (encoding == 0x7) |
261 | return (5 * 1000); /* > 4us */ | |
262 | return (64 << encoding); | |
263 | } | |
7d715a6c | 264 | |
5e0eaa7d KK |
265 | /* Convert L0s acceptable latency encoding to ns */ |
266 | static u32 calc_l0s_acceptable(u32 encoding) | |
267 | { | |
268 | if (encoding == 0x7) | |
269 | return -1U; | |
270 | return (64 << encoding); | |
7d715a6c SL |
271 | } |
272 | ||
5e0eaa7d KK |
273 | /* Convert L1 latency encoding to ns */ |
274 | static u32 calc_l1_latency(u32 encoding) | |
7d715a6c | 275 | { |
5e0eaa7d KK |
276 | if (encoding == 0x7) |
277 | return (65 * 1000); /* > 64us */ | |
278 | return (1000 << encoding); | |
279 | } | |
7d715a6c | 280 | |
5e0eaa7d KK |
281 | /* Convert L1 acceptable latency encoding to ns */ |
282 | static u32 calc_l1_acceptable(u32 encoding) | |
283 | { | |
284 | if (encoding == 0x7) | |
285 | return -1U; | |
286 | return (1000 << encoding); | |
7d715a6c SL |
287 | } |
288 | ||
ac18018a KK |
289 | struct aspm_register_info { |
290 | u32 support:2; | |
291 | u32 enabled:2; | |
292 | u32 latency_encoding_l0s; | |
293 | u32 latency_encoding_l1; | |
294 | }; | |
295 | ||
296 | static void pcie_get_aspm_reg(struct pci_dev *pdev, | |
297 | struct aspm_register_info *info) | |
7d715a6c SL |
298 | { |
299 | int pos; | |
300 | u16 reg16; | |
ac18018a | 301 | u32 reg32; |
7d715a6c | 302 | |
db9538a7 | 303 | pos = pci_pcie_cap(pdev); |
7d715a6c | 304 | pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); |
ac18018a | 305 | info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; |
ac18018a KK |
306 | info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; |
307 | info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; | |
7d715a6c | 308 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); |
ac18018a | 309 | info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; |
7d715a6c SL |
310 | } |
311 | ||
07d92760 KK |
312 | static void pcie_aspm_check_latency(struct pci_dev *endpoint) |
313 | { | |
ac18018a | 314 | u32 latency, l1_switch_latency = 0; |
07d92760 KK |
315 | struct aspm_latency *acceptable; |
316 | struct pcie_link_state *link; | |
317 | ||
318 | /* Device not in D0 doesn't need latency check */ | |
319 | if ((endpoint->current_state != PCI_D0) && | |
320 | (endpoint->current_state != PCI_UNKNOWN)) | |
321 | return; | |
322 | ||
323 | link = endpoint->bus->self->link_state; | |
324 | acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; | |
325 | ||
326 | while (link) { | |
ac18018a KK |
327 | /* Check upstream direction L0s latency */ |
328 | if ((link->aspm_capable & ASPM_STATE_L0S_UP) && | |
329 | (link->latency_up.l0s > acceptable->l0s)) | |
330 | link->aspm_capable &= ~ASPM_STATE_L0S_UP; | |
331 | ||
332 | /* Check downstream direction L0s latency */ | |
333 | if ((link->aspm_capable & ASPM_STATE_L0S_DW) && | |
334 | (link->latency_dw.l0s > acceptable->l0s)) | |
335 | link->aspm_capable &= ~ASPM_STATE_L0S_DW; | |
07d92760 KK |
336 | /* |
337 | * Check L1 latency. | |
338 | * Every switch on the path to root complex need 1 | |
339 | * more microsecond for L1. Spec doesn't mention L0s. | |
340 | */ | |
ac18018a KK |
341 | latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); |
342 | if ((link->aspm_capable & ASPM_STATE_L1) && | |
343 | (latency + l1_switch_latency > acceptable->l1)) | |
344 | link->aspm_capable &= ~ASPM_STATE_L1; | |
07d92760 KK |
345 | l1_switch_latency += 1000; |
346 | ||
347 | link = link->parent; | |
348 | } | |
349 | } | |
350 | ||
8d349ace | 351 | static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 352 | { |
5aa63583 KK |
353 | struct pci_dev *child, *parent = link->pdev; |
354 | struct pci_bus *linkbus = parent->subordinate; | |
ac18018a | 355 | struct aspm_register_info upreg, dwreg; |
7d715a6c | 356 | |
8d349ace | 357 | if (blacklist) { |
f1c0ca29 | 358 | /* Set enabled/disable so that we will disable ASPM later */ |
ac18018a KK |
359 | link->aspm_enabled = ASPM_STATE_ALL; |
360 | link->aspm_disable = ASPM_STATE_ALL; | |
8d349ace KK |
361 | return; |
362 | } | |
363 | ||
364 | /* Configure common clock before checking latencies */ | |
365 | pcie_aspm_configure_common_clock(link); | |
366 | ||
ac18018a KK |
367 | /* Get upstream/downstream components' register state */ |
368 | pcie_get_aspm_reg(parent, &upreg); | |
5aa63583 | 369 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); |
ac18018a KK |
370 | pcie_get_aspm_reg(child, &dwreg); |
371 | ||
372 | /* | |
373 | * Setup L0s state | |
374 | * | |
375 | * Note that we must not enable L0s in either direction on a | |
376 | * given link unless components on both sides of the link each | |
377 | * support L0s. | |
378 | */ | |
379 | if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) | |
380 | link->aspm_support |= ASPM_STATE_L0S; | |
381 | if (dwreg.enabled & PCIE_LINK_STATE_L0S) | |
382 | link->aspm_enabled |= ASPM_STATE_L0S_UP; | |
383 | if (upreg.enabled & PCIE_LINK_STATE_L0S) | |
384 | link->aspm_enabled |= ASPM_STATE_L0S_DW; | |
385 | link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); | |
386 | link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); | |
387 | ||
388 | /* Setup L1 state */ | |
389 | if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) | |
390 | link->aspm_support |= ASPM_STATE_L1; | |
391 | if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) | |
392 | link->aspm_enabled |= ASPM_STATE_L1; | |
393 | link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); | |
394 | link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); | |
5aa63583 | 395 | |
b127bd55 KK |
396 | /* Save default state */ |
397 | link->aspm_default = link->aspm_enabled; | |
07d92760 KK |
398 | |
399 | /* Setup initial capable state. Will be updated later */ | |
400 | link->aspm_capable = link->aspm_support; | |
f1c0ca29 KK |
401 | /* |
402 | * If the downstream component has pci bridge function, don't | |
403 | * do ASPM for now. | |
404 | */ | |
405 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
406 | if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { | |
ac18018a | 407 | link->aspm_disable = ASPM_STATE_ALL; |
f1c0ca29 KK |
408 | break; |
409 | } | |
410 | } | |
b127bd55 | 411 | |
b7206cbf | 412 | /* Get and check endpoint acceptable latencies */ |
5aa63583 | 413 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
7d715a6c | 414 | int pos; |
5e0eaa7d | 415 | u32 reg32, encoding; |
b6c2e54d | 416 | struct aspm_latency *acceptable = |
5aa63583 | 417 | &link->acceptable[PCI_FUNC(child->devfn)]; |
7d715a6c | 418 | |
5aa63583 KK |
419 | if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT && |
420 | child->pcie_type != PCI_EXP_TYPE_LEG_END) | |
7d715a6c SL |
421 | continue; |
422 | ||
db9538a7 | 423 | pos = pci_pcie_cap(child); |
5aa63583 | 424 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); |
07d92760 | 425 | /* Calculate endpoint L0s acceptable latency */ |
5e0eaa7d KK |
426 | encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; |
427 | acceptable->l0s = calc_l0s_acceptable(encoding); | |
07d92760 KK |
428 | /* Calculate endpoint L1 acceptable latency */ |
429 | encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; | |
430 | acceptable->l1 = calc_l1_acceptable(encoding); | |
431 | ||
432 | pcie_aspm_check_latency(child); | |
7d715a6c SL |
433 | } |
434 | } | |
435 | ||
ac18018a | 436 | static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) |
7d715a6c SL |
437 | { |
438 | u16 reg16; | |
db9538a7 | 439 | int pos = pci_pcie_cap(pdev); |
7d715a6c SL |
440 | |
441 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
442 | reg16 &= ~0x3; | |
ac18018a | 443 | reg16 |= val; |
7d715a6c SL |
444 | pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); |
445 | } | |
446 | ||
b7206cbf | 447 | static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) |
7d715a6c | 448 | { |
ac18018a | 449 | u32 upstream = 0, dwstream = 0; |
5aa63583 KK |
450 | struct pci_dev *child, *parent = link->pdev; |
451 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 452 | |
f1c0ca29 | 453 | /* Nothing to do if the link is already in the requested state */ |
b7206cbf | 454 | state &= (link->aspm_capable & ~link->aspm_disable); |
f1c0ca29 KK |
455 | if (link->aspm_enabled == state) |
456 | return; | |
ac18018a KK |
457 | /* Convert ASPM state to upstream/downstream ASPM register state */ |
458 | if (state & ASPM_STATE_L0S_UP) | |
459 | dwstream |= PCIE_LINK_STATE_L0S; | |
460 | if (state & ASPM_STATE_L0S_DW) | |
461 | upstream |= PCIE_LINK_STATE_L0S; | |
462 | if (state & ASPM_STATE_L1) { | |
463 | upstream |= PCIE_LINK_STATE_L1; | |
464 | dwstream |= PCIE_LINK_STATE_L1; | |
465 | } | |
7d715a6c | 466 | /* |
5aa63583 KK |
467 | * Spec 2.0 suggests all functions should be configured the |
468 | * same setting for ASPM. Enabling ASPM L1 should be done in | |
469 | * upstream component first and then downstream, and vice | |
470 | * versa for disabling ASPM L1. Spec doesn't mention L0S. | |
7d715a6c | 471 | */ |
ac18018a KK |
472 | if (state & ASPM_STATE_L1) |
473 | pcie_config_aspm_dev(parent, upstream); | |
5aa63583 | 474 | list_for_each_entry(child, &linkbus->devices, bus_list) |
ac18018a KK |
475 | pcie_config_aspm_dev(child, dwstream); |
476 | if (!(state & ASPM_STATE_L1)) | |
477 | pcie_config_aspm_dev(parent, upstream); | |
7d715a6c | 478 | |
5aa63583 | 479 | link->aspm_enabled = state; |
7d715a6c SL |
480 | } |
481 | ||
b7206cbf | 482 | static void pcie_config_aspm_path(struct pcie_link_state *link) |
7d715a6c | 483 | { |
b7206cbf KK |
484 | while (link) { |
485 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
486 | link = link->parent; | |
46bbdfa4 | 487 | } |
7d715a6c SL |
488 | } |
489 | ||
5aa63583 | 490 | static void free_link_state(struct pcie_link_state *link) |
7d715a6c | 491 | { |
5aa63583 KK |
492 | link->pdev->link_state = NULL; |
493 | kfree(link); | |
7d715a6c SL |
494 | } |
495 | ||
ddc9753f SL |
496 | static int pcie_aspm_sanity_check(struct pci_dev *pdev) |
497 | { | |
3647584d KK |
498 | struct pci_dev *child; |
499 | int pos; | |
149e1637 | 500 | u32 reg32; |
2f671e2d MG |
501 | |
502 | if (aspm_clear_state) | |
503 | return -EINVAL; | |
504 | ||
ddc9753f | 505 | /* |
45e829ea | 506 | * Some functions in a slot might not all be PCIe functions, |
3647584d | 507 | * very strange. Disable ASPM for the whole slot |
ddc9753f | 508 | */ |
3647584d | 509 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
db9538a7 | 510 | pos = pci_pcie_cap(child); |
3647584d | 511 | if (!pos) |
ddc9753f | 512 | return -EINVAL; |
149e1637 SL |
513 | /* |
514 | * Disable ASPM for pre-1.1 PCIe device, we follow MS to use | |
515 | * RBER bit to determine if a function is 1.1 version device | |
516 | */ | |
3647584d | 517 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); |
e1f4f59d | 518 | if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { |
3647584d | 519 | dev_printk(KERN_INFO, &child->dev, "disabling ASPM" |
f393d9b1 VL |
520 | " on pre-1.1 PCIe device. You can enable it" |
521 | " with 'pcie_aspm=force'\n"); | |
149e1637 SL |
522 | return -EINVAL; |
523 | } | |
ddc9753f SL |
524 | } |
525 | return 0; | |
526 | } | |
527 | ||
b7206cbf | 528 | static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev) |
8d349ace KK |
529 | { |
530 | struct pcie_link_state *link; | |
8d349ace KK |
531 | |
532 | link = kzalloc(sizeof(*link), GFP_KERNEL); | |
533 | if (!link) | |
534 | return NULL; | |
535 | INIT_LIST_HEAD(&link->sibling); | |
536 | INIT_LIST_HEAD(&link->children); | |
537 | INIT_LIST_HEAD(&link->link); | |
538 | link->pdev = pdev; | |
8d349ace KK |
539 | if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) { |
540 | struct pcie_link_state *parent; | |
541 | parent = pdev->bus->parent->self->link_state; | |
542 | if (!parent) { | |
543 | kfree(link); | |
544 | return NULL; | |
545 | } | |
546 | link->parent = parent; | |
547 | list_add(&link->link, &parent->children); | |
548 | } | |
5c92ffb1 KK |
549 | /* Setup a pointer to the root port link */ |
550 | if (!link->parent) | |
551 | link->root = link; | |
552 | else | |
553 | link->root = link->parent->root; | |
554 | ||
8d349ace | 555 | list_add(&link->sibling, &link_list); |
8d349ace | 556 | pdev->link_state = link; |
8d349ace KK |
557 | return link; |
558 | } | |
559 | ||
7d715a6c SL |
560 | /* |
561 | * pcie_aspm_init_link_state: Initiate PCI express link state. | |
562 | * It is called after the pcie and its children devices are scaned. | |
563 | * @pdev: the root port or switch downstream port | |
564 | */ | |
565 | void pcie_aspm_init_link_state(struct pci_dev *pdev) | |
566 | { | |
8d349ace | 567 | struct pcie_link_state *link; |
b7206cbf | 568 | int blacklist = !!pcie_aspm_sanity_check(pdev); |
7d715a6c | 569 | |
2f671e2d | 570 | if (!pci_is_pcie(pdev) || pdev->link_state) |
7d715a6c SL |
571 | return; |
572 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 573 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) |
7d715a6c | 574 | return; |
8d349ace | 575 | |
2f671e2d MG |
576 | if (aspm_disabled && !aspm_clear_state) |
577 | return; | |
578 | ||
8e822df7 SL |
579 | /* VIA has a strange chipset, root port is under a bridge */ |
580 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 581 | pdev->bus->self) |
8e822df7 | 582 | return; |
8d349ace | 583 | |
7d715a6c SL |
584 | down_read(&pci_bus_sem); |
585 | if (list_empty(&pdev->subordinate->devices)) | |
586 | goto out; | |
587 | ||
588 | mutex_lock(&aspm_lock); | |
b7206cbf | 589 | link = alloc_pcie_link_state(pdev); |
8d349ace KK |
590 | if (!link) |
591 | goto unlock; | |
592 | /* | |
b7206cbf KK |
593 | * Setup initial ASPM state. Note that we need to configure |
594 | * upstream links also because capable state of them can be | |
595 | * update through pcie_aspm_cap_init(). | |
8d349ace | 596 | */ |
b7206cbf | 597 | pcie_aspm_cap_init(link, blacklist); |
7d715a6c | 598 | |
8d349ace | 599 | /* Setup initial Clock PM state */ |
b7206cbf | 600 | pcie_clkpm_cap_init(link, blacklist); |
41cd766b MG |
601 | |
602 | /* | |
603 | * At this stage drivers haven't had an opportunity to change the | |
604 | * link policy setting. Enabling ASPM on broken hardware can cripple | |
605 | * it even before the driver has had a chance to disable ASPM, so | |
606 | * default to a safe level right now. If we're enabling ASPM beyond | |
607 | * the BIOS's expectation, we'll do so once pci_enable_device() is | |
608 | * called. | |
609 | */ | |
610 | if (aspm_policy != POLICY_POWERSAVE) { | |
611 | pcie_config_aspm_path(link); | |
612 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
613 | } | |
614 | ||
8d349ace | 615 | unlock: |
7d715a6c SL |
616 | mutex_unlock(&aspm_lock); |
617 | out: | |
618 | up_read(&pci_bus_sem); | |
619 | } | |
620 | ||
07d92760 KK |
621 | /* Recheck latencies and update aspm_capable for links under the root */ |
622 | static void pcie_update_aspm_capable(struct pcie_link_state *root) | |
623 | { | |
624 | struct pcie_link_state *link; | |
625 | BUG_ON(root->parent); | |
626 | list_for_each_entry(link, &link_list, sibling) { | |
627 | if (link->root != root) | |
628 | continue; | |
629 | link->aspm_capable = link->aspm_support; | |
630 | } | |
631 | list_for_each_entry(link, &link_list, sibling) { | |
632 | struct pci_dev *child; | |
633 | struct pci_bus *linkbus = link->pdev->subordinate; | |
634 | if (link->root != root) | |
635 | continue; | |
636 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
637 | if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT) && | |
638 | (child->pcie_type != PCI_EXP_TYPE_LEG_END)) | |
639 | continue; | |
640 | pcie_aspm_check_latency(child); | |
641 | } | |
642 | } | |
643 | } | |
644 | ||
7d715a6c SL |
645 | /* @pdev: the endpoint device */ |
646 | void pcie_aspm_exit_link_state(struct pci_dev *pdev) | |
647 | { | |
648 | struct pci_dev *parent = pdev->bus->self; | |
b7206cbf | 649 | struct pcie_link_state *link, *root, *parent_link; |
7d715a6c | 650 | |
2f671e2d | 651 | if ((aspm_disabled && !aspm_clear_state) || !pci_is_pcie(pdev) || |
8b06477d | 652 | !parent || !parent->link_state) |
7d715a6c | 653 | return; |
b7206cbf KK |
654 | if ((parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && |
655 | (parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) | |
7d715a6c | 656 | return; |
fc87e919 | 657 | |
7d715a6c SL |
658 | down_read(&pci_bus_sem); |
659 | mutex_lock(&aspm_lock); | |
7d715a6c SL |
660 | /* |
661 | * All PCIe functions are in one slot, remove one function will remove | |
3419c75e | 662 | * the whole slot, so just wait until we are the last function left. |
7d715a6c | 663 | */ |
3419c75e | 664 | if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices)) |
7d715a6c SL |
665 | goto out; |
666 | ||
fc87e919 | 667 | link = parent->link_state; |
07d92760 | 668 | root = link->root; |
b7206cbf | 669 | parent_link = link->parent; |
fc87e919 | 670 | |
7d715a6c | 671 | /* All functions are removed, so just disable ASPM for the link */ |
b7206cbf | 672 | pcie_config_aspm_link(link, 0); |
fc87e919 KK |
673 | list_del(&link->sibling); |
674 | list_del(&link->link); | |
7d715a6c | 675 | /* Clock PM is for endpoint device */ |
fc87e919 | 676 | free_link_state(link); |
07d92760 KK |
677 | |
678 | /* Recheck latencies and configure upstream links */ | |
b26a34aa KK |
679 | if (parent_link) { |
680 | pcie_update_aspm_capable(root); | |
681 | pcie_config_aspm_path(parent_link); | |
682 | } | |
7d715a6c SL |
683 | out: |
684 | mutex_unlock(&aspm_lock); | |
685 | up_read(&pci_bus_sem); | |
686 | } | |
687 | ||
688 | /* @pdev: the root port or switch downstream port */ | |
689 | void pcie_aspm_pm_state_change(struct pci_dev *pdev) | |
690 | { | |
07d92760 | 691 | struct pcie_link_state *link = pdev->link_state; |
7d715a6c | 692 | |
8b06477d | 693 | if (aspm_disabled || !pci_is_pcie(pdev) || !link) |
7d715a6c | 694 | return; |
07d92760 KK |
695 | if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && |
696 | (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) | |
7d715a6c SL |
697 | return; |
698 | /* | |
07d92760 KK |
699 | * Devices changed PM state, we should recheck if latency |
700 | * meets all functions' requirement | |
7d715a6c | 701 | */ |
07d92760 KK |
702 | down_read(&pci_bus_sem); |
703 | mutex_lock(&aspm_lock); | |
704 | pcie_update_aspm_capable(link->root); | |
b7206cbf | 705 | pcie_config_aspm_path(link); |
07d92760 KK |
706 | mutex_unlock(&aspm_lock); |
707 | up_read(&pci_bus_sem); | |
7d715a6c SL |
708 | } |
709 | ||
710 | /* | |
711 | * pci_disable_link_state - disable pci device's link state, so the link will | |
712 | * never enter specific states | |
713 | */ | |
714 | void pci_disable_link_state(struct pci_dev *pdev, int state) | |
715 | { | |
716 | struct pci_dev *parent = pdev->bus->self; | |
f1c0ca29 | 717 | struct pcie_link_state *link; |
7d715a6c | 718 | |
8b06477d | 719 | if (aspm_disabled || !pci_is_pcie(pdev)) |
7d715a6c SL |
720 | return; |
721 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
722 | pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) | |
723 | parent = pdev; | |
724 | if (!parent || !parent->link_state) | |
725 | return; | |
726 | ||
727 | down_read(&pci_bus_sem); | |
728 | mutex_lock(&aspm_lock); | |
f1c0ca29 | 729 | link = parent->link_state; |
ac18018a KK |
730 | if (state & PCIE_LINK_STATE_L0S) |
731 | link->aspm_disable |= ASPM_STATE_L0S; | |
732 | if (state & PCIE_LINK_STATE_L1) | |
733 | link->aspm_disable |= ASPM_STATE_L1; | |
b7206cbf KK |
734 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); |
735 | ||
430842e2 | 736 | if (state & PCIE_LINK_STATE_CLKPM) { |
f1c0ca29 KK |
737 | link->clkpm_capable = 0; |
738 | pcie_set_clkpm(link, 0); | |
430842e2 | 739 | } |
7d715a6c SL |
740 | mutex_unlock(&aspm_lock); |
741 | up_read(&pci_bus_sem); | |
742 | } | |
743 | EXPORT_SYMBOL(pci_disable_link_state); | |
744 | ||
745 | static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) | |
746 | { | |
747 | int i; | |
b7206cbf | 748 | struct pcie_link_state *link; |
7d715a6c SL |
749 | |
750 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
751 | if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) | |
752 | break; | |
753 | if (i >= ARRAY_SIZE(policy_str)) | |
754 | return -EINVAL; | |
755 | if (i == aspm_policy) | |
756 | return 0; | |
757 | ||
758 | down_read(&pci_bus_sem); | |
759 | mutex_lock(&aspm_lock); | |
760 | aspm_policy = i; | |
b7206cbf KK |
761 | list_for_each_entry(link, &link_list, sibling) { |
762 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
763 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
7d715a6c SL |
764 | } |
765 | mutex_unlock(&aspm_lock); | |
766 | up_read(&pci_bus_sem); | |
767 | return 0; | |
768 | } | |
769 | ||
770 | static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) | |
771 | { | |
772 | int i, cnt = 0; | |
773 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
774 | if (i == aspm_policy) | |
775 | cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); | |
776 | else | |
777 | cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); | |
778 | return cnt; | |
779 | } | |
780 | ||
781 | module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, | |
782 | NULL, 0644); | |
783 | ||
784 | #ifdef CONFIG_PCIEASPM_DEBUG | |
785 | static ssize_t link_state_show(struct device *dev, | |
786 | struct device_attribute *attr, | |
787 | char *buf) | |
788 | { | |
789 | struct pci_dev *pci_device = to_pci_dev(dev); | |
790 | struct pcie_link_state *link_state = pci_device->link_state; | |
791 | ||
80bfdbe3 | 792 | return sprintf(buf, "%d\n", link_state->aspm_enabled); |
7d715a6c SL |
793 | } |
794 | ||
795 | static ssize_t link_state_store(struct device *dev, | |
796 | struct device_attribute *attr, | |
797 | const char *buf, | |
798 | size_t n) | |
799 | { | |
5aa63583 | 800 | struct pci_dev *pdev = to_pci_dev(dev); |
b7206cbf | 801 | struct pcie_link_state *link, *root = pdev->link_state->root; |
ac18018a | 802 | u32 val = buf[0] - '0', state = 0; |
7d715a6c | 803 | |
ac18018a | 804 | if (n < 1 || val > 3) |
7d715a6c | 805 | return -EINVAL; |
7d715a6c | 806 | |
ac18018a KK |
807 | /* Convert requested state to ASPM state */ |
808 | if (val & PCIE_LINK_STATE_L0S) | |
809 | state |= ASPM_STATE_L0S; | |
810 | if (val & PCIE_LINK_STATE_L1) | |
811 | state |= ASPM_STATE_L1; | |
812 | ||
b7206cbf KK |
813 | down_read(&pci_bus_sem); |
814 | mutex_lock(&aspm_lock); | |
815 | list_for_each_entry(link, &link_list, sibling) { | |
816 | if (link->root != root) | |
817 | continue; | |
818 | pcie_config_aspm_link(link, state); | |
819 | } | |
820 | mutex_unlock(&aspm_lock); | |
821 | up_read(&pci_bus_sem); | |
822 | return n; | |
7d715a6c SL |
823 | } |
824 | ||
825 | static ssize_t clk_ctl_show(struct device *dev, | |
826 | struct device_attribute *attr, | |
827 | char *buf) | |
828 | { | |
829 | struct pci_dev *pci_device = to_pci_dev(dev); | |
830 | struct pcie_link_state *link_state = pci_device->link_state; | |
831 | ||
4d246e45 | 832 | return sprintf(buf, "%d\n", link_state->clkpm_enabled); |
7d715a6c SL |
833 | } |
834 | ||
835 | static ssize_t clk_ctl_store(struct device *dev, | |
836 | struct device_attribute *attr, | |
837 | const char *buf, | |
838 | size_t n) | |
839 | { | |
430842e2 | 840 | struct pci_dev *pdev = to_pci_dev(dev); |
7d715a6c SL |
841 | int state; |
842 | ||
843 | if (n < 1) | |
844 | return -EINVAL; | |
845 | state = buf[0]-'0'; | |
846 | ||
847 | down_read(&pci_bus_sem); | |
848 | mutex_lock(&aspm_lock); | |
430842e2 | 849 | pcie_set_clkpm_nocheck(pdev->link_state, !!state); |
7d715a6c SL |
850 | mutex_unlock(&aspm_lock); |
851 | up_read(&pci_bus_sem); | |
852 | ||
853 | return n; | |
854 | } | |
855 | ||
856 | static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store); | |
857 | static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store); | |
858 | ||
859 | static char power_group[] = "power"; | |
860 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | |
861 | { | |
862 | struct pcie_link_state *link_state = pdev->link_state; | |
863 | ||
8b06477d KK |
864 | if (!pci_is_pcie(pdev) || |
865 | (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
866 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
7d715a6c SL |
867 | return; |
868 | ||
80bfdbe3 | 869 | if (link_state->aspm_support) |
7d715a6c SL |
870 | sysfs_add_file_to_group(&pdev->dev.kobj, |
871 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 872 | if (link_state->clkpm_capable) |
7d715a6c SL |
873 | sysfs_add_file_to_group(&pdev->dev.kobj, |
874 | &dev_attr_clk_ctl.attr, power_group); | |
875 | } | |
876 | ||
877 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | |
878 | { | |
879 | struct pcie_link_state *link_state = pdev->link_state; | |
880 | ||
8b06477d KK |
881 | if (!pci_is_pcie(pdev) || |
882 | (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
883 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
7d715a6c SL |
884 | return; |
885 | ||
80bfdbe3 | 886 | if (link_state->aspm_support) |
7d715a6c SL |
887 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
888 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 889 | if (link_state->clkpm_capable) |
7d715a6c SL |
890 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
891 | &dev_attr_clk_ctl.attr, power_group); | |
892 | } | |
893 | #endif | |
894 | ||
895 | static int __init pcie_aspm_disable(char *str) | |
896 | { | |
d6d38574 SL |
897 | if (!strcmp(str, "off")) { |
898 | aspm_disabled = 1; | |
899 | printk(KERN_INFO "PCIe ASPM is disabled\n"); | |
900 | } else if (!strcmp(str, "force")) { | |
901 | aspm_force = 1; | |
902 | printk(KERN_INFO "PCIe ASPM is forcedly enabled\n"); | |
903 | } | |
7d715a6c SL |
904 | return 1; |
905 | } | |
906 | ||
d6d38574 | 907 | __setup("pcie_aspm=", pcie_aspm_disable); |
7d715a6c | 908 | |
2f671e2d MG |
909 | void pcie_clear_aspm(void) |
910 | { | |
911 | if (!aspm_force) | |
912 | aspm_clear_state = 1; | |
913 | } | |
914 | ||
5fde244d SL |
915 | void pcie_no_aspm(void) |
916 | { | |
d6d38574 SL |
917 | if (!aspm_force) |
918 | aspm_disabled = 1; | |
5fde244d SL |
919 | } |
920 | ||
3e1b1600 AP |
921 | /** |
922 | * pcie_aspm_enabled - is PCIe ASPM enabled? | |
923 | * | |
924 | * Returns true if ASPM has not been disabled by the command-line option | |
925 | * pcie_aspm=off. | |
926 | **/ | |
927 | int pcie_aspm_enabled(void) | |
7d715a6c | 928 | { |
3e1b1600 | 929 | return !aspm_disabled; |
7d715a6c | 930 | } |
3e1b1600 | 931 | EXPORT_SYMBOL(pcie_aspm_enabled); |
7d715a6c | 932 |