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PCI/AER: Remove duplicate PCI_EXP_AER_FLAGS definition
[linux-2.6-block.git] / drivers / pci / pcie / aer.c
CommitLineData
e1e86ee0 1// SPDX-License-Identifier: GPL-2.0
6c2b374d 2/*
df62ab5e
BH		 3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects root port status and schedules work.
6c2b374d
ZY		 6 *
7 * Copyright (C) 2006 Intel Corp.
8 * Tom Long Nguyen (tom.l.nguyen@intel.com)
9 * Zhang Yanmin (yanmin.zhang@intel.com)
41cbc9eb
BH		 10 *
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
12 * Andrew Patterson <andrew.patterson@hp.com>
6c2b374d
ZY		 13 */
14
0319c9a0 15#include <linux/cper.h>
6c2b374d 16#include <linux/pci.h>
415e12b2 17#include <linux/pci-acpi.h>
d43c36dc 18#include <linux/sched.h>
6c2b374d
ZY		 19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/pm.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
fd3362cb 25#include <linux/kfifo.h>
5a0e3ad6 26#include <linux/slab.h>
256a4593 27#include <acpi/apei.h>
0319c9a0 28#include <ras/ras_event.h>
6c2b374d 29
4696b828
BH		 30#include "../pci.h"
31#include "portdrv.h"
23e672bc
BH		 32
33#define AER_ERROR_SOURCES_MAX 100
23e672bc 34
db89ccbe
RJ		 35#define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
36#define AER_MAX_TYPEOF_UNCOR_ERRS 26 /* as per PCI_ERR_UNCOR_STATUS*/
37
23e672bc
BH		 38struct aer_err_source {
39 unsigned int status;
40 unsigned int id;
41};
42
43struct aer_rpc {
44 struct pci_dev *rpd; /* Root Port device */
45 struct work_struct dpc_handler;
46 struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
47 struct aer_err_info e_info;
48 unsigned short prod_idx; /* Error Producer Index */
49 unsigned short cons_idx; /* Error Consumer Index */
50 int isr;
51 spinlock_t e_lock; /*
52 * Lock access to Error Status/ID Regs
53 * and error producer/consumer index
54 */
55 struct mutex rpc_mutex; /*
56 * only one thread could do
57 * recovery on the same
58 * root port hierarchy
59 */
60};
61
db89ccbe
RJ		 62/* AER stats for the device */
63struct aer_stats {
64
65 /*
66 * Fields for all AER capable devices. They indicate the errors
67 * "as seen by this device". Note that this may mean that if an
68 * end point is causing problems, the AER counters may increment
69 * at its link partner (e.g. root port) because the errors will be
70 * "seen" by the link partner and not the the problematic end point
71 * itself (which may report all counters as 0 as it never saw any
72 * problems).
73 */
74 /* Counters for different type of correctable errors */
75 u64 dev_cor_errs[AER_MAX_TYPEOF_COR_ERRS];
76 /* Counters for different type of fatal uncorrectable errors */
77 u64 dev_fatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
78 /* Counters for different type of nonfatal uncorrectable errors */
79 u64 dev_nonfatal_errs[AER_MAX_TYPEOF_UNCOR_ERRS];
80 /* Total number of ERR_COR sent by this device */
81 u64 dev_total_cor_errs;
82 /* Total number of ERR_FATAL sent by this device */
83 u64 dev_total_fatal_errs;
84 /* Total number of ERR_NONFATAL sent by this device */
85 u64 dev_total_nonfatal_errs;
86
87 /*
88 * Fields for Root ports & root complex event collectors only, these
89 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
90 * messages received by the root port / event collector, INCLUDING the
91 * ones that are generated internally (by the rootport itself)
92 */
93 u64 rootport_total_cor_errs;
94 u64 rootport_total_fatal_errs;
95 u64 rootport_total_nonfatal_errs;
96};
97
23e672bc
BH		 98#define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
99 PCI_ERR_UNC_ECRC| \
100 PCI_ERR_UNC_UNSUP| \
101 PCI_ERR_UNC_COMP_ABORT| \
102 PCI_ERR_UNC_UNX_COMP| \
103 PCI_ERR_UNC_MALF_TLP)
104
105#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
106 PCI_EXP_RTCTL_SENFEE| \
107 PCI_EXP_RTCTL_SEFEE)
108#define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
109 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
110 PCI_ERR_ROOT_CMD_FATAL_EN)
111#define ERR_COR_ID(d) (d & 0xffff)
112#define ERR_UNCOR_ID(d) (d >> 16)
6c2b374d 113
7f785763
RD		 114static int pcie_aer_disable;
115
116void pci_no_aer(void)
117{
7ece1417 118 pcie_aer_disable = 1;
7f785763
RD		 119}
120
f1a7bfaf
RW		 121bool pci_aer_available(void)
122{
123 return !pcie_aer_disable && pci_msi_enabled();
124}
125
41cbc9eb
BH		 126#ifdef CONFIG_PCIE_ECRC
127
128#define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
129#define ECRC_POLICY_OFF 1 /* ECRC off for performance */
130#define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
131
132static int ecrc_policy = ECRC_POLICY_DEFAULT;
133
134static const char *ecrc_policy_str[] = {
135 [ECRC_POLICY_DEFAULT] = "bios",
136 [ECRC_POLICY_OFF] = "off",
137 [ECRC_POLICY_ON] = "on"
138};
139
140/**
141 * enable_ercr_checking - enable PCIe ECRC checking for a device
142 * @dev: the PCI device
143 *
144 * Returns 0 on success, or negative on failure.
145 */
146static int enable_ecrc_checking(struct pci_dev *dev)
147{
148 int pos;
149 u32 reg32;
150
151 if (!pci_is_pcie(dev))
152 return -ENODEV;
153
154 pos = dev->aer_cap;
155 if (!pos)
156 return -ENODEV;
157
158 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
159 if (reg32 & PCI_ERR_CAP_ECRC_GENC)
160 reg32 |= PCI_ERR_CAP_ECRC_GENE;
161 if (reg32 & PCI_ERR_CAP_ECRC_CHKC)
162 reg32 |= PCI_ERR_CAP_ECRC_CHKE;
163 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
164
165 return 0;
166}
167
168/**
169 * disable_ercr_checking - disables PCIe ECRC checking for a device
170 * @dev: the PCI device
171 *
172 * Returns 0 on success, or negative on failure.
173 */
174static int disable_ecrc_checking(struct pci_dev *dev)
175{
176 int pos;
177 u32 reg32;
178
179 if (!pci_is_pcie(dev))
180 return -ENODEV;
181
182 pos = dev->aer_cap;
183 if (!pos)
184 return -ENODEV;
185
186 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
187 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
188 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
189
190 return 0;
191}
192
193/**
194 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
195 * @dev: the PCI device
196 */
197void pcie_set_ecrc_checking(struct pci_dev *dev)
198{
199 switch (ecrc_policy) {
200 case ECRC_POLICY_DEFAULT:
201 return;
202 case ECRC_POLICY_OFF:
203 disable_ecrc_checking(dev);
204 break;
205 case ECRC_POLICY_ON:
206 enable_ecrc_checking(dev);
207 break;
208 default:
209 return;
210 }
211}
212
213/**
214 * pcie_ecrc_get_policy - parse kernel command-line ecrc option
215 */
216void pcie_ecrc_get_policy(char *str)
217{
218 int i;
219
220 for (i = 0; i < ARRAY_SIZE(ecrc_policy_str); i++)
221 if (!strncmp(str, ecrc_policy_str[i],
222 strlen(ecrc_policy_str[i])))
223 break;
224 if (i >= ARRAY_SIZE(ecrc_policy_str))
225 return;
226
227 ecrc_policy = i;
228}
229#endif /* CONFIG_PCIE_ECRC */
230
256a4593
BH		 231#ifdef CONFIG_ACPI_APEI
232static inline int hest_match_pci(struct acpi_hest_aer_common *p,
233 struct pci_dev *pci)
234{
235 return ACPI_HEST_SEGMENT(p->bus) == pci_domain_nr(pci->bus) &&
236 ACPI_HEST_BUS(p->bus) == pci->bus->number &&
237 p->device == PCI_SLOT(pci->devfn) &&
238 p->function == PCI_FUNC(pci->devfn);
239}
240
241static inline bool hest_match_type(struct acpi_hest_header *hest_hdr,
242 struct pci_dev *dev)
243{
244 u16 hest_type = hest_hdr->type;
245 u8 pcie_type = pci_pcie_type(dev);
246
247 if ((hest_type == ACPI_HEST_TYPE_AER_ROOT_PORT &&
248 pcie_type == PCI_EXP_TYPE_ROOT_PORT) ||
249 (hest_type == ACPI_HEST_TYPE_AER_ENDPOINT &&
250 pcie_type == PCI_EXP_TYPE_ENDPOINT) ||
251 (hest_type == ACPI_HEST_TYPE_AER_BRIDGE &&
252 (dev->class >> 16) == PCI_BASE_CLASS_BRIDGE))
253 return true;
254 return false;
255}
256
257struct aer_hest_parse_info {
258 struct pci_dev *pci_dev;
259 int firmware_first;
260};
261
262static int hest_source_is_pcie_aer(struct acpi_hest_header *hest_hdr)
263{
264 if (hest_hdr->type == ACPI_HEST_TYPE_AER_ROOT_PORT ||
265 hest_hdr->type == ACPI_HEST_TYPE_AER_ENDPOINT ||
266 hest_hdr->type == ACPI_HEST_TYPE_AER_BRIDGE)
267 return 1;
268 return 0;
269}
270
271static int aer_hest_parse(struct acpi_hest_header *hest_hdr, void *data)
272{
273 struct aer_hest_parse_info *info = data;
274 struct acpi_hest_aer_common *p;
275 int ff;
276
277 if (!hest_source_is_pcie_aer(hest_hdr))
278 return 0;
279
280 p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
281 ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
282
283 /*
284 * If no specific device is supplied, determine whether
285 * FIRMWARE_FIRST is set for *any* PCIe device.
286 */
287 if (!info->pci_dev) {
288 info->firmware_first |= ff;
289 return 0;
290 }
291
292 /* Otherwise, check the specific device */
293 if (p->flags & ACPI_HEST_GLOBAL) {
294 if (hest_match_type(hest_hdr, info->pci_dev))
295 info->firmware_first = ff;
296 } else
297 if (hest_match_pci(p, info->pci_dev))
298 info->firmware_first = ff;
299
300 return 0;
301}
302
303static void aer_set_firmware_first(struct pci_dev *pci_dev)
304{
305 int rc;
306 struct aer_hest_parse_info info = {
307 .pci_dev = pci_dev,
308 .firmware_first = 0,
309 };
310
311 rc = apei_hest_parse(aer_hest_parse, &info);
312
313 if (rc)
314 pci_dev->__aer_firmware_first = 0;
315 else
316 pci_dev->__aer_firmware_first = info.firmware_first;
317 pci_dev->__aer_firmware_first_valid = 1;
318}
319
320int pcie_aer_get_firmware_first(struct pci_dev *dev)
321{
322 if (!pci_is_pcie(dev))
323 return 0;
324
7af02fcd
AG		 325 if (pcie_ports_native)
326 return 0;
327
256a4593
BH		 328 if (!dev->__aer_firmware_first_valid)
329 aer_set_firmware_first(dev);
330 return dev->__aer_firmware_first;
331}
332
333static bool aer_firmware_first;
334
335/**
336 * aer_acpi_firmware_first - Check if APEI should control AER.
337 */
338bool aer_acpi_firmware_first(void)
339{
340 static bool parsed = false;
341 struct aer_hest_parse_info info = {
342 .pci_dev = NULL, /* Check all PCIe devices */
343 .firmware_first = 0,
344 };
345
7af02fcd
AG		 346 if (pcie_ports_native)
347 return false;
348
256a4593
BH		 349 if (!parsed) {
350 apei_hest_parse(aer_hest_parse, &info);
351 aer_firmware_first = info.firmware_first;
352 parsed = true;
353 }
354 return aer_firmware_first;
355}
356#endif
357
fd3362cb
BH		 358#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
359 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
360
361int pci_enable_pcie_error_reporting(struct pci_dev *dev)
362{
363 if (pcie_aer_get_firmware_first(dev))
364 return -EIO;
365
366 if (!dev->aer_cap)
367 return -EIO;
368
369 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
370}
371EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
372
373int pci_disable_pcie_error_reporting(struct pci_dev *dev)
374{
375 if (pcie_aer_get_firmware_first(dev))
376 return -EIO;
377
378 return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
379 PCI_EXP_AER_FLAGS);
380}
381EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
382
ec752f5d
OP		 383void pci_aer_clear_device_status(struct pci_dev *dev)
384{
385 u16 sta;
386
387 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
388 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
389}
390
fd3362cb
BH		 391int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
392{
393 int pos;
e7b0b847 394 u32 status, sev;
fd3362cb
BH		 395
396 pos = dev->aer_cap;
397 if (!pos)
398 return -EIO;
399
e7b0b847 400 /* Clear status bits for ERR_NONFATAL errors only */
fd3362cb 401 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
e7b0b847
OP		 402 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
403 status &= ~sev;
fd3362cb
BH		 404 if (status)
405 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
406
407 return 0;
408}
409EXPORT_SYMBOL_GPL(pci_cleanup_aer_uncorrect_error_status);
410
7ab92e89
BH		 411void pci_aer_clear_fatal_status(struct pci_dev *dev)
412{
413 int pos;
414 u32 status, sev;
415
416 pos = dev->aer_cap;
417 if (!pos)
418 return;
419
420 /* Clear status bits for ERR_FATAL errors only */
421 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
422 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
423 status &= sev;
424 if (status)
425 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
426}
427
fd3362cb
BH		 428int pci_cleanup_aer_error_status_regs(struct pci_dev *dev)
429{
430 int pos;
431 u32 status;
432 int port_type;
433
434 if (!pci_is_pcie(dev))
435 return -ENODEV;
436
437 pos = dev->aer_cap;
438 if (!pos)
439 return -EIO;
440
441 port_type = pci_pcie_type(dev);
442 if (port_type == PCI_EXP_TYPE_ROOT_PORT) {
443 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &status);
444 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, status);
445 }
446
447 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &status);
448 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, status);
449
450 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
451 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, status);
452
453 return 0;
454}
455
60ed982a 456void pci_aer_init(struct pci_dev *dev)
fd3362cb
BH		 457{
458 dev->aer_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
db89ccbe
RJ		 459
460 if (dev->aer_cap)
461 dev->aer_stats = kzalloc(sizeof(struct aer_stats), GFP_KERNEL);
462
60ed982a 463 pci_cleanup_aer_error_status_regs(dev);
fd3362cb
BH		 464}
465
db89ccbe
RJ		 466void pci_aer_exit(struct pci_dev *dev)
467{
468 kfree(dev->aer_stats);
469 dev->aer_stats = NULL;
470}
471
0319c9a0
BH		 472#define AER_AGENT_RECEIVER 0
473#define AER_AGENT_REQUESTER 1
474#define AER_AGENT_COMPLETER 2
475#define AER_AGENT_TRANSMITTER 3
476
477#define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
478 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
479#define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
480 0 : PCI_ERR_UNC_COMP_ABORT)
481#define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
482 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
483
484#define AER_GET_AGENT(t, e) \
485 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
486 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
487 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
488 AER_AGENT_RECEIVER)
489
490#define AER_PHYSICAL_LAYER_ERROR 0
491#define AER_DATA_LINK_LAYER_ERROR 1
492#define AER_TRANSACTION_LAYER_ERROR 2
493
494#define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
495 PCI_ERR_COR_RCVR : 0)
496#define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
497 (PCI_ERR_COR_BAD_TLP| \
498 PCI_ERR_COR_BAD_DLLP| \
499 PCI_ERR_COR_REP_ROLL| \
500 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
501
502#define AER_GET_LAYER_ERROR(t, e) \
503 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
504 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
505 AER_TRANSACTION_LAYER_ERROR)
506
507/*
508 * AER error strings
509 */
510static const char *aer_error_severity_string[] = {
511 "Uncorrected (Non-Fatal)",
512 "Uncorrected (Fatal)",
513 "Corrected"
514};
515
516static const char *aer_error_layer[] = {
517 "Physical Layer",
518 "Data Link Layer",
519 "Transaction Layer"
520};
521
db89ccbe 522static const char *aer_correctable_error_string[AER_MAX_TYPEOF_COR_ERRS] = {
bd237801 523 "RxErr", /* Bit Position 0 */
0319c9a0
BH		 524 NULL,
525 NULL,
526 NULL,
527 NULL,
528 NULL,
bd237801
TB		 529 "BadTLP", /* Bit Position 6 */
530 "BadDLLP", /* Bit Position 7 */
531 "Rollover", /* Bit Position 8 */
0319c9a0
BH		 532 NULL,
533 NULL,
534 NULL,
bd237801
TB		 535 "Timeout", /* Bit Position 12 */
536 "NonFatalErr", /* Bit Position 13 */
537 "CorrIntErr", /* Bit Position 14 */
538 "HeaderOF", /* Bit Position 15 */
0319c9a0
BH		 539};
540
db89ccbe 541static const char *aer_uncorrectable_error_string[AER_MAX_TYPEOF_UNCOR_ERRS] = {
0319c9a0
BH		 542 "Undefined", /* Bit Position 0 */
543 NULL,
544 NULL,
545 NULL,
bd237801
TB		 546 "DLP", /* Bit Position 4 */
547 "SDES", /* Bit Position 5 */
0319c9a0
BH		 548 NULL,
549 NULL,
550 NULL,
551 NULL,
552 NULL,
553 NULL,
bd237801
TB		 554 "TLP", /* Bit Position 12 */
555 "FCP", /* Bit Position 13 */
556 "CmpltTO", /* Bit Position 14 */
557 "CmpltAbrt", /* Bit Position 15 */
558 "UnxCmplt", /* Bit Position 16 */
559 "RxOF", /* Bit Position 17 */
560 "MalfTLP", /* Bit Position 18 */
0319c9a0 561 "ECRC", /* Bit Position 19 */
bd237801
TB		 562 "UnsupReq", /* Bit Position 20 */
563 "ACSViol", /* Bit Position 21 */
564 "UncorrIntErr", /* Bit Position 22 */
565 "BlockedTLP", /* Bit Position 23 */
566 "AtomicOpBlocked", /* Bit Position 24 */
567 "TLPBlockedErr", /* Bit Position 25 */
0319c9a0
BH		 568};
569
570static const char *aer_agent_string[] = {
571 "Receiver ID",
572 "Requester ID",
573 "Completer ID",
574 "Transmitter ID"
575};
576
81aa5206
RJ		 577#define aer_stats_dev_attr(name, stats_array, strings_array, \
578 total_string, total_field) \
579 static ssize_t \
580 name##_show(struct device *dev, struct device_attribute *attr, \
581 char *buf) \
582{ \
583 unsigned int i; \
584 char *str = buf; \
585 struct pci_dev *pdev = to_pci_dev(dev); \
586 u64 *stats = pdev->aer_stats->stats_array; \
587 \
588 for (i = 0; i < ARRAY_SIZE(strings_array); i++) { \
589 if (strings_array[i]) \
590 str += sprintf(str, "%s %llu\n", \
591 strings_array[i], stats[i]); \
592 else if (stats[i]) \
593 str += sprintf(str, #stats_array "_bit[%d] %llu\n",\
594 i, stats[i]); \
595 } \
596 str += sprintf(str, "TOTAL_%s %llu\n", total_string, \
597 pdev->aer_stats->total_field); \
598 return str-buf; \
599} \
600static DEVICE_ATTR_RO(name)
601
602aer_stats_dev_attr(aer_dev_correctable, dev_cor_errs,
603 aer_correctable_error_string, "ERR_COR",
604 dev_total_cor_errs);
605aer_stats_dev_attr(aer_dev_fatal, dev_fatal_errs,
606 aer_uncorrectable_error_string, "ERR_FATAL",
607 dev_total_fatal_errs);
608aer_stats_dev_attr(aer_dev_nonfatal, dev_nonfatal_errs,
609 aer_uncorrectable_error_string, "ERR_NONFATAL",
610 dev_total_nonfatal_errs);
611
12833017
RJ		 612#define aer_stats_rootport_attr(name, field) \
613 static ssize_t \
614 name##_show(struct device *dev, struct device_attribute *attr, \
615 char *buf) \
616{ \
617 struct pci_dev *pdev = to_pci_dev(dev); \
618 return sprintf(buf, "%llu\n", pdev->aer_stats->field); \
619} \
620static DEVICE_ATTR_RO(name)
621
622aer_stats_rootport_attr(aer_rootport_total_err_cor,
623 rootport_total_cor_errs);
624aer_stats_rootport_attr(aer_rootport_total_err_fatal,
625 rootport_total_fatal_errs);
626aer_stats_rootport_attr(aer_rootport_total_err_nonfatal,
627 rootport_total_nonfatal_errs);
628
81aa5206
RJ		 629static struct attribute *aer_stats_attrs[] __ro_after_init = {
630 &dev_attr_aer_dev_correctable.attr,
631 &dev_attr_aer_dev_fatal.attr,
632 &dev_attr_aer_dev_nonfatal.attr,
12833017
RJ		 633 &dev_attr_aer_rootport_total_err_cor.attr,
634 &dev_attr_aer_rootport_total_err_fatal.attr,
635 &dev_attr_aer_rootport_total_err_nonfatal.attr,
81aa5206
RJ		 636 NULL
637};
638
639static umode_t aer_stats_attrs_are_visible(struct kobject *kobj,
640 struct attribute *a, int n)
641{
642 struct device *dev = kobj_to_dev(kobj);
643 struct pci_dev *pdev = to_pci_dev(dev);
644
645 if (!pdev->aer_stats)
646 return 0;
647
12833017
RJ		 648 if ((a == &dev_attr_aer_rootport_total_err_cor.attr ||
649 a == &dev_attr_aer_rootport_total_err_fatal.attr ||
650 a == &dev_attr_aer_rootport_total_err_nonfatal.attr) &&
651 pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT)
652 return 0;
653
81aa5206
RJ		 654 return a->mode;
655}
656
657const struct attribute_group aer_stats_attr_group = {
658 .attrs = aer_stats_attrs,
659 .is_visible = aer_stats_attrs_are_visible,
660};
661
662static void pci_dev_aer_stats_incr(struct pci_dev *pdev,
663 struct aer_err_info *info)
664{
665 int status, i, max = -1;
666 u64 *counter = NULL;
667 struct aer_stats *aer_stats = pdev->aer_stats;
668
669 if (!aer_stats)
670 return;
671
672 switch (info->severity) {
673 case AER_CORRECTABLE:
674 aer_stats->dev_total_cor_errs++;
675 counter = &aer_stats->dev_cor_errs[0];
676 max = AER_MAX_TYPEOF_COR_ERRS;
677 break;
678 case AER_NONFATAL:
679 aer_stats->dev_total_nonfatal_errs++;
680 counter = &aer_stats->dev_nonfatal_errs[0];
681 max = AER_MAX_TYPEOF_UNCOR_ERRS;
682 break;
683 case AER_FATAL:
684 aer_stats->dev_total_fatal_errs++;
685 counter = &aer_stats->dev_fatal_errs[0];
686 max = AER_MAX_TYPEOF_UNCOR_ERRS;
687 break;
688 }
689
690 status = (info->status & ~info->mask);
691 for (i = 0; i < max; i++)
692 if (status & (1 << i))
693 counter[i]++;
694}
695
12833017
RJ		 696static void pci_rootport_aer_stats_incr(struct pci_dev *pdev,
697 struct aer_err_source *e_src)
698{
699 struct aer_stats *aer_stats = pdev->aer_stats;
700
701 if (!aer_stats)
702 return;
703
704 if (e_src->status & PCI_ERR_ROOT_COR_RCV)
705 aer_stats->rootport_total_cor_errs++;
706
707 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
708 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
709 aer_stats->rootport_total_fatal_errs++;
710 else
711 aer_stats->rootport_total_nonfatal_errs++;
712 }
713}
714
0319c9a0
BH		 715static void __print_tlp_header(struct pci_dev *dev,
716 struct aer_header_log_regs *t)
717{
718 pci_err(dev, " TLP Header: %08x %08x %08x %08x\n",
719 t->dw0, t->dw1, t->dw2, t->dw3);
720}
721
722static void __aer_print_error(struct pci_dev *dev,
723 struct aer_err_info *info)
724{
725 int i, status;
726 const char *errmsg = NULL;
727 status = (info->status & ~info->mask);
728
729 for (i = 0; i < 32; i++) {
730 if (!(status & (1 << i)))
731 continue;
732
733 if (info->severity == AER_CORRECTABLE)
734 errmsg = i < ARRAY_SIZE(aer_correctable_error_string) ?
735 aer_correctable_error_string[i] : NULL;
736 else
737 errmsg = i < ARRAY_SIZE(aer_uncorrectable_error_string) ?
738 aer_uncorrectable_error_string[i] : NULL;
739
740 if (errmsg)
741 pci_err(dev, " [%2d] %-22s%s\n", i, errmsg,
742 info->first_error == i ? " (First)" : "");
743 else
744 pci_err(dev, " [%2d] Unknown Error Bit%s\n",
745 i, info->first_error == i ? " (First)" : "");
746 }
81aa5206 747 pci_dev_aer_stats_incr(dev, info);
0319c9a0
BH		 748}
749
1e451160 750void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
0319c9a0
BH		 751{
752 int layer, agent;
753 int id = ((dev->bus->number << 8) | dev->devfn);
754
755 if (!info->status) {
756 pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
757 aer_error_severity_string[info->severity]);
758 goto out;
759 }
760
761 layer = AER_GET_LAYER_ERROR(info->severity, info->status);
762 agent = AER_GET_AGENT(info->severity, info->status);
763
764 pci_err(dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
765 aer_error_severity_string[info->severity],
766 aer_error_layer[layer], aer_agent_string[agent]);
767
768 pci_err(dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
769 dev->vendor, dev->device,
770 info->status, info->mask);
771
772 __aer_print_error(dev, info);
773
774 if (info->tlp_header_valid)
775 __print_tlp_header(dev, &info->tlp);
776
777out:
778 if (info->id && info->error_dev_num > 1 && info->id == id)
779 pci_err(dev, " Error of this Agent is reported first\n");
780
781 trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
782 info->severity, info->tlp_header_valid, &info->tlp);
783}
784
785static void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
786{
787 u8 bus = info->id >> 8;
788 u8 devfn = info->id & 0xff;
789
790 pci_info(dev, "AER: %s%s error received: %04x:%02x:%02x.%d\n",
791 info->multi_error_valid ? "Multiple " : "",
792 aer_error_severity_string[info->severity],
793 pci_domain_nr(dev->bus), bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
794}
795
796#ifdef CONFIG_ACPI_APEI_PCIEAER
797int cper_severity_to_aer(int cper_severity)
798{
799 switch (cper_severity) {
800 case CPER_SEV_RECOVERABLE:
801 return AER_NONFATAL;
802 case CPER_SEV_FATAL:
803 return AER_FATAL;
804 default:
805 return AER_CORRECTABLE;
806 }
807}
808EXPORT_SYMBOL_GPL(cper_severity_to_aer);
809
810void cper_print_aer(struct pci_dev *dev, int aer_severity,
811 struct aer_capability_regs *aer)
812{
813 int layer, agent, tlp_header_valid = 0;
814 u32 status, mask;
815 struct aer_err_info info;
816
817 if (aer_severity == AER_CORRECTABLE) {
818 status = aer->cor_status;
819 mask = aer->cor_mask;
820 } else {
821 status = aer->uncor_status;
822 mask = aer->uncor_mask;
823 tlp_header_valid = status & AER_LOG_TLP_MASKS;
824 }
825
826 layer = AER_GET_LAYER_ERROR(aer_severity, status);
827 agent = AER_GET_AGENT(aer_severity, status);
828
829 memset(&info, 0, sizeof(info));
830 info.severity = aer_severity;
831 info.status = status;
832 info.mask = mask;
833 info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);
834
835 pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
836 __aer_print_error(dev, &info);
837 pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
838 aer_error_layer[layer], aer_agent_string[agent]);
839
840 if (aer_severity != AER_CORRECTABLE)
841 pci_err(dev, "aer_uncor_severity: 0x%08x\n",
842 aer->uncor_severity);
843
844 if (tlp_header_valid)
845 __print_tlp_header(dev, &aer->header_log);
846
847 trace_aer_event(dev_name(&dev->dev), (status & ~mask),
848 aer_severity, tlp_header_valid, &aer->header_log);
849}
850#endif
851
fd3362cb
BH		 852/**
853 * add_error_device - list device to be handled
854 * @e_info: pointer to error info
855 * @dev: pointer to pci_dev to be added
856 */
857static int add_error_device(struct aer_err_info *e_info, struct pci_dev *dev)
858{
859 if (e_info->error_dev_num < AER_MAX_MULTI_ERR_DEVICES) {
860 e_info->dev[e_info->error_dev_num] = dev;
861 e_info->error_dev_num++;
862 return 0;
863 }
864 return -ENOSPC;
865}
866
867/**
868 * is_error_source - check whether the device is source of reported error
869 * @dev: pointer to pci_dev to be checked
870 * @e_info: pointer to reported error info
871 */
872static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
873{
874 int pos;
875 u32 status, mask;
876 u16 reg16;
877
878 /*
879 * When bus id is equal to 0, it might be a bad id
880 * reported by root port.
881 */
882 if ((PCI_BUS_NUM(e_info->id) != 0) &&
883 !(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_AERSID)) {
884 /* Device ID match? */
885 if (e_info->id == ((dev->bus->number << 8) | dev->devfn))
886 return true;
887
888 /* Continue id comparing if there is no multiple error */
889 if (!e_info->multi_error_valid)
890 return false;
891 }
892
893 /*
894 * When either
895 * 1) bus id is equal to 0. Some ports might lose the bus
896 * id of error source id;
897 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
898 * 3) There are multiple errors and prior ID comparing fails;
899 * We check AER status registers to find possible reporter.
900 */
901 if (atomic_read(&dev->enable_cnt) == 0)
902 return false;
903
904 /* Check if AER is enabled */
905 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &reg16);
906 if (!(reg16 & PCI_EXP_AER_FLAGS))
907 return false;
908
909 pos = dev->aer_cap;
910 if (!pos)
911 return false;
912
913 /* Check if error is recorded */
914 if (e_info->severity == AER_CORRECTABLE) {
915 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &status);
916 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &mask);
917 } else {
918 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
919 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask);
920 }
921 if (status & ~mask)
922 return true;
923
924 return false;
925}
926
927static int find_device_iter(struct pci_dev *dev, void *data)
928{
929 struct aer_err_info *e_info = (struct aer_err_info *)data;
930
931 if (is_error_source(dev, e_info)) {
932 /* List this device */
933 if (add_error_device(e_info, dev)) {
934 /* We cannot handle more... Stop iteration */
935 /* TODO: Should print error message here? */
936 return 1;
937 }
938
939 /* If there is only a single error, stop iteration */
940 if (!e_info->multi_error_valid)
941 return 1;
942 }
943 return 0;
944}
945
946/**
947 * find_source_device - search through device hierarchy for source device
948 * @parent: pointer to Root Port pci_dev data structure
949 * @e_info: including detailed error information such like id
950 *
951 * Return true if found.
952 *
953 * Invoked by DPC when error is detected at the Root Port.
954 * Caller of this function must set id, severity, and multi_error_valid of
955 * struct aer_err_info pointed by @e_info properly. This function must fill
956 * e_info->error_dev_num and e_info->dev[], based on the given information.
957 */
958static bool find_source_device(struct pci_dev *parent,
959 struct aer_err_info *e_info)
960{
961 struct pci_dev *dev = parent;
962 int result;
963
964 /* Must reset in this function */
965 e_info->error_dev_num = 0;
966
967 /* Is Root Port an agent that sends error message? */
968 result = find_device_iter(dev, e_info);
969 if (result)
970 return true;
971
972 pci_walk_bus(parent->subordinate, find_device_iter, e_info);
973
974 if (!e_info->error_dev_num) {
975 pci_printk(KERN_DEBUG, parent, "can't find device of ID%04x\n",
976 e_info->id);
977 return false;
978 }
979 return true;
980}
981
982/**
983 * handle_error_source - handle logging error into an event log
984 * @dev: pointer to pci_dev data structure of error source device
985 * @info: comprehensive error information
986 *
987 * Invoked when an error being detected by Root Port.
988 */
989static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
990{
991 int pos;
992
993 if (info->severity == AER_CORRECTABLE) {
994 /*
995 * Correctable error does not need software intervention.
996 * No need to go through error recovery process.
997 */
998 pos = dev->aer_cap;
999 if (pos)
1000 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS,
1001 info->status);
10d790d9 1002 pci_aer_clear_device_status(dev);
fd3362cb
BH		 1003 } else if (info->severity == AER_NONFATAL)
1004 pcie_do_nonfatal_recovery(dev);
1005 else if (info->severity == AER_FATAL)
1006 pcie_do_fatal_recovery(dev, PCIE_PORT_SERVICE_AER);
1007}
1008
1009#ifdef CONFIG_ACPI_APEI_PCIEAER
1010
1011#define AER_RECOVER_RING_ORDER 4
1012#define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
1013
1014struct aer_recover_entry {
1015 u8 bus;
1016 u8 devfn;
1017 u16 domain;
1018 int severity;
1019 struct aer_capability_regs *regs;
1020};
1021
1022static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
1023 AER_RECOVER_RING_SIZE);
1024
1025static void aer_recover_work_func(struct work_struct *work)
1026{
1027 struct aer_recover_entry entry;
1028 struct pci_dev *pdev;
1029
1030 while (kfifo_get(&aer_recover_ring, &entry)) {
1031 pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
1032 entry.devfn);
1033 if (!pdev) {
1034 pr_err("AER recover: Can not find pci_dev for %04x:%02x:%02x:%x\n",
1035 entry.domain, entry.bus,
1036 PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
1037 continue;
1038 }
1039 cper_print_aer(pdev, entry.severity, entry.regs);
1040 if (entry.severity == AER_NONFATAL)
1041 pcie_do_nonfatal_recovery(pdev);
1042 else if (entry.severity == AER_FATAL)
1043 pcie_do_fatal_recovery(pdev, PCIE_PORT_SERVICE_AER);
1044 pci_dev_put(pdev);
1045 }
1046}
1047
1048/*
1049 * Mutual exclusion for writers of aer_recover_ring, reader side don't
1050 * need lock, because there is only one reader and lock is not needed
1051 * between reader and writer.
1052 */
1053static DEFINE_SPINLOCK(aer_recover_ring_lock);
1054static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
1055
1056void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
1057 int severity, struct aer_capability_regs *aer_regs)
1058{
1059 unsigned long flags;
1060 struct aer_recover_entry entry = {
1061 .bus = bus,
1062 .devfn = devfn,
1063 .domain = domain,
1064 .severity = severity,
1065 .regs = aer_regs,
1066 };
1067
1068 spin_lock_irqsave(&aer_recover_ring_lock, flags);
1069 if (kfifo_put(&aer_recover_ring, entry))
1070 schedule_work(&aer_recover_work);
1071 else
1072 pr_err("AER recover: Buffer overflow when recovering AER for %04x:%02x:%02x:%x\n",
1073 domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1074 spin_unlock_irqrestore(&aer_recover_ring_lock, flags);
1075}
1076EXPORT_SYMBOL_GPL(aer_recover_queue);
1077#endif
1078
1079/**
1e451160 1080 * aer_get_device_error_info - read error status from dev and store it to info
fd3362cb
BH		 1081 * @dev: pointer to the device expected to have a error record
1082 * @info: pointer to structure to store the error record
1083 *
1084 * Return 1 on success, 0 on error.
1085 *
1086 * Note that @info is reused among all error devices. Clear fields properly.
1087 */
1e451160 1088int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
fd3362cb
BH		 1089{
1090 int pos, temp;
1091
1092 /* Must reset in this function */
1093 info->status = 0;
1094 info->tlp_header_valid = 0;
1095
1096 pos = dev->aer_cap;
1097
1098 /* The device might not support AER */
1099 if (!pos)
1100 return 0;
1101
1102 if (info->severity == AER_CORRECTABLE) {
1103 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS,
1104 &info->status);
1105 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK,
1106 &info->mask);
1107 if (!(info->status & ~info->mask))
1108 return 0;
1109 } else if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1110 info->severity == AER_NONFATAL) {
1111
1112 /* Link is still healthy for IO reads */
1113 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
1114 &info->status);
1115 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK,
1116 &info->mask);
1117 if (!(info->status & ~info->mask))
1118 return 0;
1119
1120 /* Get First Error Pointer */
1121 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &temp);
1122 info->first_error = PCI_ERR_CAP_FEP(temp);
1123
1124 if (info->status & AER_LOG_TLP_MASKS) {
1125 info->tlp_header_valid = 1;
1126 pci_read_config_dword(dev,
1127 pos + PCI_ERR_HEADER_LOG, &info->tlp.dw0);
1128 pci_read_config_dword(dev,
1129 pos + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);
1130 pci_read_config_dword(dev,
1131 pos + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);
1132 pci_read_config_dword(dev,
1133 pos + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);
1134 }
1135 }
1136
1137 return 1;
1138}
1139
1140static inline void aer_process_err_devices(struct aer_err_info *e_info)
1141{
1142 int i;
1143
1144 /* Report all before handle them, not to lost records by reset etc. */
1145 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1e451160 1146 if (aer_get_device_error_info(e_info->dev[i], e_info))
fd3362cb
BH		 1147 aer_print_error(e_info->dev[i], e_info);
1148 }
1149 for (i = 0; i < e_info->error_dev_num && e_info->dev[i]; i++) {
1e451160 1150 if (aer_get_device_error_info(e_info->dev[i], e_info))
fd3362cb
BH		 1151 handle_error_source(e_info->dev[i], e_info);
1152 }
1153}
1154
1155/**
1156 * aer_isr_one_error - consume an error detected by root port
1157 * @rpc: pointer to the root port which holds an error
1158 * @e_src: pointer to an error source
1159 */
1160static void aer_isr_one_error(struct aer_rpc *rpc,
1161 struct aer_err_source *e_src)
1162{
1163 struct pci_dev *pdev = rpc->rpd;
1164 struct aer_err_info *e_info = &rpc->e_info;
1165
12833017
RJ		 1166 pci_rootport_aer_stats_incr(pdev, e_src);
1167
fd3362cb
BH		 1168 /*
1169 * There is a possibility that both correctable error and
1170 * uncorrectable error being logged. Report correctable error first.
1171 */
1172 if (e_src->status & PCI_ERR_ROOT_COR_RCV) {
1173 e_info->id = ERR_COR_ID(e_src->id);
1174 e_info->severity = AER_CORRECTABLE;
1175
1176 if (e_src->status & PCI_ERR_ROOT_MULTI_COR_RCV)
1177 e_info->multi_error_valid = 1;
1178 else
1179 e_info->multi_error_valid = 0;
1180 aer_print_port_info(pdev, e_info);
1181
1182 if (find_source_device(pdev, e_info))
1183 aer_process_err_devices(e_info);
1184 }
1185
1186 if (e_src->status & PCI_ERR_ROOT_UNCOR_RCV) {
1187 e_info->id = ERR_UNCOR_ID(e_src->id);
1188
1189 if (e_src->status & PCI_ERR_ROOT_FATAL_RCV)
1190 e_info->severity = AER_FATAL;
1191 else
1192 e_info->severity = AER_NONFATAL;
1193
1194 if (e_src->status & PCI_ERR_ROOT_MULTI_UNCOR_RCV)
1195 e_info->multi_error_valid = 1;
1196 else
1197 e_info->multi_error_valid = 0;
1198
1199 aer_print_port_info(pdev, e_info);
1200
1201 if (find_source_device(pdev, e_info))
1202 aer_process_err_devices(e_info);
1203 }
1204}
1205
1206/**
1207 * get_e_source - retrieve an error source
1208 * @rpc: pointer to the root port which holds an error
1209 * @e_src: pointer to store retrieved error source
1210 *
1211 * Return 1 if an error source is retrieved, otherwise 0.
1212 *
1213 * Invoked by DPC handler to consume an error.
1214 */
1215static int get_e_source(struct aer_rpc *rpc, struct aer_err_source *e_src)
1216{
1217 unsigned long flags;
1218
1219 /* Lock access to Root error producer/consumer index */
1220 spin_lock_irqsave(&rpc->e_lock, flags);
1221 if (rpc->prod_idx == rpc->cons_idx) {
1222 spin_unlock_irqrestore(&rpc->e_lock, flags);
1223 return 0;
1224 }
1225
1226 *e_src = rpc->e_sources[rpc->cons_idx];
1227 rpc->cons_idx++;
1228 if (rpc->cons_idx == AER_ERROR_SOURCES_MAX)
1229 rpc->cons_idx = 0;
1230 spin_unlock_irqrestore(&rpc->e_lock, flags);
1231
1232 return 1;
1233}
1234
1235/**
1236 * aer_isr - consume errors detected by root port
1237 * @work: definition of this work item
1238 *
1239 * Invoked, as DPC, when root port records new detected error
1240 */
1241static void aer_isr(struct work_struct *work)
1242{
1243 struct aer_rpc *rpc = container_of(work, struct aer_rpc, dpc_handler);
1244 struct aer_err_source uninitialized_var(e_src);
1245
1246 mutex_lock(&rpc->rpc_mutex);
1247 while (get_e_source(rpc, &e_src))
1248 aer_isr_one_error(rpc, &e_src);
1249 mutex_unlock(&rpc->rpc_mutex);
1250}
1251
3c43a64c
BH		 1252/**
1253 * aer_irq - Root Port's ISR
1254 * @irq: IRQ assigned to Root Port
1255 * @context: pointer to Root Port data structure
1256 *
1257 * Invoked when Root Port detects AER messages.
1258 */
1259irqreturn_t aer_irq(int irq, void *context)
1260{
1261 unsigned int status, id;
1262 struct pcie_device *pdev = (struct pcie_device *)context;
1263 struct aer_rpc *rpc = get_service_data(pdev);
1264 int next_prod_idx;
1265 unsigned long flags;
1266 int pos;
1267
1268 pos = pdev->port->aer_cap;
1269 /*
1270 * Must lock access to Root Error Status Reg, Root Error ID Reg,
1271 * and Root error producer/consumer index
1272 */
1273 spin_lock_irqsave(&rpc->e_lock, flags);
1274
1275 /* Read error status */
1276 pci_read_config_dword(pdev->port, pos + PCI_ERR_ROOT_STATUS, &status);
1277 if (!(status & (PCI_ERR_ROOT_UNCOR_RCV|PCI_ERR_ROOT_COR_RCV))) {
1278 spin_unlock_irqrestore(&rpc->e_lock, flags);
1279 return IRQ_NONE;
1280 }
1281
1282 /* Read error source and clear error status */
1283 pci_read_config_dword(pdev->port, pos + PCI_ERR_ROOT_ERR_SRC, &id);
1284 pci_write_config_dword(pdev->port, pos + PCI_ERR_ROOT_STATUS, status);
1285
1286 /* Store error source for later DPC handler */
1287 next_prod_idx = rpc->prod_idx + 1;
1288 if (next_prod_idx == AER_ERROR_SOURCES_MAX)
1289 next_prod_idx = 0;
1290 if (next_prod_idx == rpc->cons_idx) {
1291 /*
1292 * Error Storm Condition - possibly the same error occurred.
1293 * Drop the error.
1294 */
1295 spin_unlock_irqrestore(&rpc->e_lock, flags);
1296 return IRQ_HANDLED;
1297 }
1298 rpc->e_sources[rpc->prod_idx].status = status;
1299 rpc->e_sources[rpc->prod_idx].id = id;
1300 rpc->prod_idx = next_prod_idx;
1301 spin_unlock_irqrestore(&rpc->e_lock, flags);
1302
1303 /* Invoke DPC handler */
1304 schedule_work(&rpc->dpc_handler);
1305
1306 return IRQ_HANDLED;
1307}
1308EXPORT_SYMBOL_GPL(aer_irq);
1309
843f4697
HS		 1310static int set_device_error_reporting(struct pci_dev *dev, void *data)
1311{
1312 bool enable = *((bool *)data);
62f87c0e 1313 int type = pci_pcie_type(dev);
843f4697 1314
62f87c0e
YW		 1315 if ((type == PCI_EXP_TYPE_ROOT_PORT) ||
1316 (type == PCI_EXP_TYPE_UPSTREAM) ||
1317 (type == PCI_EXP_TYPE_DOWNSTREAM)) {
843f4697
HS		 1318 if (enable)
1319 pci_enable_pcie_error_reporting(dev);
1320 else
1321 pci_disable_pcie_error_reporting(dev);
1322 }
1323
1324 if (enable)
1325 pcie_set_ecrc_checking(dev);
1326
1327 return 0;
1328}
1329
1330/**
1331 * set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports.
1332 * @dev: pointer to root port's pci_dev data structure
1333 * @enable: true = enable error reporting, false = disable error reporting.
1334 */
1335static void set_downstream_devices_error_reporting(struct pci_dev *dev,
1336 bool enable)
1337{
1338 set_device_error_reporting(dev, &enable);
1339
1340 if (!dev->subordinate)
1341 return;
1342 pci_walk_bus(dev->subordinate, set_device_error_reporting, &enable);
1343}
1344
1345/**
1346 * aer_enable_rootport - enable Root Port's interrupts when receiving messages
1347 * @rpc: pointer to a Root Port data structure
1348 *
1349 * Invoked when PCIe bus loads AER service driver.
1350 */
1351static void aer_enable_rootport(struct aer_rpc *rpc)
1352{
e13d17f7 1353 struct pci_dev *pdev = rpc->rpd;
43bd4ee8 1354 int aer_pos;
843f4697
HS		 1355 u16 reg16;
1356 u32 reg32;
1357
843f4697 1358 /* Clear PCIe Capability's Device Status */
43bd4ee8
JL		 1359 pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, &reg16);
1360 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16);
843f4697
HS		 1361
1362 /* Disable system error generation in response to error messages */
43bd4ee8
JL		 1363 pcie_capability_clear_word(pdev, PCI_EXP_RTCTL,
1364 SYSTEM_ERROR_INTR_ON_MESG_MASK);
843f4697 1365
66b80809 1366 aer_pos = pdev->aer_cap;
843f4697
HS		 1367 /* Clear error status */
1368 pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, &reg32);
1369 pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, reg32);
1370 pci_read_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, &reg32);
1371 pci_write_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, reg32);
1372 pci_read_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, &reg32);
1373 pci_write_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, reg32);
1374
1375 /*
1376 * Enable error reporting for the root port device and downstream port
1377 * devices.
1378 */
1379 set_downstream_devices_error_reporting(pdev, true);
1380
1381 /* Enable Root Port's interrupt in response to error messages */
1382 pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, &reg32);
1383 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1384 pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, reg32);
1385}
1386
1387/**
1388 * aer_disable_rootport - disable Root Port's interrupts when receiving messages
1389 * @rpc: pointer to a Root Port data structure
1390 *
1391 * Invoked when PCIe bus unloads AER service driver.
1392 */
1393static void aer_disable_rootport(struct aer_rpc *rpc)
1394{
e13d17f7 1395 struct pci_dev *pdev = rpc->rpd;
843f4697
HS		 1396 u32 reg32;
1397 int pos;
1398
1399 /*
1400 * Disable error reporting for the root port device and downstream port
1401 * devices.
1402 */
1403 set_downstream_devices_error_reporting(pdev, false);
1404
66b80809 1405 pos = pdev->aer_cap;
843f4697
HS		 1406 /* Disable Root's interrupt in response to error messages */
1407 pci_read_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, &reg32);
1408 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1409 pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, reg32);
1410
1411 /* Clear Root's error status reg */
1412 pci_read_config_dword(pdev, pos + PCI_ERR_ROOT_STATUS, &reg32);
1413 pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_STATUS, reg32);
1414}
1415
6c2b374d
ZY		 1416/**
1417 * aer_alloc_rpc - allocate Root Port data structure
1418 * @dev: pointer to the pcie_dev data structure
1419 *
1420 * Invoked when Root Port's AER service is loaded.
f6d37800 1421 */
c9a91883 1422static struct aer_rpc *aer_alloc_rpc(struct pcie_device *dev)
6c2b374d
ZY		 1423{
1424 struct aer_rpc *rpc;
1425
c9a91883
HS		 1426 rpc = kzalloc(sizeof(struct aer_rpc), GFP_KERNEL);
1427 if (!rpc)
6c2b374d
ZY		 1428 return NULL;
1429
f6d37800 1430 /* Initialize Root lock access, e_lock, to Root Error Status Reg */
f5609d7e 1431 spin_lock_init(&rpc->e_lock);
6c2b374d 1432
e13d17f7 1433 rpc->rpd = dev->port;
65f27f38 1434 INIT_WORK(&rpc->dpc_handler, aer_isr);
6c2b374d 1435 mutex_init(&rpc->rpc_mutex);
6c2b374d 1436
45e829ea 1437 /* Use PCIe bus function to store rpc into PCIe device */
6c2b374d
ZY		 1438 set_service_data(dev, rpc);
1439
1440 return rpc;
1441}
1442
1443/**
1444 * aer_remove - clean up resources
1445 * @dev: pointer to the pcie_dev data structure
1446 *
1447 * Invoked when PCI Express bus unloads or AER probe fails.
f6d37800 1448 */
6c2b374d
ZY		 1449static void aer_remove(struct pcie_device *dev)
1450{
1451 struct aer_rpc *rpc = get_service_data(dev);
1452
1453 if (rpc) {
1454 /* If register interrupt service, it must be free. */
1455 if (rpc->isr)
1456 free_irq(dev->irq, dev);
1457
4ae2182b 1458 flush_work(&rpc->dpc_handler);
460d298d
HS		 1459 aer_disable_rootport(rpc);
1460 kfree(rpc);
6c2b374d
ZY		 1461 set_service_data(dev, NULL);
1462 }
1463}
1464
1465/**
1466 * aer_probe - initialize resources
1467 * @dev: pointer to the pcie_dev data structure
6c2b374d
ZY		 1468 *
1469 * Invoked when PCI Express bus loads AER service driver.
f6d37800 1470 */
15856ad5 1471static int aer_probe(struct pcie_device *dev)
6c2b374d
ZY		 1472{
1473 int status;
1474 struct aer_rpc *rpc;
576700b6 1475 struct device *device = &dev->port->dev;
6c2b374d 1476
6c2b374d 1477 /* Alloc rpc data structure */
c9a91883
HS		 1478 rpc = aer_alloc_rpc(dev);
1479 if (!rpc) {
576700b6 1480 dev_printk(KERN_DEBUG, device, "alloc AER rpc failed\n");
6c2b374d
ZY		 1481 aer_remove(dev);
1482 return -ENOMEM;
1483 }
1484
1485 /* Request IRQ ISR */
c9a91883
HS		 1486 status = request_irq(dev->irq, aer_irq, IRQF_SHARED, "aerdrv", dev);
1487 if (status) {
576700b6
BH		 1488 dev_printk(KERN_DEBUG, device, "request AER IRQ %d failed\n",
1489 dev->irq);
6c2b374d
ZY		 1490 aer_remove(dev);
1491 return status;
1492 }
1493
1494 rpc->isr = 1;
1495
1496 aer_enable_rootport(rpc);
68a55ae5
BH		 1497 dev_info(device, "AER enabled with IRQ %d\n", dev->irq);
1498 return 0;
6c2b374d
ZY		 1499}
1500
1501/**
1502 * aer_root_reset - reset link on Root Port
1503 * @dev: pointer to Root Port's pci_dev data structure
1504 *
1505 * Invoked by Port Bus driver when performing link reset at Root Port.
f6d37800 1506 */
6c2b374d
ZY		 1507static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
1508{
c6d34edd 1509 u32 reg32;
6c2b374d
ZY		 1510 int pos;
1511
66b80809 1512 pos = dev->aer_cap;
6c2b374d
ZY		 1513
1514 /* Disable Root's interrupt in response to error messages */
c6d34edd
HS		 1515 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, &reg32);
1516 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
1517 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
6c2b374d 1518
1b95ce8f 1519 pci_reset_bridge_secondary_bus(dev);
7506dc79 1520 pci_printk(KERN_DEBUG, dev, "Root Port link has been reset\n");
6c2b374d 1521
c6d34edd
HS		 1522 /* Clear Root Error Status */
1523 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &reg32);
1524 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, reg32);
1525
6c2b374d 1526 /* Enable Root Port's interrupt in response to error messages */
c6d34edd
HS		 1527 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, &reg32);
1528 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
1529 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
6c2b374d
ZY		 1530
1531 return PCI_ERS_RESULT_RECOVERED;
1532}
1533
6c2b374d
ZY		 1534/**
1535 * aer_error_resume - clean up corresponding error status bits
1536 * @dev: pointer to Root Port's pci_dev data structure
1537 *
1538 * Invoked by Port Bus driver during nonfatal recovery.
f6d37800 1539 */
6c2b374d
ZY		 1540static void aer_error_resume(struct pci_dev *dev)
1541{
ec752f5d 1542 pci_aer_clear_device_status(dev);
5b6c0966 1543 pci_cleanup_aer_uncorrect_error_status(dev);
6c2b374d
ZY		 1544}
1545
0054ca8e
BH		 1546static struct pcie_port_service_driver aerdriver = {
1547 .name = "aer",
1548 .port_type = PCI_EXP_TYPE_ROOT_PORT,
1549 .service = PCIE_PORT_SERVICE_AER,
1550
1551 .probe = aer_probe,
1552 .remove = aer_remove,
1553 .error_resume = aer_error_resume,
1554 .reset_link = aer_root_reset,
1555};
1556
6c2b374d
ZY		 1557/**
1558 * aer_service_init - register AER root service driver
1559 *
1560 * Invoked when AER root service driver is loaded.
f6d37800 1561 */
6c2b374d
ZY		 1562static int __init aer_service_init(void)
1563{
b22c3d82 1564 if (!pci_aer_available() || aer_acpi_firmware_first())
3e77a3f7 1565 return -ENXIO;
c1996c27 1566 return pcie_port_service_register(&aerdriver);
6c2b374d 1567}
8756336c 1568device_initcall(aer_service_init);
Linux 6.x block layer and io_uring tree(s)