[linux-2.6-block.git] / drivers / pci / pci.h

#ifndef DRIVERS_PCI_H
#define DRIVERS_PCI_H

#include <linux/workqueue.h>

#define PCI_CFG_SPACE_SIZE	256
#define PCI_CFG_SPACE_EXP_SIZE	4096

extern const unsigned char pcix_bus_speed[];
extern const unsigned char pcie_link_speed[];

/* Functions internal to the PCI core code */

int pci_create_sysfs_dev_files(struct pci_dev *pdev);
void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
{ return; }
static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
{ return; }
#else
void pci_create_firmware_label_files(struct pci_dev *pdev);
void pci_remove_firmware_label_files(struct pci_dev *pdev);
#endif
void pci_cleanup_rom(struct pci_dev *dev);
#ifdef HAVE_PCI_MMAP
enum pci_mmap_api {
	PCI_MMAP_SYSFS,	/* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	PCI_MMAP_PROCFS	/* mmap on /proc/bus/pci/<BDF> */
};
int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
		  enum pci_mmap_api mmap_api);
#endif
int pci_probe_reset_function(struct pci_dev *dev);

/**
 * struct pci_platform_pm_ops - Firmware PM callbacks
 *
 * @is_manageable: returns 'true' if given device is power manageable by the
 *                 platform firmware
 *
 * @set_state: invokes the platform firmware to set the device's power state
 *
 * @choose_state: returns PCI power state of given device preferred by the
 *                platform; to be used during system-wide transitions from a
 *                sleeping state to the working state and vice versa
 *
 * @sleep_wake: enables/disables the system wake up capability of given device
 *
 * @run_wake: enables/disables the platform to generate run-time wake-up events
 *		for given device (the device's wake-up capability has to be
 *		enabled by @sleep_wake for this feature to work)
 *
 * If given platform is generally capable of power managing PCI devices, all of
 * these callbacks are mandatory.
 */
struct pci_platform_pm_ops {
	bool (*is_manageable)(struct pci_dev *dev);
	int (*set_state)(struct pci_dev *dev, pci_power_t state);
	pci_power_t (*choose_state)(struct pci_dev *dev);
	int (*sleep_wake)(struct pci_dev *dev, bool enable);
	int (*run_wake)(struct pci_dev *dev, bool enable);
};

int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
void pci_power_up(struct pci_dev *dev);
void pci_disable_enabled_device(struct pci_dev *dev);
int pci_finish_runtime_suspend(struct pci_dev *dev);
int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
void pci_wakeup_bus(struct pci_bus *bus);
void pci_config_pm_runtime_get(struct pci_dev *dev);
void pci_config_pm_runtime_put(struct pci_dev *dev);
void pci_pm_init(struct pci_dev *dev);
void pci_allocate_cap_save_buffers(struct pci_dev *dev);
void pci_free_cap_save_buffers(struct pci_dev *dev);

static inline void pci_wakeup_event(struct pci_dev *dev)
{
	/* Wait 100 ms before the system can be put into a sleep state. */
	pm_wakeup_event(&dev->dev, 100);
}

static inline bool pci_is_bridge(struct pci_dev *pci_dev)
{
	return !!(pci_dev->subordinate);
}

struct pci_vpd_ops {
	ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
	ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
	void (*release)(struct pci_dev *dev);
};

struct pci_vpd {
	unsigned int len;
	const struct pci_vpd_ops *ops;
	struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
};

int pci_vpd_pci22_init(struct pci_dev *dev);
static inline void pci_vpd_release(struct pci_dev *dev)
{
	if (dev->vpd)
		dev->vpd->ops->release(dev);
}

/* PCI /proc functions */
#ifdef CONFIG_PROC_FS
int pci_proc_attach_device(struct pci_dev *dev);
int pci_proc_detach_device(struct pci_dev *dev);
int pci_proc_detach_bus(struct pci_bus *bus);
#else
static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
#endif

/* Functions for PCI Hotplug drivers to use */
int pci_hp_add_bridge(struct pci_dev *dev);

#ifdef HAVE_PCI_LEGACY
void pci_create_legacy_files(struct pci_bus *bus);
void pci_remove_legacy_files(struct pci_bus *bus);
#else
static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
#endif

/* Lock for read/write access to pci device and bus lists */
extern struct rw_semaphore pci_bus_sem;

extern raw_spinlock_t pci_lock;

extern unsigned int pci_pm_d3_delay;

#ifdef CONFIG_PCI_MSI
void pci_no_msi(void);
void pci_msi_init_pci_dev(struct pci_dev *dev);
#else
static inline void pci_no_msi(void) { }
static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
#endif

void pci_realloc_get_opt(char *);

static inline int pci_no_d1d2(struct pci_dev *dev)
{
	unsigned int parent_dstates = 0;

	if (dev->bus->self)
		parent_dstates = dev->bus->self->no_d1d2;
	return (dev->no_d1d2 || parent_dstates);

}
extern struct device_attribute pci_dev_attrs[];
extern const struct attribute_group *pcibus_groups[];
extern struct device_type pci_dev_type;
extern const struct attribute_group *pci_bus_groups[];


/**
 * pci_match_one_device - Tell if a PCI device structure has a matching
 *                        PCI device id structure
 * @id: single PCI device id structure to match
 * @dev: the PCI device structure to match against
 *
 * Returns the matching pci_device_id structure or %NULL if there is no match.
 */
static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
{
	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
	    (id->device == PCI_ANY_ID || id->device == dev->device) &&
	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
	    !((id->class ^ dev->class) & id->class_mask))
		return id;
	return NULL;
}

/* PCI slot sysfs helper code */
#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)

extern struct kset *pci_slots_kset;

struct pci_slot_attribute {
	struct attribute attr;
	ssize_t (*show)(struct pci_slot *, char *);
	ssize_t (*store)(struct pci_slot *, const char *, size_t);
};
#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)

enum pci_bar_type {
	pci_bar_unknown,	/* Standard PCI BAR probe */
	pci_bar_io,		/* An io port BAR */
	pci_bar_mem32,		/* A 32-bit memory BAR */
	pci_bar_mem64,		/* A 64-bit memory BAR */
};

bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
				int crs_timeout);
int pci_setup_device(struct pci_dev *dev);
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
		    struct resource *res, unsigned int reg);
int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type);
void pci_configure_ari(struct pci_dev *dev);
void __ref __pci_bus_size_bridges(struct pci_bus *bus,
			struct list_head *realloc_head);
void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
				      struct list_head *realloc_head,
				      struct list_head *fail_head);

/**
 * pci_ari_enabled - query ARI forwarding status
 * @bus: the PCI bus
 *
 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 */
static inline int pci_ari_enabled(struct pci_bus *bus)
{
	return bus->self && bus->self->ari_enabled;
}

void pci_reassigndev_resource_alignment(struct pci_dev *dev);
void pci_disable_bridge_window(struct pci_dev *dev);

/* Single Root I/O Virtualization */
struct pci_sriov {
	int pos;		/* capability position */
	int nres;		/* number of resources */
	u32 cap;		/* SR-IOV Capabilities */
	u16 ctrl;		/* SR-IOV Control */
	u16 total_VFs;		/* total VFs associated with the PF */
	u16 initial_VFs;	/* initial VFs associated with the PF */
	u16 num_VFs;		/* number of VFs available */
	u16 offset;		/* first VF Routing ID offset */
	u16 stride;		/* following VF stride */
	u32 pgsz;		/* page size for BAR alignment */
	u8 link;		/* Function Dependency Link */
	u16 driver_max_VFs;	/* max num VFs driver supports */
	struct pci_dev *dev;	/* lowest numbered PF */
	struct pci_dev *self;	/* this PF */
	struct mutex lock;	/* lock for VF bus */
	struct work_struct mtask; /* VF Migration task */
	u8 __iomem *mstate;	/* VF Migration State Array */
};

#ifdef CONFIG_PCI_ATS
void pci_restore_ats_state(struct pci_dev *dev);
#else
static inline void pci_restore_ats_state(struct pci_dev *dev)
{
}
#endif /* CONFIG_PCI_ATS */

#ifdef CONFIG_PCI_IOV
int pci_iov_init(struct pci_dev *dev);
void pci_iov_release(struct pci_dev *dev);
int pci_iov_resource_bar(struct pci_dev *dev, int resno,
			 enum pci_bar_type *type);
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
void pci_restore_iov_state(struct pci_dev *dev);
int pci_iov_bus_range(struct pci_bus *bus);

#else
static inline int pci_iov_init(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline void pci_iov_release(struct pci_dev *dev)

{
}
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				       enum pci_bar_type *type)
{
	return 0;
}
static inline void pci_restore_iov_state(struct pci_dev *dev)
{
}
static inline int pci_iov_bus_range(struct pci_bus *bus)
{
	return 0;
}

#endif /* CONFIG_PCI_IOV */

unsigned long pci_cardbus_resource_alignment(struct resource *);

static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
						     struct resource *res)
{
#ifdef CONFIG_PCI_IOV
	int resno = res - dev->resource;

	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		return pci_sriov_resource_alignment(dev, resno);
#endif
	if (dev->class >> 8  == PCI_CLASS_BRIDGE_CARDBUS)
		return pci_cardbus_resource_alignment(res);
	return resource_alignment(res);
}

void pci_enable_acs(struct pci_dev *dev);

struct pci_dev_reset_methods {
	u16 vendor;
	u16 device;
	int (*reset)(struct pci_dev *dev, int probe);
};

#ifdef CONFIG_PCI_QUIRKS
int pci_dev_specific_reset(struct pci_dev *dev, int probe);
#else
static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	return -ENOTTY;
}
#endif

#endif /* DRIVERS_PCI_H */
Commit	Line	Data
557848c3 ZY	1	#ifndef DRIVERS_PCI_H
	2	#define DRIVERS_PCI_H
	3
74bb1bcc YZ	4	#include <linux/workqueue.h>
74bb1bcc YZ	5
557848c3 ZY	6	#define PCI_CFG_SPACE_SIZE 256
	7	#define PCI_CFG_SPACE_EXP_SIZE 4096
	8
343e51ae JK	9	extern const unsigned char pcix_bus_speed[];
	10	extern const unsigned char pcie_link_speed[];
	11
1da177e4 LT	12	/* Functions internal to the PCI core code */
1da177e4 LT	13
f39d5b72 BH	14	int pci_create_sysfs_dev_files(struct pci_dev *pdev);
f39d5b72 BH	15	void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
6058989b	16	#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
911e1c9b	17	static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
b879743f	18	{ return; }
911e1c9b	19	static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
b879743f	20	{ return; }
911e1c9b	21	#else
f39d5b72 BH	22	void pci_create_firmware_label_files(struct pci_dev *pdev);
f39d5b72 BH	23	void pci_remove_firmware_label_files(struct pci_dev *pdev);
911e1c9b	24	#endif
f39d5b72	25	void pci_cleanup_rom(struct pci_dev *dev);
9eff02e2	26	#ifdef HAVE_PCI_MMAP
3b519e4e MW	27	enum pci_mmap_api {
	28	PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	29	PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
	30	};
f39d5b72 BH	31	int pci_mmap_fits(struct pci_dev pdev, int resno, struct vm_area_struct vmai,
f39d5b72 BH	32	enum pci_mmap_api mmap_api);
9eff02e2	33	#endif
711d5779	34	int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef	35
961d9120	36	/**
b33bfdef	37	* struct pci_platform_pm_ops - Firmware PM callbacks
961d9120	38	*
b33bfdef RD	39	* @is_manageable: returns 'true' if given device is power manageable by the
b33bfdef RD	40	* platform firmware
961d9120	41	*
b33bfdef	42	* @set_state: invokes the platform firmware to set the device's power state
961d9120	43	*
b33bfdef RD	44	* @choose_state: returns PCI power state of given device preferred by the
	45	* platform; to be used during system-wide transitions from a
	46	* sleeping state to the working state and vice versa
961d9120	47	*
b33bfdef	48	* @sleep_wake: enables/disables the system wake up capability of given device
eb9d0fe4	49	*
b67ea761 RW	50	* @run_wake: enables/disables the platform to generate run-time wake-up events
	51	* for given device (the device's wake-up capability has to be
	52	* enabled by @sleep_wake for this feature to work)
	53	*
961d9120 RW	54	* If given platform is generally capable of power managing PCI devices, all of
	55	* these callbacks are mandatory.
	56	*/
	57	struct pci_platform_pm_ops {
	58	bool (is_manageable)(struct pci_dev dev);
	59	int (set_state)(struct pci_dev dev, pci_power_t state);
	60	pci_power_t (choose_state)(struct pci_dev dev);
eb9d0fe4	61	int (sleep_wake)(struct pci_dev dev, bool enable);
b67ea761	62	int (run_wake)(struct pci_dev dev, bool enable);
961d9120 RW	63	};
961d9120 RW	64
f39d5b72 BH	65	int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
	66	void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
	67	void pci_power_up(struct pci_dev *dev);
	68	void pci_disable_enabled_device(struct pci_dev *dev);
	69	int pci_finish_runtime_suspend(struct pci_dev *dev);
	70	int __pci_pme_wakeup(struct pci_dev dev, void ign);
	71	void pci_wakeup_bus(struct pci_bus *bus);
	72	void pci_config_pm_runtime_get(struct pci_dev *dev);
	73	void pci_config_pm_runtime_put(struct pci_dev *dev);
	74	void pci_pm_init(struct pci_dev *dev);
	75	void pci_allocate_cap_save_buffers(struct pci_dev *dev);
f796841e	76	void pci_free_cap_save_buffers(struct pci_dev *dev);
aa8c6c93	77
b6e335ae RW	78	static inline void pci_wakeup_event(struct pci_dev *dev)
	79	{
	80	/* Wait 100 ms before the system can be put into a sleep state. */
	81	pm_wakeup_event(&dev->dev, 100);
	82	}
	83
aa8c6c93 RW	84	static inline bool pci_is_bridge(struct pci_dev *pci_dev)
	85	{
	86	return !!(pci_dev->subordinate);
	87	}
0f64474b	88
94e61088	89	struct pci_vpd_ops {
287d19ce SH	90	ssize_t (read)(struct pci_dev dev, loff_t pos, size_t count, void *buf);
287d19ce SH	91	ssize_t (write)(struct pci_dev dev, loff_t pos, size_t count, const void *buf);
94e61088 BH	92	void (release)(struct pci_dev dev);
	93	};
	94
	95	struct pci_vpd {
99cb233d	96	unsigned int len;
287d19ce	97	const struct pci_vpd_ops *ops;
94e61088 BH	98	struct bin_attribute attr; / descriptor for sysfs VPD entry */
	99	};
	100
f39d5b72	101	int pci_vpd_pci22_init(struct pci_dev *dev);
94e61088 BH	102	static inline void pci_vpd_release(struct pci_dev *dev)
	103	{
	104	if (dev->vpd)
	105	dev->vpd->ops->release(dev);
	106	}
	107
1da177e4 LT	108	/* PCI /proc functions */
1da177e4 LT	109	#ifdef CONFIG_PROC_FS
f39d5b72 BH	110	int pci_proc_attach_device(struct pci_dev *dev);
	111	int pci_proc_detach_device(struct pci_dev *dev);
	112	int pci_proc_detach_bus(struct pci_bus *bus);
1da177e4 LT	113	#else
	114	static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
	115	static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4 LT	116	static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
	117	#endif
	118
	119	/* Functions for PCI Hotplug drivers to use */
a8e4b9c1	120	int pci_hp_add_bridge(struct pci_dev *dev);
1da177e4	121
f19aeb1f	122	#ifdef HAVE_PCI_LEGACY
f39d5b72 BH	123	void pci_create_legacy_files(struct pci_bus *bus);
f39d5b72 BH	124	void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f BH	125	#else
	126	static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
	127	static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
	128	#endif
1da177e4 LT	129
1da177e4 LT	130	/* Lock for read/write access to pci device and bus lists */
d71374da	131	extern struct rw_semaphore pci_bus_sem;
1da177e4	132
a2e27787 JK	133	extern raw_spinlock_t pci_lock;
a2e27787 JK	134
ffadcc2f	135	extern unsigned int pci_pm_d3_delay;
88187dfa	136
4b47b0ee	137	#ifdef CONFIG_PCI_MSI
309e57df	138	void pci_no_msi(void);
f39d5b72	139	void pci_msi_init_pci_dev(struct pci_dev *dev);
4b47b0ee	140	#else
309e57df	141	static inline void pci_no_msi(void) { }
4aa9bc95	142	static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
4b47b0ee	143	#endif
8fed4b65	144
b55438fd	145	void pci_realloc_get_opt(char *);
f483d392	146
ffadcc2f KCA	147	static inline int pci_no_d1d2(struct pci_dev *dev)
	148	{
	149	unsigned int parent_dstates = 0;
4b47b0ee	150
ffadcc2f KCA	151	if (dev->bus->self)
	152	parent_dstates = dev->bus->self->no_d1d2;
	153	return (dev->no_d1d2 \|\| parent_dstates);
	154
	155	}
1da177e4	156	extern struct device_attribute pci_dev_attrs[];
56039e65	157	extern const struct attribute_group *pcibus_groups[];
4e15c46b	158	extern struct device_type pci_dev_type;
0f49ba55	159	extern const struct attribute_group *pci_bus_groups[];
705b1aaa	160
1da177e4 LT	161
	162	/**
	163	* pci_match_one_device - Tell if a PCI device structure has a matching
	164	* PCI device id structure
	165	* @id: single PCI device id structure to match
	166	* @dev: the PCI device structure to match against
367b09fe	167	*
1da177e4 LT	168	* Returns the matching pci_device_id structure or %NULL if there is no match.
	169	*/
	170	static inline const struct pci_device_id *
	171	pci_match_one_device(const struct pci_device_id id, const struct pci_dev dev)
	172	{
	173	if ((id->vendor == PCI_ANY_ID \|\| id->vendor == dev->vendor) &&
	174	(id->device == PCI_ANY_ID \|\| id->device == dev->device) &&
	175	(id->subvendor == PCI_ANY_ID \|\| id->subvendor == dev->subsystem_vendor) &&
	176	(id->subdevice == PCI_ANY_ID \|\| id->subdevice == dev->subsystem_device) &&
	177	!((id->class ^ dev->class) & id->class_mask))
	178	return id;
	179	return NULL;
	180	}
	181
f46753c5 AC	182	/* PCI slot sysfs helper code */
	183	#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
	184
	185	extern struct kset *pci_slots_kset;
	186
	187	struct pci_slot_attribute {
	188	struct attribute attr;
	189	ssize_t (show)(struct pci_slot , char *);
	190	ssize_t (store)(struct pci_slot , const char *, size_t);
	191	};
	192	#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
	193
0b400c7e YZ	194	enum pci_bar_type {
	195	pci_bar_unknown, /* Standard PCI BAR probe */
	196	pci_bar_io, /* An io port BAR */
	197	pci_bar_mem32, /* A 32-bit memory BAR */
	198	pci_bar_mem64, /* A 64-bit memory BAR */
	199	};
	200
efdc87da YL	201	bool pci_bus_read_dev_vendor_id(struct pci_bus bus, int devfn, u32 pl,
efdc87da YL	202	int crs_timeout);
f39d5b72 BH	203	int pci_setup_device(struct pci_dev *dev);
	204	int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
	205	struct resource *res, unsigned int reg);
	206	int pci_resource_bar(struct pci_dev dev, int resno, enum pci_bar_type type);
	207	void pci_configure_ari(struct pci_dev *dev);
d66ecb72 JL	208	void __ref __pci_bus_size_bridges(struct pci_bus *bus,
	209	struct list_head *realloc_head);
	210	void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
	211	struct list_head *realloc_head,
	212	struct list_head *fail_head);
939de1d6	213
58c3a727 YZ	214	/**
58c3a727 YZ	215	* pci_ari_enabled - query ARI forwarding status
6a49d812	216	* @bus: the PCI bus
58c3a727 YZ	217	*
	218	* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
	219	*/
6a49d812	220	static inline int pci_ari_enabled(struct pci_bus *bus)
58c3a727	221	{
6a49d812	222	return bus->self && bus->self->ari_enabled;
58c3a727 YZ	223	}
58c3a727 YZ	224
2069ecfb	225	void pci_reassigndev_resource_alignment(struct pci_dev *dev);
f39d5b72	226	void pci_disable_bridge_window(struct pci_dev *dev);
32a9a682	227
d1b054da YZ	228	/* Single Root I/O Virtualization */
	229	struct pci_sriov {
	230	int pos; /* capability position */
	231	int nres; /* number of resources */
	232	u32 cap; /* SR-IOV Capabilities */
	233	u16 ctrl; /* SR-IOV Control */
6b136724 BH	234	u16 total_VFs; /* total VFs associated with the PF */
	235	u16 initial_VFs; /* initial VFs associated with the PF */
	236	u16 num_VFs; /* number of VFs available */
d1b054da YZ	237	u16 offset; /* first VF Routing ID offset */
	238	u16 stride; /* following VF stride */
	239	u32 pgsz; /* page size for BAR alignment */
	240	u8 link; /* Function Dependency Link */
6b136724	241	u16 driver_max_VFs; /* max num VFs driver supports */
d1b054da YZ	242	struct pci_dev dev; / lowest numbered PF */
	243	struct pci_dev self; / this PF */
	244	struct mutex lock; /* lock for VF bus */
74bb1bcc YZ	245	struct work_struct mtask; /* VF Migration task */
74bb1bcc YZ	246	u8 __iomem mstate; / VF Migration State Array */
d1b054da YZ	247	};
d1b054da YZ	248
1900ca13	249	#ifdef CONFIG_PCI_ATS
f39d5b72	250	void pci_restore_ats_state(struct pci_dev *dev);
1900ca13 HX	251	#else
	252	static inline void pci_restore_ats_state(struct pci_dev *dev)
	253	{
	254	}
	255	#endif /* CONFIG_PCI_ATS */
	256
d1b054da	257	#ifdef CONFIG_PCI_IOV
f39d5b72 BH	258	int pci_iov_init(struct pci_dev *dev);
	259	void pci_iov_release(struct pci_dev *dev);
	260	int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	261	enum pci_bar_type *type);
	262	resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
	263	void pci_restore_iov_state(struct pci_dev *dev);
	264	int pci_iov_bus_range(struct pci_bus *bus);
302b4215	265
d1b054da YZ	266	#else
	267	static inline int pci_iov_init(struct pci_dev *dev)
	268	{
	269	return -ENODEV;
	270	}
	271	static inline void pci_iov_release(struct pci_dev *dev)
	272
	273	{
	274	}
	275	static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	276	enum pci_bar_type *type)
	277	{
	278	return 0;
	279	}
8c5cdb6a YZ	280	static inline void pci_restore_iov_state(struct pci_dev *dev)
	281	{
	282	}
a28724b0 YZ	283	static inline int pci_iov_bus_range(struct pci_bus *bus)
	284	{
	285	return 0;
	286	}
302b4215	287
d1b054da YZ	288	#endif /* CONFIG_PCI_IOV */
d1b054da YZ	289
f39d5b72	290	unsigned long pci_cardbus_resource_alignment(struct resource *);
0a2daa1c	291
0e52247a	292	static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
f39d5b72	293	struct resource *res)
6faf17f6 CW	294	{
	295	#ifdef CONFIG_PCI_IOV
	296	int resno = res - dev->resource;
	297
	298	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	299	return pci_sriov_resource_alignment(dev, resno);
	300	#endif
0a2daa1c RP	301	if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
0a2daa1c RP	302	return pci_cardbus_resource_alignment(res);
6faf17f6 CW	303	return resource_alignment(res);
	304	}
	305
f39d5b72	306	void pci_enable_acs(struct pci_dev *dev);
ae21ee65	307
b9c3b266 DC	308	struct pci_dev_reset_methods {
	309	u16 vendor;
	310	u16 device;
	311	int (reset)(struct pci_dev dev, int probe);
	312	};
	313
93177a74	314	#ifdef CONFIG_PCI_QUIRKS
f39d5b72	315	int pci_dev_specific_reset(struct pci_dev *dev, int probe);
93177a74 RW	316	#else
	317	static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
	318	{
	319	return -ENOTTY;
	320	}
	321	#endif
b9c3b266	322
557848c3	323	#endif /* DRIVERS_PCI_H */