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Merge branch 'pm-cpufreq-fixes'
[linux-2.6-block.git] / drivers / pci / pci.h
CommitLineData
557848c3
ZY		 1#ifndef DRIVERS_PCI_H
2#define DRIVERS_PCI_H
3
4#define PCI_CFG_SPACE_SIZE 256
5#define PCI_CFG_SPACE_EXP_SIZE 4096
6
fff905f3
WY		 7#define PCI_FIND_CAP_TTL 48
8
343e51ae
JK		 9extern const unsigned char pcie_link_speed[];
10
7a1562d4
YL		 11bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
12
1da177e4
LT		 13/* Functions internal to the PCI core code */
14
f39d5b72
BH		 15int pci_create_sysfs_dev_files(struct pci_dev *pdev);
16void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
6058989b 17#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
911e1c9b 18static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
b879743f 19{ return; }
911e1c9b 20static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
b879743f 21{ return; }
911e1c9b 22#else
f39d5b72
BH		 23void pci_create_firmware_label_files(struct pci_dev *pdev);
24void pci_remove_firmware_label_files(struct pci_dev *pdev);
911e1c9b 25#endif
f39d5b72 26void pci_cleanup_rom(struct pci_dev *dev);
9eff02e2 27#ifdef HAVE_PCI_MMAP
3b519e4e
MW		 28enum pci_mmap_api {
29 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
30 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
31};
f39d5b72
BH		 32int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
33 enum pci_mmap_api mmap_api);
9eff02e2 34#endif
711d5779 35int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef 36
961d9120 37/**
b33bfdef 38 * struct pci_platform_pm_ops - Firmware PM callbacks
961d9120 39 *
b33bfdef
RD		 40 * @is_manageable: returns 'true' if given device is power manageable by the
41 * platform firmware
961d9120 42 *
b33bfdef 43 * @set_state: invokes the platform firmware to set the device's power state
961d9120 44 *
b33bfdef
RD		 45 * @choose_state: returns PCI power state of given device preferred by the
46 * platform; to be used during system-wide transitions from a
47 * sleeping state to the working state and vice versa
961d9120 48 *
b33bfdef 49 * @sleep_wake: enables/disables the system wake up capability of given device
eb9d0fe4 50 *
b67ea761
RW		 51 * @run_wake: enables/disables the platform to generate run-time wake-up events
52 * for given device (the device's wake-up capability has to be
53 * enabled by @sleep_wake for this feature to work)
54 *
bac2a909
RW		 55 * @need_resume: returns 'true' if the given device (which is currently
56 * suspended) needs to be resumed to be configured for system
57 * wakeup.
58 *
961d9120
RW		 59 * If given platform is generally capable of power managing PCI devices, all of
60 * these callbacks are mandatory.
61 */
62struct pci_platform_pm_ops {
63 bool (*is_manageable)(struct pci_dev *dev);
64 int (*set_state)(struct pci_dev *dev, pci_power_t state);
65 pci_power_t (*choose_state)(struct pci_dev *dev);
eb9d0fe4 66 int (*sleep_wake)(struct pci_dev *dev, bool enable);
b67ea761 67 int (*run_wake)(struct pci_dev *dev, bool enable);
bac2a909 68 bool (*need_resume)(struct pci_dev *dev);
961d9120
RW		 69};
70
299f2ffe 71int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
f39d5b72
BH		 72void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
73void pci_power_up(struct pci_dev *dev);
74void pci_disable_enabled_device(struct pci_dev *dev);
75int pci_finish_runtime_suspend(struct pci_dev *dev);
76int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
bac2a909 77bool pci_dev_keep_suspended(struct pci_dev *dev);
2cef548a 78void pci_dev_complete_resume(struct pci_dev *pci_dev);
f39d5b72
BH		 79void pci_config_pm_runtime_get(struct pci_dev *dev);
80void pci_config_pm_runtime_put(struct pci_dev *dev);
81void pci_pm_init(struct pci_dev *dev);
938174e5 82void pci_ea_init(struct pci_dev *dev);
f39d5b72 83void pci_allocate_cap_save_buffers(struct pci_dev *dev);
f796841e 84void pci_free_cap_save_buffers(struct pci_dev *dev);
aa8c6c93 85
b6e335ae
RW		 86static inline void pci_wakeup_event(struct pci_dev *dev)
87{
88 /* Wait 100 ms before the system can be put into a sleep state. */
89 pm_wakeup_event(&dev->dev, 100);
90}
91
326c1cda 92static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
aa8c6c93
RW		 93{
94 return !!(pci_dev->subordinate);
95}
0f64474b 96
94e61088 97struct pci_vpd_ops {
287d19ce
SH		 98 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
99 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
cb92148b 100 int (*set_size)(struct pci_dev *dev, size_t len);
94e61088
BH		 101};
102
103struct pci_vpd {
287d19ce 104 const struct pci_vpd_ops *ops;
94e61088 105 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
408641e9
BH		 106 struct mutex lock;
107 unsigned int len;
108 u16 flag;
109 u8 cap;
110 u8 busy:1;
111 u8 valid:1;
94e61088
BH		 112};
113
f1cd93f9 114int pci_vpd_init(struct pci_dev *dev);
64379079 115void pci_vpd_release(struct pci_dev *dev);
94e61088 116
1da177e4
LT		 117/* PCI /proc functions */
118#ifdef CONFIG_PROC_FS
f39d5b72
BH		 119int pci_proc_attach_device(struct pci_dev *dev);
120int pci_proc_detach_device(struct pci_dev *dev);
121int pci_proc_detach_bus(struct pci_bus *bus);
1da177e4
LT		 122#else
123static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
124static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4
LT		 125static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
126#endif
127
128/* Functions for PCI Hotplug drivers to use */
a8e4b9c1 129int pci_hp_add_bridge(struct pci_dev *dev);
1da177e4 130
f19aeb1f 131#ifdef HAVE_PCI_LEGACY
f39d5b72
BH		 132void pci_create_legacy_files(struct pci_bus *bus);
133void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f
BH		 134#else
135static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
136static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
137#endif
1da177e4
LT		 138
139/* Lock for read/write access to pci device and bus lists */
d71374da 140extern struct rw_semaphore pci_bus_sem;
1da177e4 141
a2e27787
JK		 142extern raw_spinlock_t pci_lock;
143
ffadcc2f 144extern unsigned int pci_pm_d3_delay;
88187dfa 145
4b47b0ee 146#ifdef CONFIG_PCI_MSI
309e57df 147void pci_no_msi(void);
4b47b0ee 148#else
309e57df 149static inline void pci_no_msi(void) { }
4b47b0ee 150#endif
8fed4b65 151
6a25f5e3
MT		 152static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
153{
154 u16 control;
155
156 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
157 control &= ~PCI_MSI_FLAGS_ENABLE;
158 if (enable)
159 control |= PCI_MSI_FLAGS_ENABLE;
160 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
161}
162
163static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
164{
165 u16 ctrl;
166
167 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
168 ctrl &= ~clear;
169 ctrl |= set;
170 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
171}
172
b55438fd 173void pci_realloc_get_opt(char *);
f483d392 174
ffadcc2f
KCA		 175static inline int pci_no_d1d2(struct pci_dev *dev)
176{
177 unsigned int parent_dstates = 0;
4b47b0ee 178
ffadcc2f
KCA		 179 if (dev->bus->self)
180 parent_dstates = dev->bus->self->no_d1d2;
181 return (dev->no_d1d2 || parent_dstates);
182
183}
5136b2da 184extern const struct attribute_group *pci_dev_groups[];
56039e65 185extern const struct attribute_group *pcibus_groups[];
4e15c46b 186extern struct device_type pci_dev_type;
0f49ba55 187extern const struct attribute_group *pci_bus_groups[];
705b1aaa 188
1da177e4
LT		 189
190/**
191 * pci_match_one_device - Tell if a PCI device structure has a matching
192 * PCI device id structure
193 * @id: single PCI device id structure to match
194 * @dev: the PCI device structure to match against
367b09fe 195 *
1da177e4
LT		 196 * Returns the matching pci_device_id structure or %NULL if there is no match.
197 */
198static inline const struct pci_device_id *
199pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
200{
201 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
202 (id->device == PCI_ANY_ID || id->device == dev->device) &&
203 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
204 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
205 !((id->class ^ dev->class) & id->class_mask))
206 return id;
207 return NULL;
208}
209
f46753c5
AC		 210/* PCI slot sysfs helper code */
211#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
212
213extern struct kset *pci_slots_kset;
214
215struct pci_slot_attribute {
216 struct attribute attr;
217 ssize_t (*show)(struct pci_slot *, char *);
218 ssize_t (*store)(struct pci_slot *, const char *, size_t);
219};
220#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
221
0b400c7e
YZ		 222enum pci_bar_type {
223 pci_bar_unknown, /* Standard PCI BAR probe */
224 pci_bar_io, /* An io port BAR */
225 pci_bar_mem32, /* A 32-bit memory BAR */
226 pci_bar_mem64, /* A 64-bit memory BAR */
227};
228
efdc87da
YL		 229bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
230 int crs_timeout);
f39d5b72
BH		 231int pci_setup_device(struct pci_dev *dev);
232int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
233 struct resource *res, unsigned int reg);
234int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type);
235void pci_configure_ari(struct pci_dev *dev);
10874f5a 236void __pci_bus_size_bridges(struct pci_bus *bus,
d66ecb72 237 struct list_head *realloc_head);
10874f5a
BH		 238void __pci_bus_assign_resources(const struct pci_bus *bus,
239 struct list_head *realloc_head,
240 struct list_head *fail_head);
0f7e7aee 241bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
939de1d6 242
2069ecfb 243void pci_reassigndev_resource_alignment(struct pci_dev *dev);
f39d5b72 244void pci_disable_bridge_window(struct pci_dev *dev);
32a9a682 245
d1b054da
YZ		 246/* Single Root I/O Virtualization */
247struct pci_sriov {
248 int pos; /* capability position */
249 int nres; /* number of resources */
250 u32 cap; /* SR-IOV Capabilities */
251 u16 ctrl; /* SR-IOV Control */
6b136724
BH		 252 u16 total_VFs; /* total VFs associated with the PF */
253 u16 initial_VFs; /* initial VFs associated with the PF */
254 u16 num_VFs; /* number of VFs available */
d1b054da
YZ		 255 u16 offset; /* first VF Routing ID offset */
256 u16 stride; /* following VF stride */
257 u32 pgsz; /* page size for BAR alignment */
258 u8 link; /* Function Dependency Link */
4449f079 259 u8 max_VF_buses; /* max buses consumed by VFs */
6b136724 260 u16 driver_max_VFs; /* max num VFs driver supports */
d1b054da
YZ		 261 struct pci_dev *dev; /* lowest numbered PF */
262 struct pci_dev *self; /* this PF */
263 struct mutex lock; /* lock for VF bus */
0e6c9122 264 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
d1b054da
YZ		 265};
266
1900ca13 267#ifdef CONFIG_PCI_ATS
f39d5b72 268void pci_restore_ats_state(struct pci_dev *dev);
1900ca13
HX		 269#else
270static inline void pci_restore_ats_state(struct pci_dev *dev)
271{
272}
273#endif /* CONFIG_PCI_ATS */
274
d1b054da 275#ifdef CONFIG_PCI_IOV
f39d5b72
BH		 276int pci_iov_init(struct pci_dev *dev);
277void pci_iov_release(struct pci_dev *dev);
26ff46c6 278int pci_iov_resource_bar(struct pci_dev *dev, int resno);
f39d5b72
BH		 279resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
280void pci_restore_iov_state(struct pci_dev *dev);
281int pci_iov_bus_range(struct pci_bus *bus);
302b4215 282
d1b054da
YZ		 283#else
284static inline int pci_iov_init(struct pci_dev *dev)
285{
286 return -ENODEV;
287}
288static inline void pci_iov_release(struct pci_dev *dev)
289
290{
291}
26ff46c6 292static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno)
d1b054da
YZ		 293{
294 return 0;
295}
8c5cdb6a
YZ		 296static inline void pci_restore_iov_state(struct pci_dev *dev)
297{
298}
a28724b0
YZ		 299static inline int pci_iov_bus_range(struct pci_bus *bus)
300{
301 return 0;
302}
302b4215 303
d1b054da
YZ		 304#endif /* CONFIG_PCI_IOV */
305
f39d5b72 306unsigned long pci_cardbus_resource_alignment(struct resource *);
0a2daa1c 307
0e52247a 308static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
f39d5b72 309 struct resource *res)
6faf17f6
CW		 310{
311#ifdef CONFIG_PCI_IOV
312 int resno = res - dev->resource;
313
314 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
315 return pci_sriov_resource_alignment(dev, resno);
316#endif
0a2daa1c
RP		 317 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
318 return pci_cardbus_resource_alignment(res);
6faf17f6
CW		 319 return resource_alignment(res);
320}
321
f39d5b72 322void pci_enable_acs(struct pci_dev *dev);
ae21ee65 323
b9c3b266
DC		 324struct pci_dev_reset_methods {
325 u16 vendor;
326 u16 device;
327 int (*reset)(struct pci_dev *dev, int probe);
328};
329
93177a74 330#ifdef CONFIG_PCI_QUIRKS
f39d5b72 331int pci_dev_specific_reset(struct pci_dev *dev, int probe);
93177a74
RW		 332#else
333static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
334{
335 return -ENOTTY;
336}
337#endif
b9c3b266 338
557848c3 339#endif /* DRIVERS_PCI_H */
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