Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
557848c3 ZY |
2 | #ifndef DRIVERS_PCI_H |
3 | #define DRIVERS_PCI_H | |
4 | ||
2209e06f AG |
5 | #include <linux/pci.h> |
6 | ||
fff905f3 WY |
7 | #define PCI_FIND_CAP_TTL 48 |
8 | ||
8531e283 LW |
9 | #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ |
10 | ||
343e51ae | 11 | extern const unsigned char pcie_link_speed[]; |
11eb0e0e | 12 | extern bool pci_early_dump; |
343e51ae | 13 | |
7a1562d4 YL |
14 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
15 | ||
1da177e4 LT |
16 | /* Functions internal to the PCI core code */ |
17 | ||
f39d5b72 BH |
18 | int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
19 | void pci_remove_sysfs_dev_files(struct pci_dev *pdev); | |
6058989b | 20 | #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) |
911e1c9b | 21 | static inline void pci_create_firmware_label_files(struct pci_dev *pdev) |
b879743f | 22 | { return; } |
911e1c9b | 23 | static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) |
b879743f | 24 | { return; } |
911e1c9b | 25 | #else |
f39d5b72 BH |
26 | void pci_create_firmware_label_files(struct pci_dev *pdev); |
27 | void pci_remove_firmware_label_files(struct pci_dev *pdev); | |
911e1c9b | 28 | #endif |
f39d5b72 | 29 | void pci_cleanup_rom(struct pci_dev *dev); |
f7195824 | 30 | |
3b519e4e MW |
31 | enum pci_mmap_api { |
32 | PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ | |
33 | PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ | |
34 | }; | |
f39d5b72 BH |
35 | int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
36 | enum pci_mmap_api mmap_api); | |
f7195824 | 37 | |
711d5779 | 38 | int pci_probe_reset_function(struct pci_dev *dev); |
381634ca | 39 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); |
c4eed62a | 40 | int pci_bus_error_reset(struct pci_dev *dev); |
ce5ccdef | 41 | |
961d9120 | 42 | /** |
b33bfdef | 43 | * struct pci_platform_pm_ops - Firmware PM callbacks |
961d9120 | 44 | * |
26ad34d5 MW |
45 | * @bridge_d3: Does the bridge allow entering into D3 |
46 | * | |
b33bfdef | 47 | * @is_manageable: returns 'true' if given device is power manageable by the |
0aa0f5d1 | 48 | * platform firmware |
961d9120 | 49 | * |
b33bfdef | 50 | * @set_state: invokes the platform firmware to set the device's power state |
961d9120 | 51 | * |
cc7cc02b LW |
52 | * @get_state: queries the platform firmware for a device's current power state |
53 | * | |
b33bfdef | 54 | * @choose_state: returns PCI power state of given device preferred by the |
0aa0f5d1 BH |
55 | * platform; to be used during system-wide transitions from a |
56 | * sleeping state to the working state and vice versa | |
961d9120 | 57 | * |
0847684c | 58 | * @set_wakeup: enables/disables wakeup capability for the device |
b67ea761 | 59 | * |
bac2a909 | 60 | * @need_resume: returns 'true' if the given device (which is currently |
0aa0f5d1 BH |
61 | * suspended) needs to be resumed to be configured for system |
62 | * wakeup. | |
bac2a909 | 63 | * |
961d9120 RW |
64 | * If given platform is generally capable of power managing PCI devices, all of |
65 | * these callbacks are mandatory. | |
66 | */ | |
67 | struct pci_platform_pm_ops { | |
26ad34d5 | 68 | bool (*bridge_d3)(struct pci_dev *dev); |
961d9120 RW |
69 | bool (*is_manageable)(struct pci_dev *dev); |
70 | int (*set_state)(struct pci_dev *dev, pci_power_t state); | |
cc7cc02b | 71 | pci_power_t (*get_state)(struct pci_dev *dev); |
961d9120 | 72 | pci_power_t (*choose_state)(struct pci_dev *dev); |
0847684c | 73 | int (*set_wakeup)(struct pci_dev *dev, bool enable); |
bac2a909 | 74 | bool (*need_resume)(struct pci_dev *dev); |
961d9120 RW |
75 | }; |
76 | ||
299f2ffe | 77 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); |
f39d5b72 BH |
78 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
79 | void pci_power_up(struct pci_dev *dev); | |
80 | void pci_disable_enabled_device(struct pci_dev *dev); | |
81 | int pci_finish_runtime_suspend(struct pci_dev *dev); | |
dcb0453d | 82 | void pcie_clear_root_pme_status(struct pci_dev *dev); |
f39d5b72 | 83 | int __pci_pme_wakeup(struct pci_dev *dev, void *ign); |
0ce3fcaf | 84 | void pci_pme_restore(struct pci_dev *dev); |
bac2a909 | 85 | bool pci_dev_keep_suspended(struct pci_dev *dev); |
2cef548a | 86 | void pci_dev_complete_resume(struct pci_dev *pci_dev); |
f39d5b72 BH |
87 | void pci_config_pm_runtime_get(struct pci_dev *dev); |
88 | void pci_config_pm_runtime_put(struct pci_dev *dev); | |
89 | void pci_pm_init(struct pci_dev *dev); | |
938174e5 | 90 | void pci_ea_init(struct pci_dev *dev); |
f39d5b72 | 91 | void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
f796841e | 92 | void pci_free_cap_save_buffers(struct pci_dev *dev); |
c6a63307 | 93 | bool pci_bridge_d3_possible(struct pci_dev *dev); |
1ed276a7 | 94 | void pci_bridge_d3_update(struct pci_dev *dev); |
aa8c6c93 | 95 | |
b6e335ae RW |
96 | static inline void pci_wakeup_event(struct pci_dev *dev) |
97 | { | |
98 | /* Wait 100 ms before the system can be put into a sleep state. */ | |
99 | pm_wakeup_event(&dev->dev, 100); | |
100 | } | |
101 | ||
326c1cda | 102 | static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
aa8c6c93 RW |
103 | { |
104 | return !!(pci_dev->subordinate); | |
105 | } | |
0f64474b | 106 | |
9d26d3a8 MW |
107 | static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
108 | { | |
109 | /* | |
110 | * Currently we allow normal PCI devices and PCI bridges transition | |
111 | * into D3 if their bridge_d3 is set. | |
112 | */ | |
113 | return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; | |
114 | } | |
115 | ||
f1cd93f9 | 116 | int pci_vpd_init(struct pci_dev *dev); |
64379079 | 117 | void pci_vpd_release(struct pci_dev *dev); |
b1c615c4 BH |
118 | void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); |
119 | void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); | |
94e61088 | 120 | |
1da177e4 LT |
121 | /* PCI /proc functions */ |
122 | #ifdef CONFIG_PROC_FS | |
f39d5b72 BH |
123 | int pci_proc_attach_device(struct pci_dev *dev); |
124 | int pci_proc_detach_device(struct pci_dev *dev); | |
125 | int pci_proc_detach_bus(struct pci_bus *bus); | |
1da177e4 LT |
126 | #else |
127 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } | |
128 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } | |
1da177e4 LT |
129 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
130 | #endif | |
131 | ||
132 | /* Functions for PCI Hotplug drivers to use */ | |
a8e4b9c1 | 133 | int pci_hp_add_bridge(struct pci_dev *dev); |
1da177e4 | 134 | |
f19aeb1f | 135 | #ifdef HAVE_PCI_LEGACY |
f39d5b72 BH |
136 | void pci_create_legacy_files(struct pci_bus *bus); |
137 | void pci_remove_legacy_files(struct pci_bus *bus); | |
f19aeb1f BH |
138 | #else |
139 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
140 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
141 | #endif | |
1da177e4 LT |
142 | |
143 | /* Lock for read/write access to pci device and bus lists */ | |
d71374da | 144 | extern struct rw_semaphore pci_bus_sem; |
c4eed62a | 145 | extern struct mutex pci_slot_mutex; |
1da177e4 | 146 | |
a2e27787 JK |
147 | extern raw_spinlock_t pci_lock; |
148 | ||
ffadcc2f | 149 | extern unsigned int pci_pm_d3_delay; |
88187dfa | 150 | |
4b47b0ee | 151 | #ifdef CONFIG_PCI_MSI |
309e57df | 152 | void pci_no_msi(void); |
4b47b0ee | 153 | #else |
309e57df | 154 | static inline void pci_no_msi(void) { } |
4b47b0ee | 155 | #endif |
8fed4b65 | 156 | |
6a25f5e3 MT |
157 | static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) |
158 | { | |
159 | u16 control; | |
160 | ||
161 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
162 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
163 | if (enable) | |
164 | control |= PCI_MSI_FLAGS_ENABLE; | |
165 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
166 | } | |
167 | ||
168 | static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) | |
169 | { | |
170 | u16 ctrl; | |
171 | ||
172 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
173 | ctrl &= ~clear; | |
174 | ctrl |= set; | |
175 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
176 | } | |
177 | ||
b55438fd | 178 | void pci_realloc_get_opt(char *); |
f483d392 | 179 | |
ffadcc2f KCA |
180 | static inline int pci_no_d1d2(struct pci_dev *dev) |
181 | { | |
182 | unsigned int parent_dstates = 0; | |
4b47b0ee | 183 | |
ffadcc2f KCA |
184 | if (dev->bus->self) |
185 | parent_dstates = dev->bus->self->no_d1d2; | |
186 | return (dev->no_d1d2 || parent_dstates); | |
187 | ||
188 | } | |
5136b2da | 189 | extern const struct attribute_group *pci_dev_groups[]; |
56039e65 | 190 | extern const struct attribute_group *pcibus_groups[]; |
69f2dc24 | 191 | extern const struct device_type pci_dev_type; |
0f49ba55 | 192 | extern const struct attribute_group *pci_bus_groups[]; |
705b1aaa | 193 | |
1da177e4 LT |
194 | |
195 | /** | |
196 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
0aa0f5d1 | 197 | * PCI device id structure |
1da177e4 LT |
198 | * @id: single PCI device id structure to match |
199 | * @dev: the PCI device structure to match against | |
367b09fe | 200 | * |
1da177e4 LT |
201 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
202 | */ | |
203 | static inline const struct pci_device_id * | |
204 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) | |
205 | { | |
206 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && | |
207 | (id->device == PCI_ANY_ID || id->device == dev->device) && | |
208 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && | |
209 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && | |
210 | !((id->class ^ dev->class) & id->class_mask)) | |
211 | return id; | |
212 | return NULL; | |
213 | } | |
214 | ||
f46753c5 AC |
215 | /* PCI slot sysfs helper code */ |
216 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) | |
217 | ||
218 | extern struct kset *pci_slots_kset; | |
219 | ||
220 | struct pci_slot_attribute { | |
221 | struct attribute attr; | |
222 | ssize_t (*show)(struct pci_slot *, char *); | |
223 | ssize_t (*store)(struct pci_slot *, const char *, size_t); | |
224 | }; | |
225 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) | |
226 | ||
0b400c7e YZ |
227 | enum pci_bar_type { |
228 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
0aa0f5d1 | 229 | pci_bar_io, /* An I/O port BAR */ |
0b400c7e YZ |
230 | pci_bar_mem32, /* A 32-bit memory BAR */ |
231 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
232 | }; | |
233 | ||
62ce94a7 | 234 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign); |
efdc87da YL |
235 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
236 | int crs_timeout); | |
aa667c64 JP |
237 | bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
238 | int crs_timeout); | |
239 | int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); | |
240 | ||
f39d5b72 BH |
241 | int pci_setup_device(struct pci_dev *dev); |
242 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
243 | struct resource *res, unsigned int reg); | |
f39d5b72 | 244 | void pci_configure_ari(struct pci_dev *dev); |
10874f5a | 245 | void __pci_bus_size_bridges(struct pci_bus *bus, |
d66ecb72 | 246 | struct list_head *realloc_head); |
10874f5a BH |
247 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
248 | struct list_head *realloc_head, | |
249 | struct list_head *fail_head); | |
0f7e7aee | 250 | bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
939de1d6 | 251 | |
2069ecfb | 252 | void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
f39d5b72 | 253 | void pci_disable_bridge_window(struct pci_dev *dev); |
32a9a682 | 254 | |
6cf57be0 TG |
255 | /* PCIe link information */ |
256 | #define PCIE_SPEED2STR(speed) \ | |
257 | ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ | |
258 | (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ | |
259 | (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ | |
260 | (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ | |
261 | "Unknown speed") | |
262 | ||
b852f63a TG |
263 | /* PCIe speed to Mb/s reduced by encoding overhead */ |
264 | #define PCIE_SPEED2MBS_ENC(speed) \ | |
265 | ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ | |
266 | (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ | |
267 | (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ | |
268 | (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ | |
269 | 0) | |
270 | ||
6cf57be0 | 271 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
c70b65fb | 272 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); |
b852f63a TG |
273 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, |
274 | enum pcie_link_width *width); | |
2d1ce5ec | 275 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose); |
0fa635ae | 276 | void pcie_report_downtraining(struct pci_dev *dev); |
6cf57be0 | 277 | |
d1b054da YZ |
278 | /* Single Root I/O Virtualization */ |
279 | struct pci_sriov { | |
0aa0f5d1 BH |
280 | int pos; /* Capability position */ |
281 | int nres; /* Number of resources */ | |
282 | u32 cap; /* SR-IOV Capabilities */ | |
283 | u16 ctrl; /* SR-IOV Control */ | |
284 | u16 total_VFs; /* Total VFs associated with the PF */ | |
285 | u16 initial_VFs; /* Initial VFs associated with the PF */ | |
286 | u16 num_VFs; /* Number of VFs available */ | |
287 | u16 offset; /* First VF Routing ID offset */ | |
288 | u16 stride; /* Following VF stride */ | |
289 | u16 vf_device; /* VF device ID */ | |
290 | u32 pgsz; /* Page size for BAR alignment */ | |
291 | u8 link; /* Function Dependency Link */ | |
292 | u8 max_VF_buses; /* Max buses consumed by VFs */ | |
293 | u16 driver_max_VFs; /* Max num VFs driver supports */ | |
294 | struct pci_dev *dev; /* Lowest numbered PF */ | |
295 | struct pci_dev *self; /* This PF */ | |
975bb8b4 | 296 | u32 cfg_size; /* VF config space size */ |
cf0921be KA |
297 | u32 class; /* VF device */ |
298 | u8 hdr_type; /* VF header type */ | |
299 | u16 subsystem_vendor; /* VF subsystem vendor */ | |
300 | u16 subsystem_device; /* VF subsystem device */ | |
0aa0f5d1 BH |
301 | resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
302 | bool drivers_autoprobe; /* Auto probing of VFs by driver */ | |
d1b054da YZ |
303 | }; |
304 | ||
a6bd101b KB |
305 | /** |
306 | * pci_dev_set_io_state - Set the new error state if possible. | |
307 | * | |
308 | * @dev - pci device to set new error_state | |
309 | * @new - the state we want dev to be in | |
310 | * | |
311 | * Must be called with device_lock held. | |
312 | * | |
313 | * Returns true if state has been changed to the requested state. | |
314 | */ | |
315 | static inline bool pci_dev_set_io_state(struct pci_dev *dev, | |
316 | pci_channel_state_t new) | |
317 | { | |
318 | bool changed = false; | |
319 | ||
320 | device_lock_assert(&dev->dev); | |
321 | switch (new) { | |
322 | case pci_channel_io_perm_failure: | |
323 | switch (dev->error_state) { | |
324 | case pci_channel_io_frozen: | |
325 | case pci_channel_io_normal: | |
326 | case pci_channel_io_perm_failure: | |
327 | changed = true; | |
328 | break; | |
329 | } | |
330 | break; | |
331 | case pci_channel_io_frozen: | |
332 | switch (dev->error_state) { | |
333 | case pci_channel_io_frozen: | |
334 | case pci_channel_io_normal: | |
335 | changed = true; | |
336 | break; | |
337 | } | |
338 | break; | |
339 | case pci_channel_io_normal: | |
340 | switch (dev->error_state) { | |
341 | case pci_channel_io_frozen: | |
342 | case pci_channel_io_normal: | |
343 | changed = true; | |
344 | break; | |
345 | } | |
346 | break; | |
347 | } | |
348 | if (changed) | |
349 | dev->error_state = new; | |
350 | return changed; | |
351 | } | |
89ee9f76 KB |
352 | |
353 | static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) | |
354 | { | |
a6bd101b KB |
355 | device_lock(&dev->dev); |
356 | pci_dev_set_io_state(dev, pci_channel_io_perm_failure); | |
357 | device_unlock(&dev->dev); | |
358 | ||
89ee9f76 KB |
359 | return 0; |
360 | } | |
361 | ||
362 | static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) | |
363 | { | |
a6bd101b | 364 | return dev->error_state == pci_channel_io_perm_failure; |
89ee9f76 KB |
365 | } |
366 | ||
a6bd101b KB |
367 | /* pci_dev priv_flags */ |
368 | #define PCI_DEV_ADDED 0 | |
369 | ||
44bda4b7 HV |
370 | static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) |
371 | { | |
372 | assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); | |
373 | } | |
374 | ||
375 | static inline bool pci_dev_is_added(const struct pci_dev *dev) | |
376 | { | |
377 | return test_bit(PCI_DEV_ADDED, &dev->priv_flags); | |
378 | } | |
379 | ||
1e451160 KB |
380 | #ifdef CONFIG_PCIEAER |
381 | #include <linux/aer.h> | |
382 | ||
383 | #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ | |
384 | ||
385 | struct aer_err_info { | |
386 | struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; | |
387 | int error_dev_num; | |
388 | ||
389 | unsigned int id:16; | |
390 | ||
391 | unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ | |
392 | unsigned int __pad1:5; | |
393 | unsigned int multi_error_valid:1; | |
394 | ||
395 | unsigned int first_error:5; | |
396 | unsigned int __pad2:2; | |
397 | unsigned int tlp_header_valid:1; | |
398 | ||
399 | unsigned int status; /* COR/UNCOR Error Status */ | |
400 | unsigned int mask; /* COR/UNCOR Error Mask */ | |
401 | struct aer_header_log_regs tlp; /* TLP Header */ | |
402 | }; | |
403 | ||
404 | int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); | |
405 | void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); | |
406 | #endif /* CONFIG_PCIEAER */ | |
407 | ||
4f802170 KB |
408 | #ifdef CONFIG_PCIE_DPC |
409 | void pci_save_dpc_state(struct pci_dev *dev); | |
410 | void pci_restore_dpc_state(struct pci_dev *dev); | |
411 | #else | |
412 | static inline void pci_save_dpc_state(struct pci_dev *dev) {} | |
413 | static inline void pci_restore_dpc_state(struct pci_dev *dev) {} | |
414 | #endif | |
415 | ||
1900ca13 | 416 | #ifdef CONFIG_PCI_ATS |
f39d5b72 | 417 | void pci_restore_ats_state(struct pci_dev *dev); |
1900ca13 HX |
418 | #else |
419 | static inline void pci_restore_ats_state(struct pci_dev *dev) | |
420 | { | |
421 | } | |
422 | #endif /* CONFIG_PCI_ATS */ | |
423 | ||
d1b054da | 424 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
425 | int pci_iov_init(struct pci_dev *dev); |
426 | void pci_iov_release(struct pci_dev *dev); | |
38972375 | 427 | void pci_iov_remove(struct pci_dev *dev); |
6ffa2489 | 428 | void pci_iov_update_resource(struct pci_dev *dev, int resno); |
f39d5b72 BH |
429 | resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
430 | void pci_restore_iov_state(struct pci_dev *dev); | |
431 | int pci_iov_bus_range(struct pci_bus *bus); | |
302b4215 | 432 | |
d1b054da YZ |
433 | #else |
434 | static inline int pci_iov_init(struct pci_dev *dev) | |
435 | { | |
436 | return -ENODEV; | |
437 | } | |
438 | static inline void pci_iov_release(struct pci_dev *dev) | |
439 | ||
38972375 JK |
440 | { |
441 | } | |
442 | static inline void pci_iov_remove(struct pci_dev *dev) | |
d1b054da YZ |
443 | { |
444 | } | |
8c5cdb6a YZ |
445 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
446 | { | |
447 | } | |
a28724b0 YZ |
448 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
449 | { | |
450 | return 0; | |
451 | } | |
302b4215 | 452 | |
d1b054da YZ |
453 | #endif /* CONFIG_PCI_IOV */ |
454 | ||
f39d5b72 | 455 | unsigned long pci_cardbus_resource_alignment(struct resource *); |
0a2daa1c | 456 | |
0e52247a | 457 | static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
f39d5b72 | 458 | struct resource *res) |
6faf17f6 CW |
459 | { |
460 | #ifdef CONFIG_PCI_IOV | |
461 | int resno = res - dev->resource; | |
462 | ||
463 | if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) | |
464 | return pci_sriov_resource_alignment(dev, resno); | |
465 | #endif | |
0aa0f5d1 | 466 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
0a2daa1c | 467 | return pci_cardbus_resource_alignment(res); |
6faf17f6 CW |
468 | return resource_alignment(res); |
469 | } | |
470 | ||
f39d5b72 | 471 | void pci_enable_acs(struct pci_dev *dev); |
bd2e9567 BH |
472 | #ifdef CONFIG_PCI_QUIRKS |
473 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); | |
474 | int pci_dev_specific_enable_acs(struct pci_dev *dev); | |
73c47dde | 475 | int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); |
bd2e9567 BH |
476 | #else |
477 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, | |
478 | u16 acs_flags) | |
479 | { | |
480 | return -ENOTTY; | |
481 | } | |
482 | static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) | |
483 | { | |
484 | return -ENOTTY; | |
485 | } | |
73c47dde LG |
486 | static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) |
487 | { | |
488 | return -ENOTTY; | |
489 | } | |
bd2e9567 | 490 | #endif |
ae21ee65 | 491 | |
2e28bc84 | 492 | /* PCI error reporting and recovery */ |
bdb5ac85 KB |
493 | void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state, |
494 | u32 service); | |
2e28bc84 | 495 | |
9f5a70f1 | 496 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active); |
7d8e7d19 BH |
497 | #ifdef CONFIG_PCIEASPM |
498 | void pcie_aspm_init_link_state(struct pci_dev *pdev); | |
499 | void pcie_aspm_exit_link_state(struct pci_dev *pdev); | |
500 | void pcie_aspm_pm_state_change(struct pci_dev *pdev); | |
501 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev); | |
502 | #else | |
503 | static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } | |
504 | static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } | |
505 | static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } | |
506 | static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } | |
507 | #endif | |
508 | ||
509 | #ifdef CONFIG_PCIEASPM_DEBUG | |
510 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); | |
511 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); | |
512 | #else | |
513 | static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { } | |
514 | static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { } | |
515 | #endif | |
516 | ||
9bb04a0c JY |
517 | #ifdef CONFIG_PCIE_PTM |
518 | void pci_ptm_init(struct pci_dev *dev); | |
519 | #else | |
520 | static inline void pci_ptm_init(struct pci_dev *dev) { } | |
521 | #endif | |
522 | ||
b9c3b266 DC |
523 | struct pci_dev_reset_methods { |
524 | u16 vendor; | |
525 | u16 device; | |
526 | int (*reset)(struct pci_dev *dev, int probe); | |
527 | }; | |
528 | ||
93177a74 | 529 | #ifdef CONFIG_PCI_QUIRKS |
f39d5b72 | 530 | int pci_dev_specific_reset(struct pci_dev *dev, int probe); |
93177a74 RW |
531 | #else |
532 | static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
533 | { | |
534 | return -ENOTTY; | |
535 | } | |
536 | #endif | |
b9c3b266 | 537 | |
169de969 DL |
538 | #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) |
539 | int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, | |
540 | struct resource *res); | |
541 | #endif | |
542 | ||
276b738d CK |
543 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); |
544 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); | |
545 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); | |
546 | static inline u64 pci_rebar_size_to_bytes(int size) | |
547 | { | |
548 | return 1ULL << (size + 20); | |
549 | } | |
550 | ||
9e2aee80 RH |
551 | struct device_node; |
552 | ||
553 | #ifdef CONFIG_OF | |
554 | int of_pci_parse_bus_range(struct device_node *node, struct resource *res); | |
555 | int of_get_pci_domain_nr(struct device_node *node); | |
556 | int of_pci_get_max_link_speed(struct device_node *node); | |
557 | ||
558 | #else | |
559 | static inline int | |
560 | of_pci_parse_bus_range(struct device_node *node, struct resource *res) | |
561 | { | |
562 | return -EINVAL; | |
563 | } | |
564 | ||
565 | static inline int | |
566 | of_get_pci_domain_nr(struct device_node *node) | |
567 | { | |
568 | return -1; | |
569 | } | |
570 | ||
571 | static inline int | |
572 | of_pci_get_max_link_speed(struct device_node *node) | |
573 | { | |
574 | return -EINVAL; | |
575 | } | |
576 | #endif /* CONFIG_OF */ | |
577 | ||
578 | #if defined(CONFIG_OF_ADDRESS) | |
f03c7aa4 | 579 | int devm_of_pci_get_host_bridge_resources(struct device *dev, |
9e2aee80 RH |
580 | unsigned char busno, unsigned char bus_max, |
581 | struct list_head *resources, resource_size_t *io_base); | |
582 | #else | |
f03c7aa4 | 583 | static inline int devm_of_pci_get_host_bridge_resources(struct device *dev, |
9e2aee80 RH |
584 | unsigned char busno, unsigned char bus_max, |
585 | struct list_head *resources, resource_size_t *io_base) | |
586 | { | |
587 | return -EINVAL; | |
588 | } | |
589 | #endif | |
590 | ||
60ed982a RJ |
591 | #ifdef CONFIG_PCIEAER |
592 | void pci_no_aer(void); | |
593 | void pci_aer_init(struct pci_dev *dev); | |
db89ccbe | 594 | void pci_aer_exit(struct pci_dev *dev); |
81aa5206 | 595 | extern const struct attribute_group aer_stats_attr_group; |
7ab92e89 | 596 | void pci_aer_clear_fatal_status(struct pci_dev *dev); |
ec752f5d | 597 | void pci_aer_clear_device_status(struct pci_dev *dev); |
60ed982a RJ |
598 | #else |
599 | static inline void pci_no_aer(void) { } | |
31f996ef | 600 | static inline void pci_aer_init(struct pci_dev *d) { } |
db89ccbe | 601 | static inline void pci_aer_exit(struct pci_dev *d) { } |
7ab92e89 | 602 | static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } |
ec752f5d | 603 | static inline void pci_aer_clear_device_status(struct pci_dev *dev) { } |
60ed982a RJ |
604 | #endif |
605 | ||
557848c3 | 606 | #endif /* DRIVERS_PCI_H */ |