Commit | Line | Data |
---|---|---|
557848c3 ZY |
1 | #ifndef DRIVERS_PCI_H |
2 | #define DRIVERS_PCI_H | |
3 | ||
4 | #define PCI_CFG_SPACE_SIZE 256 | |
5 | #define PCI_CFG_SPACE_EXP_SIZE 4096 | |
6 | ||
fff905f3 WY |
7 | #define PCI_FIND_CAP_TTL 48 |
8 | ||
343e51ae JK |
9 | extern const unsigned char pcie_link_speed[]; |
10 | ||
7a1562d4 YL |
11 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
12 | ||
1da177e4 LT |
13 | /* Functions internal to the PCI core code */ |
14 | ||
f39d5b72 BH |
15 | int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
16 | void pci_remove_sysfs_dev_files(struct pci_dev *pdev); | |
6058989b | 17 | #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) |
911e1c9b | 18 | static inline void pci_create_firmware_label_files(struct pci_dev *pdev) |
b879743f | 19 | { return; } |
911e1c9b | 20 | static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) |
b879743f | 21 | { return; } |
911e1c9b | 22 | #else |
f39d5b72 BH |
23 | void pci_create_firmware_label_files(struct pci_dev *pdev); |
24 | void pci_remove_firmware_label_files(struct pci_dev *pdev); | |
911e1c9b | 25 | #endif |
f39d5b72 | 26 | void pci_cleanup_rom(struct pci_dev *dev); |
9eff02e2 | 27 | #ifdef HAVE_PCI_MMAP |
3b519e4e MW |
28 | enum pci_mmap_api { |
29 | PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ | |
30 | PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ | |
31 | }; | |
f39d5b72 BH |
32 | int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
33 | enum pci_mmap_api mmap_api); | |
9eff02e2 | 34 | #endif |
711d5779 | 35 | int pci_probe_reset_function(struct pci_dev *dev); |
ce5ccdef | 36 | |
961d9120 | 37 | /** |
b33bfdef | 38 | * struct pci_platform_pm_ops - Firmware PM callbacks |
961d9120 | 39 | * |
b33bfdef RD |
40 | * @is_manageable: returns 'true' if given device is power manageable by the |
41 | * platform firmware | |
961d9120 | 42 | * |
b33bfdef | 43 | * @set_state: invokes the platform firmware to set the device's power state |
961d9120 | 44 | * |
cc7cc02b LW |
45 | * @get_state: queries the platform firmware for a device's current power state |
46 | * | |
b33bfdef RD |
47 | * @choose_state: returns PCI power state of given device preferred by the |
48 | * platform; to be used during system-wide transitions from a | |
49 | * sleeping state to the working state and vice versa | |
961d9120 | 50 | * |
b33bfdef | 51 | * @sleep_wake: enables/disables the system wake up capability of given device |
eb9d0fe4 | 52 | * |
b67ea761 RW |
53 | * @run_wake: enables/disables the platform to generate run-time wake-up events |
54 | * for given device (the device's wake-up capability has to be | |
55 | * enabled by @sleep_wake for this feature to work) | |
56 | * | |
bac2a909 RW |
57 | * @need_resume: returns 'true' if the given device (which is currently |
58 | * suspended) needs to be resumed to be configured for system | |
59 | * wakeup. | |
60 | * | |
961d9120 RW |
61 | * If given platform is generally capable of power managing PCI devices, all of |
62 | * these callbacks are mandatory. | |
63 | */ | |
64 | struct pci_platform_pm_ops { | |
65 | bool (*is_manageable)(struct pci_dev *dev); | |
66 | int (*set_state)(struct pci_dev *dev, pci_power_t state); | |
cc7cc02b | 67 | pci_power_t (*get_state)(struct pci_dev *dev); |
961d9120 | 68 | pci_power_t (*choose_state)(struct pci_dev *dev); |
eb9d0fe4 | 69 | int (*sleep_wake)(struct pci_dev *dev, bool enable); |
b67ea761 | 70 | int (*run_wake)(struct pci_dev *dev, bool enable); |
bac2a909 | 71 | bool (*need_resume)(struct pci_dev *dev); |
961d9120 RW |
72 | }; |
73 | ||
299f2ffe | 74 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); |
f39d5b72 BH |
75 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
76 | void pci_power_up(struct pci_dev *dev); | |
77 | void pci_disable_enabled_device(struct pci_dev *dev); | |
78 | int pci_finish_runtime_suspend(struct pci_dev *dev); | |
79 | int __pci_pme_wakeup(struct pci_dev *dev, void *ign); | |
bac2a909 | 80 | bool pci_dev_keep_suspended(struct pci_dev *dev); |
2cef548a | 81 | void pci_dev_complete_resume(struct pci_dev *pci_dev); |
f39d5b72 BH |
82 | void pci_config_pm_runtime_get(struct pci_dev *dev); |
83 | void pci_config_pm_runtime_put(struct pci_dev *dev); | |
84 | void pci_pm_init(struct pci_dev *dev); | |
938174e5 | 85 | void pci_ea_init(struct pci_dev *dev); |
f39d5b72 | 86 | void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
f796841e | 87 | void pci_free_cap_save_buffers(struct pci_dev *dev); |
9d26d3a8 MW |
88 | void pci_bridge_d3_device_changed(struct pci_dev *dev); |
89 | void pci_bridge_d3_device_removed(struct pci_dev *dev); | |
aa8c6c93 | 90 | |
b6e335ae RW |
91 | static inline void pci_wakeup_event(struct pci_dev *dev) |
92 | { | |
93 | /* Wait 100 ms before the system can be put into a sleep state. */ | |
94 | pm_wakeup_event(&dev->dev, 100); | |
95 | } | |
96 | ||
326c1cda | 97 | static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
aa8c6c93 RW |
98 | { |
99 | return !!(pci_dev->subordinate); | |
100 | } | |
0f64474b | 101 | |
9d26d3a8 MW |
102 | static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
103 | { | |
104 | /* | |
105 | * Currently we allow normal PCI devices and PCI bridges transition | |
106 | * into D3 if their bridge_d3 is set. | |
107 | */ | |
108 | return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; | |
109 | } | |
110 | ||
94e61088 | 111 | struct pci_vpd_ops { |
287d19ce SH |
112 | ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
113 | ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
cb92148b | 114 | int (*set_size)(struct pci_dev *dev, size_t len); |
94e61088 BH |
115 | }; |
116 | ||
117 | struct pci_vpd { | |
287d19ce | 118 | const struct pci_vpd_ops *ops; |
94e61088 | 119 | struct bin_attribute *attr; /* descriptor for sysfs VPD entry */ |
408641e9 BH |
120 | struct mutex lock; |
121 | unsigned int len; | |
122 | u16 flag; | |
123 | u8 cap; | |
124 | u8 busy:1; | |
125 | u8 valid:1; | |
94e61088 BH |
126 | }; |
127 | ||
f1cd93f9 | 128 | int pci_vpd_init(struct pci_dev *dev); |
64379079 | 129 | void pci_vpd_release(struct pci_dev *dev); |
94e61088 | 130 | |
1da177e4 LT |
131 | /* PCI /proc functions */ |
132 | #ifdef CONFIG_PROC_FS | |
f39d5b72 BH |
133 | int pci_proc_attach_device(struct pci_dev *dev); |
134 | int pci_proc_detach_device(struct pci_dev *dev); | |
135 | int pci_proc_detach_bus(struct pci_bus *bus); | |
1da177e4 LT |
136 | #else |
137 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } | |
138 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } | |
1da177e4 LT |
139 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
140 | #endif | |
141 | ||
142 | /* Functions for PCI Hotplug drivers to use */ | |
a8e4b9c1 | 143 | int pci_hp_add_bridge(struct pci_dev *dev); |
1da177e4 | 144 | |
f19aeb1f | 145 | #ifdef HAVE_PCI_LEGACY |
f39d5b72 BH |
146 | void pci_create_legacy_files(struct pci_bus *bus); |
147 | void pci_remove_legacy_files(struct pci_bus *bus); | |
f19aeb1f BH |
148 | #else |
149 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
150 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
151 | #endif | |
1da177e4 LT |
152 | |
153 | /* Lock for read/write access to pci device and bus lists */ | |
d71374da | 154 | extern struct rw_semaphore pci_bus_sem; |
1da177e4 | 155 | |
a2e27787 JK |
156 | extern raw_spinlock_t pci_lock; |
157 | ||
ffadcc2f | 158 | extern unsigned int pci_pm_d3_delay; |
88187dfa | 159 | |
4b47b0ee | 160 | #ifdef CONFIG_PCI_MSI |
309e57df | 161 | void pci_no_msi(void); |
4b47b0ee | 162 | #else |
309e57df | 163 | static inline void pci_no_msi(void) { } |
4b47b0ee | 164 | #endif |
8fed4b65 | 165 | |
6a25f5e3 MT |
166 | static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) |
167 | { | |
168 | u16 control; | |
169 | ||
170 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
171 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
172 | if (enable) | |
173 | control |= PCI_MSI_FLAGS_ENABLE; | |
174 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
175 | } | |
176 | ||
177 | static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) | |
178 | { | |
179 | u16 ctrl; | |
180 | ||
181 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
182 | ctrl &= ~clear; | |
183 | ctrl |= set; | |
184 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
185 | } | |
186 | ||
b55438fd | 187 | void pci_realloc_get_opt(char *); |
f483d392 | 188 | |
ffadcc2f KCA |
189 | static inline int pci_no_d1d2(struct pci_dev *dev) |
190 | { | |
191 | unsigned int parent_dstates = 0; | |
4b47b0ee | 192 | |
ffadcc2f KCA |
193 | if (dev->bus->self) |
194 | parent_dstates = dev->bus->self->no_d1d2; | |
195 | return (dev->no_d1d2 || parent_dstates); | |
196 | ||
197 | } | |
5136b2da | 198 | extern const struct attribute_group *pci_dev_groups[]; |
56039e65 | 199 | extern const struct attribute_group *pcibus_groups[]; |
4e15c46b | 200 | extern struct device_type pci_dev_type; |
0f49ba55 | 201 | extern const struct attribute_group *pci_bus_groups[]; |
705b1aaa | 202 | |
1da177e4 LT |
203 | |
204 | /** | |
205 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
206 | * PCI device id structure | |
207 | * @id: single PCI device id structure to match | |
208 | * @dev: the PCI device structure to match against | |
367b09fe | 209 | * |
1da177e4 LT |
210 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
211 | */ | |
212 | static inline const struct pci_device_id * | |
213 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) | |
214 | { | |
215 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && | |
216 | (id->device == PCI_ANY_ID || id->device == dev->device) && | |
217 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && | |
218 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && | |
219 | !((id->class ^ dev->class) & id->class_mask)) | |
220 | return id; | |
221 | return NULL; | |
222 | } | |
223 | ||
f46753c5 AC |
224 | /* PCI slot sysfs helper code */ |
225 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) | |
226 | ||
227 | extern struct kset *pci_slots_kset; | |
228 | ||
229 | struct pci_slot_attribute { | |
230 | struct attribute attr; | |
231 | ssize_t (*show)(struct pci_slot *, char *); | |
232 | ssize_t (*store)(struct pci_slot *, const char *, size_t); | |
233 | }; | |
234 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) | |
235 | ||
0b400c7e YZ |
236 | enum pci_bar_type { |
237 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
238 | pci_bar_io, /* An io port BAR */ | |
239 | pci_bar_mem32, /* A 32-bit memory BAR */ | |
240 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
241 | }; | |
242 | ||
efdc87da YL |
243 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
244 | int crs_timeout); | |
f39d5b72 BH |
245 | int pci_setup_device(struct pci_dev *dev); |
246 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
247 | struct resource *res, unsigned int reg); | |
248 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type); | |
249 | void pci_configure_ari(struct pci_dev *dev); | |
10874f5a | 250 | void __pci_bus_size_bridges(struct pci_bus *bus, |
d66ecb72 | 251 | struct list_head *realloc_head); |
10874f5a BH |
252 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
253 | struct list_head *realloc_head, | |
254 | struct list_head *fail_head); | |
0f7e7aee | 255 | bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
939de1d6 | 256 | |
2069ecfb | 257 | void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
f39d5b72 | 258 | void pci_disable_bridge_window(struct pci_dev *dev); |
32a9a682 | 259 | |
d1b054da YZ |
260 | /* Single Root I/O Virtualization */ |
261 | struct pci_sriov { | |
262 | int pos; /* capability position */ | |
263 | int nres; /* number of resources */ | |
264 | u32 cap; /* SR-IOV Capabilities */ | |
265 | u16 ctrl; /* SR-IOV Control */ | |
6b136724 BH |
266 | u16 total_VFs; /* total VFs associated with the PF */ |
267 | u16 initial_VFs; /* initial VFs associated with the PF */ | |
268 | u16 num_VFs; /* number of VFs available */ | |
d1b054da YZ |
269 | u16 offset; /* first VF Routing ID offset */ |
270 | u16 stride; /* following VF stride */ | |
271 | u32 pgsz; /* page size for BAR alignment */ | |
272 | u8 link; /* Function Dependency Link */ | |
4449f079 | 273 | u8 max_VF_buses; /* max buses consumed by VFs */ |
6b136724 | 274 | u16 driver_max_VFs; /* max num VFs driver supports */ |
d1b054da YZ |
275 | struct pci_dev *dev; /* lowest numbered PF */ |
276 | struct pci_dev *self; /* this PF */ | |
277 | struct mutex lock; /* lock for VF bus */ | |
0e6c9122 | 278 | resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
d1b054da YZ |
279 | }; |
280 | ||
1900ca13 | 281 | #ifdef CONFIG_PCI_ATS |
f39d5b72 | 282 | void pci_restore_ats_state(struct pci_dev *dev); |
1900ca13 HX |
283 | #else |
284 | static inline void pci_restore_ats_state(struct pci_dev *dev) | |
285 | { | |
286 | } | |
287 | #endif /* CONFIG_PCI_ATS */ | |
288 | ||
d1b054da | 289 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
290 | int pci_iov_init(struct pci_dev *dev); |
291 | void pci_iov_release(struct pci_dev *dev); | |
26ff46c6 | 292 | int pci_iov_resource_bar(struct pci_dev *dev, int resno); |
f39d5b72 BH |
293 | resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
294 | void pci_restore_iov_state(struct pci_dev *dev); | |
295 | int pci_iov_bus_range(struct pci_bus *bus); | |
302b4215 | 296 | |
d1b054da YZ |
297 | #else |
298 | static inline int pci_iov_init(struct pci_dev *dev) | |
299 | { | |
300 | return -ENODEV; | |
301 | } | |
302 | static inline void pci_iov_release(struct pci_dev *dev) | |
303 | ||
304 | { | |
305 | } | |
26ff46c6 | 306 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno) |
d1b054da YZ |
307 | { |
308 | return 0; | |
309 | } | |
8c5cdb6a YZ |
310 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
311 | { | |
312 | } | |
a28724b0 YZ |
313 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
314 | { | |
315 | return 0; | |
316 | } | |
302b4215 | 317 | |
d1b054da YZ |
318 | #endif /* CONFIG_PCI_IOV */ |
319 | ||
f39d5b72 | 320 | unsigned long pci_cardbus_resource_alignment(struct resource *); |
0a2daa1c | 321 | |
0e52247a | 322 | static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
f39d5b72 | 323 | struct resource *res) |
6faf17f6 CW |
324 | { |
325 | #ifdef CONFIG_PCI_IOV | |
326 | int resno = res - dev->resource; | |
327 | ||
328 | if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) | |
329 | return pci_sriov_resource_alignment(dev, resno); | |
330 | #endif | |
0a2daa1c RP |
331 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
332 | return pci_cardbus_resource_alignment(res); | |
6faf17f6 CW |
333 | return resource_alignment(res); |
334 | } | |
335 | ||
f39d5b72 | 336 | void pci_enable_acs(struct pci_dev *dev); |
ae21ee65 | 337 | |
9bb04a0c JY |
338 | #ifdef CONFIG_PCIE_PTM |
339 | void pci_ptm_init(struct pci_dev *dev); | |
340 | #else | |
341 | static inline void pci_ptm_init(struct pci_dev *dev) { } | |
342 | #endif | |
343 | ||
b9c3b266 DC |
344 | struct pci_dev_reset_methods { |
345 | u16 vendor; | |
346 | u16 device; | |
347 | int (*reset)(struct pci_dev *dev, int probe); | |
348 | }; | |
349 | ||
93177a74 | 350 | #ifdef CONFIG_PCI_QUIRKS |
f39d5b72 | 351 | int pci_dev_specific_reset(struct pci_dev *dev, int probe); |
93177a74 RW |
352 | #else |
353 | static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
354 | { | |
355 | return -ENOTTY; | |
356 | } | |
357 | #endif | |
b9c3b266 | 358 | |
557848c3 | 359 | #endif /* DRIVERS_PCI_H */ |