Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
557848c3 ZY |
2 | #ifndef DRIVERS_PCI_H |
3 | #define DRIVERS_PCI_H | |
4 | ||
fff905f3 WY |
5 | #define PCI_FIND_CAP_TTL 48 |
6 | ||
8531e283 LW |
7 | #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ |
8 | ||
343e51ae JK |
9 | extern const unsigned char pcie_link_speed[]; |
10 | ||
7a1562d4 YL |
11 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
12 | ||
1da177e4 LT |
13 | /* Functions internal to the PCI core code */ |
14 | ||
f39d5b72 BH |
15 | int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
16 | void pci_remove_sysfs_dev_files(struct pci_dev *pdev); | |
6058989b | 17 | #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) |
911e1c9b | 18 | static inline void pci_create_firmware_label_files(struct pci_dev *pdev) |
b879743f | 19 | { return; } |
911e1c9b | 20 | static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) |
b879743f | 21 | { return; } |
911e1c9b | 22 | #else |
f39d5b72 BH |
23 | void pci_create_firmware_label_files(struct pci_dev *pdev); |
24 | void pci_remove_firmware_label_files(struct pci_dev *pdev); | |
911e1c9b | 25 | #endif |
f39d5b72 | 26 | void pci_cleanup_rom(struct pci_dev *dev); |
f7195824 | 27 | |
3b519e4e MW |
28 | enum pci_mmap_api { |
29 | PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ | |
30 | PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ | |
31 | }; | |
f39d5b72 BH |
32 | int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
33 | enum pci_mmap_api mmap_api); | |
f7195824 | 34 | |
711d5779 | 35 | int pci_probe_reset_function(struct pci_dev *dev); |
ce5ccdef | 36 | |
961d9120 | 37 | /** |
b33bfdef | 38 | * struct pci_platform_pm_ops - Firmware PM callbacks |
961d9120 | 39 | * |
b33bfdef | 40 | * @is_manageable: returns 'true' if given device is power manageable by the |
0aa0f5d1 | 41 | * platform firmware |
961d9120 | 42 | * |
b33bfdef | 43 | * @set_state: invokes the platform firmware to set the device's power state |
961d9120 | 44 | * |
cc7cc02b LW |
45 | * @get_state: queries the platform firmware for a device's current power state |
46 | * | |
b33bfdef | 47 | * @choose_state: returns PCI power state of given device preferred by the |
0aa0f5d1 BH |
48 | * platform; to be used during system-wide transitions from a |
49 | * sleeping state to the working state and vice versa | |
961d9120 | 50 | * |
0847684c | 51 | * @set_wakeup: enables/disables wakeup capability for the device |
b67ea761 | 52 | * |
bac2a909 | 53 | * @need_resume: returns 'true' if the given device (which is currently |
0aa0f5d1 BH |
54 | * suspended) needs to be resumed to be configured for system |
55 | * wakeup. | |
bac2a909 | 56 | * |
961d9120 RW |
57 | * If given platform is generally capable of power managing PCI devices, all of |
58 | * these callbacks are mandatory. | |
59 | */ | |
60 | struct pci_platform_pm_ops { | |
61 | bool (*is_manageable)(struct pci_dev *dev); | |
62 | int (*set_state)(struct pci_dev *dev, pci_power_t state); | |
cc7cc02b | 63 | pci_power_t (*get_state)(struct pci_dev *dev); |
961d9120 | 64 | pci_power_t (*choose_state)(struct pci_dev *dev); |
0847684c | 65 | int (*set_wakeup)(struct pci_dev *dev, bool enable); |
bac2a909 | 66 | bool (*need_resume)(struct pci_dev *dev); |
961d9120 RW |
67 | }; |
68 | ||
299f2ffe | 69 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); |
f39d5b72 BH |
70 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
71 | void pci_power_up(struct pci_dev *dev); | |
72 | void pci_disable_enabled_device(struct pci_dev *dev); | |
73 | int pci_finish_runtime_suspend(struct pci_dev *dev); | |
dcb0453d | 74 | void pcie_clear_root_pme_status(struct pci_dev *dev); |
f39d5b72 | 75 | int __pci_pme_wakeup(struct pci_dev *dev, void *ign); |
0ce3fcaf | 76 | void pci_pme_restore(struct pci_dev *dev); |
bac2a909 | 77 | bool pci_dev_keep_suspended(struct pci_dev *dev); |
2cef548a | 78 | void pci_dev_complete_resume(struct pci_dev *pci_dev); |
f39d5b72 BH |
79 | void pci_config_pm_runtime_get(struct pci_dev *dev); |
80 | void pci_config_pm_runtime_put(struct pci_dev *dev); | |
81 | void pci_pm_init(struct pci_dev *dev); | |
938174e5 | 82 | void pci_ea_init(struct pci_dev *dev); |
f39d5b72 | 83 | void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
f796841e | 84 | void pci_free_cap_save_buffers(struct pci_dev *dev); |
c6a63307 | 85 | bool pci_bridge_d3_possible(struct pci_dev *dev); |
1ed276a7 | 86 | void pci_bridge_d3_update(struct pci_dev *dev); |
aa8c6c93 | 87 | |
b6e335ae RW |
88 | static inline void pci_wakeup_event(struct pci_dev *dev) |
89 | { | |
90 | /* Wait 100 ms before the system can be put into a sleep state. */ | |
91 | pm_wakeup_event(&dev->dev, 100); | |
92 | } | |
93 | ||
326c1cda | 94 | static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
aa8c6c93 RW |
95 | { |
96 | return !!(pci_dev->subordinate); | |
97 | } | |
0f64474b | 98 | |
9d26d3a8 MW |
99 | static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
100 | { | |
101 | /* | |
102 | * Currently we allow normal PCI devices and PCI bridges transition | |
103 | * into D3 if their bridge_d3 is set. | |
104 | */ | |
105 | return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; | |
106 | } | |
107 | ||
f1cd93f9 | 108 | int pci_vpd_init(struct pci_dev *dev); |
64379079 | 109 | void pci_vpd_release(struct pci_dev *dev); |
b1c615c4 BH |
110 | void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); |
111 | void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); | |
94e61088 | 112 | |
1da177e4 LT |
113 | /* PCI /proc functions */ |
114 | #ifdef CONFIG_PROC_FS | |
f39d5b72 BH |
115 | int pci_proc_attach_device(struct pci_dev *dev); |
116 | int pci_proc_detach_device(struct pci_dev *dev); | |
117 | int pci_proc_detach_bus(struct pci_bus *bus); | |
1da177e4 LT |
118 | #else |
119 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } | |
120 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } | |
1da177e4 LT |
121 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
122 | #endif | |
123 | ||
124 | /* Functions for PCI Hotplug drivers to use */ | |
a8e4b9c1 | 125 | int pci_hp_add_bridge(struct pci_dev *dev); |
1da177e4 | 126 | |
f19aeb1f | 127 | #ifdef HAVE_PCI_LEGACY |
f39d5b72 BH |
128 | void pci_create_legacy_files(struct pci_bus *bus); |
129 | void pci_remove_legacy_files(struct pci_bus *bus); | |
f19aeb1f BH |
130 | #else |
131 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
132 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
133 | #endif | |
1da177e4 LT |
134 | |
135 | /* Lock for read/write access to pci device and bus lists */ | |
d71374da | 136 | extern struct rw_semaphore pci_bus_sem; |
1da177e4 | 137 | |
a2e27787 JK |
138 | extern raw_spinlock_t pci_lock; |
139 | ||
ffadcc2f | 140 | extern unsigned int pci_pm_d3_delay; |
88187dfa | 141 | |
4b47b0ee | 142 | #ifdef CONFIG_PCI_MSI |
309e57df | 143 | void pci_no_msi(void); |
4b47b0ee | 144 | #else |
309e57df | 145 | static inline void pci_no_msi(void) { } |
4b47b0ee | 146 | #endif |
8fed4b65 | 147 | |
6a25f5e3 MT |
148 | static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) |
149 | { | |
150 | u16 control; | |
151 | ||
152 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
153 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
154 | if (enable) | |
155 | control |= PCI_MSI_FLAGS_ENABLE; | |
156 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
157 | } | |
158 | ||
159 | static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) | |
160 | { | |
161 | u16 ctrl; | |
162 | ||
163 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
164 | ctrl &= ~clear; | |
165 | ctrl |= set; | |
166 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
167 | } | |
168 | ||
b55438fd | 169 | void pci_realloc_get_opt(char *); |
f483d392 | 170 | |
ffadcc2f KCA |
171 | static inline int pci_no_d1d2(struct pci_dev *dev) |
172 | { | |
173 | unsigned int parent_dstates = 0; | |
4b47b0ee | 174 | |
ffadcc2f KCA |
175 | if (dev->bus->self) |
176 | parent_dstates = dev->bus->self->no_d1d2; | |
177 | return (dev->no_d1d2 || parent_dstates); | |
178 | ||
179 | } | |
5136b2da | 180 | extern const struct attribute_group *pci_dev_groups[]; |
56039e65 | 181 | extern const struct attribute_group *pcibus_groups[]; |
69f2dc24 | 182 | extern const struct device_type pci_dev_type; |
0f49ba55 | 183 | extern const struct attribute_group *pci_bus_groups[]; |
705b1aaa | 184 | |
1da177e4 LT |
185 | |
186 | /** | |
187 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
0aa0f5d1 | 188 | * PCI device id structure |
1da177e4 LT |
189 | * @id: single PCI device id structure to match |
190 | * @dev: the PCI device structure to match against | |
367b09fe | 191 | * |
1da177e4 LT |
192 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
193 | */ | |
194 | static inline const struct pci_device_id * | |
195 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) | |
196 | { | |
197 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && | |
198 | (id->device == PCI_ANY_ID || id->device == dev->device) && | |
199 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && | |
200 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && | |
201 | !((id->class ^ dev->class) & id->class_mask)) | |
202 | return id; | |
203 | return NULL; | |
204 | } | |
205 | ||
f46753c5 AC |
206 | /* PCI slot sysfs helper code */ |
207 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) | |
208 | ||
209 | extern struct kset *pci_slots_kset; | |
210 | ||
211 | struct pci_slot_attribute { | |
212 | struct attribute attr; | |
213 | ssize_t (*show)(struct pci_slot *, char *); | |
214 | ssize_t (*store)(struct pci_slot *, const char *, size_t); | |
215 | }; | |
216 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) | |
217 | ||
0b400c7e YZ |
218 | enum pci_bar_type { |
219 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
0aa0f5d1 | 220 | pci_bar_io, /* An I/O port BAR */ |
0b400c7e YZ |
221 | pci_bar_mem32, /* A 32-bit memory BAR */ |
222 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
223 | }; | |
224 | ||
62ce94a7 | 225 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign); |
efdc87da YL |
226 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
227 | int crs_timeout); | |
f39d5b72 BH |
228 | int pci_setup_device(struct pci_dev *dev); |
229 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
230 | struct resource *res, unsigned int reg); | |
f39d5b72 | 231 | void pci_configure_ari(struct pci_dev *dev); |
10874f5a | 232 | void __pci_bus_size_bridges(struct pci_bus *bus, |
d66ecb72 | 233 | struct list_head *realloc_head); |
10874f5a BH |
234 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
235 | struct list_head *realloc_head, | |
236 | struct list_head *fail_head); | |
0f7e7aee | 237 | bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
939de1d6 | 238 | |
2069ecfb | 239 | void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
f39d5b72 | 240 | void pci_disable_bridge_window(struct pci_dev *dev); |
32a9a682 | 241 | |
6cf57be0 TG |
242 | /* PCIe link information */ |
243 | #define PCIE_SPEED2STR(speed) \ | |
244 | ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ | |
245 | (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ | |
246 | (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ | |
247 | (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ | |
248 | "Unknown speed") | |
249 | ||
b852f63a TG |
250 | /* PCIe speed to Mb/s reduced by encoding overhead */ |
251 | #define PCIE_SPEED2MBS_ENC(speed) \ | |
252 | ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ | |
253 | (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ | |
254 | (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ | |
255 | (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ | |
256 | 0) | |
257 | ||
6cf57be0 | 258 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
c70b65fb | 259 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); |
b852f63a TG |
260 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, |
261 | enum pcie_link_width *width); | |
6cf57be0 | 262 | |
d1b054da YZ |
263 | /* Single Root I/O Virtualization */ |
264 | struct pci_sriov { | |
0aa0f5d1 BH |
265 | int pos; /* Capability position */ |
266 | int nres; /* Number of resources */ | |
267 | u32 cap; /* SR-IOV Capabilities */ | |
268 | u16 ctrl; /* SR-IOV Control */ | |
269 | u16 total_VFs; /* Total VFs associated with the PF */ | |
270 | u16 initial_VFs; /* Initial VFs associated with the PF */ | |
271 | u16 num_VFs; /* Number of VFs available */ | |
272 | u16 offset; /* First VF Routing ID offset */ | |
273 | u16 stride; /* Following VF stride */ | |
274 | u16 vf_device; /* VF device ID */ | |
275 | u32 pgsz; /* Page size for BAR alignment */ | |
276 | u8 link; /* Function Dependency Link */ | |
277 | u8 max_VF_buses; /* Max buses consumed by VFs */ | |
278 | u16 driver_max_VFs; /* Max num VFs driver supports */ | |
279 | struct pci_dev *dev; /* Lowest numbered PF */ | |
280 | struct pci_dev *self; /* This PF */ | |
cf0921be KA |
281 | u32 class; /* VF device */ |
282 | u8 hdr_type; /* VF header type */ | |
283 | u16 subsystem_vendor; /* VF subsystem vendor */ | |
284 | u16 subsystem_device; /* VF subsystem device */ | |
0aa0f5d1 BH |
285 | resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
286 | bool drivers_autoprobe; /* Auto probing of VFs by driver */ | |
d1b054da YZ |
287 | }; |
288 | ||
89ee9f76 KB |
289 | /* pci_dev priv_flags */ |
290 | #define PCI_DEV_DISCONNECTED 0 | |
291 | ||
292 | static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) | |
293 | { | |
294 | set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags); | |
295 | return 0; | |
296 | } | |
297 | ||
298 | static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) | |
299 | { | |
300 | return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags); | |
301 | } | |
302 | ||
1900ca13 | 303 | #ifdef CONFIG_PCI_ATS |
f39d5b72 | 304 | void pci_restore_ats_state(struct pci_dev *dev); |
1900ca13 HX |
305 | #else |
306 | static inline void pci_restore_ats_state(struct pci_dev *dev) | |
307 | { | |
308 | } | |
309 | #endif /* CONFIG_PCI_ATS */ | |
310 | ||
d1b054da | 311 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
312 | int pci_iov_init(struct pci_dev *dev); |
313 | void pci_iov_release(struct pci_dev *dev); | |
6ffa2489 | 314 | void pci_iov_update_resource(struct pci_dev *dev, int resno); |
f39d5b72 BH |
315 | resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
316 | void pci_restore_iov_state(struct pci_dev *dev); | |
317 | int pci_iov_bus_range(struct pci_bus *bus); | |
302b4215 | 318 | |
d1b054da YZ |
319 | #else |
320 | static inline int pci_iov_init(struct pci_dev *dev) | |
321 | { | |
322 | return -ENODEV; | |
323 | } | |
324 | static inline void pci_iov_release(struct pci_dev *dev) | |
325 | ||
326 | { | |
327 | } | |
8c5cdb6a YZ |
328 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
329 | { | |
330 | } | |
a28724b0 YZ |
331 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
332 | { | |
333 | return 0; | |
334 | } | |
302b4215 | 335 | |
d1b054da YZ |
336 | #endif /* CONFIG_PCI_IOV */ |
337 | ||
f39d5b72 | 338 | unsigned long pci_cardbus_resource_alignment(struct resource *); |
0a2daa1c | 339 | |
0e52247a | 340 | static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
f39d5b72 | 341 | struct resource *res) |
6faf17f6 CW |
342 | { |
343 | #ifdef CONFIG_PCI_IOV | |
344 | int resno = res - dev->resource; | |
345 | ||
346 | if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) | |
347 | return pci_sriov_resource_alignment(dev, resno); | |
348 | #endif | |
0aa0f5d1 | 349 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
0a2daa1c | 350 | return pci_cardbus_resource_alignment(res); |
6faf17f6 CW |
351 | return resource_alignment(res); |
352 | } | |
353 | ||
f39d5b72 | 354 | void pci_enable_acs(struct pci_dev *dev); |
ae21ee65 | 355 | |
7d8e7d19 BH |
356 | #ifdef CONFIG_PCIEASPM |
357 | void pcie_aspm_init_link_state(struct pci_dev *pdev); | |
358 | void pcie_aspm_exit_link_state(struct pci_dev *pdev); | |
359 | void pcie_aspm_pm_state_change(struct pci_dev *pdev); | |
360 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev); | |
361 | #else | |
362 | static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } | |
363 | static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } | |
364 | static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } | |
365 | static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } | |
366 | #endif | |
367 | ||
368 | #ifdef CONFIG_PCIEASPM_DEBUG | |
369 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); | |
370 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); | |
371 | #else | |
372 | static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { } | |
373 | static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { } | |
374 | #endif | |
375 | ||
9bb04a0c JY |
376 | #ifdef CONFIG_PCIE_PTM |
377 | void pci_ptm_init(struct pci_dev *dev); | |
378 | #else | |
379 | static inline void pci_ptm_init(struct pci_dev *dev) { } | |
380 | #endif | |
381 | ||
b9c3b266 DC |
382 | struct pci_dev_reset_methods { |
383 | u16 vendor; | |
384 | u16 device; | |
385 | int (*reset)(struct pci_dev *dev, int probe); | |
386 | }; | |
387 | ||
93177a74 | 388 | #ifdef CONFIG_PCI_QUIRKS |
f39d5b72 | 389 | int pci_dev_specific_reset(struct pci_dev *dev, int probe); |
93177a74 RW |
390 | #else |
391 | static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
392 | { | |
393 | return -ENOTTY; | |
394 | } | |
395 | #endif | |
b9c3b266 | 396 | |
169de969 DL |
397 | #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) |
398 | int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, | |
399 | struct resource *res); | |
400 | #endif | |
401 | ||
276b738d CK |
402 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); |
403 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); | |
404 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); | |
405 | static inline u64 pci_rebar_size_to_bytes(int size) | |
406 | { | |
407 | return 1ULL << (size + 20); | |
408 | } | |
409 | ||
557848c3 | 410 | #endif /* DRIVERS_PCI_H */ |