Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/spinlock.h> | |
4e57b681 | 17 | #include <linux/string.h> |
229f5afd | 18 | #include <linux/log2.h> |
7d715a6c | 19 | #include <linux/pci-aspm.h> |
c300bd2f | 20 | #include <linux/pm_wakeup.h> |
8dd7f803 | 21 | #include <linux/interrupt.h> |
1da177e4 | 22 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 23 | #include "pci.h" |
1da177e4 | 24 | |
ffadcc2f | 25 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 | 26 | |
32a2eea7 JG |
27 | #ifdef CONFIG_PCI_DOMAINS |
28 | int pci_domains_supported = 1; | |
29 | #endif | |
30 | ||
4516a618 AN |
31 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
32 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
33 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
34 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
35 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
36 | ||
1da177e4 LT |
37 | /** |
38 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
39 | * @bus: pointer to PCI bus structure to search | |
40 | * | |
41 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
42 | * including the given PCI bus and its list of child PCI buses. | |
43 | */ | |
96bde06a | 44 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
45 | { |
46 | struct list_head *tmp; | |
47 | unsigned char max, n; | |
48 | ||
b82db5ce | 49 | max = bus->subordinate; |
1da177e4 LT |
50 | list_for_each(tmp, &bus->children) { |
51 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
52 | if(n > max) | |
53 | max = n; | |
54 | } | |
55 | return max; | |
56 | } | |
b82db5ce | 57 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 58 | |
b82db5ce | 59 | #if 0 |
1da177e4 LT |
60 | /** |
61 | * pci_max_busnr - returns maximum PCI bus number | |
62 | * | |
63 | * Returns the highest PCI bus number present in the system global list of | |
64 | * PCI buses. | |
65 | */ | |
66 | unsigned char __devinit | |
67 | pci_max_busnr(void) | |
68 | { | |
69 | struct pci_bus *bus = NULL; | |
70 | unsigned char max, n; | |
71 | ||
72 | max = 0; | |
73 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
74 | n = pci_bus_max_busnr(bus); | |
75 | if(n > max) | |
76 | max = n; | |
77 | } | |
78 | return max; | |
79 | } | |
80 | ||
54c762fe AB |
81 | #endif /* 0 */ |
82 | ||
687d5fe3 ME |
83 | #define PCI_FIND_CAP_TTL 48 |
84 | ||
85 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
86 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
87 | { |
88 | u8 id; | |
24a4e377 | 89 | |
687d5fe3 | 90 | while ((*ttl)--) { |
24a4e377 RD |
91 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
92 | if (pos < 0x40) | |
93 | break; | |
94 | pos &= ~3; | |
95 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
96 | &id); | |
97 | if (id == 0xff) | |
98 | break; | |
99 | if (id == cap) | |
100 | return pos; | |
101 | pos += PCI_CAP_LIST_NEXT; | |
102 | } | |
103 | return 0; | |
104 | } | |
105 | ||
687d5fe3 ME |
106 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
107 | u8 pos, int cap) | |
108 | { | |
109 | int ttl = PCI_FIND_CAP_TTL; | |
110 | ||
111 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
112 | } | |
113 | ||
24a4e377 RD |
114 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
115 | { | |
116 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
117 | pos + PCI_CAP_LIST_NEXT, cap); | |
118 | } | |
119 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
120 | ||
d3bac118 ME |
121 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
122 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
123 | { |
124 | u16 status; | |
1da177e4 LT |
125 | |
126 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
127 | if (!(status & PCI_STATUS_CAP_LIST)) | |
128 | return 0; | |
129 | ||
130 | switch (hdr_type) { | |
131 | case PCI_HEADER_TYPE_NORMAL: | |
132 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 133 | return PCI_CAPABILITY_LIST; |
1da177e4 | 134 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 135 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
136 | default: |
137 | return 0; | |
138 | } | |
d3bac118 ME |
139 | |
140 | return 0; | |
1da177e4 LT |
141 | } |
142 | ||
143 | /** | |
144 | * pci_find_capability - query for devices' capabilities | |
145 | * @dev: PCI device to query | |
146 | * @cap: capability code | |
147 | * | |
148 | * Tell if a device supports a given PCI capability. | |
149 | * Returns the address of the requested capability structure within the | |
150 | * device's PCI configuration space or 0 in case the device does not | |
151 | * support it. Possible values for @cap: | |
152 | * | |
153 | * %PCI_CAP_ID_PM Power Management | |
154 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
155 | * %PCI_CAP_ID_VPD Vital Product Data | |
156 | * %PCI_CAP_ID_SLOTID Slot Identification | |
157 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
158 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
159 | * %PCI_CAP_ID_PCIX PCI-X | |
160 | * %PCI_CAP_ID_EXP PCI Express | |
161 | */ | |
162 | int pci_find_capability(struct pci_dev *dev, int cap) | |
163 | { | |
d3bac118 ME |
164 | int pos; |
165 | ||
166 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
167 | if (pos) | |
168 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
169 | ||
170 | return pos; | |
1da177e4 LT |
171 | } |
172 | ||
173 | /** | |
174 | * pci_bus_find_capability - query for devices' capabilities | |
175 | * @bus: the PCI bus to query | |
176 | * @devfn: PCI device to query | |
177 | * @cap: capability code | |
178 | * | |
179 | * Like pci_find_capability() but works for pci devices that do not have a | |
180 | * pci_dev structure set up yet. | |
181 | * | |
182 | * Returns the address of the requested capability structure within the | |
183 | * device's PCI configuration space or 0 in case the device does not | |
184 | * support it. | |
185 | */ | |
186 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
187 | { | |
d3bac118 | 188 | int pos; |
1da177e4 LT |
189 | u8 hdr_type; |
190 | ||
191 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
192 | ||
d3bac118 ME |
193 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
194 | if (pos) | |
195 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
196 | ||
197 | return pos; | |
1da177e4 LT |
198 | } |
199 | ||
200 | /** | |
201 | * pci_find_ext_capability - Find an extended capability | |
202 | * @dev: PCI device to query | |
203 | * @cap: capability code | |
204 | * | |
205 | * Returns the address of the requested extended capability structure | |
206 | * within the device's PCI configuration space or 0 if the device does | |
207 | * not support it. Possible values for @cap: | |
208 | * | |
209 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
210 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
211 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
212 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
213 | */ | |
214 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
215 | { | |
216 | u32 header; | |
557848c3 ZY |
217 | int ttl; |
218 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 219 | |
557848c3 ZY |
220 | /* minimum 8 bytes per capability */ |
221 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
222 | ||
223 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
224 | return 0; |
225 | ||
226 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
227 | return 0; | |
228 | ||
229 | /* | |
230 | * If we have no capabilities, this is indicated by cap ID, | |
231 | * cap version and next pointer all being 0. | |
232 | */ | |
233 | if (header == 0) | |
234 | return 0; | |
235 | ||
236 | while (ttl-- > 0) { | |
237 | if (PCI_EXT_CAP_ID(header) == cap) | |
238 | return pos; | |
239 | ||
240 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 241 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
242 | break; |
243 | ||
244 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
245 | break; | |
246 | } | |
247 | ||
248 | return 0; | |
249 | } | |
3a720d72 | 250 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 251 | |
687d5fe3 ME |
252 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
253 | { | |
254 | int rc, ttl = PCI_FIND_CAP_TTL; | |
255 | u8 cap, mask; | |
256 | ||
257 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
258 | mask = HT_3BIT_CAP_MASK; | |
259 | else | |
260 | mask = HT_5BIT_CAP_MASK; | |
261 | ||
262 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
263 | PCI_CAP_ID_HT, &ttl); | |
264 | while (pos) { | |
265 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
266 | if (rc != PCIBIOS_SUCCESSFUL) | |
267 | return 0; | |
268 | ||
269 | if ((cap & mask) == ht_cap) | |
270 | return pos; | |
271 | ||
47a4d5be BG |
272 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
273 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
274 | PCI_CAP_ID_HT, &ttl); |
275 | } | |
276 | ||
277 | return 0; | |
278 | } | |
279 | /** | |
280 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
281 | * @dev: PCI device to query | |
282 | * @pos: Position from which to continue searching | |
283 | * @ht_cap: Hypertransport capability code | |
284 | * | |
285 | * To be used in conjunction with pci_find_ht_capability() to search for | |
286 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
287 | * from pci_find_ht_capability(). | |
288 | * | |
289 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
290 | * steps to avoid an infinite loop. | |
291 | */ | |
292 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
293 | { | |
294 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
295 | } | |
296 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
297 | ||
298 | /** | |
299 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
300 | * @dev: PCI device to query | |
301 | * @ht_cap: Hypertransport capability code | |
302 | * | |
303 | * Tell if a device supports a given Hypertransport capability. | |
304 | * Returns an address within the device's PCI configuration space | |
305 | * or 0 in case the device does not support the request capability. | |
306 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
307 | * which has a Hypertransport capability matching @ht_cap. | |
308 | */ | |
309 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
310 | { | |
311 | int pos; | |
312 | ||
313 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
314 | if (pos) | |
315 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
316 | ||
317 | return pos; | |
318 | } | |
319 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
320 | ||
1da177e4 LT |
321 | /** |
322 | * pci_find_parent_resource - return resource region of parent bus of given region | |
323 | * @dev: PCI device structure contains resources to be searched | |
324 | * @res: child resource record for which parent is sought | |
325 | * | |
326 | * For given resource region of given device, return the resource | |
327 | * region of parent bus the given region is contained in or where | |
328 | * it should be allocated from. | |
329 | */ | |
330 | struct resource * | |
331 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
332 | { | |
333 | const struct pci_bus *bus = dev->bus; | |
334 | int i; | |
335 | struct resource *best = NULL; | |
336 | ||
337 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
338 | struct resource *r = bus->resource[i]; | |
339 | if (!r) | |
340 | continue; | |
341 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
342 | continue; /* Not contained */ | |
343 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
344 | continue; /* Wrong type */ | |
345 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
346 | return r; /* Exact match */ | |
347 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
348 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
349 | } | |
350 | return best; | |
351 | } | |
352 | ||
064b53db JL |
353 | /** |
354 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
355 | * @dev: PCI device to have its BARs restored | |
356 | * | |
357 | * Restore the BAR values for a given device, so as to make it | |
358 | * accessible by its driver. | |
359 | */ | |
ad668599 | 360 | static void |
064b53db JL |
361 | pci_restore_bars(struct pci_dev *dev) |
362 | { | |
363 | int i, numres; | |
364 | ||
365 | switch (dev->hdr_type) { | |
366 | case PCI_HEADER_TYPE_NORMAL: | |
367 | numres = 6; | |
368 | break; | |
369 | case PCI_HEADER_TYPE_BRIDGE: | |
370 | numres = 2; | |
371 | break; | |
372 | case PCI_HEADER_TYPE_CARDBUS: | |
373 | numres = 1; | |
374 | break; | |
375 | default: | |
376 | /* Should never get here, but just in case... */ | |
377 | return; | |
378 | } | |
379 | ||
380 | for (i = 0; i < numres; i ++) | |
381 | pci_update_resource(dev, &dev->resource[i], i); | |
382 | } | |
383 | ||
961d9120 RW |
384 | static struct pci_platform_pm_ops *pci_platform_pm; |
385 | ||
386 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
387 | { | |
eb9d0fe4 RW |
388 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
389 | || !ops->sleep_wake || !ops->can_wakeup) | |
961d9120 RW |
390 | return -EINVAL; |
391 | pci_platform_pm = ops; | |
392 | return 0; | |
393 | } | |
394 | ||
395 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
396 | { | |
397 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
398 | } | |
399 | ||
400 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
401 | pci_power_t t) | |
402 | { | |
403 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
404 | } | |
405 | ||
406 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
407 | { | |
408 | return pci_platform_pm ? | |
409 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
410 | } | |
8f7020d3 | 411 | |
eb9d0fe4 RW |
412 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
413 | { | |
414 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; | |
415 | } | |
416 | ||
417 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) | |
418 | { | |
419 | return pci_platform_pm ? | |
420 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
421 | } | |
422 | ||
1da177e4 | 423 | /** |
44e4e66e RW |
424 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
425 | * given PCI device | |
426 | * @dev: PCI device to handle. | |
44e4e66e | 427 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 428 | * |
44e4e66e RW |
429 | * RETURN VALUE: |
430 | * -EINVAL if the requested state is invalid. | |
431 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
432 | * wrong version, or device doesn't support the requested state. | |
433 | * 0 if device already is in the requested state. | |
434 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 435 | */ |
44e4e66e | 436 | static int |
337001b6 | 437 | pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 438 | { |
337001b6 | 439 | u16 pmcsr; |
44e4e66e | 440 | bool need_restore = false; |
1da177e4 | 441 | |
337001b6 | 442 | if (!dev->pm_cap) |
cca03dec AL |
443 | return -EIO; |
444 | ||
44e4e66e RW |
445 | if (state < PCI_D0 || state > PCI_D3hot) |
446 | return -EINVAL; | |
447 | ||
1da177e4 LT |
448 | /* Validate current state: |
449 | * Can enter D0 from any state, but if we can only go deeper | |
450 | * to sleep if we're already in a low power state | |
451 | */ | |
44e4e66e RW |
452 | if (dev->current_state == state) { |
453 | /* we're already there */ | |
454 | return 0; | |
455 | } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold | |
456 | && dev->current_state > state) { | |
80ccba11 BH |
457 | dev_err(&dev->dev, "invalid power transition " |
458 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 459 | return -EINVAL; |
44e4e66e | 460 | } |
1da177e4 | 461 | |
1da177e4 | 462 | /* check if this device supports the desired state */ |
337001b6 RW |
463 | if ((state == PCI_D1 && !dev->d1_support) |
464 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 465 | return -EIO; |
1da177e4 | 466 | |
337001b6 | 467 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 468 | |
32a36585 | 469 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
470 | * This doesn't affect PME_Status, disables PME_En, and |
471 | * sets PowerState to 0. | |
472 | */ | |
32a36585 | 473 | switch (dev->current_state) { |
d3535fbb JL |
474 | case PCI_D0: |
475 | case PCI_D1: | |
476 | case PCI_D2: | |
477 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
478 | pmcsr |= state; | |
479 | break; | |
32a36585 JL |
480 | case PCI_UNKNOWN: /* Boot-up */ |
481 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
482 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
44e4e66e | 483 | need_restore = true; |
32a36585 | 484 | /* Fall-through: force to D0 */ |
32a36585 | 485 | default: |
d3535fbb | 486 | pmcsr = 0; |
32a36585 | 487 | break; |
1da177e4 LT |
488 | } |
489 | ||
490 | /* enter specified state */ | |
337001b6 | 491 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
492 | |
493 | /* Mandatory power management transition delays */ | |
494 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
495 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 496 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
497 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
498 | udelay(200); | |
1da177e4 | 499 | |
b913100d | 500 | dev->current_state = state; |
064b53db JL |
501 | |
502 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
503 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
504 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
505 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
506 | * For example, at least some versions of the 3c905B and the | |
507 | * 3c556B exhibit this behaviour. | |
508 | * | |
509 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
510 | * devices in a D3hot state at boot. Consequently, we need to | |
511 | * restore at least the BARs so that the device will be | |
512 | * accessible to its driver. | |
513 | */ | |
514 | if (need_restore) | |
515 | pci_restore_bars(dev); | |
516 | ||
7d715a6c SL |
517 | if (dev->bus->self) |
518 | pcie_aspm_pm_state_change(dev->bus->self); | |
519 | ||
1da177e4 LT |
520 | return 0; |
521 | } | |
522 | ||
44e4e66e RW |
523 | /** |
524 | * pci_update_current_state - Read PCI power state of given device from its | |
525 | * PCI PM registers and cache it | |
526 | * @dev: PCI device to handle. | |
44e4e66e | 527 | */ |
337001b6 | 528 | static void pci_update_current_state(struct pci_dev *dev) |
44e4e66e | 529 | { |
337001b6 | 530 | if (dev->pm_cap) { |
44e4e66e RW |
531 | u16 pmcsr; |
532 | ||
337001b6 | 533 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e RW |
534 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
535 | } | |
536 | } | |
537 | ||
538 | /** | |
539 | * pci_set_power_state - Set the power state of a PCI device | |
540 | * @dev: PCI device to handle. | |
541 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
542 | * | |
543 | * Transition a device to a new power state, using the platform formware and/or | |
544 | * the device's PCI PM registers. | |
545 | * | |
546 | * RETURN VALUE: | |
547 | * -EINVAL if the requested state is invalid. | |
548 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
549 | * wrong version, or device doesn't support the requested state. | |
550 | * 0 if device already is in the requested state. | |
551 | * 0 if device's power state has been successfully changed. | |
552 | */ | |
553 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
554 | { | |
337001b6 | 555 | int error; |
44e4e66e RW |
556 | |
557 | /* bound the state we're entering */ | |
558 | if (state > PCI_D3hot) | |
559 | state = PCI_D3hot; | |
560 | else if (state < PCI_D0) | |
561 | state = PCI_D0; | |
562 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
563 | /* | |
564 | * If the device or the parent bridge do not support PCI PM, | |
565 | * ignore the request if we're doing anything other than putting | |
566 | * it into D0 (which would only happen on boot). | |
567 | */ | |
568 | return 0; | |
569 | ||
44e4e66e RW |
570 | if (state == PCI_D0 && platform_pci_power_manageable(dev)) { |
571 | /* | |
572 | * Allow the platform to change the state, for example via ACPI | |
573 | * _PR0, _PS0 and some such, but do not trust it. | |
574 | */ | |
575 | int ret = platform_pci_set_power_state(dev, PCI_D0); | |
576 | if (!ret) | |
337001b6 | 577 | pci_update_current_state(dev); |
44e4e66e | 578 | } |
979b1791 AC |
579 | /* This device is quirked not to be put into D3, so |
580 | don't put it in D3 */ | |
581 | if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) | |
582 | return 0; | |
44e4e66e | 583 | |
337001b6 | 584 | error = pci_raw_set_power_state(dev, state); |
44e4e66e RW |
585 | |
586 | if (state > PCI_D0 && platform_pci_power_manageable(dev)) { | |
587 | /* Allow the platform to finalize the transition */ | |
588 | int ret = platform_pci_set_power_state(dev, state); | |
589 | if (!ret) { | |
337001b6 | 590 | pci_update_current_state(dev); |
44e4e66e RW |
591 | error = 0; |
592 | } | |
593 | } | |
594 | ||
595 | return error; | |
596 | } | |
597 | ||
1da177e4 LT |
598 | /** |
599 | * pci_choose_state - Choose the power state of a PCI device | |
600 | * @dev: PCI device to be suspended | |
601 | * @state: target sleep state for the whole system. This is the value | |
602 | * that is passed to suspend() function. | |
603 | * | |
604 | * Returns PCI power state suitable for given device and given system | |
605 | * message. | |
606 | */ | |
607 | ||
608 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
609 | { | |
ab826ca4 | 610 | pci_power_t ret; |
0f64474b | 611 | |
1da177e4 LT |
612 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
613 | return PCI_D0; | |
614 | ||
961d9120 RW |
615 | ret = platform_pci_choose_state(dev); |
616 | if (ret != PCI_POWER_ERROR) | |
617 | return ret; | |
ca078bae PM |
618 | |
619 | switch (state.event) { | |
620 | case PM_EVENT_ON: | |
621 | return PCI_D0; | |
622 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
623 | case PM_EVENT_PRETHAW: |
624 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 625 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 626 | case PM_EVENT_HIBERNATE: |
ca078bae | 627 | return PCI_D3hot; |
1da177e4 | 628 | default: |
80ccba11 BH |
629 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
630 | state.event); | |
1da177e4 LT |
631 | BUG(); |
632 | } | |
633 | return PCI_D0; | |
634 | } | |
635 | ||
636 | EXPORT_SYMBOL(pci_choose_state); | |
637 | ||
b56a5a23 MT |
638 | static int pci_save_pcie_state(struct pci_dev *dev) |
639 | { | |
640 | int pos, i = 0; | |
641 | struct pci_cap_saved_state *save_state; | |
642 | u16 *cap; | |
017fc480 | 643 | int found = 0; |
b56a5a23 MT |
644 | |
645 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
646 | if (pos <= 0) | |
647 | return 0; | |
648 | ||
9f35575d EB |
649 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
650 | if (!save_state) | |
651 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
017fc480 SL |
652 | else |
653 | found = 1; | |
b56a5a23 | 654 | if (!save_state) { |
80ccba11 | 655 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
b56a5a23 MT |
656 | return -ENOMEM; |
657 | } | |
658 | cap = (u16 *)&save_state->data[0]; | |
659 | ||
660 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
661 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
662 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
663 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
ec0a3a27 | 664 | save_state->cap_nr = PCI_CAP_ID_EXP; |
017fc480 SL |
665 | if (!found) |
666 | pci_add_saved_cap(dev, save_state); | |
b56a5a23 MT |
667 | return 0; |
668 | } | |
669 | ||
670 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
671 | { | |
672 | int i = 0, pos; | |
673 | struct pci_cap_saved_state *save_state; | |
674 | u16 *cap; | |
675 | ||
676 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
677 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
678 | if (!save_state || pos <= 0) | |
679 | return; | |
680 | cap = (u16 *)&save_state->data[0]; | |
681 | ||
682 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
683 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
684 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
685 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
b56a5a23 MT |
686 | } |
687 | ||
cc692a5f SH |
688 | |
689 | static int pci_save_pcix_state(struct pci_dev *dev) | |
690 | { | |
691 | int pos, i = 0; | |
692 | struct pci_cap_saved_state *save_state; | |
693 | u16 *cap; | |
017fc480 | 694 | int found = 0; |
cc692a5f SH |
695 | |
696 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
697 | if (pos <= 0) | |
698 | return 0; | |
699 | ||
f34303de | 700 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
9f35575d EB |
701 | if (!save_state) |
702 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); | |
017fc480 SL |
703 | else |
704 | found = 1; | |
cc692a5f | 705 | if (!save_state) { |
80ccba11 | 706 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
cc692a5f SH |
707 | return -ENOMEM; |
708 | } | |
709 | cap = (u16 *)&save_state->data[0]; | |
710 | ||
711 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); | |
ec0a3a27 | 712 | save_state->cap_nr = PCI_CAP_ID_PCIX; |
017fc480 SL |
713 | if (!found) |
714 | pci_add_saved_cap(dev, save_state); | |
cc692a5f SH |
715 | return 0; |
716 | } | |
717 | ||
718 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
719 | { | |
720 | int i = 0, pos; | |
721 | struct pci_cap_saved_state *save_state; | |
722 | u16 *cap; | |
723 | ||
724 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
725 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
726 | if (!save_state || pos <= 0) | |
727 | return; | |
728 | cap = (u16 *)&save_state->data[0]; | |
729 | ||
730 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
731 | } |
732 | ||
733 | ||
1da177e4 LT |
734 | /** |
735 | * pci_save_state - save the PCI configuration space of a device before suspending | |
736 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
737 | */ |
738 | int | |
739 | pci_save_state(struct pci_dev *dev) | |
740 | { | |
741 | int i; | |
742 | /* XXX: 100% dword access ok here? */ | |
743 | for (i = 0; i < 16; i++) | |
744 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
b56a5a23 MT |
745 | if ((i = pci_save_pcie_state(dev)) != 0) |
746 | return i; | |
cc692a5f SH |
747 | if ((i = pci_save_pcix_state(dev)) != 0) |
748 | return i; | |
1da177e4 LT |
749 | return 0; |
750 | } | |
751 | ||
752 | /** | |
753 | * pci_restore_state - Restore the saved state of a PCI device | |
754 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
755 | */ |
756 | int | |
757 | pci_restore_state(struct pci_dev *dev) | |
758 | { | |
759 | int i; | |
b4482a4b | 760 | u32 val; |
1da177e4 | 761 | |
b56a5a23 MT |
762 | /* PCI Express register must be restored first */ |
763 | pci_restore_pcie_state(dev); | |
764 | ||
8b8c8d28 YL |
765 | /* |
766 | * The Base Address register should be programmed before the command | |
767 | * register(s) | |
768 | */ | |
769 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
770 | pci_read_config_dword(dev, i * 4, &val); |
771 | if (val != dev->saved_config_space[i]) { | |
80ccba11 BH |
772 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
773 | "space at offset %#x (was %#x, writing %#x)\n", | |
774 | i, val, (int)dev->saved_config_space[i]); | |
04d9c1a1 DJ |
775 | pci_write_config_dword(dev,i * 4, |
776 | dev->saved_config_space[i]); | |
777 | } | |
778 | } | |
cc692a5f | 779 | pci_restore_pcix_state(dev); |
41017f0c | 780 | pci_restore_msi_state(dev); |
8fed4b65 | 781 | |
1da177e4 LT |
782 | return 0; |
783 | } | |
784 | ||
38cc1302 HS |
785 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
786 | { | |
787 | int err; | |
788 | ||
789 | err = pci_set_power_state(dev, PCI_D0); | |
790 | if (err < 0 && err != -EIO) | |
791 | return err; | |
792 | err = pcibios_enable_device(dev, bars); | |
793 | if (err < 0) | |
794 | return err; | |
795 | pci_fixup_device(pci_fixup_enable, dev); | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | /** | |
0b62e13b | 801 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
802 | * @dev: PCI device to be resumed |
803 | * | |
804 | * Note this function is a backend of pci_default_resume and is not supposed | |
805 | * to be called by normal code, write proper resume handler and use it instead. | |
806 | */ | |
0b62e13b | 807 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 HS |
808 | { |
809 | if (atomic_read(&dev->enable_cnt)) | |
810 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
811 | return 0; | |
812 | } | |
813 | ||
b718989d BH |
814 | static int __pci_enable_device_flags(struct pci_dev *dev, |
815 | resource_size_t flags) | |
1da177e4 LT |
816 | { |
817 | int err; | |
b718989d | 818 | int i, bars = 0; |
1da177e4 | 819 | |
9fb625c3 HS |
820 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
821 | return 0; /* already enabled */ | |
822 | ||
b718989d BH |
823 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
824 | if (dev->resource[i].flags & flags) | |
825 | bars |= (1 << i); | |
826 | ||
38cc1302 | 827 | err = do_pci_enable_device(dev, bars); |
95a62965 | 828 | if (err < 0) |
38cc1302 | 829 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 830 | return err; |
1da177e4 LT |
831 | } |
832 | ||
b718989d BH |
833 | /** |
834 | * pci_enable_device_io - Initialize a device for use with IO space | |
835 | * @dev: PCI device to be initialized | |
836 | * | |
837 | * Initialize device before it's used by a driver. Ask low-level code | |
838 | * to enable I/O resources. Wake up the device if it was suspended. | |
839 | * Beware, this function can fail. | |
840 | */ | |
841 | int pci_enable_device_io(struct pci_dev *dev) | |
842 | { | |
843 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
844 | } | |
845 | ||
846 | /** | |
847 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
848 | * @dev: PCI device to be initialized | |
849 | * | |
850 | * Initialize device before it's used by a driver. Ask low-level code | |
851 | * to enable Memory resources. Wake up the device if it was suspended. | |
852 | * Beware, this function can fail. | |
853 | */ | |
854 | int pci_enable_device_mem(struct pci_dev *dev) | |
855 | { | |
856 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
857 | } | |
858 | ||
bae94d02 IPG |
859 | /** |
860 | * pci_enable_device - Initialize device before it's used by a driver. | |
861 | * @dev: PCI device to be initialized | |
862 | * | |
863 | * Initialize device before it's used by a driver. Ask low-level code | |
864 | * to enable I/O and memory. Wake up the device if it was suspended. | |
865 | * Beware, this function can fail. | |
866 | * | |
867 | * Note we don't actually enable the device many times if we call | |
868 | * this function repeatedly (we just increment the count). | |
869 | */ | |
870 | int pci_enable_device(struct pci_dev *dev) | |
871 | { | |
b718989d | 872 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
873 | } |
874 | ||
9ac7849e TH |
875 | /* |
876 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
877 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
878 | * there's no need to track it separately. pci_devres is initialized | |
879 | * when a device is enabled using managed PCI device enable interface. | |
880 | */ | |
881 | struct pci_devres { | |
7f375f32 TH |
882 | unsigned int enabled:1; |
883 | unsigned int pinned:1; | |
9ac7849e TH |
884 | unsigned int orig_intx:1; |
885 | unsigned int restore_intx:1; | |
886 | u32 region_mask; | |
887 | }; | |
888 | ||
889 | static void pcim_release(struct device *gendev, void *res) | |
890 | { | |
891 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
892 | struct pci_devres *this = res; | |
893 | int i; | |
894 | ||
895 | if (dev->msi_enabled) | |
896 | pci_disable_msi(dev); | |
897 | if (dev->msix_enabled) | |
898 | pci_disable_msix(dev); | |
899 | ||
900 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
901 | if (this->region_mask & (1 << i)) | |
902 | pci_release_region(dev, i); | |
903 | ||
904 | if (this->restore_intx) | |
905 | pci_intx(dev, this->orig_intx); | |
906 | ||
7f375f32 | 907 | if (this->enabled && !this->pinned) |
9ac7849e TH |
908 | pci_disable_device(dev); |
909 | } | |
910 | ||
911 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
912 | { | |
913 | struct pci_devres *dr, *new_dr; | |
914 | ||
915 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
916 | if (dr) | |
917 | return dr; | |
918 | ||
919 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
920 | if (!new_dr) | |
921 | return NULL; | |
922 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
923 | } | |
924 | ||
925 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
926 | { | |
927 | if (pci_is_managed(pdev)) | |
928 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
929 | return NULL; | |
930 | } | |
931 | ||
932 | /** | |
933 | * pcim_enable_device - Managed pci_enable_device() | |
934 | * @pdev: PCI device to be initialized | |
935 | * | |
936 | * Managed pci_enable_device(). | |
937 | */ | |
938 | int pcim_enable_device(struct pci_dev *pdev) | |
939 | { | |
940 | struct pci_devres *dr; | |
941 | int rc; | |
942 | ||
943 | dr = get_pci_dr(pdev); | |
944 | if (unlikely(!dr)) | |
945 | return -ENOMEM; | |
b95d58ea TH |
946 | if (dr->enabled) |
947 | return 0; | |
9ac7849e TH |
948 | |
949 | rc = pci_enable_device(pdev); | |
950 | if (!rc) { | |
951 | pdev->is_managed = 1; | |
7f375f32 | 952 | dr->enabled = 1; |
9ac7849e TH |
953 | } |
954 | return rc; | |
955 | } | |
956 | ||
957 | /** | |
958 | * pcim_pin_device - Pin managed PCI device | |
959 | * @pdev: PCI device to pin | |
960 | * | |
961 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
962 | * driver detach. @pdev must have been enabled with | |
963 | * pcim_enable_device(). | |
964 | */ | |
965 | void pcim_pin_device(struct pci_dev *pdev) | |
966 | { | |
967 | struct pci_devres *dr; | |
968 | ||
969 | dr = find_pci_dr(pdev); | |
7f375f32 | 970 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 971 | if (dr) |
7f375f32 | 972 | dr->pinned = 1; |
9ac7849e TH |
973 | } |
974 | ||
1da177e4 LT |
975 | /** |
976 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
977 | * @dev: the PCI device to disable | |
978 | * | |
979 | * Disables architecture specific PCI resources for the device. This | |
980 | * is the default implementation. Architecture implementations can | |
981 | * override this. | |
982 | */ | |
983 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
984 | ||
985 | /** | |
986 | * pci_disable_device - Disable PCI device after use | |
987 | * @dev: PCI device to be disabled | |
988 | * | |
989 | * Signal to the system that the PCI device is not in use by the system | |
990 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
991 | * |
992 | * Note we don't actually disable the device until all callers of | |
993 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
994 | */ |
995 | void | |
996 | pci_disable_device(struct pci_dev *dev) | |
997 | { | |
9ac7849e | 998 | struct pci_devres *dr; |
1da177e4 | 999 | u16 pci_command; |
99dc804d | 1000 | |
9ac7849e TH |
1001 | dr = find_pci_dr(dev); |
1002 | if (dr) | |
7f375f32 | 1003 | dr->enabled = 0; |
9ac7849e | 1004 | |
bae94d02 IPG |
1005 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
1006 | return; | |
1007 | ||
1da177e4 LT |
1008 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
1009 | if (pci_command & PCI_COMMAND_MASTER) { | |
1010 | pci_command &= ~PCI_COMMAND_MASTER; | |
1011 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1012 | } | |
ceb43744 | 1013 | dev->is_busmaster = 0; |
1da177e4 LT |
1014 | |
1015 | pcibios_disable_device(dev); | |
1016 | } | |
1017 | ||
f7bdd12d BK |
1018 | /** |
1019 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
1020 | * @dev: the PCI-E device reset | |
1021 | * @state: Reset state to enter into | |
1022 | * | |
1023 | * | |
1024 | * Sets the PCI-E reset state for the device. This is the default | |
1025 | * implementation. Architecture implementations can override this. | |
1026 | */ | |
1027 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1028 | enum pcie_reset_state state) | |
1029 | { | |
1030 | return -EINVAL; | |
1031 | } | |
1032 | ||
1033 | /** | |
1034 | * pci_set_pcie_reset_state - set reset state for device dev | |
1035 | * @dev: the PCI-E device reset | |
1036 | * @state: Reset state to enter into | |
1037 | * | |
1038 | * | |
1039 | * Sets the PCI reset state for the device. | |
1040 | */ | |
1041 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1042 | { | |
1043 | return pcibios_set_pcie_reset_state(dev, state); | |
1044 | } | |
1045 | ||
eb9d0fe4 RW |
1046 | /** |
1047 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1048 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1049 | * @state: PCI state from which device will issue PME#. |
1050 | */ | |
e5899e1b | 1051 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1052 | { |
337001b6 | 1053 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1054 | return false; |
1055 | ||
337001b6 | 1056 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 RW |
1057 | } |
1058 | ||
1059 | /** | |
1060 | * pci_pme_active - enable or disable PCI device's PME# function | |
1061 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1062 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1063 | * | |
1064 | * The caller must verify that the device is capable of generating PME# before | |
1065 | * calling this function with @enable equal to 'true'. | |
1066 | */ | |
5a6c9b60 | 1067 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1068 | { |
1069 | u16 pmcsr; | |
1070 | ||
337001b6 | 1071 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1072 | return; |
1073 | ||
337001b6 | 1074 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1075 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1076 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1077 | if (!enable) | |
1078 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1079 | ||
337001b6 | 1080 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 RW |
1081 | |
1082 | dev_printk(KERN_INFO, &dev->dev, "PME# %s\n", | |
1083 | enable ? "enabled" : "disabled"); | |
1084 | } | |
1085 | ||
1da177e4 | 1086 | /** |
075c1771 DB |
1087 | * pci_enable_wake - enable PCI device as wakeup event source |
1088 | * @dev: PCI device affected | |
1089 | * @state: PCI state from which device will issue wakeup events | |
1090 | * @enable: True to enable event generation; false to disable | |
1091 | * | |
1092 | * This enables the device as a wakeup event source, or disables it. | |
1093 | * When such events involves platform-specific hooks, those hooks are | |
1094 | * called automatically by this routine. | |
1095 | * | |
1096 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1097 | * always require such platform hooks. |
075c1771 | 1098 | * |
eb9d0fe4 RW |
1099 | * RETURN VALUE: |
1100 | * 0 is returned on success | |
1101 | * -EINVAL is returned if device is not supposed to wake up the system | |
1102 | * Error code depending on the platform is returned if both the platform and | |
1103 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 LT |
1104 | */ |
1105 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
1106 | { | |
eb9d0fe4 RW |
1107 | int error = 0; |
1108 | bool pme_done = false; | |
075c1771 | 1109 | |
eb9d0fe4 RW |
1110 | if (!device_may_wakeup(&dev->dev)) |
1111 | return -EINVAL; | |
1da177e4 | 1112 | |
eb9d0fe4 RW |
1113 | /* |
1114 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1115 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1116 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1117 | */ |
1da177e4 | 1118 | |
eb9d0fe4 RW |
1119 | if (!enable && platform_pci_can_wakeup(dev)) |
1120 | error = platform_pci_sleep_wake(dev, false); | |
1da177e4 | 1121 | |
337001b6 RW |
1122 | if (!enable || pci_pme_capable(dev, state)) { |
1123 | pci_pme_active(dev, enable); | |
eb9d0fe4 | 1124 | pme_done = true; |
075c1771 | 1125 | } |
1da177e4 | 1126 | |
eb9d0fe4 RW |
1127 | if (enable && platform_pci_can_wakeup(dev)) |
1128 | error = platform_pci_sleep_wake(dev, true); | |
1da177e4 | 1129 | |
eb9d0fe4 RW |
1130 | return pme_done ? 0 : error; |
1131 | } | |
1da177e4 | 1132 | |
0235c4fc RW |
1133 | /** |
1134 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1135 | * @dev: PCI device to prepare | |
1136 | * @enable: True to enable wake-up event generation; false to disable | |
1137 | * | |
1138 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1139 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1140 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1141 | * ordering constraints. | |
1142 | * | |
1143 | * This function only returns error code if the device is not capable of | |
1144 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1145 | * enable wake-up power for it. | |
1146 | */ | |
1147 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1148 | { | |
1149 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1150 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1151 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1152 | } | |
1153 | ||
404cc2d8 | 1154 | /** |
37139074 JB |
1155 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1156 | * @dev: PCI device | |
1157 | * | |
1158 | * Use underlying platform code to find a supported low power state for @dev. | |
1159 | * If the platform can't manage @dev, return the deepest state from which it | |
1160 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1161 | */ |
e5899e1b | 1162 | pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1163 | { |
1164 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1165 | |
1166 | if (platform_pci_power_manageable(dev)) { | |
1167 | /* | |
1168 | * Call the platform to choose the target state of the device | |
1169 | * and enable wake-up from this state if supported. | |
1170 | */ | |
1171 | pci_power_t state = platform_pci_choose_state(dev); | |
1172 | ||
1173 | switch (state) { | |
1174 | case PCI_POWER_ERROR: | |
1175 | case PCI_UNKNOWN: | |
1176 | break; | |
1177 | case PCI_D1: | |
1178 | case PCI_D2: | |
1179 | if (pci_no_d1d2(dev)) | |
1180 | break; | |
1181 | default: | |
1182 | target_state = state; | |
404cc2d8 RW |
1183 | } |
1184 | } else if (device_may_wakeup(&dev->dev)) { | |
1185 | /* | |
1186 | * Find the deepest state from which the device can generate | |
1187 | * wake-up events, make it the target state and enable device | |
1188 | * to generate PME#. | |
1189 | */ | |
337001b6 | 1190 | if (!dev->pm_cap) |
e5899e1b | 1191 | return PCI_POWER_ERROR; |
404cc2d8 | 1192 | |
337001b6 RW |
1193 | if (dev->pme_support) { |
1194 | while (target_state | |
1195 | && !(dev->pme_support & (1 << target_state))) | |
1196 | target_state--; | |
404cc2d8 RW |
1197 | } |
1198 | } | |
1199 | ||
e5899e1b RW |
1200 | return target_state; |
1201 | } | |
1202 | ||
1203 | /** | |
1204 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1205 | * @dev: Device to handle. | |
1206 | * | |
1207 | * Choose the power state appropriate for the device depending on whether | |
1208 | * it can wake up the system and/or is power manageable by the platform | |
1209 | * (PCI_D3hot is the default) and put the device into that state. | |
1210 | */ | |
1211 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1212 | { | |
1213 | pci_power_t target_state = pci_target_state(dev); | |
1214 | int error; | |
1215 | ||
1216 | if (target_state == PCI_POWER_ERROR) | |
1217 | return -EIO; | |
1218 | ||
c157dfa3 RW |
1219 | pci_enable_wake(dev, target_state, true); |
1220 | ||
404cc2d8 RW |
1221 | error = pci_set_power_state(dev, target_state); |
1222 | ||
1223 | if (error) | |
1224 | pci_enable_wake(dev, target_state, false); | |
1225 | ||
1226 | return error; | |
1227 | } | |
1228 | ||
1229 | /** | |
443bd1c4 | 1230 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1231 | * @dev: Device to handle. |
1232 | * | |
1233 | * Disable device's sytem wake-up capability and put it into D0. | |
1234 | */ | |
1235 | int pci_back_from_sleep(struct pci_dev *dev) | |
1236 | { | |
1237 | pci_enable_wake(dev, PCI_D0, false); | |
1238 | return pci_set_power_state(dev, PCI_D0); | |
1239 | } | |
1240 | ||
eb9d0fe4 RW |
1241 | /** |
1242 | * pci_pm_init - Initialize PM functions of given PCI device | |
1243 | * @dev: PCI device to handle. | |
1244 | */ | |
1245 | void pci_pm_init(struct pci_dev *dev) | |
1246 | { | |
1247 | int pm; | |
1248 | u16 pmc; | |
1da177e4 | 1249 | |
337001b6 RW |
1250 | dev->pm_cap = 0; |
1251 | ||
eb9d0fe4 RW |
1252 | /* find PCI PM capability in list */ |
1253 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1254 | if (!pm) | |
1255 | return; | |
1256 | /* Check device's ability to generate PME# */ | |
1257 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 1258 | |
eb9d0fe4 RW |
1259 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1260 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
1261 | pmc & PCI_PM_CAP_VER_MASK); | |
1262 | return; | |
1263 | } | |
1264 | ||
337001b6 RW |
1265 | dev->pm_cap = pm; |
1266 | ||
1267 | dev->d1_support = false; | |
1268 | dev->d2_support = false; | |
1269 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 1270 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 1271 | dev->d1_support = true; |
c9ed77ee | 1272 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 1273 | dev->d2_support = true; |
c9ed77ee BH |
1274 | |
1275 | if (dev->d1_support || dev->d2_support) | |
1276 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
1277 | dev->d1_support ? " D1" : "", |
1278 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
1279 | } |
1280 | ||
1281 | pmc &= PCI_PM_CAP_PME_MASK; | |
1282 | if (pmc) { | |
c9ed77ee BH |
1283 | dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n", |
1284 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", | |
1285 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
1286 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
1287 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
1288 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 1289 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
eb9d0fe4 RW |
1290 | /* |
1291 | * Make device's PM flags reflect the wake-up capability, but | |
1292 | * let the user space enable it to wake up the system as needed. | |
1293 | */ | |
1294 | device_set_wakeup_capable(&dev->dev, true); | |
1295 | device_set_wakeup_enable(&dev->dev, false); | |
1296 | /* Disable the PME# generation functionality */ | |
337001b6 RW |
1297 | pci_pme_active(dev, false); |
1298 | } else { | |
1299 | dev->pme_support = 0; | |
eb9d0fe4 | 1300 | } |
1da177e4 LT |
1301 | } |
1302 | ||
58c3a727 YZ |
1303 | /** |
1304 | * pci_enable_ari - enable ARI forwarding if hardware support it | |
1305 | * @dev: the PCI device | |
1306 | */ | |
1307 | void pci_enable_ari(struct pci_dev *dev) | |
1308 | { | |
1309 | int pos; | |
1310 | u32 cap; | |
1311 | u16 ctrl; | |
8113587c | 1312 | struct pci_dev *bridge; |
58c3a727 | 1313 | |
8113587c | 1314 | if (!dev->is_pcie || dev->devfn) |
58c3a727 YZ |
1315 | return; |
1316 | ||
8113587c ZY |
1317 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); |
1318 | if (!pos) | |
58c3a727 YZ |
1319 | return; |
1320 | ||
8113587c ZY |
1321 | bridge = dev->bus->self; |
1322 | if (!bridge || !bridge->is_pcie) | |
1323 | return; | |
1324 | ||
1325 | pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
58c3a727 YZ |
1326 | if (!pos) |
1327 | return; | |
1328 | ||
8113587c | 1329 | pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
1330 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
1331 | return; | |
1332 | ||
8113587c | 1333 | pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); |
58c3a727 | 1334 | ctrl |= PCI_EXP_DEVCTL2_ARI; |
8113587c | 1335 | pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); |
58c3a727 | 1336 | |
8113587c | 1337 | bridge->ari_enabled = 1; |
58c3a727 YZ |
1338 | } |
1339 | ||
1da177e4 LT |
1340 | int |
1341 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1342 | { | |
1343 | u8 pin; | |
1344 | ||
514d207d | 1345 | pin = dev->pin; |
1da177e4 LT |
1346 | if (!pin) |
1347 | return -1; | |
1348 | pin--; | |
1349 | while (dev->bus->self) { | |
1350 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
1351 | dev = dev->bus->self; | |
1352 | } | |
1353 | *bridge = dev; | |
1354 | return pin; | |
1355 | } | |
1356 | ||
1357 | /** | |
1358 | * pci_release_region - Release a PCI bar | |
1359 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1360 | * @bar: BAR to release | |
1361 | * | |
1362 | * Releases the PCI I/O and memory resources previously reserved by a | |
1363 | * successful call to pci_request_region. Call this function only | |
1364 | * after all use of the PCI regions has ceased. | |
1365 | */ | |
1366 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1367 | { | |
9ac7849e TH |
1368 | struct pci_devres *dr; |
1369 | ||
1da177e4 LT |
1370 | if (pci_resource_len(pdev, bar) == 0) |
1371 | return; | |
1372 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1373 | release_region(pci_resource_start(pdev, bar), | |
1374 | pci_resource_len(pdev, bar)); | |
1375 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1376 | release_mem_region(pci_resource_start(pdev, bar), | |
1377 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1378 | |
1379 | dr = find_pci_dr(pdev); | |
1380 | if (dr) | |
1381 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1382 | } |
1383 | ||
1384 | /** | |
1385 | * pci_request_region - Reserved PCI I/O and memory resource | |
1386 | * @pdev: PCI device whose resources are to be reserved | |
1387 | * @bar: BAR to be reserved | |
1388 | * @res_name: Name to be associated with resource. | |
1389 | * | |
1390 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1391 | * being reserved by owner @res_name. Do not access any | |
1392 | * address inside the PCI regions unless this call returns | |
1393 | * successfully. | |
1394 | * | |
1395 | * Returns 0 on success, or %EBUSY on error. A warning | |
1396 | * message is also printed on failure. | |
1397 | */ | |
3c990e92 | 1398 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 | 1399 | { |
9ac7849e TH |
1400 | struct pci_devres *dr; |
1401 | ||
1da177e4 LT |
1402 | if (pci_resource_len(pdev, bar) == 0) |
1403 | return 0; | |
1404 | ||
1405 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1406 | if (!request_region(pci_resource_start(pdev, bar), | |
1407 | pci_resource_len(pdev, bar), res_name)) | |
1408 | goto err_out; | |
1409 | } | |
1410 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
1411 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
1412 | pci_resource_len(pdev, bar), res_name)) | |
1413 | goto err_out; | |
1414 | } | |
9ac7849e TH |
1415 | |
1416 | dr = find_pci_dr(pdev); | |
1417 | if (dr) | |
1418 | dr->region_mask |= 1 << bar; | |
1419 | ||
1da177e4 LT |
1420 | return 0; |
1421 | ||
1422 | err_out: | |
096e6f67 | 1423 | dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n", |
e4ec7a00 JB |
1424 | bar, |
1425 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", | |
096e6f67 | 1426 | &pdev->resource[bar]); |
1da177e4 LT |
1427 | return -EBUSY; |
1428 | } | |
1429 | ||
c87deff7 HS |
1430 | /** |
1431 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1432 | * @pdev: PCI device whose resources were previously reserved | |
1433 | * @bars: Bitmask of BARs to be released | |
1434 | * | |
1435 | * Release selected PCI I/O and memory resources previously reserved. | |
1436 | * Call this function only after all use of the PCI regions has ceased. | |
1437 | */ | |
1438 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1439 | { | |
1440 | int i; | |
1441 | ||
1442 | for (i = 0; i < 6; i++) | |
1443 | if (bars & (1 << i)) | |
1444 | pci_release_region(pdev, i); | |
1445 | } | |
1446 | ||
1447 | /** | |
1448 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1449 | * @pdev: PCI device whose resources are to be reserved | |
1450 | * @bars: Bitmask of BARs to be requested | |
1451 | * @res_name: Name to be associated with resource | |
1452 | */ | |
1453 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1454 | const char *res_name) | |
1455 | { | |
1456 | int i; | |
1457 | ||
1458 | for (i = 0; i < 6; i++) | |
1459 | if (bars & (1 << i)) | |
1460 | if(pci_request_region(pdev, i, res_name)) | |
1461 | goto err_out; | |
1462 | return 0; | |
1463 | ||
1464 | err_out: | |
1465 | while(--i >= 0) | |
1466 | if (bars & (1 << i)) | |
1467 | pci_release_region(pdev, i); | |
1468 | ||
1469 | return -EBUSY; | |
1470 | } | |
1da177e4 LT |
1471 | |
1472 | /** | |
1473 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1474 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1475 | * | |
1476 | * Releases all PCI I/O and memory resources previously reserved by a | |
1477 | * successful call to pci_request_regions. Call this function only | |
1478 | * after all use of the PCI regions has ceased. | |
1479 | */ | |
1480 | ||
1481 | void pci_release_regions(struct pci_dev *pdev) | |
1482 | { | |
c87deff7 | 1483 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1484 | } |
1485 | ||
1486 | /** | |
1487 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1488 | * @pdev: PCI device whose resources are to be reserved | |
1489 | * @res_name: Name to be associated with resource. | |
1490 | * | |
1491 | * Mark all PCI regions associated with PCI device @pdev as | |
1492 | * being reserved by owner @res_name. Do not access any | |
1493 | * address inside the PCI regions unless this call returns | |
1494 | * successfully. | |
1495 | * | |
1496 | * Returns 0 on success, or %EBUSY on error. A warning | |
1497 | * message is also printed on failure. | |
1498 | */ | |
3c990e92 | 1499 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1500 | { |
c87deff7 | 1501 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1502 | } |
1503 | ||
1504 | /** | |
1505 | * pci_set_master - enables bus-mastering for device dev | |
1506 | * @dev: the PCI device to enable | |
1507 | * | |
1508 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1509 | * to do the needed arch specific settings. | |
1510 | */ | |
1511 | void | |
1512 | pci_set_master(struct pci_dev *dev) | |
1513 | { | |
1514 | u16 cmd; | |
1515 | ||
1516 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1517 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
80ccba11 | 1518 | dev_dbg(&dev->dev, "enabling bus mastering\n"); |
1da177e4 LT |
1519 | cmd |= PCI_COMMAND_MASTER; |
1520 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1521 | } | |
1522 | dev->is_busmaster = 1; | |
1523 | pcibios_set_master(dev); | |
1524 | } | |
1525 | ||
edb2d97e MW |
1526 | #ifdef PCI_DISABLE_MWI |
1527 | int pci_set_mwi(struct pci_dev *dev) | |
1528 | { | |
1529 | return 0; | |
1530 | } | |
1531 | ||
694625c0 RD |
1532 | int pci_try_set_mwi(struct pci_dev *dev) |
1533 | { | |
1534 | return 0; | |
1535 | } | |
1536 | ||
edb2d97e MW |
1537 | void pci_clear_mwi(struct pci_dev *dev) |
1538 | { | |
1539 | } | |
1540 | ||
1541 | #else | |
ebf5a248 MW |
1542 | |
1543 | #ifndef PCI_CACHE_LINE_BYTES | |
1544 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1545 | #endif | |
1546 | ||
1da177e4 | 1547 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1548 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1549 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1550 | |
1551 | /** | |
edb2d97e MW |
1552 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1553 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1554 | * |
edb2d97e MW |
1555 | * Helper function for pci_set_mwi. |
1556 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1557 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1558 | * | |
1559 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1560 | */ | |
1561 | static int | |
edb2d97e | 1562 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1563 | { |
1564 | u8 cacheline_size; | |
1565 | ||
1566 | if (!pci_cache_line_size) | |
1567 | return -EINVAL; /* The system doesn't support MWI. */ | |
1568 | ||
1569 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1570 | equal to or multiple of the right value. */ | |
1571 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1572 | if (cacheline_size >= pci_cache_line_size && | |
1573 | (cacheline_size % pci_cache_line_size) == 0) | |
1574 | return 0; | |
1575 | ||
1576 | /* Write the correct value. */ | |
1577 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1578 | /* Read it back. */ | |
1579 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1580 | if (cacheline_size == pci_cache_line_size) | |
1581 | return 0; | |
1582 | ||
80ccba11 BH |
1583 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
1584 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
1585 | |
1586 | return -EINVAL; | |
1587 | } | |
1da177e4 LT |
1588 | |
1589 | /** | |
1590 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1591 | * @dev: the PCI device for which MWI is enabled | |
1592 | * | |
694625c0 | 1593 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
1594 | * |
1595 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1596 | */ | |
1597 | int | |
1598 | pci_set_mwi(struct pci_dev *dev) | |
1599 | { | |
1600 | int rc; | |
1601 | u16 cmd; | |
1602 | ||
edb2d97e | 1603 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1604 | if (rc) |
1605 | return rc; | |
1606 | ||
1607 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1608 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 1609 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
1610 | cmd |= PCI_COMMAND_INVALIDATE; |
1611 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1612 | } | |
1613 | ||
1614 | return 0; | |
1615 | } | |
1616 | ||
694625c0 RD |
1617 | /** |
1618 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
1619 | * @dev: the PCI device for which MWI is enabled | |
1620 | * | |
1621 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
1622 | * Callers are not required to check the return value. | |
1623 | * | |
1624 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1625 | */ | |
1626 | int pci_try_set_mwi(struct pci_dev *dev) | |
1627 | { | |
1628 | int rc = pci_set_mwi(dev); | |
1629 | return rc; | |
1630 | } | |
1631 | ||
1da177e4 LT |
1632 | /** |
1633 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1634 | * @dev: the PCI device to disable | |
1635 | * | |
1636 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1637 | */ | |
1638 | void | |
1639 | pci_clear_mwi(struct pci_dev *dev) | |
1640 | { | |
1641 | u16 cmd; | |
1642 | ||
1643 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1644 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1645 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1646 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1647 | } | |
1648 | } | |
edb2d97e | 1649 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1650 | |
a04ce0ff BR |
1651 | /** |
1652 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1653 | * @pdev: the PCI device to operate on |
1654 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1655 | * |
1656 | * Enables/disables PCI INTx for device dev | |
1657 | */ | |
1658 | void | |
1659 | pci_intx(struct pci_dev *pdev, int enable) | |
1660 | { | |
1661 | u16 pci_command, new; | |
1662 | ||
1663 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1664 | ||
1665 | if (enable) { | |
1666 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1667 | } else { | |
1668 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1669 | } | |
1670 | ||
1671 | if (new != pci_command) { | |
9ac7849e TH |
1672 | struct pci_devres *dr; |
1673 | ||
2fd9d74b | 1674 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1675 | |
1676 | dr = find_pci_dr(pdev); | |
1677 | if (dr && !dr->restore_intx) { | |
1678 | dr->restore_intx = 1; | |
1679 | dr->orig_intx = !enable; | |
1680 | } | |
a04ce0ff BR |
1681 | } |
1682 | } | |
1683 | ||
f5f2b131 EB |
1684 | /** |
1685 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 1686 | * @dev: the PCI device to operate on |
f5f2b131 EB |
1687 | * |
1688 | * If you want to use msi see pci_enable_msi and friends. | |
1689 | * This is a lower level primitive that allows us to disable | |
1690 | * msi operation at the device level. | |
1691 | */ | |
1692 | void pci_msi_off(struct pci_dev *dev) | |
1693 | { | |
1694 | int pos; | |
1695 | u16 control; | |
1696 | ||
1697 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1698 | if (pos) { | |
1699 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1700 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1701 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1702 | } | |
1703 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1704 | if (pos) { | |
1705 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1706 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1707 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1708 | } | |
1709 | } | |
1710 | ||
1da177e4 LT |
1711 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1712 | /* | |
1713 | * These can be overridden by arch-specific implementations | |
1714 | */ | |
1715 | int | |
1716 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1717 | { | |
1718 | if (!pci_dma_supported(dev, mask)) | |
1719 | return -EIO; | |
1720 | ||
1721 | dev->dma_mask = mask; | |
1722 | ||
1723 | return 0; | |
1724 | } | |
1725 | ||
1da177e4 LT |
1726 | int |
1727 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1728 | { | |
1729 | if (!pci_dma_supported(dev, mask)) | |
1730 | return -EIO; | |
1731 | ||
1732 | dev->dev.coherent_dma_mask = mask; | |
1733 | ||
1734 | return 0; | |
1735 | } | |
1736 | #endif | |
c87deff7 | 1737 | |
4d57cdfa FT |
1738 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
1739 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) | |
1740 | { | |
1741 | return dma_set_max_seg_size(&dev->dev, size); | |
1742 | } | |
1743 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
1744 | #endif | |
1745 | ||
59fc67de FT |
1746 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
1747 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |
1748 | { | |
1749 | return dma_set_seg_boundary(&dev->dev, mask); | |
1750 | } | |
1751 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
1752 | #endif | |
1753 | ||
8dd7f803 SY |
1754 | /** |
1755 | * pci_execute_reset_function() - Reset a PCI device function | |
1756 | * @dev: Device function to reset | |
1757 | * | |
1758 | * Some devices allow an individual function to be reset without affecting | |
1759 | * other functions in the same device. The PCI device must be responsive | |
1760 | * to PCI config space in order to use this function. | |
1761 | * | |
1762 | * The device function is presumed to be unused when this function is called. | |
1763 | * Resetting the device will make the contents of PCI configuration space | |
1764 | * random, so any caller of this must be prepared to reinitialise the | |
1765 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
1766 | * etc. | |
1767 | * | |
1768 | * Returns 0 if the device function was successfully reset or -ENOTTY if the | |
1769 | * device doesn't support resetting a single function. | |
1770 | */ | |
1771 | int pci_execute_reset_function(struct pci_dev *dev) | |
1772 | { | |
1773 | u16 status; | |
1774 | u32 cap; | |
1775 | int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1776 | ||
1777 | if (!exppos) | |
1778 | return -ENOTTY; | |
1779 | pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap); | |
1780 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
1781 | return -ENOTTY; | |
1782 | ||
1783 | pci_block_user_cfg_access(dev); | |
1784 | ||
1785 | /* Wait for Transaction Pending bit clean */ | |
1786 | msleep(100); | |
1787 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); | |
1788 | if (status & PCI_EXP_DEVSTA_TRPND) { | |
1789 | dev_info(&dev->dev, "Busy after 100ms while trying to reset; " | |
1790 | "sleeping for 1 second\n"); | |
1791 | ssleep(1); | |
1792 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); | |
1793 | if (status & PCI_EXP_DEVSTA_TRPND) | |
1794 | dev_info(&dev->dev, "Still busy after 1s; " | |
1795 | "proceeding with reset anyway\n"); | |
1796 | } | |
1797 | ||
1798 | pci_write_config_word(dev, exppos + PCI_EXP_DEVCTL, | |
1799 | PCI_EXP_DEVCTL_BCR_FLR); | |
1800 | mdelay(100); | |
1801 | ||
1802 | pci_unblock_user_cfg_access(dev); | |
1803 | return 0; | |
1804 | } | |
1805 | EXPORT_SYMBOL_GPL(pci_execute_reset_function); | |
1806 | ||
1807 | /** | |
1808 | * pci_reset_function() - quiesce and reset a PCI device function | |
1809 | * @dev: Device function to reset | |
1810 | * | |
1811 | * Some devices allow an individual function to be reset without affecting | |
1812 | * other functions in the same device. The PCI device must be responsive | |
1813 | * to PCI config space in order to use this function. | |
1814 | * | |
1815 | * This function does not just reset the PCI portion of a device, but | |
1816 | * clears all the state associated with the device. This function differs | |
1817 | * from pci_execute_reset_function in that it saves and restores device state | |
1818 | * over the reset. | |
1819 | * | |
1820 | * Returns 0 if the device function was successfully reset or -ENOTTY if the | |
1821 | * device doesn't support resetting a single function. | |
1822 | */ | |
1823 | int pci_reset_function(struct pci_dev *dev) | |
1824 | { | |
1825 | u32 cap; | |
1826 | int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1827 | int r; | |
1828 | ||
1829 | if (!exppos) | |
1830 | return -ENOTTY; | |
1831 | pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap); | |
1832 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
1833 | return -ENOTTY; | |
1834 | ||
1df8fb3d | 1835 | if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) |
8dd7f803 SY |
1836 | disable_irq(dev->irq); |
1837 | pci_save_state(dev); | |
1838 | ||
1839 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
1840 | ||
1841 | r = pci_execute_reset_function(dev); | |
1842 | ||
1843 | pci_restore_state(dev); | |
1df8fb3d | 1844 | if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) |
8dd7f803 SY |
1845 | enable_irq(dev->irq); |
1846 | ||
1847 | return r; | |
1848 | } | |
1849 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
1850 | ||
d556ad4b PO |
1851 | /** |
1852 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
1853 | * @dev: PCI device to query | |
1854 | * | |
1855 | * Returns mmrbc: maximum designed memory read count in bytes | |
1856 | * or appropriate error value. | |
1857 | */ | |
1858 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
1859 | { | |
b7b095c1 | 1860 | int err, cap; |
d556ad4b PO |
1861 | u32 stat; |
1862 | ||
1863 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1864 | if (!cap) | |
1865 | return -EINVAL; | |
1866 | ||
1867 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1868 | if (err) | |
1869 | return -EINVAL; | |
1870 | ||
b7b095c1 | 1871 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
1872 | } |
1873 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
1874 | ||
1875 | /** | |
1876 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
1877 | * @dev: PCI device to query | |
1878 | * | |
1879 | * Returns mmrbc: maximum memory read count in bytes | |
1880 | * or appropriate error value. | |
1881 | */ | |
1882 | int pcix_get_mmrbc(struct pci_dev *dev) | |
1883 | { | |
1884 | int ret, cap; | |
1885 | u32 cmd; | |
1886 | ||
1887 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1888 | if (!cap) | |
1889 | return -EINVAL; | |
1890 | ||
1891 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1892 | if (!ret) | |
1893 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
1894 | ||
1895 | return ret; | |
1896 | } | |
1897 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
1898 | ||
1899 | /** | |
1900 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
1901 | * @dev: PCI device to query | |
1902 | * @mmrbc: maximum memory read count in bytes | |
1903 | * valid values are 512, 1024, 2048, 4096 | |
1904 | * | |
1905 | * If possible sets maximum memory read byte count, some bridges have erratas | |
1906 | * that prevent this. | |
1907 | */ | |
1908 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
1909 | { | |
1910 | int cap, err = -EINVAL; | |
1911 | u32 stat, cmd, v, o; | |
1912 | ||
229f5afd | 1913 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
1914 | goto out; |
1915 | ||
1916 | v = ffs(mmrbc) - 10; | |
1917 | ||
1918 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1919 | if (!cap) | |
1920 | goto out; | |
1921 | ||
1922 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1923 | if (err) | |
1924 | goto out; | |
1925 | ||
1926 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
1927 | return -E2BIG; | |
1928 | ||
1929 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1930 | if (err) | |
1931 | goto out; | |
1932 | ||
1933 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
1934 | if (o != v) { | |
1935 | if (v > o && dev->bus && | |
1936 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
1937 | return -EIO; | |
1938 | ||
1939 | cmd &= ~PCI_X_CMD_MAX_READ; | |
1940 | cmd |= v << 2; | |
1941 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
1942 | } | |
1943 | out: | |
1944 | return err; | |
1945 | } | |
1946 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
1947 | ||
1948 | /** | |
1949 | * pcie_get_readrq - get PCI Express read request size | |
1950 | * @dev: PCI device to query | |
1951 | * | |
1952 | * Returns maximum memory read request in bytes | |
1953 | * or appropriate error value. | |
1954 | */ | |
1955 | int pcie_get_readrq(struct pci_dev *dev) | |
1956 | { | |
1957 | int ret, cap; | |
1958 | u16 ctl; | |
1959 | ||
1960 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1961 | if (!cap) | |
1962 | return -EINVAL; | |
1963 | ||
1964 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1965 | if (!ret) | |
1966 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
1967 | ||
1968 | return ret; | |
1969 | } | |
1970 | EXPORT_SYMBOL(pcie_get_readrq); | |
1971 | ||
1972 | /** | |
1973 | * pcie_set_readrq - set PCI Express maximum memory read request | |
1974 | * @dev: PCI device to query | |
42e61f4a | 1975 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
1976 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
1977 | * | |
1978 | * If possible sets maximum read byte count | |
1979 | */ | |
1980 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
1981 | { | |
1982 | int cap, err = -EINVAL; | |
1983 | u16 ctl, v; | |
1984 | ||
229f5afd | 1985 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
1986 | goto out; |
1987 | ||
1988 | v = (ffs(rq) - 8) << 12; | |
1989 | ||
1990 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1991 | if (!cap) | |
1992 | goto out; | |
1993 | ||
1994 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1995 | if (err) | |
1996 | goto out; | |
1997 | ||
1998 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
1999 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
2000 | ctl |= v; | |
2001 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
2002 | } | |
2003 | ||
2004 | out: | |
2005 | return err; | |
2006 | } | |
2007 | EXPORT_SYMBOL(pcie_set_readrq); | |
2008 | ||
c87deff7 HS |
2009 | /** |
2010 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 2011 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
2012 | * @flags: resource type mask to be selected |
2013 | * | |
2014 | * This helper routine makes bar mask from the type of resource. | |
2015 | */ | |
2016 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
2017 | { | |
2018 | int i, bars = 0; | |
2019 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
2020 | if (pci_resource_flags(dev, i) & flags) | |
2021 | bars |= (1 << i); | |
2022 | return bars; | |
2023 | } | |
2024 | ||
32a2eea7 JG |
2025 | static void __devinit pci_no_domains(void) |
2026 | { | |
2027 | #ifdef CONFIG_PCI_DOMAINS | |
2028 | pci_domains_supported = 0; | |
2029 | #endif | |
2030 | } | |
2031 | ||
1da177e4 LT |
2032 | static int __devinit pci_init(void) |
2033 | { | |
2034 | struct pci_dev *dev = NULL; | |
2035 | ||
2036 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
2037 | pci_fixup_device(pci_fixup_final, dev); | |
2038 | } | |
d389fec6 TI |
2039 | |
2040 | msi_init(); | |
2041 | ||
1da177e4 LT |
2042 | return 0; |
2043 | } | |
2044 | ||
ad04d31e | 2045 | static int __init pci_setup(char *str) |
1da177e4 LT |
2046 | { |
2047 | while (str) { | |
2048 | char *k = strchr(str, ','); | |
2049 | if (k) | |
2050 | *k++ = 0; | |
2051 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
2052 | if (!strcmp(str, "nomsi")) { |
2053 | pci_no_msi(); | |
7f785763 RD |
2054 | } else if (!strcmp(str, "noaer")) { |
2055 | pci_no_aer(); | |
32a2eea7 JG |
2056 | } else if (!strcmp(str, "nodomains")) { |
2057 | pci_no_domains(); | |
4516a618 AN |
2058 | } else if (!strncmp(str, "cbiosize=", 9)) { |
2059 | pci_cardbus_io_size = memparse(str + 9, &str); | |
2060 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
2061 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
2062 | } else { |
2063 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
2064 | str); | |
2065 | } | |
1da177e4 LT |
2066 | } |
2067 | str = k; | |
2068 | } | |
0637a70a | 2069 | return 0; |
1da177e4 | 2070 | } |
0637a70a | 2071 | early_param("pci", pci_setup); |
1da177e4 LT |
2072 | |
2073 | device_initcall(pci_init); | |
1da177e4 | 2074 | |
0b62e13b | 2075 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
2076 | EXPORT_SYMBOL(pci_enable_device_io); |
2077 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 2078 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
2079 | EXPORT_SYMBOL(pcim_enable_device); |
2080 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 2081 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
2082 | EXPORT_SYMBOL(pci_find_capability); |
2083 | EXPORT_SYMBOL(pci_bus_find_capability); | |
2084 | EXPORT_SYMBOL(pci_release_regions); | |
2085 | EXPORT_SYMBOL(pci_request_regions); | |
2086 | EXPORT_SYMBOL(pci_release_region); | |
2087 | EXPORT_SYMBOL(pci_request_region); | |
c87deff7 HS |
2088 | EXPORT_SYMBOL(pci_release_selected_regions); |
2089 | EXPORT_SYMBOL(pci_request_selected_regions); | |
1da177e4 LT |
2090 | EXPORT_SYMBOL(pci_set_master); |
2091 | EXPORT_SYMBOL(pci_set_mwi); | |
694625c0 | 2092 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 2093 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 2094 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 2095 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
2096 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
2097 | EXPORT_SYMBOL(pci_assign_resource); | |
2098 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 2099 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
2100 | |
2101 | EXPORT_SYMBOL(pci_set_power_state); | |
2102 | EXPORT_SYMBOL(pci_save_state); | |
2103 | EXPORT_SYMBOL(pci_restore_state); | |
e5899e1b | 2104 | EXPORT_SYMBOL(pci_pme_capable); |
5a6c9b60 | 2105 | EXPORT_SYMBOL(pci_pme_active); |
1da177e4 | 2106 | EXPORT_SYMBOL(pci_enable_wake); |
0235c4fc | 2107 | EXPORT_SYMBOL(pci_wake_from_d3); |
e5899e1b | 2108 | EXPORT_SYMBOL(pci_target_state); |
404cc2d8 RW |
2109 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
2110 | EXPORT_SYMBOL(pci_back_from_sleep); | |
f7bdd12d | 2111 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 2112 |