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Driver core: create lock/unlock functions for struct device
[linux-2.6-block.git] / drivers / pci / pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
075c1771 14#include <linux/pm.h>
1da177e4
LT		 15#include <linux/module.h>
16#include <linux/spinlock.h>
4e57b681 17#include <linux/string.h>
229f5afd 18#include <linux/log2.h>
7d715a6c 19#include <linux/pci-aspm.h>
c300bd2f 20#include <linux/pm_wakeup.h>
8dd7f803 21#include <linux/interrupt.h>
32a9a682 22#include <linux/device.h>
b67ea761 23#include <linux/pm_runtime.h>
32a9a682 24#include <asm/setup.h>
bc56b9e0 25#include "pci.h"
1da177e4 26
00240c38
AS		 27const char *pci_power_names[] = {
28 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
29};
30EXPORT_SYMBOL_GPL(pci_power_names);
31
93177a74
RW		 32int isa_dma_bridge_buggy;
33EXPORT_SYMBOL(isa_dma_bridge_buggy);
34
35int pci_pci_problems;
36EXPORT_SYMBOL(pci_pci_problems);
37
1ae861e6
RW		 38unsigned int pci_pm_d3_delay;
39
40static void pci_dev_d3_sleep(struct pci_dev *dev)
41{
42 unsigned int delay = dev->d3_delay;
43
44 if (delay < pci_pm_d3_delay)
45 delay = pci_pm_d3_delay;
46
47 msleep(delay);
48}
1da177e4 49
32a2eea7
JG		 50#ifdef CONFIG_PCI_DOMAINS
51int pci_domains_supported = 1;
52#endif
53
4516a618
AN		 54#define DEFAULT_CARDBUS_IO_SIZE (256)
55#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
56/* pci=cbmemsize=nnM,cbiosize=nn can override this */
57unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
58unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
59
28760489
EB		 60#define DEFAULT_HOTPLUG_IO_SIZE (256)
61#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
62/* pci=hpmemsize=nnM,hpiosize=nn can override this */
63unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
64unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
65
ac1aa47b
JB		 66/*
67 * The default CLS is used if arch didn't set CLS explicitly and not
68 * all pci devices agree on the same value. Arch can override either
69 * the dfl or actual value as it sees fit. Don't forget this is
70 * measured in 32-bit words, not bytes.
71 */
98e724c7 72u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
ac1aa47b
JB		 73u8 pci_cache_line_size;
74
1da177e4
LT		 75/**
76 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
77 * @bus: pointer to PCI bus structure to search
78 *
79 * Given a PCI bus, returns the highest PCI bus number present in the set
80 * including the given PCI bus and its list of child PCI buses.
81 */
96bde06a 82unsigned char pci_bus_max_busnr(struct pci_bus* bus)
1da177e4
LT		 83{
84 struct list_head *tmp;
85 unsigned char max, n;
86
b82db5ce 87 max = bus->subordinate;
1da177e4
LT		 88 list_for_each(tmp, &bus->children) {
89 n = pci_bus_max_busnr(pci_bus_b(tmp));
90 if(n > max)
91 max = n;
92 }
93 return max;
94}
b82db5ce 95EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
1da177e4 96
1684f5dd
AM		 97#ifdef CONFIG_HAS_IOMEM
98void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
99{
100 /*
101 * Make sure the BAR is actually a memory resource, not an IO resource
102 */
103 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
104 WARN_ON(1);
105 return NULL;
106 }
107 return ioremap_nocache(pci_resource_start(pdev, bar),
108 pci_resource_len(pdev, bar));
109}
110EXPORT_SYMBOL_GPL(pci_ioremap_bar);
111#endif
112
b82db5ce 113#if 0
1da177e4
LT		 114/**
115 * pci_max_busnr - returns maximum PCI bus number
116 *
117 * Returns the highest PCI bus number present in the system global list of
118 * PCI buses.
119 */
120unsigned char __devinit
121pci_max_busnr(void)
122{
123 struct pci_bus *bus = NULL;
124 unsigned char max, n;
125
126 max = 0;
127 while ((bus = pci_find_next_bus(bus)) != NULL) {
128 n = pci_bus_max_busnr(bus);
129 if(n > max)
130 max = n;
131 }
132 return max;
133}
134
54c762fe
AB		 135#endif /* 0 */
136
687d5fe3
ME		 137#define PCI_FIND_CAP_TTL 48
138
139static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
140 u8 pos, int cap, int *ttl)
24a4e377
RD		 141{
142 u8 id;
24a4e377 143
687d5fe3 144 while ((*ttl)--) {
24a4e377
RD		 145 pci_bus_read_config_byte(bus, devfn, pos, &pos);
146 if (pos < 0x40)
147 break;
148 pos &= ~3;
149 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
150 &id);
151 if (id == 0xff)
152 break;
153 if (id == cap)
154 return pos;
155 pos += PCI_CAP_LIST_NEXT;
156 }
157 return 0;
158}
159
687d5fe3
ME		 160static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
161 u8 pos, int cap)
162{
163 int ttl = PCI_FIND_CAP_TTL;
164
165 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
166}
167
24a4e377
RD		 168int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
169{
170 return __pci_find_next_cap(dev->bus, dev->devfn,
171 pos + PCI_CAP_LIST_NEXT, cap);
172}
173EXPORT_SYMBOL_GPL(pci_find_next_capability);
174
d3bac118
ME		 175static int __pci_bus_find_cap_start(struct pci_bus *bus,
176 unsigned int devfn, u8 hdr_type)
1da177e4
LT		 177{
178 u16 status;
1da177e4
LT		 179
180 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
181 if (!(status & PCI_STATUS_CAP_LIST))
182 return 0;
183
184 switch (hdr_type) {
185 case PCI_HEADER_TYPE_NORMAL:
186 case PCI_HEADER_TYPE_BRIDGE:
d3bac118 187 return PCI_CAPABILITY_LIST;
1da177e4 188 case PCI_HEADER_TYPE_CARDBUS:
d3bac118 189 return PCI_CB_CAPABILITY_LIST;
1da177e4
LT		 190 default:
191 return 0;
192 }
d3bac118
ME		 193
194 return 0;
1da177e4
LT		 195}
196
197/**
198 * pci_find_capability - query for devices' capabilities
199 * @dev: PCI device to query
200 * @cap: capability code
201 *
202 * Tell if a device supports a given PCI capability.
203 * Returns the address of the requested capability structure within the
204 * device's PCI configuration space or 0 in case the device does not
205 * support it. Possible values for @cap:
206 *
207 * %PCI_CAP_ID_PM Power Management
208 * %PCI_CAP_ID_AGP Accelerated Graphics Port
209 * %PCI_CAP_ID_VPD Vital Product Data
210 * %PCI_CAP_ID_SLOTID Slot Identification
211 * %PCI_CAP_ID_MSI Message Signalled Interrupts
212 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
213 * %PCI_CAP_ID_PCIX PCI-X
214 * %PCI_CAP_ID_EXP PCI Express
215 */
216int pci_find_capability(struct pci_dev *dev, int cap)
217{
d3bac118
ME		 218 int pos;
219
220 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
221 if (pos)
222 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
223
224 return pos;
1da177e4
LT		 225}
226
227/**
228 * pci_bus_find_capability - query for devices' capabilities
229 * @bus: the PCI bus to query
230 * @devfn: PCI device to query
231 * @cap: capability code
232 *
233 * Like pci_find_capability() but works for pci devices that do not have a
234 * pci_dev structure set up yet.
235 *
236 * Returns the address of the requested capability structure within the
237 * device's PCI configuration space or 0 in case the device does not
238 * support it.
239 */
240int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
241{
d3bac118 242 int pos;
1da177e4
LT		 243 u8 hdr_type;
244
245 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
246
d3bac118
ME		 247 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
248 if (pos)
249 pos = __pci_find_next_cap(bus, devfn, pos, cap);
250
251 return pos;
1da177e4
LT		 252}
253
254/**
255 * pci_find_ext_capability - Find an extended capability
256 * @dev: PCI device to query
257 * @cap: capability code
258 *
259 * Returns the address of the requested extended capability structure
260 * within the device's PCI configuration space or 0 if the device does
261 * not support it. Possible values for @cap:
262 *
263 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
264 * %PCI_EXT_CAP_ID_VC Virtual Channel
265 * %PCI_EXT_CAP_ID_DSN Device Serial Number
266 * %PCI_EXT_CAP_ID_PWR Power Budgeting
267 */
268int pci_find_ext_capability(struct pci_dev *dev, int cap)
269{
270 u32 header;
557848c3
ZY		 271 int ttl;
272 int pos = PCI_CFG_SPACE_SIZE;
1da177e4 273
557848c3
ZY		 274 /* minimum 8 bytes per capability */
275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
276
277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
1da177e4
LT		 278 return 0;
279
280 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
281 return 0;
282
283 /*
284 * If we have no capabilities, this is indicated by cap ID,
285 * cap version and next pointer all being 0.
286 */
287 if (header == 0)
288 return 0;
289
290 while (ttl-- > 0) {
291 if (PCI_EXT_CAP_ID(header) == cap)
292 return pos;
293
294 pos = PCI_EXT_CAP_NEXT(header);
557848c3 295 if (pos < PCI_CFG_SPACE_SIZE)
1da177e4
LT		 296 break;
297
298 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
299 break;
300 }
301
302 return 0;
303}
3a720d72 304EXPORT_SYMBOL_GPL(pci_find_ext_capability);
1da177e4 305
cf4c43dd
JB		 306/**
307 * pci_bus_find_ext_capability - find an extended capability
308 * @bus: the PCI bus to query
309 * @devfn: PCI device to query
310 * @cap: capability code
311 *
312 * Like pci_find_ext_capability() but works for pci devices that do not have a
313 * pci_dev structure set up yet.
314 *
315 * Returns the address of the requested capability structure within the
316 * device's PCI configuration space or 0 in case the device does not
317 * support it.
318 */
319int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
320 int cap)
321{
322 u32 header;
323 int ttl;
324 int pos = PCI_CFG_SPACE_SIZE;
325
326 /* minimum 8 bytes per capability */
327 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
328
329 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
330 return 0;
331 if (header == 0xffffffff || header == 0)
332 return 0;
333
334 while (ttl-- > 0) {
335 if (PCI_EXT_CAP_ID(header) == cap)
336 return pos;
337
338 pos = PCI_EXT_CAP_NEXT(header);
339 if (pos < PCI_CFG_SPACE_SIZE)
340 break;
341
342 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
343 break;
344 }
345
346 return 0;
347}
348
687d5fe3
ME		 349static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
350{
351 int rc, ttl = PCI_FIND_CAP_TTL;
352 u8 cap, mask;
353
354 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
355 mask = HT_3BIT_CAP_MASK;
356 else
357 mask = HT_5BIT_CAP_MASK;
358
359 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
360 PCI_CAP_ID_HT, &ttl);
361 while (pos) {
362 rc = pci_read_config_byte(dev, pos + 3, &cap);
363 if (rc != PCIBIOS_SUCCESSFUL)
364 return 0;
365
366 if ((cap & mask) == ht_cap)
367 return pos;
368
47a4d5be
BG		 369 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
370 pos + PCI_CAP_LIST_NEXT,
687d5fe3
ME		 371 PCI_CAP_ID_HT, &ttl);
372 }
373
374 return 0;
375}
376/**
377 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
378 * @dev: PCI device to query
379 * @pos: Position from which to continue searching
380 * @ht_cap: Hypertransport capability code
381 *
382 * To be used in conjunction with pci_find_ht_capability() to search for
383 * all capabilities matching @ht_cap. @pos should always be a value returned
384 * from pci_find_ht_capability().
385 *
386 * NB. To be 100% safe against broken PCI devices, the caller should take
387 * steps to avoid an infinite loop.
388 */
389int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
390{
391 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
392}
393EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
394
395/**
396 * pci_find_ht_capability - query a device's Hypertransport capabilities
397 * @dev: PCI device to query
398 * @ht_cap: Hypertransport capability code
399 *
400 * Tell if a device supports a given Hypertransport capability.
401 * Returns an address within the device's PCI configuration space
402 * or 0 in case the device does not support the request capability.
403 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
404 * which has a Hypertransport capability matching @ht_cap.
405 */
406int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
407{
408 int pos;
409
410 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
411 if (pos)
412 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
413
414 return pos;
415}
416EXPORT_SYMBOL_GPL(pci_find_ht_capability);
417
1da177e4
LT		 418/**
419 * pci_find_parent_resource - return resource region of parent bus of given region
420 * @dev: PCI device structure contains resources to be searched
421 * @res: child resource record for which parent is sought
422 *
423 * For given resource region of given device, return the resource
424 * region of parent bus the given region is contained in or where
425 * it should be allocated from.
426 */
427struct resource *
428pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
429{
430 const struct pci_bus *bus = dev->bus;
431 int i;
89a74ecc 432 struct resource *best = NULL, *r;
1da177e4 433
89a74ecc 434 pci_bus_for_each_resource(bus, r, i) {
1da177e4
LT		 435 if (!r)
436 continue;
437 if (res->start && !(res->start >= r->start && res->end <= r->end))
438 continue; /* Not contained */
439 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
440 continue; /* Wrong type */
441 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
442 return r; /* Exact match */
8c8def26
LT		 443 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
444 if (r->flags & IORESOURCE_PREFETCH)
445 continue;
446 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
447 if (!best)
448 best = r;
1da177e4
LT		 449 }
450 return best;
451}
452
064b53db
JL		 453/**
454 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
455 * @dev: PCI device to have its BARs restored
456 *
457 * Restore the BAR values for a given device, so as to make it
458 * accessible by its driver.
459 */
ad668599 460static void
064b53db
JL		 461pci_restore_bars(struct pci_dev *dev)
462{
bc5f5a82 463 int i;
064b53db 464
bc5f5a82 465 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
14add80b 466 pci_update_resource(dev, i);
064b53db
JL		 467}
468
961d9120
RW		 469static struct pci_platform_pm_ops *pci_platform_pm;
470
471int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
472{
eb9d0fe4
RW		 473 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
474 || !ops->sleep_wake || !ops->can_wakeup)
961d9120
RW		 475 return -EINVAL;
476 pci_platform_pm = ops;
477 return 0;
478}
479
480static inline bool platform_pci_power_manageable(struct pci_dev *dev)
481{
482 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
483}
484
485static inline int platform_pci_set_power_state(struct pci_dev *dev,
486 pci_power_t t)
487{
488 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
489}
490
491static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
492{
493 return pci_platform_pm ?
494 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
495}
8f7020d3 496
eb9d0fe4
RW		 497static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
498{
499 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
500}
501
502static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
503{
504 return pci_platform_pm ?
505 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
506}
507
b67ea761
RW		 508static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
509{
510 return pci_platform_pm ?
511 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
512}
513
1da177e4 514/**
44e4e66e
RW		 515 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
516 * given PCI device
517 * @dev: PCI device to handle.
44e4e66e 518 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1da177e4 519 *
44e4e66e
RW		 520 * RETURN VALUE:
521 * -EINVAL if the requested state is invalid.
522 * -EIO if device does not support PCI PM or its PM capabilities register has a
523 * wrong version, or device doesn't support the requested state.
524 * 0 if device already is in the requested state.
525 * 0 if device's power state has been successfully changed.
1da177e4 526 */
f00a20ef 527static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1da177e4 528{
337001b6 529 u16 pmcsr;
44e4e66e 530 bool need_restore = false;
1da177e4 531
4a865905
RW		 532 /* Check if we're already there */
533 if (dev->current_state == state)
534 return 0;
535
337001b6 536 if (!dev->pm_cap)
cca03dec
AL		 537 return -EIO;
538
44e4e66e
RW		 539 if (state < PCI_D0 || state > PCI_D3hot)
540 return -EINVAL;
541
1da177e4
LT		 542 /* Validate current state:
543 * Can enter D0 from any state, but if we can only go deeper
544 * to sleep if we're already in a low power state
545 */
4a865905 546 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
44e4e66e 547 && dev->current_state > state) {
80ccba11
BH		 548 dev_err(&dev->dev, "invalid power transition "
549 "(from state %d to %d)\n", dev->current_state, state);
1da177e4 550 return -EINVAL;
44e4e66e 551 }
1da177e4 552
1da177e4 553 /* check if this device supports the desired state */
337001b6
RW		 554 if ((state == PCI_D1 && !dev->d1_support)
555 || (state == PCI_D2 && !dev->d2_support))
3fe9d19f 556 return -EIO;
1da177e4 557
337001b6 558 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
064b53db 559
32a36585 560 /* If we're (effectively) in D3, force entire word to 0.
1da177e4
LT		 561 * This doesn't affect PME_Status, disables PME_En, and
562 * sets PowerState to 0.
563 */
32a36585 564 switch (dev->current_state) {
d3535fbb
JL		 565 case PCI_D0:
566 case PCI_D1:
567 case PCI_D2:
568 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
569 pmcsr |= state;
570 break;
f62795f1
RW		 571 case PCI_D3hot:
572 case PCI_D3cold:
32a36585
JL		 573 case PCI_UNKNOWN: /* Boot-up */
574 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
f00a20ef 575 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
44e4e66e 576 need_restore = true;
32a36585 577 /* Fall-through: force to D0 */
32a36585 578 default:
d3535fbb 579 pmcsr = 0;
32a36585 580 break;
1da177e4
LT		 581 }
582
583 /* enter specified state */
337001b6 584 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1da177e4
LT		 585
586 /* Mandatory power management transition delays */
587 /* see PCI PM 1.1 5.6.1 table 18 */
588 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1ae861e6 589 pci_dev_d3_sleep(dev);
1da177e4 590 else if (state == PCI_D2 || dev->current_state == PCI_D2)
aa8c6c93 591 udelay(PCI_PM_D2_DELAY);
1da177e4 592
e13cdbd7
RW		 593 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
594 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
595 if (dev->current_state != state && printk_ratelimit())
596 dev_info(&dev->dev, "Refused to change power state, "
597 "currently in D%d\n", dev->current_state);
064b53db
JL		 598
599 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
600 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
601 * from D3hot to D0 _may_ perform an internal reset, thereby
602 * going to "D0 Uninitialized" rather than "D0 Initialized".
603 * For example, at least some versions of the 3c905B and the
604 * 3c556B exhibit this behaviour.
605 *
606 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
607 * devices in a D3hot state at boot. Consequently, we need to
608 * restore at least the BARs so that the device will be
609 * accessible to its driver.
610 */
611 if (need_restore)
612 pci_restore_bars(dev);
613
f00a20ef 614 if (dev->bus->self)
7d715a6c
SL		 615 pcie_aspm_pm_state_change(dev->bus->self);
616
1da177e4
LT		 617 return 0;
618}
619
44e4e66e
RW		 620/**
621 * pci_update_current_state - Read PCI power state of given device from its
622 * PCI PM registers and cache it
623 * @dev: PCI device to handle.
f06fc0b6 624 * @state: State to cache in case the device doesn't have the PM capability
44e4e66e 625 */
73410429 626void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
44e4e66e 627{
337001b6 628 if (dev->pm_cap) {
44e4e66e
RW		 629 u16 pmcsr;
630
337001b6 631 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
44e4e66e 632 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
f06fc0b6
RW		 633 } else {
634 dev->current_state = state;
44e4e66e
RW		 635 }
636}
637
0e5dd46b
RW		 638/**
639 * pci_platform_power_transition - Use platform to change device power state
640 * @dev: PCI device to handle.
641 * @state: State to put the device into.
642 */
643static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
644{
645 int error;
646
647 if (platform_pci_power_manageable(dev)) {
648 error = platform_pci_set_power_state(dev, state);
649 if (!error)
650 pci_update_current_state(dev, state);
651 } else {
652 error = -ENODEV;
653 /* Fall back to PCI_D0 if native PM is not supported */
b3bad72e
RW		 654 if (!dev->pm_cap)
655 dev->current_state = PCI_D0;
0e5dd46b
RW		 656 }
657
658 return error;
659}
660
661/**
662 * __pci_start_power_transition - Start power transition of a PCI device
663 * @dev: PCI device to handle.
664 * @state: State to put the device into.
665 */
666static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
667{
668 if (state == PCI_D0)
669 pci_platform_power_transition(dev, PCI_D0);
670}
671
672/**
673 * __pci_complete_power_transition - Complete power transition of a PCI device
674 * @dev: PCI device to handle.
675 * @state: State to put the device into.
676 *
677 * This function should not be called directly by device drivers.
678 */
679int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
680{
681 return state > PCI_D0 ?
682 pci_platform_power_transition(dev, state) : -EINVAL;
683}
684EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
685
44e4e66e
RW		 686/**
687 * pci_set_power_state - Set the power state of a PCI device
688 * @dev: PCI device to handle.
689 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
690 *
877d0310 691 * Transition a device to a new power state, using the platform firmware and/or
44e4e66e
RW		 692 * the device's PCI PM registers.
693 *
694 * RETURN VALUE:
695 * -EINVAL if the requested state is invalid.
696 * -EIO if device does not support PCI PM or its PM capabilities register has a
697 * wrong version, or device doesn't support the requested state.
698 * 0 if device already is in the requested state.
699 * 0 if device's power state has been successfully changed.
700 */
701int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
702{
337001b6 703 int error;
44e4e66e
RW		 704
705 /* bound the state we're entering */
706 if (state > PCI_D3hot)
707 state = PCI_D3hot;
708 else if (state < PCI_D0)
709 state = PCI_D0;
710 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
711 /*
712 * If the device or the parent bridge do not support PCI PM,
713 * ignore the request if we're doing anything other than putting
714 * it into D0 (which would only happen on boot).
715 */
716 return 0;
717
4a865905
RW		 718 /* Check if we're already there */
719 if (dev->current_state == state)
720 return 0;
721
0e5dd46b
RW		 722 __pci_start_power_transition(dev, state);
723
979b1791
AC		 724 /* This device is quirked not to be put into D3, so
725 don't put it in D3 */
726 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
727 return 0;
44e4e66e 728
f00a20ef 729 error = pci_raw_set_power_state(dev, state);
44e4e66e 730
0e5dd46b
RW		 731 if (!__pci_complete_power_transition(dev, state))
732 error = 0;
44e4e66e
RW		 733
734 return error;
735}
736
1da177e4
LT		 737/**
738 * pci_choose_state - Choose the power state of a PCI device
739 * @dev: PCI device to be suspended
740 * @state: target sleep state for the whole system. This is the value
741 * that is passed to suspend() function.
742 *
743 * Returns PCI power state suitable for given device and given system
744 * message.
745 */
746
747pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
748{
ab826ca4 749 pci_power_t ret;
0f64474b 750
1da177e4
LT		 751 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
752 return PCI_D0;
753
961d9120
RW		 754 ret = platform_pci_choose_state(dev);
755 if (ret != PCI_POWER_ERROR)
756 return ret;
ca078bae
PM		 757
758 switch (state.event) {
759 case PM_EVENT_ON:
760 return PCI_D0;
761 case PM_EVENT_FREEZE:
b887d2e6
DB		 762 case PM_EVENT_PRETHAW:
763 /* REVISIT both freeze and pre-thaw "should" use D0 */
ca078bae 764 case PM_EVENT_SUSPEND:
3a2d5b70 765 case PM_EVENT_HIBERNATE:
ca078bae 766 return PCI_D3hot;
1da177e4 767 default:
80ccba11
BH		 768 dev_info(&dev->dev, "unrecognized suspend event %d\n",
769 state.event);
1da177e4
LT		 770 BUG();
771 }
772 return PCI_D0;
773}
774
775EXPORT_SYMBOL(pci_choose_state);
776
89858517
YZ		 777#define PCI_EXP_SAVE_REGS 7
778
1b6b8ce2
YZ		 779#define pcie_cap_has_devctl(type, flags) 1
780#define pcie_cap_has_lnkctl(type, flags) \
781 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
782 (type == PCI_EXP_TYPE_ROOT_PORT || \
783 type == PCI_EXP_TYPE_ENDPOINT || \
784 type == PCI_EXP_TYPE_LEG_END))
785#define pcie_cap_has_sltctl(type, flags) \
786 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
787 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
788 (type == PCI_EXP_TYPE_DOWNSTREAM && \
789 (flags & PCI_EXP_FLAGS_SLOT))))
790#define pcie_cap_has_rtctl(type, flags) \
791 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
792 (type == PCI_EXP_TYPE_ROOT_PORT || \
793 type == PCI_EXP_TYPE_RC_EC))
794#define pcie_cap_has_devctl2(type, flags) \
795 ((flags & PCI_EXP_FLAGS_VERS) > 1)
796#define pcie_cap_has_lnkctl2(type, flags) \
797 ((flags & PCI_EXP_FLAGS_VERS) > 1)
798#define pcie_cap_has_sltctl2(type, flags) \
799 ((flags & PCI_EXP_FLAGS_VERS) > 1)
800
b56a5a23
MT		 801static int pci_save_pcie_state(struct pci_dev *dev)
802{
803 int pos, i = 0;
804 struct pci_cap_saved_state *save_state;
805 u16 *cap;
1b6b8ce2 806 u16 flags;
b56a5a23 807
06a1cbaf
KK		 808 pos = pci_pcie_cap(dev);
809 if (!pos)
b56a5a23
MT		 810 return 0;
811
9f35575d 812 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
b56a5a23 813 if (!save_state) {
e496b617 814 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
b56a5a23
MT		 815 return -ENOMEM;
816 }
817 cap = (u16 *)&save_state->data[0];
818
1b6b8ce2
YZ		 819 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
820
821 if (pcie_cap_has_devctl(dev->pcie_type, flags))
822 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
823 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
824 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
825 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
826 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
827 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
828 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
829 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
830 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
831 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
832 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
833 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
834 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
63f4898a 835
b56a5a23
MT		 836 return 0;
837}
838
839static void pci_restore_pcie_state(struct pci_dev *dev)
840{
841 int i = 0, pos;
842 struct pci_cap_saved_state *save_state;
843 u16 *cap;
1b6b8ce2 844 u16 flags;
b56a5a23
MT		 845
846 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
847 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
848 if (!save_state || pos <= 0)
849 return;
850 cap = (u16 *)&save_state->data[0];
851
1b6b8ce2
YZ		 852 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
853
854 if (pcie_cap_has_devctl(dev->pcie_type, flags))
855 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
856 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
857 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
858 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
859 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
860 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
861 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
862 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
863 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
864 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
865 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
866 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
867 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
b56a5a23
MT		 868}
869
cc692a5f
SH		 870
871static int pci_save_pcix_state(struct pci_dev *dev)
872{
63f4898a 873 int pos;
cc692a5f 874 struct pci_cap_saved_state *save_state;
cc692a5f
SH		 875
876 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
877 if (pos <= 0)
878 return 0;
879
f34303de 880 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
cc692a5f 881 if (!save_state) {
e496b617 882 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
cc692a5f
SH		 883 return -ENOMEM;
884 }
cc692a5f 885
63f4898a
RW		 886 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
887
cc692a5f
SH		 888 return 0;
889}
890
891static void pci_restore_pcix_state(struct pci_dev *dev)
892{
893 int i = 0, pos;
894 struct pci_cap_saved_state *save_state;
895 u16 *cap;
896
897 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
898 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
899 if (!save_state || pos <= 0)
900 return;
901 cap = (u16 *)&save_state->data[0];
902
903 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
cc692a5f
SH		 904}
905
906
1da177e4
LT		 907/**
908 * pci_save_state - save the PCI configuration space of a device before suspending
909 * @dev: - PCI device that we're dealing with
1da177e4
LT		 910 */
911int
912pci_save_state(struct pci_dev *dev)
913{
914 int i;
915 /* XXX: 100% dword access ok here? */
916 for (i = 0; i < 16; i++)
9e0b5b2c 917 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
aa8c6c93 918 dev->state_saved = true;
b56a5a23
MT		 919 if ((i = pci_save_pcie_state(dev)) != 0)
920 return i;
cc692a5f
SH		 921 if ((i = pci_save_pcix_state(dev)) != 0)
922 return i;
1da177e4
LT		 923 return 0;
924}
925
926/**
927 * pci_restore_state - Restore the saved state of a PCI device
928 * @dev: - PCI device that we're dealing with
1da177e4
LT		 929 */
930int
931pci_restore_state(struct pci_dev *dev)
932{
933 int i;
b4482a4b 934 u32 val;
1da177e4 935
c82f63e4
AD		 936 if (!dev->state_saved)
937 return 0;
4b77b0a2 938
b56a5a23
MT		 939 /* PCI Express register must be restored first */
940 pci_restore_pcie_state(dev);
941
8b8c8d28
YL		 942 /*
943 * The Base Address register should be programmed before the command
944 * register(s)
945 */
946 for (i = 15; i >= 0; i--) {
04d9c1a1
DJ		 947 pci_read_config_dword(dev, i * 4, &val);
948 if (val != dev->saved_config_space[i]) {
80ccba11
BH		 949 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
950 "space at offset %#x (was %#x, writing %#x)\n",
951 i, val, (int)dev->saved_config_space[i]);
04d9c1a1
DJ		 952 pci_write_config_dword(dev,i * 4,
953 dev->saved_config_space[i]);
954 }
955 }
cc692a5f 956 pci_restore_pcix_state(dev);
41017f0c 957 pci_restore_msi_state(dev);
8c5cdb6a 958 pci_restore_iov_state(dev);
8fed4b65 959
4b77b0a2
RW		 960 dev->state_saved = false;
961
1da177e4
LT		 962 return 0;
963}
964
38cc1302
HS		 965static int do_pci_enable_device(struct pci_dev *dev, int bars)
966{
967 int err;
968
969 err = pci_set_power_state(dev, PCI_D0);
970 if (err < 0 && err != -EIO)
971 return err;
972 err = pcibios_enable_device(dev, bars);
973 if (err < 0)
974 return err;
975 pci_fixup_device(pci_fixup_enable, dev);
976
977 return 0;
978}
979
980/**
0b62e13b 981 * pci_reenable_device - Resume abandoned device
38cc1302
HS		 982 * @dev: PCI device to be resumed
983 *
984 * Note this function is a backend of pci_default_resume and is not supposed
985 * to be called by normal code, write proper resume handler and use it instead.
986 */
0b62e13b 987int pci_reenable_device(struct pci_dev *dev)
38cc1302 988{
296ccb08 989 if (pci_is_enabled(dev))
38cc1302
HS		 990 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
991 return 0;
992}
993
b718989d
BH		 994static int __pci_enable_device_flags(struct pci_dev *dev,
995 resource_size_t flags)
1da177e4
LT		 996{
997 int err;
b718989d 998 int i, bars = 0;
1da177e4 999
9fb625c3
HS		 1000 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1001 return 0; /* already enabled */
1002
b718989d
BH		 1003 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1004 if (dev->resource[i].flags & flags)
1005 bars |= (1 << i);
1006
38cc1302 1007 err = do_pci_enable_device(dev, bars);
95a62965 1008 if (err < 0)
38cc1302 1009 atomic_dec(&dev->enable_cnt);
9fb625c3 1010 return err;
1da177e4
LT		 1011}
1012
b718989d
BH		 1013/**
1014 * pci_enable_device_io - Initialize a device for use with IO space
1015 * @dev: PCI device to be initialized
1016 *
1017 * Initialize device before it's used by a driver. Ask low-level code
1018 * to enable I/O resources. Wake up the device if it was suspended.
1019 * Beware, this function can fail.
1020 */
1021int pci_enable_device_io(struct pci_dev *dev)
1022{
1023 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1024}
1025
1026/**
1027 * pci_enable_device_mem - Initialize a device for use with Memory space
1028 * @dev: PCI device to be initialized
1029 *
1030 * Initialize device before it's used by a driver. Ask low-level code
1031 * to enable Memory resources. Wake up the device if it was suspended.
1032 * Beware, this function can fail.
1033 */
1034int pci_enable_device_mem(struct pci_dev *dev)
1035{
1036 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1037}
1038
bae94d02
IPG		 1039/**
1040 * pci_enable_device - Initialize device before it's used by a driver.
1041 * @dev: PCI device to be initialized
1042 *
1043 * Initialize device before it's used by a driver. Ask low-level code
1044 * to enable I/O and memory. Wake up the device if it was suspended.
1045 * Beware, this function can fail.
1046 *
1047 * Note we don't actually enable the device many times if we call
1048 * this function repeatedly (we just increment the count).
1049 */
1050int pci_enable_device(struct pci_dev *dev)
1051{
b718989d 1052 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
bae94d02
IPG		 1053}
1054
9ac7849e
TH		 1055/*
1056 * Managed PCI resources. This manages device on/off, intx/msi/msix
1057 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1058 * there's no need to track it separately. pci_devres is initialized
1059 * when a device is enabled using managed PCI device enable interface.
1060 */
1061struct pci_devres {
7f375f32
TH		 1062 unsigned int enabled:1;
1063 unsigned int pinned:1;
9ac7849e
TH		 1064 unsigned int orig_intx:1;
1065 unsigned int restore_intx:1;
1066 u32 region_mask;
1067};
1068
1069static void pcim_release(struct device *gendev, void *res)
1070{
1071 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1072 struct pci_devres *this = res;
1073 int i;
1074
1075 if (dev->msi_enabled)
1076 pci_disable_msi(dev);
1077 if (dev->msix_enabled)
1078 pci_disable_msix(dev);
1079
1080 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1081 if (this->region_mask & (1 << i))
1082 pci_release_region(dev, i);
1083
1084 if (this->restore_intx)
1085 pci_intx(dev, this->orig_intx);
1086
7f375f32 1087 if (this->enabled && !this->pinned)
9ac7849e
TH		 1088 pci_disable_device(dev);
1089}
1090
1091static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1092{
1093 struct pci_devres *dr, *new_dr;
1094
1095 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1096 if (dr)
1097 return dr;
1098
1099 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1100 if (!new_dr)
1101 return NULL;
1102 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1103}
1104
1105static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1106{
1107 if (pci_is_managed(pdev))
1108 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1109 return NULL;
1110}
1111
1112/**
1113 * pcim_enable_device - Managed pci_enable_device()
1114 * @pdev: PCI device to be initialized
1115 *
1116 * Managed pci_enable_device().
1117 */
1118int pcim_enable_device(struct pci_dev *pdev)
1119{
1120 struct pci_devres *dr;
1121 int rc;
1122
1123 dr = get_pci_dr(pdev);
1124 if (unlikely(!dr))
1125 return -ENOMEM;
b95d58ea
TH		 1126 if (dr->enabled)
1127 return 0;
9ac7849e
TH		 1128
1129 rc = pci_enable_device(pdev);
1130 if (!rc) {
1131 pdev->is_managed = 1;
7f375f32 1132 dr->enabled = 1;
9ac7849e
TH		 1133 }
1134 return rc;
1135}
1136
1137/**
1138 * pcim_pin_device - Pin managed PCI device
1139 * @pdev: PCI device to pin
1140 *
1141 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1142 * driver detach. @pdev must have been enabled with
1143 * pcim_enable_device().
1144 */
1145void pcim_pin_device(struct pci_dev *pdev)
1146{
1147 struct pci_devres *dr;
1148
1149 dr = find_pci_dr(pdev);
7f375f32 1150 WARN_ON(!dr || !dr->enabled);
9ac7849e 1151 if (dr)
7f375f32 1152 dr->pinned = 1;
9ac7849e
TH		 1153}
1154
1da177e4
LT		 1155/**
1156 * pcibios_disable_device - disable arch specific PCI resources for device dev
1157 * @dev: the PCI device to disable
1158 *
1159 * Disables architecture specific PCI resources for the device. This
1160 * is the default implementation. Architecture implementations can
1161 * override this.
1162 */
1163void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1164
fa58d305
RW		 1165static void do_pci_disable_device(struct pci_dev *dev)
1166{
1167 u16 pci_command;
1168
1169 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1170 if (pci_command & PCI_COMMAND_MASTER) {
1171 pci_command &= ~PCI_COMMAND_MASTER;
1172 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1173 }
1174
1175 pcibios_disable_device(dev);
1176}
1177
1178/**
1179 * pci_disable_enabled_device - Disable device without updating enable_cnt
1180 * @dev: PCI device to disable
1181 *
1182 * NOTE: This function is a backend of PCI power management routines and is
1183 * not supposed to be called drivers.
1184 */
1185void pci_disable_enabled_device(struct pci_dev *dev)
1186{
296ccb08 1187 if (pci_is_enabled(dev))
fa58d305
RW		 1188 do_pci_disable_device(dev);
1189}
1190
1da177e4
LT		 1191/**
1192 * pci_disable_device - Disable PCI device after use
1193 * @dev: PCI device to be disabled
1194 *
1195 * Signal to the system that the PCI device is not in use by the system
1196 * anymore. This only involves disabling PCI bus-mastering, if active.
bae94d02
IPG		 1197 *
1198 * Note we don't actually disable the device until all callers of
1199 * pci_device_enable() have called pci_device_disable().
1da177e4
LT		 1200 */
1201void
1202pci_disable_device(struct pci_dev *dev)
1203{
9ac7849e 1204 struct pci_devres *dr;
99dc804d 1205
9ac7849e
TH		 1206 dr = find_pci_dr(dev);
1207 if (dr)
7f375f32 1208 dr->enabled = 0;
9ac7849e 1209
bae94d02
IPG		 1210 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1211 return;
1212
fa58d305 1213 do_pci_disable_device(dev);
1da177e4 1214
fa58d305 1215 dev->is_busmaster = 0;
1da177e4
LT		 1216}
1217
f7bdd12d
BK		 1218/**
1219 * pcibios_set_pcie_reset_state - set reset state for device dev
45e829ea 1220 * @dev: the PCIe device reset
f7bdd12d
BK		 1221 * @state: Reset state to enter into
1222 *
1223 *
45e829ea 1224 * Sets the PCIe reset state for the device. This is the default
f7bdd12d
BK		 1225 * implementation. Architecture implementations can override this.
1226 */
1227int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1228 enum pcie_reset_state state)
1229{
1230 return -EINVAL;
1231}
1232
1233/**
1234 * pci_set_pcie_reset_state - set reset state for device dev
45e829ea 1235 * @dev: the PCIe device reset
f7bdd12d
BK		 1236 * @state: Reset state to enter into
1237 *
1238 *
1239 * Sets the PCI reset state for the device.
1240 */
1241int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1242{
1243 return pcibios_set_pcie_reset_state(dev, state);
1244}
1245
58ff4633
RW		 1246/**
1247 * pci_check_pme_status - Check if given device has generated PME.
1248 * @dev: Device to check.
1249 *
1250 * Check the PME status of the device and if set, clear it and clear PME enable
1251 * (if set). Return 'true' if PME status and PME enable were both set or
1252 * 'false' otherwise.
1253 */
1254bool pci_check_pme_status(struct pci_dev *dev)
1255{
1256 int pmcsr_pos;
1257 u16 pmcsr;
1258 bool ret = false;
1259
1260 if (!dev->pm_cap)
1261 return false;
1262
1263 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1264 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1265 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1266 return false;
1267
1268 /* Clear PME status. */
1269 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1270 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1271 /* Disable PME to avoid interrupt flood. */
1272 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1273 ret = true;
1274 }
1275
1276 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1277
1278 return ret;
1279}
1280
b67ea761
RW		 1281/**
1282 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1283 * @dev: Device to handle.
1284 * @ign: Ignored.
1285 *
1286 * Check if @dev has generated PME and queue a resume request for it in that
1287 * case.
1288 */
1289static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1290{
1291 if (pci_check_pme_status(dev))
1292 pm_request_resume(&dev->dev);
1293 return 0;
1294}
1295
1296/**
1297 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1298 * @bus: Top bus of the subtree to walk.
1299 */
1300void pci_pme_wakeup_bus(struct pci_bus *bus)
1301{
1302 if (bus)
1303 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1304}
1305
eb9d0fe4
RW		 1306/**
1307 * pci_pme_capable - check the capability of PCI device to generate PME#
1308 * @dev: PCI device to handle.
eb9d0fe4
RW		 1309 * @state: PCI state from which device will issue PME#.
1310 */
e5899e1b 1311bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
eb9d0fe4 1312{
337001b6 1313 if (!dev->pm_cap)
eb9d0fe4
RW		 1314 return false;
1315
337001b6 1316 return !!(dev->pme_support & (1 << state));
eb9d0fe4
RW		 1317}
1318
1319/**
1320 * pci_pme_active - enable or disable PCI device's PME# function
1321 * @dev: PCI device to handle.
eb9d0fe4
RW		 1322 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1323 *
1324 * The caller must verify that the device is capable of generating PME# before
1325 * calling this function with @enable equal to 'true'.
1326 */
5a6c9b60 1327void pci_pme_active(struct pci_dev *dev, bool enable)
eb9d0fe4
RW		 1328{
1329 u16 pmcsr;
1330
337001b6 1331 if (!dev->pm_cap)
eb9d0fe4
RW		 1332 return;
1333
337001b6 1334 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
eb9d0fe4
RW		 1335 /* Clear PME_Status by writing 1 to it and enable PME# */
1336 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1337 if (!enable)
1338 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1339
337001b6 1340 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
eb9d0fe4 1341
10c3d71d 1342 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
eb9d0fe4
RW		 1343 enable ? "enabled" : "disabled");
1344}
1345
1da177e4 1346/**
6cbf8214 1347 * __pci_enable_wake - enable PCI device as wakeup event source
075c1771
DB		 1348 * @dev: PCI device affected
1349 * @state: PCI state from which device will issue wakeup events
6cbf8214 1350 * @runtime: True if the events are to be generated at run time
075c1771
DB		 1351 * @enable: True to enable event generation; false to disable
1352 *
1353 * This enables the device as a wakeup event source, or disables it.
1354 * When such events involves platform-specific hooks, those hooks are
1355 * called automatically by this routine.
1356 *
1357 * Devices with legacy power management (no standard PCI PM capabilities)
eb9d0fe4 1358 * always require such platform hooks.
075c1771 1359 *
eb9d0fe4
RW		 1360 * RETURN VALUE:
1361 * 0 is returned on success
1362 * -EINVAL is returned if device is not supposed to wake up the system
1363 * Error code depending on the platform is returned if both the platform and
1364 * the native mechanism fail to enable the generation of wake-up events
1da177e4 1365 */
6cbf8214
RW		 1366int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1367 bool runtime, bool enable)
1da177e4 1368{
5bcc2fb4 1369 int ret = 0;
075c1771 1370
6cbf8214 1371 if (enable && !runtime && !device_may_wakeup(&dev->dev))
eb9d0fe4 1372 return -EINVAL;
1da177e4 1373
e80bb09d
RW		 1374 /* Don't do the same thing twice in a row for one device. */
1375 if (!!enable == !!dev->wakeup_prepared)
1376 return 0;
1377
eb9d0fe4
RW		 1378 /*
1379 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1380 * Anderson we should be doing PME# wake enable followed by ACPI wake
1381 * enable. To disable wake-up we call the platform first, for symmetry.
075c1771 1382 */
1da177e4 1383
5bcc2fb4
RW		 1384 if (enable) {
1385 int error;
1da177e4 1386
5bcc2fb4
RW		 1387 if (pci_pme_capable(dev, state))
1388 pci_pme_active(dev, true);
1389 else
1390 ret = 1;
6cbf8214
RW		 1391 error = runtime ? platform_pci_run_wake(dev, true) :
1392 platform_pci_sleep_wake(dev, true);
5bcc2fb4
RW		 1393 if (ret)
1394 ret = error;
e80bb09d
RW		 1395 if (!ret)
1396 dev->wakeup_prepared = true;
5bcc2fb4 1397 } else {
6cbf8214
RW		 1398 if (runtime)
1399 platform_pci_run_wake(dev, false);
1400 else
1401 platform_pci_sleep_wake(dev, false);
5bcc2fb4 1402 pci_pme_active(dev, false);
e80bb09d 1403 dev->wakeup_prepared = false;
5bcc2fb4 1404 }
1da177e4 1405
5bcc2fb4 1406 return ret;
eb9d0fe4 1407}
6cbf8214 1408EXPORT_SYMBOL(__pci_enable_wake);
1da177e4 1409
0235c4fc
RW		 1410/**
1411 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1412 * @dev: PCI device to prepare
1413 * @enable: True to enable wake-up event generation; false to disable
1414 *
1415 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1416 * and this function allows them to set that up cleanly - pci_enable_wake()
1417 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1418 * ordering constraints.
1419 *
1420 * This function only returns error code if the device is not capable of
1421 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1422 * enable wake-up power for it.
1423 */
1424int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1425{
1426 return pci_pme_capable(dev, PCI_D3cold) ?
1427 pci_enable_wake(dev, PCI_D3cold, enable) :
1428 pci_enable_wake(dev, PCI_D3hot, enable);
1429}
1430
404cc2d8 1431/**
37139074
JB		 1432 * pci_target_state - find an appropriate low power state for a given PCI dev
1433 * @dev: PCI device
1434 *
1435 * Use underlying platform code to find a supported low power state for @dev.
1436 * If the platform can't manage @dev, return the deepest state from which it
1437 * can generate wake events, based on any available PME info.
404cc2d8 1438 */
e5899e1b 1439pci_power_t pci_target_state(struct pci_dev *dev)
404cc2d8
RW		 1440{
1441 pci_power_t target_state = PCI_D3hot;
404cc2d8
RW		 1442
1443 if (platform_pci_power_manageable(dev)) {
1444 /*
1445 * Call the platform to choose the target state of the device
1446 * and enable wake-up from this state if supported.
1447 */
1448 pci_power_t state = platform_pci_choose_state(dev);
1449
1450 switch (state) {
1451 case PCI_POWER_ERROR:
1452 case PCI_UNKNOWN:
1453 break;
1454 case PCI_D1:
1455 case PCI_D2:
1456 if (pci_no_d1d2(dev))
1457 break;
1458 default:
1459 target_state = state;
404cc2d8 1460 }
d2abdf62
RW		 1461 } else if (!dev->pm_cap) {
1462 target_state = PCI_D0;
404cc2d8
RW		 1463 } else if (device_may_wakeup(&dev->dev)) {
1464 /*
1465 * Find the deepest state from which the device can generate
1466 * wake-up events, make it the target state and enable device
1467 * to generate PME#.
1468 */
337001b6
RW		 1469 if (dev->pme_support) {
1470 while (target_state
1471 && !(dev->pme_support & (1 << target_state)))
1472 target_state--;
404cc2d8
RW		 1473 }
1474 }
1475
e5899e1b
RW		 1476 return target_state;
1477}
1478
1479/**
1480 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1481 * @dev: Device to handle.
1482 *
1483 * Choose the power state appropriate for the device depending on whether
1484 * it can wake up the system and/or is power manageable by the platform
1485 * (PCI_D3hot is the default) and put the device into that state.
1486 */
1487int pci_prepare_to_sleep(struct pci_dev *dev)
1488{
1489 pci_power_t target_state = pci_target_state(dev);
1490 int error;
1491
1492 if (target_state == PCI_POWER_ERROR)
1493 return -EIO;
1494
8efb8c76 1495 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
c157dfa3 1496
404cc2d8
RW		 1497 error = pci_set_power_state(dev, target_state);
1498
1499 if (error)
1500 pci_enable_wake(dev, target_state, false);
1501
1502 return error;
1503}
1504
1505/**
443bd1c4 1506 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
404cc2d8
RW		 1507 * @dev: Device to handle.
1508 *
1509 * Disable device's sytem wake-up capability and put it into D0.
1510 */
1511int pci_back_from_sleep(struct pci_dev *dev)
1512{
1513 pci_enable_wake(dev, PCI_D0, false);
1514 return pci_set_power_state(dev, PCI_D0);
1515}
1516
6cbf8214
RW		 1517/**
1518 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1519 * @dev: PCI device being suspended.
1520 *
1521 * Prepare @dev to generate wake-up events at run time and put it into a low
1522 * power state.
1523 */
1524int pci_finish_runtime_suspend(struct pci_dev *dev)
1525{
1526 pci_power_t target_state = pci_target_state(dev);
1527 int error;
1528
1529 if (target_state == PCI_POWER_ERROR)
1530 return -EIO;
1531
1532 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1533
1534 error = pci_set_power_state(dev, target_state);
1535
1536 if (error)
1537 __pci_enable_wake(dev, target_state, true, false);
1538
1539 return error;
1540}
1541
b67ea761
RW		 1542/**
1543 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1544 * @dev: Device to check.
1545 *
1546 * Return true if the device itself is cabable of generating wake-up events
1547 * (through the platform or using the native PCIe PME) or if the device supports
1548 * PME and one of its upstream bridges can generate wake-up events.
1549 */
1550bool pci_dev_run_wake(struct pci_dev *dev)
1551{
1552 struct pci_bus *bus = dev->bus;
1553
1554 if (device_run_wake(&dev->dev))
1555 return true;
1556
1557 if (!dev->pme_support)
1558 return false;
1559
1560 while (bus->parent) {
1561 struct pci_dev *bridge = bus->self;
1562
1563 if (device_run_wake(&bridge->dev))
1564 return true;
1565
1566 bus = bus->parent;
1567 }
1568
1569 /* We have reached the root bus. */
1570 if (bus->bridge)
1571 return device_run_wake(bus->bridge);
1572
1573 return false;
1574}
1575EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1576
eb9d0fe4
RW		 1577/**
1578 * pci_pm_init - Initialize PM functions of given PCI device
1579 * @dev: PCI device to handle.
1580 */
1581void pci_pm_init(struct pci_dev *dev)
1582{
1583 int pm;
1584 u16 pmc;
1da177e4 1585
a1e4d72c 1586 device_enable_async_suspend(&dev->dev);
e80bb09d 1587 dev->wakeup_prepared = false;
337001b6
RW		 1588 dev->pm_cap = 0;
1589
eb9d0fe4
RW		 1590 /* find PCI PM capability in list */
1591 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1592 if (!pm)
50246dd4 1593 return;
eb9d0fe4
RW		 1594 /* Check device's ability to generate PME# */
1595 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
075c1771 1596
eb9d0fe4
RW		 1597 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1598 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1599 pmc & PCI_PM_CAP_VER_MASK);
50246dd4 1600 return;
eb9d0fe4
RW		 1601 }
1602
337001b6 1603 dev->pm_cap = pm;
1ae861e6 1604 dev->d3_delay = PCI_PM_D3_WAIT;
337001b6
RW		 1605
1606 dev->d1_support = false;
1607 dev->d2_support = false;
1608 if (!pci_no_d1d2(dev)) {
c9ed77ee 1609 if (pmc & PCI_PM_CAP_D1)
337001b6 1610 dev->d1_support = true;
c9ed77ee 1611 if (pmc & PCI_PM_CAP_D2)
337001b6 1612 dev->d2_support = true;
c9ed77ee
BH		 1613
1614 if (dev->d1_support || dev->d2_support)
1615 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
ec84f126
JB		 1616 dev->d1_support ? " D1" : "",
1617 dev->d2_support ? " D2" : "");
337001b6
RW		 1618 }
1619
1620 pmc &= PCI_PM_CAP_PME_MASK;
1621 if (pmc) {
10c3d71d
BH		 1622 dev_printk(KERN_DEBUG, &dev->dev,
1623 "PME# supported from%s%s%s%s%s\n",
c9ed77ee
BH		 1624 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1625 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1626 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1627 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1628 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
337001b6 1629 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
eb9d0fe4
RW		 1630 /*
1631 * Make device's PM flags reflect the wake-up capability, but
1632 * let the user space enable it to wake up the system as needed.
1633 */
1634 device_set_wakeup_capable(&dev->dev, true);
1635 device_set_wakeup_enable(&dev->dev, false);
1636 /* Disable the PME# generation functionality */
337001b6
RW		 1637 pci_pme_active(dev, false);
1638 } else {
1639 dev->pme_support = 0;
eb9d0fe4 1640 }
1da177e4
LT		 1641}
1642
eb9c39d0
JB		 1643/**
1644 * platform_pci_wakeup_init - init platform wakeup if present
1645 * @dev: PCI device
1646 *
1647 * Some devices don't have PCI PM caps but can still generate wakeup
1648 * events through platform methods (like ACPI events). If @dev supports
1649 * platform wakeup events, set the device flag to indicate as much. This
1650 * may be redundant if the device also supports PCI PM caps, but double
1651 * initialization should be safe in that case.
1652 */
1653void platform_pci_wakeup_init(struct pci_dev *dev)
1654{
1655 if (!platform_pci_can_wakeup(dev))
1656 return;
1657
1658 device_set_wakeup_capable(&dev->dev, true);
1659 device_set_wakeup_enable(&dev->dev, false);
1660 platform_pci_sleep_wake(dev, false);
1661}
1662
63f4898a
RW		 1663/**
1664 * pci_add_save_buffer - allocate buffer for saving given capability registers
1665 * @dev: the PCI device
1666 * @cap: the capability to allocate the buffer for
1667 * @size: requested size of the buffer
1668 */
1669static int pci_add_cap_save_buffer(
1670 struct pci_dev *dev, char cap, unsigned int size)
1671{
1672 int pos;
1673 struct pci_cap_saved_state *save_state;
1674
1675 pos = pci_find_capability(dev, cap);
1676 if (pos <= 0)
1677 return 0;
1678
1679 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1680 if (!save_state)
1681 return -ENOMEM;
1682
1683 save_state->cap_nr = cap;
1684 pci_add_saved_cap(dev, save_state);
1685
1686 return 0;
1687}
1688
1689/**
1690 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1691 * @dev: the PCI device
1692 */
1693void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1694{
1695 int error;
1696
89858517
YZ		 1697 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1698 PCI_EXP_SAVE_REGS * sizeof(u16));
63f4898a
RW		 1699 if (error)
1700 dev_err(&dev->dev,
1701 "unable to preallocate PCI Express save buffer\n");
1702
1703 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1704 if (error)
1705 dev_err(&dev->dev,
1706 "unable to preallocate PCI-X save buffer\n");
1707}
1708
58c3a727
YZ		 1709/**
1710 * pci_enable_ari - enable ARI forwarding if hardware support it
1711 * @dev: the PCI device
1712 */
1713void pci_enable_ari(struct pci_dev *dev)
1714{
1715 int pos;
1716 u32 cap;
1717 u16 ctrl;
8113587c 1718 struct pci_dev *bridge;
58c3a727 1719
5f4d91a1 1720 if (!pci_is_pcie(dev) || dev->devfn)
58c3a727
YZ		 1721 return;
1722
8113587c
ZY		 1723 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1724 if (!pos)
58c3a727
YZ		 1725 return;
1726
8113587c 1727 bridge = dev->bus->self;
5f4d91a1 1728 if (!bridge || !pci_is_pcie(bridge))
8113587c
ZY		 1729 return;
1730
06a1cbaf 1731 pos = pci_pcie_cap(bridge);
58c3a727
YZ		 1732 if (!pos)
1733 return;
1734
8113587c 1735 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
58c3a727
YZ		 1736 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1737 return;
1738
8113587c 1739 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
58c3a727 1740 ctrl |= PCI_EXP_DEVCTL2_ARI;
8113587c 1741 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
58c3a727 1742
8113587c 1743 bridge->ari_enabled = 1;
58c3a727
YZ		 1744}
1745
5d990b62
CW		 1746static int pci_acs_enable;
1747
1748/**
1749 * pci_request_acs - ask for ACS to be enabled if supported
1750 */
1751void pci_request_acs(void)
1752{
1753 pci_acs_enable = 1;
1754}
1755
ae21ee65
AK		 1756/**
1757 * pci_enable_acs - enable ACS if hardware support it
1758 * @dev: the PCI device
1759 */
1760void pci_enable_acs(struct pci_dev *dev)
1761{
1762 int pos;
1763 u16 cap;
1764 u16 ctrl;
1765
5d990b62
CW		 1766 if (!pci_acs_enable)
1767 return;
1768
5f4d91a1 1769 if (!pci_is_pcie(dev))
ae21ee65
AK		 1770 return;
1771
1772 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1773 if (!pos)
1774 return;
1775
1776 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1777 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1778
1779 /* Source Validation */
1780 ctrl |= (cap & PCI_ACS_SV);
1781
1782 /* P2P Request Redirect */
1783 ctrl |= (cap & PCI_ACS_RR);
1784
1785 /* P2P Completion Redirect */
1786 ctrl |= (cap & PCI_ACS_CR);
1787
1788 /* Upstream Forwarding */
1789 ctrl |= (cap & PCI_ACS_UF);
1790
1791 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1792}
1793
57c2cf71
BH		 1794/**
1795 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1796 * @dev: the PCI device
1797 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1798 *
1799 * Perform INTx swizzling for a device behind one level of bridge. This is
1800 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
46b952a3
MW		 1801 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1802 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1803 * the PCI Express Base Specification, Revision 2.1)
57c2cf71
BH		 1804 */
1805u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1806{
46b952a3
MW		 1807 int slot;
1808
1809 if (pci_ari_enabled(dev->bus))
1810 slot = 0;
1811 else
1812 slot = PCI_SLOT(dev->devfn);
1813
1814 return (((pin - 1) + slot) % 4) + 1;
57c2cf71
BH		 1815}
1816
1da177e4
LT		 1817int
1818pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1819{
1820 u8 pin;
1821
514d207d 1822 pin = dev->pin;
1da177e4
LT		 1823 if (!pin)
1824 return -1;
878f2e50 1825
8784fd4d 1826 while (!pci_is_root_bus(dev->bus)) {
57c2cf71 1827 pin = pci_swizzle_interrupt_pin(dev, pin);
1da177e4
LT		 1828 dev = dev->bus->self;
1829 }
1830 *bridge = dev;
1831 return pin;
1832}
1833
68feac87
BH		 1834/**
1835 * pci_common_swizzle - swizzle INTx all the way to root bridge
1836 * @dev: the PCI device
1837 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1838 *
1839 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1840 * bridges all the way up to a PCI root bus.
1841 */
1842u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1843{
1844 u8 pin = *pinp;
1845
1eb39487 1846 while (!pci_is_root_bus(dev->bus)) {
68feac87
BH		 1847 pin = pci_swizzle_interrupt_pin(dev, pin);
1848 dev = dev->bus->self;
1849 }
1850 *pinp = pin;
1851 return PCI_SLOT(dev->devfn);
1852}
1853
1da177e4
LT		 1854/**
1855 * pci_release_region - Release a PCI bar
1856 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1857 * @bar: BAR to release
1858 *
1859 * Releases the PCI I/O and memory resources previously reserved by a
1860 * successful call to pci_request_region. Call this function only
1861 * after all use of the PCI regions has ceased.
1862 */
1863void pci_release_region(struct pci_dev *pdev, int bar)
1864{
9ac7849e
TH		 1865 struct pci_devres *dr;
1866
1da177e4
LT		 1867 if (pci_resource_len(pdev, bar) == 0)
1868 return;
1869 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1870 release_region(pci_resource_start(pdev, bar),
1871 pci_resource_len(pdev, bar));
1872 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1873 release_mem_region(pci_resource_start(pdev, bar),
1874 pci_resource_len(pdev, bar));
9ac7849e
TH		 1875
1876 dr = find_pci_dr(pdev);
1877 if (dr)
1878 dr->region_mask &= ~(1 << bar);
1da177e4
LT		 1879}
1880
1881/**
f5ddcac4 1882 * __pci_request_region - Reserved PCI I/O and memory resource
1da177e4
LT		 1883 * @pdev: PCI device whose resources are to be reserved
1884 * @bar: BAR to be reserved
1885 * @res_name: Name to be associated with resource.
f5ddcac4 1886 * @exclusive: whether the region access is exclusive or not
1da177e4
LT		 1887 *
1888 * Mark the PCI region associated with PCI device @pdev BR @bar as
1889 * being reserved by owner @res_name. Do not access any
1890 * address inside the PCI regions unless this call returns
1891 * successfully.
1892 *
f5ddcac4
RD		 1893 * If @exclusive is set, then the region is marked so that userspace
1894 * is explicitly not allowed to map the resource via /dev/mem or
1895 * sysfs MMIO access.
1896 *
1da177e4
LT		 1897 * Returns 0 on success, or %EBUSY on error. A warning
1898 * message is also printed on failure.
1899 */
e8de1481
AV		 1900static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1901 int exclusive)
1da177e4 1902{
9ac7849e
TH		 1903 struct pci_devres *dr;
1904
1da177e4
LT		 1905 if (pci_resource_len(pdev, bar) == 0)
1906 return 0;
1907
1908 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1909 if (!request_region(pci_resource_start(pdev, bar),
1910 pci_resource_len(pdev, bar), res_name))
1911 goto err_out;
1912 }
1913 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
e8de1481
AV		 1914 if (!__request_mem_region(pci_resource_start(pdev, bar),
1915 pci_resource_len(pdev, bar), res_name,
1916 exclusive))
1da177e4
LT		 1917 goto err_out;
1918 }
9ac7849e
TH		 1919
1920 dr = find_pci_dr(pdev);
1921 if (dr)
1922 dr->region_mask |= 1 << bar;
1923
1da177e4
LT		 1924 return 0;
1925
1926err_out:
c7dabef8 1927 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
096e6f67 1928 &pdev->resource[bar]);
1da177e4
LT		 1929 return -EBUSY;
1930}
1931
e8de1481 1932/**
f5ddcac4 1933 * pci_request_region - Reserve PCI I/O and memory resource
e8de1481
AV		 1934 * @pdev: PCI device whose resources are to be reserved
1935 * @bar: BAR to be reserved
f5ddcac4 1936 * @res_name: Name to be associated with resource
e8de1481 1937 *
f5ddcac4 1938 * Mark the PCI region associated with PCI device @pdev BAR @bar as
e8de1481
AV		 1939 * being reserved by owner @res_name. Do not access any
1940 * address inside the PCI regions unless this call returns
1941 * successfully.
1942 *
1943 * Returns 0 on success, or %EBUSY on error. A warning
1944 * message is also printed on failure.
1945 */
1946int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1947{
1948 return __pci_request_region(pdev, bar, res_name, 0);
1949}
1950
1951/**
1952 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1953 * @pdev: PCI device whose resources are to be reserved
1954 * @bar: BAR to be reserved
1955 * @res_name: Name to be associated with resource.
1956 *
1957 * Mark the PCI region associated with PCI device @pdev BR @bar as
1958 * being reserved by owner @res_name. Do not access any
1959 * address inside the PCI regions unless this call returns
1960 * successfully.
1961 *
1962 * Returns 0 on success, or %EBUSY on error. A warning
1963 * message is also printed on failure.
1964 *
1965 * The key difference that _exclusive makes it that userspace is
1966 * explicitly not allowed to map the resource via /dev/mem or
1967 * sysfs.
1968 */
1969int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1970{
1971 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1972}
c87deff7
HS		 1973/**
1974 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1975 * @pdev: PCI device whose resources were previously reserved
1976 * @bars: Bitmask of BARs to be released
1977 *
1978 * Release selected PCI I/O and memory resources previously reserved.
1979 * Call this function only after all use of the PCI regions has ceased.
1980 */
1981void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1982{
1983 int i;
1984
1985 for (i = 0; i < 6; i++)
1986 if (bars & (1 << i))
1987 pci_release_region(pdev, i);
1988}
1989
e8de1481
AV		 1990int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1991 const char *res_name, int excl)
c87deff7
HS		 1992{
1993 int i;
1994
1995 for (i = 0; i < 6; i++)
1996 if (bars & (1 << i))
e8de1481 1997 if (__pci_request_region(pdev, i, res_name, excl))
c87deff7
HS		 1998 goto err_out;
1999 return 0;
2000
2001err_out:
2002 while(--i >= 0)
2003 if (bars & (1 << i))
2004 pci_release_region(pdev, i);
2005
2006 return -EBUSY;
2007}
1da177e4 2008
e8de1481
AV		 2009
2010/**
2011 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2012 * @pdev: PCI device whose resources are to be reserved
2013 * @bars: Bitmask of BARs to be requested
2014 * @res_name: Name to be associated with resource
2015 */
2016int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2017 const char *res_name)
2018{
2019 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2020}
2021
2022int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2023 int bars, const char *res_name)
2024{
2025 return __pci_request_selected_regions(pdev, bars, res_name,
2026 IORESOURCE_EXCLUSIVE);
2027}
2028
1da177e4
LT		 2029/**
2030 * pci_release_regions - Release reserved PCI I/O and memory resources
2031 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2032 *
2033 * Releases all PCI I/O and memory resources previously reserved by a
2034 * successful call to pci_request_regions. Call this function only
2035 * after all use of the PCI regions has ceased.
2036 */
2037
2038void pci_release_regions(struct pci_dev *pdev)
2039{
c87deff7 2040 pci_release_selected_regions(pdev, (1 << 6) - 1);
1da177e4
LT		 2041}
2042
2043/**
2044 * pci_request_regions - Reserved PCI I/O and memory resources
2045 * @pdev: PCI device whose resources are to be reserved
2046 * @res_name: Name to be associated with resource.
2047 *
2048 * Mark all PCI regions associated with PCI device @pdev as
2049 * being reserved by owner @res_name. Do not access any
2050 * address inside the PCI regions unless this call returns
2051 * successfully.
2052 *
2053 * Returns 0 on success, or %EBUSY on error. A warning
2054 * message is also printed on failure.
2055 */
3c990e92 2056int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1da177e4 2057{
c87deff7 2058 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1da177e4
LT		 2059}
2060
e8de1481
AV		 2061/**
2062 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2063 * @pdev: PCI device whose resources are to be reserved
2064 * @res_name: Name to be associated with resource.
2065 *
2066 * Mark all PCI regions associated with PCI device @pdev as
2067 * being reserved by owner @res_name. Do not access any
2068 * address inside the PCI regions unless this call returns
2069 * successfully.
2070 *
2071 * pci_request_regions_exclusive() will mark the region so that
2072 * /dev/mem and the sysfs MMIO access will not be allowed.
2073 *
2074 * Returns 0 on success, or %EBUSY on error. A warning
2075 * message is also printed on failure.
2076 */
2077int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2078{
2079 return pci_request_selected_regions_exclusive(pdev,
2080 ((1 << 6) - 1), res_name);
2081}
2082
6a479079
BH		 2083static void __pci_set_master(struct pci_dev *dev, bool enable)
2084{
2085 u16 old_cmd, cmd;
2086
2087 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2088 if (enable)
2089 cmd = old_cmd | PCI_COMMAND_MASTER;
2090 else
2091 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2092 if (cmd != old_cmd) {
2093 dev_dbg(&dev->dev, "%s bus mastering\n",
2094 enable ? "enabling" : "disabling");
2095 pci_write_config_word(dev, PCI_COMMAND, cmd);
2096 }
2097 dev->is_busmaster = enable;
2098}
e8de1481 2099
1da177e4
LT		 2100/**
2101 * pci_set_master - enables bus-mastering for device dev
2102 * @dev: the PCI device to enable
2103 *
2104 * Enables bus-mastering on the device and calls pcibios_set_master()
2105 * to do the needed arch specific settings.
2106 */
6a479079 2107void pci_set_master(struct pci_dev *dev)
1da177e4 2108{
6a479079 2109 __pci_set_master(dev, true);
1da177e4
LT		 2110 pcibios_set_master(dev);
2111}
2112
6a479079
BH		 2113/**
2114 * pci_clear_master - disables bus-mastering for device dev
2115 * @dev: the PCI device to disable
2116 */
2117void pci_clear_master(struct pci_dev *dev)
2118{
2119 __pci_set_master(dev, false);
2120}
2121
1da177e4 2122/**
edb2d97e
MW		 2123 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2124 * @dev: the PCI device for which MWI is to be enabled
1da177e4 2125 *
edb2d97e
MW		 2126 * Helper function for pci_set_mwi.
2127 * Originally copied from drivers/net/acenic.c.
1da177e4
LT		 2128 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2129 *
2130 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2131 */
15ea76d4 2132int pci_set_cacheline_size(struct pci_dev *dev)
1da177e4
LT		 2133{
2134 u8 cacheline_size;
2135
2136 if (!pci_cache_line_size)
15ea76d4 2137 return -EINVAL;
1da177e4
LT		 2138
2139 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2140 equal to or multiple of the right value. */
2141 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2142 if (cacheline_size >= pci_cache_line_size &&
2143 (cacheline_size % pci_cache_line_size) == 0)
2144 return 0;
2145
2146 /* Write the correct value. */
2147 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2148 /* Read it back. */
2149 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2150 if (cacheline_size == pci_cache_line_size)
2151 return 0;
2152
80ccba11
BH		 2153 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2154 "supported\n", pci_cache_line_size << 2);
1da177e4
LT		 2155
2156 return -EINVAL;
2157}
15ea76d4
TH		 2158EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2159
2160#ifdef PCI_DISABLE_MWI
2161int pci_set_mwi(struct pci_dev *dev)
2162{
2163 return 0;
2164}
2165
2166int pci_try_set_mwi(struct pci_dev *dev)
2167{
2168 return 0;
2169}
2170
2171void pci_clear_mwi(struct pci_dev *dev)
2172{
2173}
2174
2175#else
1da177e4
LT		 2176
2177/**
2178 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2179 * @dev: the PCI device for which MWI is enabled
2180 *
694625c0 2181 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1da177e4
LT		 2182 *
2183 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2184 */
2185int
2186pci_set_mwi(struct pci_dev *dev)
2187{
2188 int rc;
2189 u16 cmd;
2190
edb2d97e 2191 rc = pci_set_cacheline_size(dev);
1da177e4
LT		 2192 if (rc)
2193 return rc;
2194
2195 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2196 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
80ccba11 2197 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1da177e4
LT		 2198 cmd |= PCI_COMMAND_INVALIDATE;
2199 pci_write_config_word(dev, PCI_COMMAND, cmd);
2200 }
2201
2202 return 0;
2203}
2204
694625c0
RD		 2205/**
2206 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2207 * @dev: the PCI device for which MWI is enabled
2208 *
2209 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2210 * Callers are not required to check the return value.
2211 *
2212 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2213 */
2214int pci_try_set_mwi(struct pci_dev *dev)
2215{
2216 int rc = pci_set_mwi(dev);
2217 return rc;
2218}
2219
1da177e4
LT		 2220/**
2221 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2222 * @dev: the PCI device to disable
2223 *
2224 * Disables PCI Memory-Write-Invalidate transaction on the device
2225 */
2226void
2227pci_clear_mwi(struct pci_dev *dev)
2228{
2229 u16 cmd;
2230
2231 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2232 if (cmd & PCI_COMMAND_INVALIDATE) {
2233 cmd &= ~PCI_COMMAND_INVALIDATE;
2234 pci_write_config_word(dev, PCI_COMMAND, cmd);
2235 }
2236}
edb2d97e 2237#endif /* ! PCI_DISABLE_MWI */
1da177e4 2238
a04ce0ff
BR		 2239/**
2240 * pci_intx - enables/disables PCI INTx for device dev
8f7020d3
RD		 2241 * @pdev: the PCI device to operate on
2242 * @enable: boolean: whether to enable or disable PCI INTx
a04ce0ff
BR		 2243 *
2244 * Enables/disables PCI INTx for device dev
2245 */
2246void
2247pci_intx(struct pci_dev *pdev, int enable)
2248{
2249 u16 pci_command, new;
2250
2251 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2252
2253 if (enable) {
2254 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2255 } else {
2256 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2257 }
2258
2259 if (new != pci_command) {
9ac7849e
TH		 2260 struct pci_devres *dr;
2261
2fd9d74b 2262 pci_write_config_word(pdev, PCI_COMMAND, new);
9ac7849e
TH		 2263
2264 dr = find_pci_dr(pdev);
2265 if (dr && !dr->restore_intx) {
2266 dr->restore_intx = 1;
2267 dr->orig_intx = !enable;
2268 }
a04ce0ff
BR		 2269 }
2270}
2271
f5f2b131
EB		 2272/**
2273 * pci_msi_off - disables any msi or msix capabilities
8d7d86e9 2274 * @dev: the PCI device to operate on
f5f2b131
EB		 2275 *
2276 * If you want to use msi see pci_enable_msi and friends.
2277 * This is a lower level primitive that allows us to disable
2278 * msi operation at the device level.
2279 */
2280void pci_msi_off(struct pci_dev *dev)
2281{
2282 int pos;
2283 u16 control;
2284
2285 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2286 if (pos) {
2287 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2288 control &= ~PCI_MSI_FLAGS_ENABLE;
2289 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2290 }
2291 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2292 if (pos) {
2293 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2294 control &= ~PCI_MSIX_FLAGS_ENABLE;
2295 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2296 }
2297}
2298
1da177e4
LT		 2299#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2300/*
2301 * These can be overridden by arch-specific implementations
2302 */
2303int
2304pci_set_dma_mask(struct pci_dev *dev, u64 mask)
2305{
2306 if (!pci_dma_supported(dev, mask))
2307 return -EIO;
2308
2309 dev->dma_mask = mask;
c6a41576 2310 dev_dbg(&dev->dev, "using %dbit DMA mask\n", fls64(mask));
1da177e4
LT		 2311
2312 return 0;
2313}
2314
1da177e4
LT		 2315int
2316pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
2317{
2318 if (!pci_dma_supported(dev, mask))
2319 return -EIO;
2320
2321 dev->dev.coherent_dma_mask = mask;
c6a41576 2322 dev_dbg(&dev->dev, "using %dbit consistent DMA mask\n", fls64(mask));
1da177e4
LT		 2323
2324 return 0;
2325}
2326#endif
c87deff7 2327
4d57cdfa
FT		 2328#ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2329int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2330{
2331 return dma_set_max_seg_size(&dev->dev, size);
2332}
2333EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2334#endif
2335
59fc67de
FT		 2336#ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2337int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2338{
2339 return dma_set_seg_boundary(&dev->dev, mask);
2340}
2341EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2342#endif
2343
8c1c699f 2344static int pcie_flr(struct pci_dev *dev, int probe)
8dd7f803 2345{
8c1c699f
YZ		 2346 int i;
2347 int pos;
8dd7f803 2348 u32 cap;
04b55c47 2349 u16 status, control;
8dd7f803 2350
06a1cbaf 2351 pos = pci_pcie_cap(dev);
8c1c699f 2352 if (!pos)
8dd7f803 2353 return -ENOTTY;
8c1c699f
YZ		 2354
2355 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
8dd7f803
SY		 2356 if (!(cap & PCI_EXP_DEVCAP_FLR))
2357 return -ENOTTY;
2358
d91cdc74
SY		 2359 if (probe)
2360 return 0;
2361
8dd7f803 2362 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 2363 for (i = 0; i < 4; i++) {
2364 if (i)
2365 msleep((1 << (i - 1)) * 100);
5fe5db05 2366
8c1c699f
YZ		 2367 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2368 if (!(status & PCI_EXP_DEVSTA_TRPND))
2369 goto clear;
2370 }
2371
2372 dev_err(&dev->dev, "transaction is not cleared; "
2373 "proceeding with reset anyway\n");
2374
2375clear:
04b55c47
SR		 2376 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2377 control |= PCI_EXP_DEVCTL_BCR_FLR;
2378 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2379
8c1c699f 2380 msleep(100);
8dd7f803 2381
8dd7f803
SY		 2382 return 0;
2383}
d91cdc74 2384
8c1c699f 2385static int pci_af_flr(struct pci_dev *dev, int probe)
1ca88797 2386{
8c1c699f
YZ		 2387 int i;
2388 int pos;
1ca88797 2389 u8 cap;
8c1c699f 2390 u8 status;
1ca88797 2391
8c1c699f
YZ		 2392 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2393 if (!pos)
1ca88797 2394 return -ENOTTY;
8c1c699f
YZ		 2395
2396 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
1ca88797
SY		 2397 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2398 return -ENOTTY;
2399
2400 if (probe)
2401 return 0;
2402
1ca88797 2403 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 2404 for (i = 0; i < 4; i++) {
2405 if (i)
2406 msleep((1 << (i - 1)) * 100);
2407
2408 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2409 if (!(status & PCI_AF_STATUS_TP))
2410 goto clear;
2411 }
5fe5db05 2412
8c1c699f
YZ		 2413 dev_err(&dev->dev, "transaction is not cleared; "
2414 "proceeding with reset anyway\n");
5fe5db05 2415
8c1c699f
YZ		 2416clear:
2417 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
1ca88797 2418 msleep(100);
8c1c699f 2419
1ca88797
SY		 2420 return 0;
2421}
2422
f85876ba 2423static int pci_pm_reset(struct pci_dev *dev, int probe)
d91cdc74 2424{
f85876ba
YZ		 2425 u16 csr;
2426
2427 if (!dev->pm_cap)
2428 return -ENOTTY;
d91cdc74 2429
f85876ba
YZ		 2430 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2431 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2432 return -ENOTTY;
d91cdc74 2433
f85876ba
YZ		 2434 if (probe)
2435 return 0;
1ca88797 2436
f85876ba
YZ		 2437 if (dev->current_state != PCI_D0)
2438 return -EINVAL;
2439
2440 csr &= ~PCI_PM_CTRL_STATE_MASK;
2441 csr |= PCI_D3hot;
2442 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 2443 pci_dev_d3_sleep(dev);
f85876ba
YZ		 2444
2445 csr &= ~PCI_PM_CTRL_STATE_MASK;
2446 csr |= PCI_D0;
2447 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 2448 pci_dev_d3_sleep(dev);
f85876ba
YZ		 2449
2450 return 0;
2451}
2452
c12ff1df
YZ		 2453static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2454{
2455 u16 ctrl;
2456 struct pci_dev *pdev;
2457
654b75e0 2458 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
c12ff1df
YZ		 2459 return -ENOTTY;
2460
2461 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2462 if (pdev != dev)
2463 return -ENOTTY;
2464
2465 if (probe)
2466 return 0;
2467
2468 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2469 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2470 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2471 msleep(100);
2472
2473 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2474 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2475 msleep(100);
2476
2477 return 0;
2478}
2479
8c1c699f 2480static int pci_dev_reset(struct pci_dev *dev, int probe)
d91cdc74 2481{
8c1c699f
YZ		 2482 int rc;
2483
2484 might_sleep();
2485
2486 if (!probe) {
2487 pci_block_user_cfg_access(dev);
2488 /* block PM suspend, driver probe, etc. */
8e9394ce 2489 device_lock(&dev->dev);
8c1c699f 2490 }
d91cdc74 2491
b9c3b266
DC		 2492 rc = pci_dev_specific_reset(dev, probe);
2493 if (rc != -ENOTTY)
2494 goto done;
2495
8c1c699f
YZ		 2496 rc = pcie_flr(dev, probe);
2497 if (rc != -ENOTTY)
2498 goto done;
d91cdc74 2499
8c1c699f 2500 rc = pci_af_flr(dev, probe);
f85876ba
YZ		 2501 if (rc != -ENOTTY)
2502 goto done;
2503
2504 rc = pci_pm_reset(dev, probe);
c12ff1df
YZ		 2505 if (rc != -ENOTTY)
2506 goto done;
2507
2508 rc = pci_parent_bus_reset(dev, probe);
8c1c699f
YZ		 2509done:
2510 if (!probe) {
8e9394ce 2511 device_unlock(&dev->dev);
8c1c699f
YZ		 2512 pci_unblock_user_cfg_access(dev);
2513 }
1ca88797 2514
8c1c699f 2515 return rc;
d91cdc74
SY		 2516}
2517
2518/**
8c1c699f
YZ		 2519 * __pci_reset_function - reset a PCI device function
2520 * @dev: PCI device to reset
d91cdc74
SY		 2521 *
2522 * Some devices allow an individual function to be reset without affecting
2523 * other functions in the same device. The PCI device must be responsive
2524 * to PCI config space in order to use this function.
2525 *
2526 * The device function is presumed to be unused when this function is called.
2527 * Resetting the device will make the contents of PCI configuration space
2528 * random, so any caller of this must be prepared to reinitialise the
2529 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2530 * etc.
2531 *
8c1c699f 2532 * Returns 0 if the device function was successfully reset or negative if the
d91cdc74
SY		 2533 * device doesn't support resetting a single function.
2534 */
8c1c699f 2535int __pci_reset_function(struct pci_dev *dev)
d91cdc74 2536{
8c1c699f 2537 return pci_dev_reset(dev, 0);
d91cdc74 2538}
8c1c699f 2539EXPORT_SYMBOL_GPL(__pci_reset_function);
8dd7f803 2540
711d5779
MT		 2541/**
2542 * pci_probe_reset_function - check whether the device can be safely reset
2543 * @dev: PCI device to reset
2544 *
2545 * Some devices allow an individual function to be reset without affecting
2546 * other functions in the same device. The PCI device must be responsive
2547 * to PCI config space in order to use this function.
2548 *
2549 * Returns 0 if the device function can be reset or negative if the
2550 * device doesn't support resetting a single function.
2551 */
2552int pci_probe_reset_function(struct pci_dev *dev)
2553{
2554 return pci_dev_reset(dev, 1);
2555}
2556
8dd7f803 2557/**
8c1c699f
YZ		 2558 * pci_reset_function - quiesce and reset a PCI device function
2559 * @dev: PCI device to reset
8dd7f803
SY		 2560 *
2561 * Some devices allow an individual function to be reset without affecting
2562 * other functions in the same device. The PCI device must be responsive
2563 * to PCI config space in order to use this function.
2564 *
2565 * This function does not just reset the PCI portion of a device, but
2566 * clears all the state associated with the device. This function differs
8c1c699f 2567 * from __pci_reset_function in that it saves and restores device state
8dd7f803
SY		 2568 * over the reset.
2569 *
8c1c699f 2570 * Returns 0 if the device function was successfully reset or negative if the
8dd7f803
SY		 2571 * device doesn't support resetting a single function.
2572 */
2573int pci_reset_function(struct pci_dev *dev)
2574{
8c1c699f 2575 int rc;
8dd7f803 2576
8c1c699f
YZ		 2577 rc = pci_dev_reset(dev, 1);
2578 if (rc)
2579 return rc;
8dd7f803 2580
8dd7f803
SY		 2581 pci_save_state(dev);
2582
8c1c699f
YZ		 2583 /*
2584 * both INTx and MSI are disabled after the Interrupt Disable bit
2585 * is set and the Bus Master bit is cleared.
2586 */
8dd7f803
SY		 2587 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2588
8c1c699f 2589 rc = pci_dev_reset(dev, 0);
8dd7f803
SY		 2590
2591 pci_restore_state(dev);
8dd7f803 2592
8c1c699f 2593 return rc;
8dd7f803
SY		 2594}
2595EXPORT_SYMBOL_GPL(pci_reset_function);
2596
d556ad4b
PO		 2597/**
2598 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2599 * @dev: PCI device to query
2600 *
2601 * Returns mmrbc: maximum designed memory read count in bytes
2602 * or appropriate error value.
2603 */
2604int pcix_get_max_mmrbc(struct pci_dev *dev)
2605{
b7b095c1 2606 int err, cap;
d556ad4b
PO		 2607 u32 stat;
2608
2609 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2610 if (!cap)
2611 return -EINVAL;
2612
2613 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2614 if (err)
2615 return -EINVAL;
2616
b7b095c1 2617 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
d556ad4b
PO		 2618}
2619EXPORT_SYMBOL(pcix_get_max_mmrbc);
2620
2621/**
2622 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2623 * @dev: PCI device to query
2624 *
2625 * Returns mmrbc: maximum memory read count in bytes
2626 * or appropriate error value.
2627 */
2628int pcix_get_mmrbc(struct pci_dev *dev)
2629{
2630 int ret, cap;
2631 u32 cmd;
2632
2633 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2634 if (!cap)
2635 return -EINVAL;
2636
2637 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2638 if (!ret)
2639 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2640
2641 return ret;
2642}
2643EXPORT_SYMBOL(pcix_get_mmrbc);
2644
2645/**
2646 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2647 * @dev: PCI device to query
2648 * @mmrbc: maximum memory read count in bytes
2649 * valid values are 512, 1024, 2048, 4096
2650 *
2651 * If possible sets maximum memory read byte count, some bridges have erratas
2652 * that prevent this.
2653 */
2654int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2655{
2656 int cap, err = -EINVAL;
2657 u32 stat, cmd, v, o;
2658
229f5afd 2659 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
d556ad4b
PO		 2660 goto out;
2661
2662 v = ffs(mmrbc) - 10;
2663
2664 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2665 if (!cap)
2666 goto out;
2667
2668 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2669 if (err)
2670 goto out;
2671
2672 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2673 return -E2BIG;
2674
2675 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2676 if (err)
2677 goto out;
2678
2679 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2680 if (o != v) {
2681 if (v > o && dev->bus &&
2682 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2683 return -EIO;
2684
2685 cmd &= ~PCI_X_CMD_MAX_READ;
2686 cmd |= v << 2;
2687 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
2688 }
2689out:
2690 return err;
2691}
2692EXPORT_SYMBOL(pcix_set_mmrbc);
2693
2694/**
2695 * pcie_get_readrq - get PCI Express read request size
2696 * @dev: PCI device to query
2697 *
2698 * Returns maximum memory read request in bytes
2699 * or appropriate error value.
2700 */
2701int pcie_get_readrq(struct pci_dev *dev)
2702{
2703 int ret, cap;
2704 u16 ctl;
2705
06a1cbaf 2706 cap = pci_pcie_cap(dev);
d556ad4b
PO		 2707 if (!cap)
2708 return -EINVAL;
2709
2710 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2711 if (!ret)
2712 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2713
2714 return ret;
2715}
2716EXPORT_SYMBOL(pcie_get_readrq);
2717
2718/**
2719 * pcie_set_readrq - set PCI Express maximum memory read request
2720 * @dev: PCI device to query
42e61f4a 2721 * @rq: maximum memory read count in bytes
d556ad4b
PO		 2722 * valid values are 128, 256, 512, 1024, 2048, 4096
2723 *
2724 * If possible sets maximum read byte count
2725 */
2726int pcie_set_readrq(struct pci_dev *dev, int rq)
2727{
2728 int cap, err = -EINVAL;
2729 u16 ctl, v;
2730
229f5afd 2731 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
d556ad4b
PO		 2732 goto out;
2733
2734 v = (ffs(rq) - 8) << 12;
2735
06a1cbaf 2736 cap = pci_pcie_cap(dev);
d556ad4b
PO		 2737 if (!cap)
2738 goto out;
2739
2740 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2741 if (err)
2742 goto out;
2743
2744 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2745 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2746 ctl |= v;
2747 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2748 }
2749
2750out:
2751 return err;
2752}
2753EXPORT_SYMBOL(pcie_set_readrq);
2754
c87deff7
HS		 2755/**
2756 * pci_select_bars - Make BAR mask from the type of resource
f95d882d 2757 * @dev: the PCI device for which BAR mask is made
c87deff7
HS		 2758 * @flags: resource type mask to be selected
2759 *
2760 * This helper routine makes bar mask from the type of resource.
2761 */
2762int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2763{
2764 int i, bars = 0;
2765 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2766 if (pci_resource_flags(dev, i) & flags)
2767 bars |= (1 << i);
2768 return bars;
2769}
2770
613e7ed6
YZ		 2771/**
2772 * pci_resource_bar - get position of the BAR associated with a resource
2773 * @dev: the PCI device
2774 * @resno: the resource number
2775 * @type: the BAR type to be filled in
2776 *
2777 * Returns BAR position in config space, or 0 if the BAR is invalid.
2778 */
2779int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2780{
d1b054da
YZ		 2781 int reg;
2782
613e7ed6
YZ		 2783 if (resno < PCI_ROM_RESOURCE) {
2784 *type = pci_bar_unknown;
2785 return PCI_BASE_ADDRESS_0 + 4 * resno;
2786 } else if (resno == PCI_ROM_RESOURCE) {
2787 *type = pci_bar_mem32;
2788 return dev->rom_base_reg;
d1b054da
YZ		 2789 } else if (resno < PCI_BRIDGE_RESOURCES) {
2790 /* device specific resource */
2791 reg = pci_iov_resource_bar(dev, resno, type);
2792 if (reg)
2793 return reg;
613e7ed6
YZ		 2794 }
2795
865df576 2796 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
613e7ed6
YZ		 2797 return 0;
2798}
2799
95a8b6ef
MT		 2800/* Some architectures require additional programming to enable VGA */
2801static arch_set_vga_state_t arch_set_vga_state;
2802
2803void __init pci_register_set_vga_state(arch_set_vga_state_t func)
2804{
2805 arch_set_vga_state = func; /* NULL disables */
2806}
2807
2808static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
2809 unsigned int command_bits, bool change_bridge)
2810{
2811 if (arch_set_vga_state)
2812 return arch_set_vga_state(dev, decode, command_bits,
2813 change_bridge);
2814 return 0;
2815}
2816
deb2d2ec
BH		 2817/**
2818 * pci_set_vga_state - set VGA decode state on device and parents if requested
19eea630
RD		 2819 * @dev: the PCI device
2820 * @decode: true = enable decoding, false = disable decoding
2821 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2822 * @change_bridge: traverse ancestors and change bridges
deb2d2ec
BH		 2823 */
2824int pci_set_vga_state(struct pci_dev *dev, bool decode,
2825 unsigned int command_bits, bool change_bridge)
2826{
2827 struct pci_bus *bus;
2828 struct pci_dev *bridge;
2829 u16 cmd;
95a8b6ef 2830 int rc;
deb2d2ec
BH		 2831
2832 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2833
95a8b6ef
MT		 2834 /* ARCH specific VGA enables */
2835 rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
2836 if (rc)
2837 return rc;
2838
deb2d2ec
BH		 2839 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2840 if (decode == true)
2841 cmd |= command_bits;
2842 else
2843 cmd &= ~command_bits;
2844 pci_write_config_word(dev, PCI_COMMAND, cmd);
2845
2846 if (change_bridge == false)
2847 return 0;
2848
2849 bus = dev->bus;
2850 while (bus) {
2851 bridge = bus->self;
2852 if (bridge) {
2853 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2854 &cmd);
2855 if (decode == true)
2856 cmd |= PCI_BRIDGE_CTL_VGA;
2857 else
2858 cmd &= ~PCI_BRIDGE_CTL_VGA;
2859 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2860 cmd);
2861 }
2862 bus = bus->parent;
2863 }
2864 return 0;
2865}
2866
32a9a682
YS		 2867#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2868static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
e9d1e492 2869static DEFINE_SPINLOCK(resource_alignment_lock);
32a9a682
YS		 2870
2871/**
2872 * pci_specified_resource_alignment - get resource alignment specified by user.
2873 * @dev: the PCI device to get
2874 *
2875 * RETURNS: Resource alignment if it is specified.
2876 * Zero if it is not specified.
2877 */
2878resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2879{
2880 int seg, bus, slot, func, align_order, count;
2881 resource_size_t align = 0;
2882 char *p;
2883
2884 spin_lock(&resource_alignment_lock);
2885 p = resource_alignment_param;
2886 while (*p) {
2887 count = 0;
2888 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2889 p[count] == '@') {
2890 p += count + 1;
2891 } else {
2892 align_order = -1;
2893 }
2894 if (sscanf(p, "%x:%x:%x.%x%n",
2895 &seg, &bus, &slot, &func, &count) != 4) {
2896 seg = 0;
2897 if (sscanf(p, "%x:%x.%x%n",
2898 &bus, &slot, &func, &count) != 3) {
2899 /* Invalid format */
2900 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2901 p);
2902 break;
2903 }
2904 }
2905 p += count;
2906 if (seg == pci_domain_nr(dev->bus) &&
2907 bus == dev->bus->number &&
2908 slot == PCI_SLOT(dev->devfn) &&
2909 func == PCI_FUNC(dev->devfn)) {
2910 if (align_order == -1) {
2911 align = PAGE_SIZE;
2912 } else {
2913 align = 1 << align_order;
2914 }
2915 /* Found */
2916 break;
2917 }
2918 if (*p != ';' && *p != ',') {
2919 /* End of param or invalid format */
2920 break;
2921 }
2922 p++;
2923 }
2924 spin_unlock(&resource_alignment_lock);
2925 return align;
2926}
2927
2928/**
2929 * pci_is_reassigndev - check if specified PCI is target device to reassign
2930 * @dev: the PCI device to check
2931 *
2932 * RETURNS: non-zero for PCI device is a target device to reassign,
2933 * or zero is not.
2934 */
2935int pci_is_reassigndev(struct pci_dev *dev)
2936{
2937 return (pci_specified_resource_alignment(dev) != 0);
2938}
2939
2940ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2941{
2942 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2943 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2944 spin_lock(&resource_alignment_lock);
2945 strncpy(resource_alignment_param, buf, count);
2946 resource_alignment_param[count] = '\0';
2947 spin_unlock(&resource_alignment_lock);
2948 return count;
2949}
2950
2951ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2952{
2953 size_t count;
2954 spin_lock(&resource_alignment_lock);
2955 count = snprintf(buf, size, "%s", resource_alignment_param);
2956 spin_unlock(&resource_alignment_lock);
2957 return count;
2958}
2959
2960static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2961{
2962 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2963}
2964
2965static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2966 const char *buf, size_t count)
2967{
2968 return pci_set_resource_alignment_param(buf, count);
2969}
2970
2971BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2972 pci_resource_alignment_store);
2973
2974static int __init pci_resource_alignment_sysfs_init(void)
2975{
2976 return bus_create_file(&pci_bus_type,
2977 &bus_attr_resource_alignment);
2978}
2979
2980late_initcall(pci_resource_alignment_sysfs_init);
2981
32a2eea7
JG		 2982static void __devinit pci_no_domains(void)
2983{
2984#ifdef CONFIG_PCI_DOMAINS
2985 pci_domains_supported = 0;
2986#endif
2987}
2988
0ef5f8f6
AP		 2989/**
2990 * pci_ext_cfg_enabled - can we access extended PCI config space?
2991 * @dev: The PCI device of the root bridge.
2992 *
2993 * Returns 1 if we can access PCI extended config space (offsets
2994 * greater than 0xff). This is the default implementation. Architecture
2995 * implementations can override this.
2996 */
2997int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2998{
2999 return 1;
3000}
3001
2d1c8618
BH		 3002void __weak pci_fixup_cardbus(struct pci_bus *bus)
3003{
3004}
3005EXPORT_SYMBOL(pci_fixup_cardbus);
3006
ad04d31e 3007static int __init pci_setup(char *str)
1da177e4
LT		 3008{
3009 while (str) {
3010 char *k = strchr(str, ',');
3011 if (k)
3012 *k++ = 0;
3013 if (*str && (str = pcibios_setup(str)) && *str) {
309e57df
MW		 3014 if (!strcmp(str, "nomsi")) {
3015 pci_no_msi();
7f785763
RD		 3016 } else if (!strcmp(str, "noaer")) {
3017 pci_no_aer();
32a2eea7
JG		 3018 } else if (!strcmp(str, "nodomains")) {
3019 pci_no_domains();
4516a618
AN		 3020 } else if (!strncmp(str, "cbiosize=", 9)) {
3021 pci_cardbus_io_size = memparse(str + 9, &str);
3022 } else if (!strncmp(str, "cbmemsize=", 10)) {
3023 pci_cardbus_mem_size = memparse(str + 10, &str);
32a9a682
YS		 3024 } else if (!strncmp(str, "resource_alignment=", 19)) {
3025 pci_set_resource_alignment_param(str + 19,
3026 strlen(str + 19));
43c16408
AP		 3027 } else if (!strncmp(str, "ecrc=", 5)) {
3028 pcie_ecrc_get_policy(str + 5);
28760489
EB		 3029 } else if (!strncmp(str, "hpiosize=", 9)) {
3030 pci_hotplug_io_size = memparse(str + 9, &str);
3031 } else if (!strncmp(str, "hpmemsize=", 10)) {
3032 pci_hotplug_mem_size = memparse(str + 10, &str);
309e57df
MW		 3033 } else {
3034 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3035 str);
3036 }
1da177e4
LT		 3037 }
3038 str = k;
3039 }
0637a70a 3040 return 0;
1da177e4 3041}
0637a70a 3042early_param("pci", pci_setup);
1da177e4 3043
0b62e13b 3044EXPORT_SYMBOL(pci_reenable_device);
b718989d
BH		 3045EXPORT_SYMBOL(pci_enable_device_io);
3046EXPORT_SYMBOL(pci_enable_device_mem);
1da177e4 3047EXPORT_SYMBOL(pci_enable_device);
9ac7849e
TH		 3048EXPORT_SYMBOL(pcim_enable_device);
3049EXPORT_SYMBOL(pcim_pin_device);
1da177e4 3050EXPORT_SYMBOL(pci_disable_device);
1da177e4
LT		 3051EXPORT_SYMBOL(pci_find_capability);
3052EXPORT_SYMBOL(pci_bus_find_capability);
95a8b6ef 3053EXPORT_SYMBOL(pci_register_set_vga_state);
1da177e4
LT		 3054EXPORT_SYMBOL(pci_release_regions);
3055EXPORT_SYMBOL(pci_request_regions);
e8de1481 3056EXPORT_SYMBOL(pci_request_regions_exclusive);
1da177e4
LT		 3057EXPORT_SYMBOL(pci_release_region);
3058EXPORT_SYMBOL(pci_request_region);
e8de1481 3059EXPORT_SYMBOL(pci_request_region_exclusive);
c87deff7
HS		 3060EXPORT_SYMBOL(pci_release_selected_regions);
3061EXPORT_SYMBOL(pci_request_selected_regions);
e8de1481 3062EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
1da177e4 3063EXPORT_SYMBOL(pci_set_master);
6a479079 3064EXPORT_SYMBOL(pci_clear_master);
1da177e4 3065EXPORT_SYMBOL(pci_set_mwi);
694625c0 3066EXPORT_SYMBOL(pci_try_set_mwi);
1da177e4 3067EXPORT_SYMBOL(pci_clear_mwi);
a04ce0ff 3068EXPORT_SYMBOL_GPL(pci_intx);
1da177e4 3069EXPORT_SYMBOL(pci_set_dma_mask);
1da177e4
LT		 3070EXPORT_SYMBOL(pci_set_consistent_dma_mask);
3071EXPORT_SYMBOL(pci_assign_resource);
3072EXPORT_SYMBOL(pci_find_parent_resource);
c87deff7 3073EXPORT_SYMBOL(pci_select_bars);
1da177e4
LT		 3074
3075EXPORT_SYMBOL(pci_set_power_state);
3076EXPORT_SYMBOL(pci_save_state);
3077EXPORT_SYMBOL(pci_restore_state);
e5899e1b 3078EXPORT_SYMBOL(pci_pme_capable);
5a6c9b60 3079EXPORT_SYMBOL(pci_pme_active);
0235c4fc 3080EXPORT_SYMBOL(pci_wake_from_d3);
e5899e1b 3081EXPORT_SYMBOL(pci_target_state);
404cc2d8
RW		 3082EXPORT_SYMBOL(pci_prepare_to_sleep);
3083EXPORT_SYMBOL(pci_back_from_sleep);
f7bdd12d 3084EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Linux 6.x block layer and io_uring tree(s)