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1da177e4 LT |
1 | /* |
2 | * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ | |
3 | * | |
4 | * PCI Bus Services, see include/linux/pci.h for further explanation. | |
5 | * | |
6 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
7 | * David Mosberger-Tang | |
8 | * | |
9 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/spinlock.h> | |
4e57b681 | 18 | #include <linux/string.h> |
1da177e4 | 19 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 20 | #include "pci.h" |
1da177e4 | 21 | |
54c762fe | 22 | #if 0 |
1da177e4 LT |
23 | |
24 | /** | |
25 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
26 | * @bus: pointer to PCI bus structure to search | |
27 | * | |
28 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
29 | * including the given PCI bus and its list of child PCI buses. | |
30 | */ | |
31 | unsigned char __devinit | |
32 | pci_bus_max_busnr(struct pci_bus* bus) | |
33 | { | |
34 | struct list_head *tmp; | |
35 | unsigned char max, n; | |
36 | ||
37 | max = bus->number; | |
38 | list_for_each(tmp, &bus->children) { | |
39 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
40 | if(n > max) | |
41 | max = n; | |
42 | } | |
43 | return max; | |
44 | } | |
45 | ||
46 | /** | |
47 | * pci_max_busnr - returns maximum PCI bus number | |
48 | * | |
49 | * Returns the highest PCI bus number present in the system global list of | |
50 | * PCI buses. | |
51 | */ | |
52 | unsigned char __devinit | |
53 | pci_max_busnr(void) | |
54 | { | |
55 | struct pci_bus *bus = NULL; | |
56 | unsigned char max, n; | |
57 | ||
58 | max = 0; | |
59 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
60 | n = pci_bus_max_busnr(bus); | |
61 | if(n > max) | |
62 | max = n; | |
63 | } | |
64 | return max; | |
65 | } | |
66 | ||
54c762fe AB |
67 | #endif /* 0 */ |
68 | ||
24a4e377 RD |
69 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap) |
70 | { | |
71 | u8 id; | |
72 | int ttl = 48; | |
73 | ||
74 | while (ttl--) { | |
75 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
76 | if (pos < 0x40) | |
77 | break; | |
78 | pos &= ~3; | |
79 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
80 | &id); | |
81 | if (id == 0xff) | |
82 | break; | |
83 | if (id == cap) | |
84 | return pos; | |
85 | pos += PCI_CAP_LIST_NEXT; | |
86 | } | |
87 | return 0; | |
88 | } | |
89 | ||
90 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) | |
91 | { | |
92 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
93 | pos + PCI_CAP_LIST_NEXT, cap); | |
94 | } | |
95 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
96 | ||
1da177e4 LT |
97 | static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap) |
98 | { | |
99 | u16 status; | |
24a4e377 | 100 | u8 pos; |
1da177e4 LT |
101 | |
102 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
103 | if (!(status & PCI_STATUS_CAP_LIST)) | |
104 | return 0; | |
105 | ||
106 | switch (hdr_type) { | |
107 | case PCI_HEADER_TYPE_NORMAL: | |
108 | case PCI_HEADER_TYPE_BRIDGE: | |
24a4e377 | 109 | pos = PCI_CAPABILITY_LIST; |
1da177e4 LT |
110 | break; |
111 | case PCI_HEADER_TYPE_CARDBUS: | |
24a4e377 | 112 | pos = PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
113 | break; |
114 | default: | |
115 | return 0; | |
116 | } | |
24a4e377 | 117 | return __pci_find_next_cap(bus, devfn, pos, cap); |
1da177e4 LT |
118 | } |
119 | ||
120 | /** | |
121 | * pci_find_capability - query for devices' capabilities | |
122 | * @dev: PCI device to query | |
123 | * @cap: capability code | |
124 | * | |
125 | * Tell if a device supports a given PCI capability. | |
126 | * Returns the address of the requested capability structure within the | |
127 | * device's PCI configuration space or 0 in case the device does not | |
128 | * support it. Possible values for @cap: | |
129 | * | |
130 | * %PCI_CAP_ID_PM Power Management | |
131 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
132 | * %PCI_CAP_ID_VPD Vital Product Data | |
133 | * %PCI_CAP_ID_SLOTID Slot Identification | |
134 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
135 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
136 | * %PCI_CAP_ID_PCIX PCI-X | |
137 | * %PCI_CAP_ID_EXP PCI Express | |
138 | */ | |
139 | int pci_find_capability(struct pci_dev *dev, int cap) | |
140 | { | |
141 | return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap); | |
142 | } | |
143 | ||
144 | /** | |
145 | * pci_bus_find_capability - query for devices' capabilities | |
146 | * @bus: the PCI bus to query | |
147 | * @devfn: PCI device to query | |
148 | * @cap: capability code | |
149 | * | |
150 | * Like pci_find_capability() but works for pci devices that do not have a | |
151 | * pci_dev structure set up yet. | |
152 | * | |
153 | * Returns the address of the requested capability structure within the | |
154 | * device's PCI configuration space or 0 in case the device does not | |
155 | * support it. | |
156 | */ | |
157 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
158 | { | |
159 | u8 hdr_type; | |
160 | ||
161 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
162 | ||
163 | return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap); | |
164 | } | |
165 | ||
166 | /** | |
167 | * pci_find_ext_capability - Find an extended capability | |
168 | * @dev: PCI device to query | |
169 | * @cap: capability code | |
170 | * | |
171 | * Returns the address of the requested extended capability structure | |
172 | * within the device's PCI configuration space or 0 if the device does | |
173 | * not support it. Possible values for @cap: | |
174 | * | |
175 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
176 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
177 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
178 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
179 | */ | |
180 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
181 | { | |
182 | u32 header; | |
183 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
184 | int pos = 0x100; | |
185 | ||
186 | if (dev->cfg_size <= 256) | |
187 | return 0; | |
188 | ||
189 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
190 | return 0; | |
191 | ||
192 | /* | |
193 | * If we have no capabilities, this is indicated by cap ID, | |
194 | * cap version and next pointer all being 0. | |
195 | */ | |
196 | if (header == 0) | |
197 | return 0; | |
198 | ||
199 | while (ttl-- > 0) { | |
200 | if (PCI_EXT_CAP_ID(header) == cap) | |
201 | return pos; | |
202 | ||
203 | pos = PCI_EXT_CAP_NEXT(header); | |
204 | if (pos < 0x100) | |
205 | break; | |
206 | ||
207 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
208 | break; | |
209 | } | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | /** | |
215 | * pci_find_parent_resource - return resource region of parent bus of given region | |
216 | * @dev: PCI device structure contains resources to be searched | |
217 | * @res: child resource record for which parent is sought | |
218 | * | |
219 | * For given resource region of given device, return the resource | |
220 | * region of parent bus the given region is contained in or where | |
221 | * it should be allocated from. | |
222 | */ | |
223 | struct resource * | |
224 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
225 | { | |
226 | const struct pci_bus *bus = dev->bus; | |
227 | int i; | |
228 | struct resource *best = NULL; | |
229 | ||
230 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
231 | struct resource *r = bus->resource[i]; | |
232 | if (!r) | |
233 | continue; | |
234 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
235 | continue; /* Not contained */ | |
236 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
237 | continue; /* Wrong type */ | |
238 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
239 | return r; /* Exact match */ | |
240 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
241 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
242 | } | |
243 | return best; | |
244 | } | |
245 | ||
064b53db JL |
246 | /** |
247 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
248 | * @dev: PCI device to have its BARs restored | |
249 | * | |
250 | * Restore the BAR values for a given device, so as to make it | |
251 | * accessible by its driver. | |
252 | */ | |
253 | void | |
254 | pci_restore_bars(struct pci_dev *dev) | |
255 | { | |
256 | int i, numres; | |
257 | ||
258 | switch (dev->hdr_type) { | |
259 | case PCI_HEADER_TYPE_NORMAL: | |
260 | numres = 6; | |
261 | break; | |
262 | case PCI_HEADER_TYPE_BRIDGE: | |
263 | numres = 2; | |
264 | break; | |
265 | case PCI_HEADER_TYPE_CARDBUS: | |
266 | numres = 1; | |
267 | break; | |
268 | default: | |
269 | /* Should never get here, but just in case... */ | |
270 | return; | |
271 | } | |
272 | ||
273 | for (i = 0; i < numres; i ++) | |
274 | pci_update_resource(dev, &dev->resource[i], i); | |
275 | } | |
276 | ||
8f7020d3 RD |
277 | int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); |
278 | ||
1da177e4 LT |
279 | /** |
280 | * pci_set_power_state - Set the power state of a PCI device | |
281 | * @dev: PCI device to be suspended | |
282 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering | |
283 | * | |
284 | * Transition a device to a new power state, using the Power Management | |
285 | * Capabilities in the device's config space. | |
286 | * | |
287 | * RETURN VALUE: | |
288 | * -EINVAL if trying to enter a lower state than we're already in. | |
289 | * 0 if we're already in the requested state. | |
290 | * -EIO if device does not support PCI PM. | |
291 | * 0 if we can successfully change the power state. | |
292 | */ | |
1da177e4 LT |
293 | int |
294 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
295 | { | |
064b53db | 296 | int pm, need_restore = 0; |
1da177e4 LT |
297 | u16 pmcsr, pmc; |
298 | ||
299 | /* bound the state we're entering */ | |
300 | if (state > PCI_D3hot) | |
301 | state = PCI_D3hot; | |
302 | ||
303 | /* Validate current state: | |
304 | * Can enter D0 from any state, but if we can only go deeper | |
305 | * to sleep if we're already in a low power state | |
306 | */ | |
307 | if (state != PCI_D0 && dev->current_state > state) | |
308 | return -EINVAL; | |
309 | else if (dev->current_state == state) | |
310 | return 0; /* we're already there */ | |
311 | ||
312 | /* find PCI PM capability in list */ | |
313 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
314 | ||
315 | /* abort if the device doesn't support PM capabilities */ | |
316 | if (!pm) | |
317 | return -EIO; | |
318 | ||
319 | pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); | |
3fe9d19f | 320 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1da177e4 LT |
321 | printk(KERN_DEBUG |
322 | "PCI: %s has unsupported PM cap regs version (%u)\n", | |
323 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); | |
324 | return -EIO; | |
325 | } | |
326 | ||
327 | /* check if this device supports the desired state */ | |
3fe9d19f DR |
328 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
329 | return -EIO; | |
330 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) | |
331 | return -EIO; | |
1da177e4 | 332 | |
064b53db JL |
333 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
334 | ||
32a36585 | 335 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
336 | * This doesn't affect PME_Status, disables PME_En, and |
337 | * sets PowerState to 0. | |
338 | */ | |
32a36585 | 339 | switch (dev->current_state) { |
d3535fbb JL |
340 | case PCI_D0: |
341 | case PCI_D1: | |
342 | case PCI_D2: | |
343 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
344 | pmcsr |= state; | |
345 | break; | |
32a36585 JL |
346 | case PCI_UNKNOWN: /* Boot-up */ |
347 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
348 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
064b53db | 349 | need_restore = 1; |
32a36585 | 350 | /* Fall-through: force to D0 */ |
32a36585 | 351 | default: |
d3535fbb | 352 | pmcsr = 0; |
32a36585 | 353 | break; |
1da177e4 LT |
354 | } |
355 | ||
356 | /* enter specified state */ | |
357 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
358 | ||
359 | /* Mandatory power management transition delays */ | |
360 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
361 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
362 | msleep(10); | |
363 | else if (state == PCI_D2 || dev->current_state == PCI_D2) | |
364 | udelay(200); | |
1da177e4 | 365 | |
b913100d DSL |
366 | /* |
367 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx | |
368 | * Firmware method after natice method ? | |
369 | */ | |
370 | if (platform_pci_set_power_state) | |
371 | platform_pci_set_power_state(dev, state); | |
372 | ||
373 | dev->current_state = state; | |
064b53db JL |
374 | |
375 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
376 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
377 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
378 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
379 | * For example, at least some versions of the 3c905B and the | |
380 | * 3c556B exhibit this behaviour. | |
381 | * | |
382 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
383 | * devices in a D3hot state at boot. Consequently, we need to | |
384 | * restore at least the BARs so that the device will be | |
385 | * accessible to its driver. | |
386 | */ | |
387 | if (need_restore) | |
388 | pci_restore_bars(dev); | |
389 | ||
1da177e4 LT |
390 | return 0; |
391 | } | |
392 | ||
f165b10f | 393 | int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); |
0f64474b | 394 | |
1da177e4 LT |
395 | /** |
396 | * pci_choose_state - Choose the power state of a PCI device | |
397 | * @dev: PCI device to be suspended | |
398 | * @state: target sleep state for the whole system. This is the value | |
399 | * that is passed to suspend() function. | |
400 | * | |
401 | * Returns PCI power state suitable for given device and given system | |
402 | * message. | |
403 | */ | |
404 | ||
405 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
406 | { | |
0f64474b DSL |
407 | int ret; |
408 | ||
1da177e4 LT |
409 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
410 | return PCI_D0; | |
411 | ||
0f64474b DSL |
412 | if (platform_pci_choose_state) { |
413 | ret = platform_pci_choose_state(dev, state); | |
414 | if (ret >= 0) | |
ca078bae | 415 | state.event = ret; |
0f64474b | 416 | } |
ca078bae PM |
417 | |
418 | switch (state.event) { | |
419 | case PM_EVENT_ON: | |
420 | return PCI_D0; | |
421 | case PM_EVENT_FREEZE: | |
422 | case PM_EVENT_SUSPEND: | |
423 | return PCI_D3hot; | |
1da177e4 | 424 | default: |
ca078bae | 425 | printk("They asked me for state %d\n", state.event); |
1da177e4 LT |
426 | BUG(); |
427 | } | |
428 | return PCI_D0; | |
429 | } | |
430 | ||
431 | EXPORT_SYMBOL(pci_choose_state); | |
432 | ||
433 | /** | |
434 | * pci_save_state - save the PCI configuration space of a device before suspending | |
435 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
436 | */ |
437 | int | |
438 | pci_save_state(struct pci_dev *dev) | |
439 | { | |
440 | int i; | |
441 | /* XXX: 100% dword access ok here? */ | |
442 | for (i = 0; i < 16; i++) | |
443 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
444 | return 0; | |
445 | } | |
446 | ||
447 | /** | |
448 | * pci_restore_state - Restore the saved state of a PCI device | |
449 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
450 | */ |
451 | int | |
452 | pci_restore_state(struct pci_dev *dev) | |
453 | { | |
454 | int i; | |
455 | ||
456 | for (i = 0; i < 16; i++) | |
457 | pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]); | |
458 | return 0; | |
459 | } | |
460 | ||
461 | /** | |
462 | * pci_enable_device_bars - Initialize some of a device for use | |
463 | * @dev: PCI device to be initialized | |
464 | * @bars: bitmask of BAR's that must be configured | |
465 | * | |
466 | * Initialize device before it's used by a driver. Ask low-level code | |
467 | * to enable selected I/O and memory resources. Wake up the device if it | |
468 | * was suspended. Beware, this function can fail. | |
469 | */ | |
470 | ||
471 | int | |
472 | pci_enable_device_bars(struct pci_dev *dev, int bars) | |
473 | { | |
474 | int err; | |
475 | ||
95a62965 | 476 | err = pci_set_power_state(dev, PCI_D0); |
11f3859b | 477 | if (err < 0 && err != -EIO) |
95a62965 GKH |
478 | return err; |
479 | err = pcibios_enable_device(dev, bars); | |
480 | if (err < 0) | |
1da177e4 LT |
481 | return err; |
482 | return 0; | |
483 | } | |
484 | ||
485 | /** | |
486 | * pci_enable_device - Initialize device before it's used by a driver. | |
487 | * @dev: PCI device to be initialized | |
488 | * | |
489 | * Initialize device before it's used by a driver. Ask low-level code | |
490 | * to enable I/O and memory. Wake up the device if it was suspended. | |
491 | * Beware, this function can fail. | |
492 | */ | |
493 | int | |
494 | pci_enable_device(struct pci_dev *dev) | |
495 | { | |
496 | int err; | |
497 | ||
1da177e4 LT |
498 | if ((err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1))) |
499 | return err; | |
500 | pci_fixup_device(pci_fixup_enable, dev); | |
ceb43744 | 501 | dev->is_enabled = 1; |
1da177e4 LT |
502 | return 0; |
503 | } | |
504 | ||
505 | /** | |
506 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
507 | * @dev: the PCI device to disable | |
508 | * | |
509 | * Disables architecture specific PCI resources for the device. This | |
510 | * is the default implementation. Architecture implementations can | |
511 | * override this. | |
512 | */ | |
513 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
514 | ||
515 | /** | |
516 | * pci_disable_device - Disable PCI device after use | |
517 | * @dev: PCI device to be disabled | |
518 | * | |
519 | * Signal to the system that the PCI device is not in use by the system | |
520 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
521 | */ | |
522 | void | |
523 | pci_disable_device(struct pci_dev *dev) | |
524 | { | |
525 | u16 pci_command; | |
526 | ||
1da177e4 LT |
527 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
528 | if (pci_command & PCI_COMMAND_MASTER) { | |
529 | pci_command &= ~PCI_COMMAND_MASTER; | |
530 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
531 | } | |
ceb43744 | 532 | dev->is_busmaster = 0; |
1da177e4 LT |
533 | |
534 | pcibios_disable_device(dev); | |
ceb43744 | 535 | dev->is_enabled = 0; |
1da177e4 LT |
536 | } |
537 | ||
538 | /** | |
539 | * pci_enable_wake - enable device to generate PME# when suspended | |
540 | * @dev: - PCI device to operate on | |
541 | * @state: - Current state of device. | |
542 | * @enable: - Flag to enable or disable generation | |
543 | * | |
544 | * Set the bits in the device's PM Capabilities to generate PME# when | |
545 | * the system is suspended. | |
546 | * | |
547 | * -EIO is returned if device doesn't have PM Capabilities. | |
548 | * -EINVAL is returned if device supports it, but can't generate wake events. | |
549 | * 0 if operation is successful. | |
550 | * | |
551 | */ | |
552 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
553 | { | |
554 | int pm; | |
555 | u16 value; | |
556 | ||
557 | /* find PCI PM capability in list */ | |
558 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
559 | ||
560 | /* If device doesn't support PM Capabilities, but request is to disable | |
561 | * wake events, it's a nop; otherwise fail */ | |
562 | if (!pm) | |
563 | return enable ? -EIO : 0; | |
564 | ||
565 | /* Check device's ability to generate PME# */ | |
566 | pci_read_config_word(dev,pm+PCI_PM_PMC,&value); | |
567 | ||
568 | value &= PCI_PM_CAP_PME_MASK; | |
569 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
570 | ||
571 | /* Check if it can generate PME# from requested state. */ | |
572 | if (!value || !(value & (1 << state))) | |
573 | return enable ? -EINVAL : 0; | |
574 | ||
575 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); | |
576 | ||
577 | /* Clear PME_Status by writing 1 to it and enable PME# */ | |
578 | value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
579 | ||
580 | if (!enable) | |
581 | value &= ~PCI_PM_CTRL_PME_ENABLE; | |
582 | ||
583 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | int | |
589 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
590 | { | |
591 | u8 pin; | |
592 | ||
514d207d | 593 | pin = dev->pin; |
1da177e4 LT |
594 | if (!pin) |
595 | return -1; | |
596 | pin--; | |
597 | while (dev->bus->self) { | |
598 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
599 | dev = dev->bus->self; | |
600 | } | |
601 | *bridge = dev; | |
602 | return pin; | |
603 | } | |
604 | ||
605 | /** | |
606 | * pci_release_region - Release a PCI bar | |
607 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
608 | * @bar: BAR to release | |
609 | * | |
610 | * Releases the PCI I/O and memory resources previously reserved by a | |
611 | * successful call to pci_request_region. Call this function only | |
612 | * after all use of the PCI regions has ceased. | |
613 | */ | |
614 | void pci_release_region(struct pci_dev *pdev, int bar) | |
615 | { | |
616 | if (pci_resource_len(pdev, bar) == 0) | |
617 | return; | |
618 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
619 | release_region(pci_resource_start(pdev, bar), | |
620 | pci_resource_len(pdev, bar)); | |
621 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
622 | release_mem_region(pci_resource_start(pdev, bar), | |
623 | pci_resource_len(pdev, bar)); | |
624 | } | |
625 | ||
626 | /** | |
627 | * pci_request_region - Reserved PCI I/O and memory resource | |
628 | * @pdev: PCI device whose resources are to be reserved | |
629 | * @bar: BAR to be reserved | |
630 | * @res_name: Name to be associated with resource. | |
631 | * | |
632 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
633 | * being reserved by owner @res_name. Do not access any | |
634 | * address inside the PCI regions unless this call returns | |
635 | * successfully. | |
636 | * | |
637 | * Returns 0 on success, or %EBUSY on error. A warning | |
638 | * message is also printed on failure. | |
639 | */ | |
640 | int pci_request_region(struct pci_dev *pdev, int bar, char *res_name) | |
641 | { | |
642 | if (pci_resource_len(pdev, bar) == 0) | |
643 | return 0; | |
644 | ||
645 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
646 | if (!request_region(pci_resource_start(pdev, bar), | |
647 | pci_resource_len(pdev, bar), res_name)) | |
648 | goto err_out; | |
649 | } | |
650 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
651 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
652 | pci_resource_len(pdev, bar), res_name)) | |
653 | goto err_out; | |
654 | } | |
655 | ||
656 | return 0; | |
657 | ||
658 | err_out: | |
659 | printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n", | |
660 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", | |
661 | bar + 1, /* PCI BAR # */ | |
662 | pci_resource_len(pdev, bar), pci_resource_start(pdev, bar), | |
663 | pci_name(pdev)); | |
664 | return -EBUSY; | |
665 | } | |
666 | ||
667 | ||
668 | /** | |
669 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
670 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
671 | * | |
672 | * Releases all PCI I/O and memory resources previously reserved by a | |
673 | * successful call to pci_request_regions. Call this function only | |
674 | * after all use of the PCI regions has ceased. | |
675 | */ | |
676 | ||
677 | void pci_release_regions(struct pci_dev *pdev) | |
678 | { | |
679 | int i; | |
680 | ||
681 | for (i = 0; i < 6; i++) | |
682 | pci_release_region(pdev, i); | |
683 | } | |
684 | ||
685 | /** | |
686 | * pci_request_regions - Reserved PCI I/O and memory resources | |
687 | * @pdev: PCI device whose resources are to be reserved | |
688 | * @res_name: Name to be associated with resource. | |
689 | * | |
690 | * Mark all PCI regions associated with PCI device @pdev as | |
691 | * being reserved by owner @res_name. Do not access any | |
692 | * address inside the PCI regions unless this call returns | |
693 | * successfully. | |
694 | * | |
695 | * Returns 0 on success, or %EBUSY on error. A warning | |
696 | * message is also printed on failure. | |
697 | */ | |
698 | int pci_request_regions(struct pci_dev *pdev, char *res_name) | |
699 | { | |
700 | int i; | |
701 | ||
702 | for (i = 0; i < 6; i++) | |
703 | if(pci_request_region(pdev, i, res_name)) | |
704 | goto err_out; | |
705 | return 0; | |
706 | ||
707 | err_out: | |
708 | while(--i >= 0) | |
709 | pci_release_region(pdev, i); | |
710 | ||
711 | return -EBUSY; | |
712 | } | |
713 | ||
714 | /** | |
715 | * pci_set_master - enables bus-mastering for device dev | |
716 | * @dev: the PCI device to enable | |
717 | * | |
718 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
719 | * to do the needed arch specific settings. | |
720 | */ | |
721 | void | |
722 | pci_set_master(struct pci_dev *dev) | |
723 | { | |
724 | u16 cmd; | |
725 | ||
726 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
727 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
728 | pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); | |
729 | cmd |= PCI_COMMAND_MASTER; | |
730 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
731 | } | |
732 | dev->is_busmaster = 1; | |
733 | pcibios_set_master(dev); | |
734 | } | |
735 | ||
736 | #ifndef HAVE_ARCH_PCI_MWI | |
737 | /* This can be overridden by arch code. */ | |
738 | u8 pci_cache_line_size = L1_CACHE_BYTES >> 2; | |
739 | ||
740 | /** | |
741 | * pci_generic_prep_mwi - helper function for pci_set_mwi | |
742 | * @dev: the PCI device for which MWI is enabled | |
743 | * | |
744 | * Helper function for generic implementation of pcibios_prep_mwi | |
745 | * function. Originally copied from drivers/net/acenic.c. | |
746 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. | |
747 | * | |
748 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
749 | */ | |
750 | static int | |
751 | pci_generic_prep_mwi(struct pci_dev *dev) | |
752 | { | |
753 | u8 cacheline_size; | |
754 | ||
755 | if (!pci_cache_line_size) | |
756 | return -EINVAL; /* The system doesn't support MWI. */ | |
757 | ||
758 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
759 | equal to or multiple of the right value. */ | |
760 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
761 | if (cacheline_size >= pci_cache_line_size && | |
762 | (cacheline_size % pci_cache_line_size) == 0) | |
763 | return 0; | |
764 | ||
765 | /* Write the correct value. */ | |
766 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
767 | /* Read it back. */ | |
768 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
769 | if (cacheline_size == pci_cache_line_size) | |
770 | return 0; | |
771 | ||
772 | printk(KERN_DEBUG "PCI: cache line size of %d is not supported " | |
773 | "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); | |
774 | ||
775 | return -EINVAL; | |
776 | } | |
777 | #endif /* !HAVE_ARCH_PCI_MWI */ | |
778 | ||
779 | /** | |
780 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
781 | * @dev: the PCI device for which MWI is enabled | |
782 | * | |
783 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, | |
784 | * and then calls @pcibios_set_mwi to do the needed arch specific | |
785 | * operations or a generic mwi-prep function. | |
786 | * | |
787 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
788 | */ | |
789 | int | |
790 | pci_set_mwi(struct pci_dev *dev) | |
791 | { | |
792 | int rc; | |
793 | u16 cmd; | |
794 | ||
795 | #ifdef HAVE_ARCH_PCI_MWI | |
796 | rc = pcibios_prep_mwi(dev); | |
797 | #else | |
798 | rc = pci_generic_prep_mwi(dev); | |
799 | #endif | |
800 | ||
801 | if (rc) | |
802 | return rc; | |
803 | ||
804 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
805 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
806 | pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); | |
807 | cmd |= PCI_COMMAND_INVALIDATE; | |
808 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
809 | } | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
814 | /** | |
815 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
816 | * @dev: the PCI device to disable | |
817 | * | |
818 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
819 | */ | |
820 | void | |
821 | pci_clear_mwi(struct pci_dev *dev) | |
822 | { | |
823 | u16 cmd; | |
824 | ||
825 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
826 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
827 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
828 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
829 | } | |
830 | } | |
831 | ||
a04ce0ff BR |
832 | /** |
833 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
834 | * @pdev: the PCI device to operate on |
835 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
836 | * |
837 | * Enables/disables PCI INTx for device dev | |
838 | */ | |
839 | void | |
840 | pci_intx(struct pci_dev *pdev, int enable) | |
841 | { | |
842 | u16 pci_command, new; | |
843 | ||
844 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
845 | ||
846 | if (enable) { | |
847 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
848 | } else { | |
849 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
850 | } | |
851 | ||
852 | if (new != pci_command) { | |
2fd9d74b | 853 | pci_write_config_word(pdev, PCI_COMMAND, new); |
a04ce0ff BR |
854 | } |
855 | } | |
856 | ||
1da177e4 LT |
857 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
858 | /* | |
859 | * These can be overridden by arch-specific implementations | |
860 | */ | |
861 | int | |
862 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
863 | { | |
864 | if (!pci_dma_supported(dev, mask)) | |
865 | return -EIO; | |
866 | ||
867 | dev->dma_mask = mask; | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
1da177e4 LT |
872 | int |
873 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
874 | { | |
875 | if (!pci_dma_supported(dev, mask)) | |
876 | return -EIO; | |
877 | ||
878 | dev->dev.coherent_dma_mask = mask; | |
879 | ||
880 | return 0; | |
881 | } | |
882 | #endif | |
883 | ||
884 | static int __devinit pci_init(void) | |
885 | { | |
886 | struct pci_dev *dev = NULL; | |
887 | ||
888 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
889 | pci_fixup_device(pci_fixup_final, dev); | |
890 | } | |
891 | return 0; | |
892 | } | |
893 | ||
894 | static int __devinit pci_setup(char *str) | |
895 | { | |
896 | while (str) { | |
897 | char *k = strchr(str, ','); | |
898 | if (k) | |
899 | *k++ = 0; | |
900 | if (*str && (str = pcibios_setup(str)) && *str) { | |
901 | /* PCI layer options should be handled here */ | |
902 | printk(KERN_ERR "PCI: Unknown option `%s'\n", str); | |
903 | } | |
904 | str = k; | |
905 | } | |
906 | return 1; | |
907 | } | |
908 | ||
909 | device_initcall(pci_init); | |
910 | ||
911 | __setup("pci=", pci_setup); | |
912 | ||
913 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
914 | /* FIXME: Some boxes have multiple ISA bridges! */ | |
915 | struct pci_dev *isa_bridge; | |
916 | EXPORT_SYMBOL(isa_bridge); | |
917 | #endif | |
918 | ||
064b53db | 919 | EXPORT_SYMBOL_GPL(pci_restore_bars); |
1da177e4 LT |
920 | EXPORT_SYMBOL(pci_enable_device_bars); |
921 | EXPORT_SYMBOL(pci_enable_device); | |
922 | EXPORT_SYMBOL(pci_disable_device); | |
1da177e4 LT |
923 | EXPORT_SYMBOL(pci_find_capability); |
924 | EXPORT_SYMBOL(pci_bus_find_capability); | |
925 | EXPORT_SYMBOL(pci_release_regions); | |
926 | EXPORT_SYMBOL(pci_request_regions); | |
927 | EXPORT_SYMBOL(pci_release_region); | |
928 | EXPORT_SYMBOL(pci_request_region); | |
929 | EXPORT_SYMBOL(pci_set_master); | |
930 | EXPORT_SYMBOL(pci_set_mwi); | |
931 | EXPORT_SYMBOL(pci_clear_mwi); | |
a04ce0ff | 932 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 933 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
934 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
935 | EXPORT_SYMBOL(pci_assign_resource); | |
936 | EXPORT_SYMBOL(pci_find_parent_resource); | |
937 | ||
938 | EXPORT_SYMBOL(pci_set_power_state); | |
939 | EXPORT_SYMBOL(pci_save_state); | |
940 | EXPORT_SYMBOL(pci_restore_state); | |
941 | EXPORT_SYMBOL(pci_enable_wake); | |
942 | ||
943 | /* Quirk info */ | |
944 | ||
945 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
946 | EXPORT_SYMBOL(pci_pci_problems); |