Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
1da177e4 | 4 | * |
df62ab5e BH |
5 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
6 | * David Mosberger-Tang | |
1da177e4 | 7 | * |
df62ab5e | 8 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> |
1da177e4 LT |
9 | */ |
10 | ||
2ab51dde | 11 | #include <linux/acpi.h> |
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/delay.h> | |
9d26d3a8 | 14 | #include <linux/dmi.h> |
1da177e4 | 15 | #include <linux/init.h> |
7c674700 LP |
16 | #include <linux/of.h> |
17 | #include <linux/of_pci.h> | |
1da177e4 | 18 | #include <linux/pci.h> |
075c1771 | 19 | #include <linux/pm.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1da177e4 LT |
21 | #include <linux/module.h> |
22 | #include <linux/spinlock.h> | |
4e57b681 | 23 | #include <linux/string.h> |
229f5afd | 24 | #include <linux/log2.h> |
5745392e | 25 | #include <linux/logic_pio.h> |
c300bd2f | 26 | #include <linux/pm_wakeup.h> |
8dd7f803 | 27 | #include <linux/interrupt.h> |
32a9a682 | 28 | #include <linux/device.h> |
b67ea761 | 29 | #include <linux/pm_runtime.h> |
608c3881 | 30 | #include <linux/pci_hotplug.h> |
4d3f1384 | 31 | #include <linux/vmalloc.h> |
4ebeb1ec | 32 | #include <linux/pci-ats.h> |
32a9a682 | 33 | #include <asm/setup.h> |
2a2aca31 | 34 | #include <asm/dma.h> |
b07461a8 | 35 | #include <linux/aer.h> |
bc56b9e0 | 36 | #include "pci.h" |
1da177e4 | 37 | |
c4eed62a KB |
38 | DEFINE_MUTEX(pci_slot_mutex); |
39 | ||
00240c38 AS |
40 | const char *pci_power_names[] = { |
41 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
42 | }; | |
43 | EXPORT_SYMBOL_GPL(pci_power_names); | |
44 | ||
93177a74 RW |
45 | int isa_dma_bridge_buggy; |
46 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
47 | ||
48 | int pci_pci_problems; | |
49 | EXPORT_SYMBOL(pci_pci_problems); | |
50 | ||
1ae861e6 RW |
51 | unsigned int pci_pm_d3_delay; |
52 | ||
df17e62e MG |
53 | static void pci_pme_list_scan(struct work_struct *work); |
54 | ||
55 | static LIST_HEAD(pci_pme_list); | |
56 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
57 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
58 | ||
59 | struct pci_pme_device { | |
60 | struct list_head list; | |
61 | struct pci_dev *dev; | |
62 | }; | |
63 | ||
64 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
65 | ||
1ae861e6 RW |
66 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
67 | { | |
68 | unsigned int delay = dev->d3_delay; | |
69 | ||
70 | if (delay < pci_pm_d3_delay) | |
71 | delay = pci_pm_d3_delay; | |
72 | ||
50b2b540 AH |
73 | if (delay) |
74 | msleep(delay); | |
1ae861e6 | 75 | } |
1da177e4 | 76 | |
32a2eea7 JG |
77 | #ifdef CONFIG_PCI_DOMAINS |
78 | int pci_domains_supported = 1; | |
79 | #endif | |
80 | ||
4516a618 AN |
81 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
82 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
83 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
84 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
85 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
86 | ||
28760489 EB |
87 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
88 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
89 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
90 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
91 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
92 | ||
e16b4660 KB |
93 | #define DEFAULT_HOTPLUG_BUS_SIZE 1 |
94 | unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
95 | ||
27d868b5 | 96 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; |
b03e7495 | 97 | |
ac1aa47b JB |
98 | /* |
99 | * The default CLS is used if arch didn't set CLS explicitly and not | |
100 | * all pci devices agree on the same value. Arch can override either | |
101 | * the dfl or actual value as it sees fit. Don't forget this is | |
102 | * measured in 32-bit words, not bytes. | |
103 | */ | |
15856ad5 | 104 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
105 | u8 pci_cache_line_size; |
106 | ||
96c55900 MS |
107 | /* |
108 | * If we set up a device for bus mastering, we need to check the latency | |
109 | * timer as certain BIOSes forget to set it properly. | |
110 | */ | |
111 | unsigned int pcibios_max_latency = 255; | |
112 | ||
6748dcc2 RW |
113 | /* If set, the PCIe ARI capability will not be used. */ |
114 | static bool pcie_ari_disabled; | |
115 | ||
cef74409 GK |
116 | /* If set, the PCIe ATS capability will not be used. */ |
117 | static bool pcie_ats_disabled; | |
118 | ||
11eb0e0e SK |
119 | /* If set, the PCI config space of each device is printed during boot. */ |
120 | bool pci_early_dump; | |
121 | ||
cef74409 GK |
122 | bool pci_ats_disabled(void) |
123 | { | |
124 | return pcie_ats_disabled; | |
125 | } | |
126 | ||
9d26d3a8 MW |
127 | /* Disable bridge_d3 for all PCIe ports */ |
128 | static bool pci_bridge_d3_disable; | |
129 | /* Force bridge_d3 for all PCIe ports */ | |
130 | static bool pci_bridge_d3_force; | |
131 | ||
132 | static int __init pcie_port_pm_setup(char *str) | |
133 | { | |
134 | if (!strcmp(str, "off")) | |
135 | pci_bridge_d3_disable = true; | |
136 | else if (!strcmp(str, "force")) | |
137 | pci_bridge_d3_force = true; | |
138 | return 1; | |
139 | } | |
140 | __setup("pcie_port_pm=", pcie_port_pm_setup); | |
141 | ||
a2758b6b SK |
142 | /* Time to wait after a reset for device to become responsive */ |
143 | #define PCIE_RESET_READY_POLL_MS 60000 | |
144 | ||
1da177e4 LT |
145 | /** |
146 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
147 | * @bus: pointer to PCI bus structure to search | |
148 | * | |
149 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
150 | * including the given PCI bus and its list of child PCI buses. | |
151 | */ | |
07656d83 | 152 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 153 | { |
94e6a9b9 | 154 | struct pci_bus *tmp; |
1da177e4 LT |
155 | unsigned char max, n; |
156 | ||
b918c62e | 157 | max = bus->busn_res.end; |
94e6a9b9 YW |
158 | list_for_each_entry(tmp, &bus->children, node) { |
159 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 160 | if (n > max) |
1da177e4 LT |
161 | max = n; |
162 | } | |
163 | return max; | |
164 | } | |
b82db5ce | 165 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 166 | |
1684f5dd AM |
167 | #ifdef CONFIG_HAS_IOMEM |
168 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
169 | { | |
1f7bf3bf BH |
170 | struct resource *res = &pdev->resource[bar]; |
171 | ||
1684f5dd AM |
172 | /* |
173 | * Make sure the BAR is actually a memory resource, not an IO resource | |
174 | */ | |
646c0282 | 175 | if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { |
7506dc79 | 176 | pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res); |
1684f5dd AM |
177 | return NULL; |
178 | } | |
1f7bf3bf | 179 | return ioremap_nocache(res->start, resource_size(res)); |
1684f5dd AM |
180 | } |
181 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
c43996f4 LR |
182 | |
183 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) | |
184 | { | |
185 | /* | |
186 | * Make sure the BAR is actually a memory resource, not an IO resource | |
187 | */ | |
188 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
189 | WARN_ON(1); | |
190 | return NULL; | |
191 | } | |
192 | return ioremap_wc(pci_resource_start(pdev, bar), | |
193 | pci_resource_len(pdev, bar)); | |
194 | } | |
195 | EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); | |
1684f5dd AM |
196 | #endif |
197 | ||
45db3370 LG |
198 | /** |
199 | * pci_dev_str_match_path - test if a path string matches a device | |
200 | * @dev: the PCI device to test | |
7eb37025 | 201 | * @path: string to match the device against |
45db3370 LG |
202 | * @endptr: pointer to the string after the match |
203 | * | |
204 | * Test if a string (typically from a kernel parameter) formatted as a | |
205 | * path of device/function addresses matches a PCI device. The string must | |
206 | * be of the form: | |
207 | * | |
208 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* | |
209 | * | |
210 | * A path for a device can be obtained using 'lspci -t'. Using a path | |
211 | * is more robust against bus renumbering than using only a single bus, | |
212 | * device and function address. | |
213 | * | |
214 | * Returns 1 if the string matches the device, 0 if it does not and | |
215 | * a negative error code if it fails to parse the string. | |
216 | */ | |
217 | static int pci_dev_str_match_path(struct pci_dev *dev, const char *path, | |
218 | const char **endptr) | |
219 | { | |
220 | int ret; | |
221 | int seg, bus, slot, func; | |
222 | char *wpath, *p; | |
223 | char end; | |
224 | ||
225 | *endptr = strchrnul(path, ';'); | |
226 | ||
227 | wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL); | |
228 | if (!wpath) | |
229 | return -ENOMEM; | |
230 | ||
231 | while (1) { | |
232 | p = strrchr(wpath, '/'); | |
233 | if (!p) | |
234 | break; | |
235 | ret = sscanf(p, "/%x.%x%c", &slot, &func, &end); | |
236 | if (ret != 2) { | |
237 | ret = -EINVAL; | |
238 | goto free_and_exit; | |
239 | } | |
240 | ||
241 | if (dev->devfn != PCI_DEVFN(slot, func)) { | |
242 | ret = 0; | |
243 | goto free_and_exit; | |
244 | } | |
245 | ||
246 | /* | |
247 | * Note: we don't need to get a reference to the upstream | |
248 | * bridge because we hold a reference to the top level | |
249 | * device which should hold a reference to the bridge, | |
250 | * and so on. | |
251 | */ | |
252 | dev = pci_upstream_bridge(dev); | |
253 | if (!dev) { | |
254 | ret = 0; | |
255 | goto free_and_exit; | |
256 | } | |
257 | ||
258 | *p = 0; | |
259 | } | |
260 | ||
261 | ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot, | |
262 | &func, &end); | |
263 | if (ret != 4) { | |
264 | seg = 0; | |
265 | ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end); | |
266 | if (ret != 3) { | |
267 | ret = -EINVAL; | |
268 | goto free_and_exit; | |
269 | } | |
270 | } | |
271 | ||
272 | ret = (seg == pci_domain_nr(dev->bus) && | |
273 | bus == dev->bus->number && | |
274 | dev->devfn == PCI_DEVFN(slot, func)); | |
275 | ||
276 | free_and_exit: | |
277 | kfree(wpath); | |
278 | return ret; | |
279 | } | |
280 | ||
07d8d7e5 LG |
281 | /** |
282 | * pci_dev_str_match - test if a string matches a device | |
283 | * @dev: the PCI device to test | |
284 | * @p: string to match the device against | |
285 | * @endptr: pointer to the string after the match | |
286 | * | |
287 | * Test if a string (typically from a kernel parameter) matches a specified | |
288 | * PCI device. The string may be of one of the following formats: | |
289 | * | |
45db3370 | 290 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* |
07d8d7e5 LG |
291 | * pci:<vendor>:<device>[:<subvendor>:<subdevice>] |
292 | * | |
293 | * The first format specifies a PCI bus/device/function address which | |
294 | * may change if new hardware is inserted, if motherboard firmware changes, | |
295 | * or due to changes caused in kernel parameters. If the domain is | |
45db3370 LG |
296 | * left unspecified, it is taken to be 0. In order to be robust against |
297 | * bus renumbering issues, a path of PCI device/function numbers may be used | |
298 | * to address the specific device. The path for a device can be determined | |
299 | * through the use of 'lspci -t'. | |
07d8d7e5 LG |
300 | * |
301 | * The second format matches devices using IDs in the configuration | |
302 | * space which may match multiple devices in the system. A value of 0 | |
303 | * for any field will match all devices. (Note: this differs from | |
304 | * in-kernel code that uses PCI_ANY_ID which is ~0; this is for | |
305 | * legacy reasons and convenience so users don't have to specify | |
306 | * FFFFFFFFs on the command line.) | |
307 | * | |
308 | * Returns 1 if the string matches the device, 0 if it does not and | |
309 | * a negative error code if the string cannot be parsed. | |
310 | */ | |
311 | static int pci_dev_str_match(struct pci_dev *dev, const char *p, | |
312 | const char **endptr) | |
313 | { | |
314 | int ret; | |
45db3370 | 315 | int count; |
07d8d7e5 LG |
316 | unsigned short vendor, device, subsystem_vendor, subsystem_device; |
317 | ||
318 | if (strncmp(p, "pci:", 4) == 0) { | |
319 | /* PCI vendor/device (subvendor/subdevice) IDs are specified */ | |
320 | p += 4; | |
321 | ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device, | |
322 | &subsystem_vendor, &subsystem_device, &count); | |
323 | if (ret != 4) { | |
324 | ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count); | |
325 | if (ret != 2) | |
326 | return -EINVAL; | |
327 | ||
328 | subsystem_vendor = 0; | |
329 | subsystem_device = 0; | |
330 | } | |
331 | ||
332 | p += count; | |
333 | ||
334 | if ((!vendor || vendor == dev->vendor) && | |
335 | (!device || device == dev->device) && | |
336 | (!subsystem_vendor || | |
337 | subsystem_vendor == dev->subsystem_vendor) && | |
338 | (!subsystem_device || | |
339 | subsystem_device == dev->subsystem_device)) | |
340 | goto found; | |
07d8d7e5 | 341 | } else { |
45db3370 LG |
342 | /* |
343 | * PCI Bus, Device, Function IDs are specified | |
344 | * (optionally, may include a path of devfns following it) | |
345 | */ | |
346 | ret = pci_dev_str_match_path(dev, p, &p); | |
347 | if (ret < 0) | |
348 | return ret; | |
349 | else if (ret) | |
07d8d7e5 LG |
350 | goto found; |
351 | } | |
352 | ||
353 | *endptr = p; | |
354 | return 0; | |
355 | ||
356 | found: | |
357 | *endptr = p; | |
358 | return 1; | |
359 | } | |
687d5fe3 ME |
360 | |
361 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
362 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
363 | { |
364 | u8 id; | |
55db3208 SS |
365 | u16 ent; |
366 | ||
367 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
24a4e377 | 368 | |
687d5fe3 | 369 | while ((*ttl)--) { |
24a4e377 RD |
370 | if (pos < 0x40) |
371 | break; | |
372 | pos &= ~3; | |
55db3208 SS |
373 | pci_bus_read_config_word(bus, devfn, pos, &ent); |
374 | ||
375 | id = ent & 0xff; | |
24a4e377 RD |
376 | if (id == 0xff) |
377 | break; | |
378 | if (id == cap) | |
379 | return pos; | |
55db3208 | 380 | pos = (ent >> 8); |
24a4e377 RD |
381 | } |
382 | return 0; | |
383 | } | |
384 | ||
687d5fe3 ME |
385 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
386 | u8 pos, int cap) | |
387 | { | |
388 | int ttl = PCI_FIND_CAP_TTL; | |
389 | ||
390 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
391 | } | |
392 | ||
24a4e377 RD |
393 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
394 | { | |
395 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
396 | pos + PCI_CAP_LIST_NEXT, cap); | |
397 | } | |
398 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
399 | ||
d3bac118 ME |
400 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
401 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
402 | { |
403 | u16 status; | |
1da177e4 LT |
404 | |
405 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
406 | if (!(status & PCI_STATUS_CAP_LIST)) | |
407 | return 0; | |
408 | ||
409 | switch (hdr_type) { | |
410 | case PCI_HEADER_TYPE_NORMAL: | |
411 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 412 | return PCI_CAPABILITY_LIST; |
1da177e4 | 413 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 414 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 | 415 | } |
d3bac118 ME |
416 | |
417 | return 0; | |
1da177e4 LT |
418 | } |
419 | ||
420 | /** | |
f7625980 | 421 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
422 | * @dev: PCI device to query |
423 | * @cap: capability code | |
424 | * | |
425 | * Tell if a device supports a given PCI capability. | |
426 | * Returns the address of the requested capability structure within the | |
427 | * device's PCI configuration space or 0 in case the device does not | |
428 | * support it. Possible values for @cap: | |
429 | * | |
f7625980 BH |
430 | * %PCI_CAP_ID_PM Power Management |
431 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
432 | * %PCI_CAP_ID_VPD Vital Product Data | |
433 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 434 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 435 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
436 | * %PCI_CAP_ID_PCIX PCI-X |
437 | * %PCI_CAP_ID_EXP PCI Express | |
438 | */ | |
439 | int pci_find_capability(struct pci_dev *dev, int cap) | |
440 | { | |
d3bac118 ME |
441 | int pos; |
442 | ||
443 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
444 | if (pos) | |
445 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
446 | ||
447 | return pos; | |
1da177e4 | 448 | } |
b7fe9434 | 449 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
450 | |
451 | /** | |
f7625980 | 452 | * pci_bus_find_capability - query for devices' capabilities |
1da177e4 LT |
453 | * @bus: the PCI bus to query |
454 | * @devfn: PCI device to query | |
455 | * @cap: capability code | |
456 | * | |
457 | * Like pci_find_capability() but works for pci devices that do not have a | |
f7625980 | 458 | * pci_dev structure set up yet. |
1da177e4 LT |
459 | * |
460 | * Returns the address of the requested capability structure within the | |
461 | * device's PCI configuration space or 0 in case the device does not | |
462 | * support it. | |
463 | */ | |
464 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
465 | { | |
d3bac118 | 466 | int pos; |
1da177e4 LT |
467 | u8 hdr_type; |
468 | ||
469 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
470 | ||
d3bac118 ME |
471 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
472 | if (pos) | |
473 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
474 | ||
475 | return pos; | |
1da177e4 | 476 | } |
b7fe9434 | 477 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
478 | |
479 | /** | |
44a9a36f | 480 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 481 | * @dev: PCI device to query |
44a9a36f | 482 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
483 | * @cap: capability code |
484 | * | |
44a9a36f | 485 | * Returns the address of the next matching extended capability structure |
1da177e4 | 486 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
487 | * not support it. Some capabilities can occur several times, e.g., the |
488 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 489 | */ |
44a9a36f | 490 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
491 | { |
492 | u32 header; | |
557848c3 ZY |
493 | int ttl; |
494 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 495 | |
557848c3 ZY |
496 | /* minimum 8 bytes per capability */ |
497 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
498 | ||
499 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
500 | return 0; |
501 | ||
44a9a36f BH |
502 | if (start) |
503 | pos = start; | |
504 | ||
1da177e4 LT |
505 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
506 | return 0; | |
507 | ||
508 | /* | |
509 | * If we have no capabilities, this is indicated by cap ID, | |
510 | * cap version and next pointer all being 0. | |
511 | */ | |
512 | if (header == 0) | |
513 | return 0; | |
514 | ||
515 | while (ttl-- > 0) { | |
44a9a36f | 516 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
517 | return pos; |
518 | ||
519 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 520 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
521 | break; |
522 | ||
523 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
524 | break; | |
525 | } | |
526 | ||
527 | return 0; | |
528 | } | |
44a9a36f BH |
529 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
530 | ||
531 | /** | |
532 | * pci_find_ext_capability - Find an extended capability | |
533 | * @dev: PCI device to query | |
534 | * @cap: capability code | |
535 | * | |
536 | * Returns the address of the requested extended capability structure | |
537 | * within the device's PCI configuration space or 0 if the device does | |
538 | * not support it. Possible values for @cap: | |
539 | * | |
540 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
541 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
542 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
543 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
544 | */ | |
545 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
546 | { | |
547 | return pci_find_next_ext_capability(dev, 0, cap); | |
548 | } | |
3a720d72 | 549 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 550 | |
687d5fe3 ME |
551 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
552 | { | |
553 | int rc, ttl = PCI_FIND_CAP_TTL; | |
554 | u8 cap, mask; | |
555 | ||
556 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
557 | mask = HT_3BIT_CAP_MASK; | |
558 | else | |
559 | mask = HT_5BIT_CAP_MASK; | |
560 | ||
561 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
562 | PCI_CAP_ID_HT, &ttl); | |
563 | while (pos) { | |
564 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
565 | if (rc != PCIBIOS_SUCCESSFUL) | |
566 | return 0; | |
567 | ||
568 | if ((cap & mask) == ht_cap) | |
569 | return pos; | |
570 | ||
47a4d5be BG |
571 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
572 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
573 | PCI_CAP_ID_HT, &ttl); |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
578 | /** | |
579 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
580 | * @dev: PCI device to query | |
581 | * @pos: Position from which to continue searching | |
582 | * @ht_cap: Hypertransport capability code | |
583 | * | |
584 | * To be used in conjunction with pci_find_ht_capability() to search for | |
585 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
586 | * from pci_find_ht_capability(). | |
587 | * | |
588 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
589 | * steps to avoid an infinite loop. | |
590 | */ | |
591 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
592 | { | |
593 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
594 | } | |
595 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
596 | ||
597 | /** | |
598 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
599 | * @dev: PCI device to query | |
600 | * @ht_cap: Hypertransport capability code | |
601 | * | |
602 | * Tell if a device supports a given Hypertransport capability. | |
603 | * Returns an address within the device's PCI configuration space | |
604 | * or 0 in case the device does not support the request capability. | |
605 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
606 | * which has a Hypertransport capability matching @ht_cap. | |
607 | */ | |
608 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
609 | { | |
610 | int pos; | |
611 | ||
612 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
613 | if (pos) | |
614 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
615 | ||
616 | return pos; | |
617 | } | |
618 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
619 | ||
1da177e4 LT |
620 | /** |
621 | * pci_find_parent_resource - return resource region of parent bus of given region | |
622 | * @dev: PCI device structure contains resources to be searched | |
623 | * @res: child resource record for which parent is sought | |
624 | * | |
625 | * For given resource region of given device, return the resource | |
f44116ae | 626 | * region of parent bus the given region is contained in. |
1da177e4 | 627 | */ |
3c78bc61 RD |
628 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
629 | struct resource *res) | |
1da177e4 LT |
630 | { |
631 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 632 | struct resource *r; |
1da177e4 | 633 | int i; |
1da177e4 | 634 | |
89a74ecc | 635 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
636 | if (!r) |
637 | continue; | |
31342330 | 638 | if (resource_contains(r, res)) { |
f44116ae BH |
639 | |
640 | /* | |
641 | * If the window is prefetchable but the BAR is | |
642 | * not, the allocator made a mistake. | |
643 | */ | |
644 | if (r->flags & IORESOURCE_PREFETCH && | |
645 | !(res->flags & IORESOURCE_PREFETCH)) | |
646 | return NULL; | |
647 | ||
648 | /* | |
649 | * If we're below a transparent bridge, there may | |
650 | * be both a positively-decoded aperture and a | |
651 | * subtractively-decoded region that contain the BAR. | |
652 | * We want the positively-decoded one, so this depends | |
653 | * on pci_bus_for_each_resource() giving us those | |
654 | * first. | |
655 | */ | |
656 | return r; | |
657 | } | |
1da177e4 | 658 | } |
f44116ae | 659 | return NULL; |
1da177e4 | 660 | } |
b7fe9434 | 661 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 662 | |
afd29f90 MW |
663 | /** |
664 | * pci_find_resource - Return matching PCI device resource | |
665 | * @dev: PCI device to query | |
666 | * @res: Resource to look for | |
667 | * | |
668 | * Goes over standard PCI resources (BARs) and checks if the given resource | |
669 | * is partially or fully contained in any of them. In that case the | |
670 | * matching resource is returned, %NULL otherwise. | |
671 | */ | |
672 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res) | |
673 | { | |
674 | int i; | |
675 | ||
676 | for (i = 0; i < PCI_ROM_RESOURCE; i++) { | |
677 | struct resource *r = &dev->resource[i]; | |
678 | ||
679 | if (r->start && resource_contains(r, res)) | |
680 | return r; | |
681 | } | |
682 | ||
683 | return NULL; | |
684 | } | |
685 | EXPORT_SYMBOL(pci_find_resource); | |
686 | ||
c56d4450 HS |
687 | /** |
688 | * pci_find_pcie_root_port - return PCIe Root Port | |
689 | * @dev: PCI device to query | |
690 | * | |
691 | * Traverse up the parent chain and return the PCIe Root Port PCI Device | |
692 | * for a given PCI Device. | |
693 | */ | |
694 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev) | |
695 | { | |
b6f6d56c | 696 | struct pci_dev *bridge, *highest_pcie_bridge = dev; |
c56d4450 HS |
697 | |
698 | bridge = pci_upstream_bridge(dev); | |
699 | while (bridge && pci_is_pcie(bridge)) { | |
700 | highest_pcie_bridge = bridge; | |
701 | bridge = pci_upstream_bridge(bridge); | |
702 | } | |
703 | ||
b6f6d56c TR |
704 | if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT) |
705 | return NULL; | |
c56d4450 | 706 | |
b6f6d56c | 707 | return highest_pcie_bridge; |
c56d4450 HS |
708 | } |
709 | EXPORT_SYMBOL(pci_find_pcie_root_port); | |
710 | ||
157e876f AW |
711 | /** |
712 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
713 | * @dev: the PCI device to operate on | |
714 | * @pos: config space offset of status word | |
715 | * @mask: mask of bit(s) to care about in status word | |
716 | * | |
717 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
718 | */ | |
719 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
720 | { | |
721 | int i; | |
722 | ||
723 | /* Wait for Transaction Pending bit clean */ | |
724 | for (i = 0; i < 4; i++) { | |
725 | u16 status; | |
726 | if (i) | |
727 | msleep((1 << (i - 1)) * 100); | |
728 | ||
729 | pci_read_config_word(dev, pos, &status); | |
730 | if (!(status & mask)) | |
731 | return 1; | |
732 | } | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
064b53db | 737 | /** |
70675e0b | 738 | * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) |
064b53db JL |
739 | * @dev: PCI device to have its BARs restored |
740 | * | |
741 | * Restore the BAR values for a given device, so as to make it | |
742 | * accessible by its driver. | |
743 | */ | |
3c78bc61 | 744 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 745 | { |
bc5f5a82 | 746 | int i; |
064b53db | 747 | |
bc5f5a82 | 748 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 749 | pci_update_resource(dev, i); |
064b53db JL |
750 | } |
751 | ||
299f2ffe | 752 | static const struct pci_platform_pm_ops *pci_platform_pm; |
961d9120 | 753 | |
299f2ffe | 754 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) |
961d9120 | 755 | { |
cc7cc02b | 756 | if (!ops->is_manageable || !ops->set_state || !ops->get_state || |
0847684c | 757 | !ops->choose_state || !ops->set_wakeup || !ops->need_resume) |
961d9120 RW |
758 | return -EINVAL; |
759 | pci_platform_pm = ops; | |
760 | return 0; | |
761 | } | |
762 | ||
763 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
764 | { | |
765 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
766 | } | |
767 | ||
768 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 769 | pci_power_t t) |
961d9120 RW |
770 | { |
771 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
772 | } | |
773 | ||
cc7cc02b LW |
774 | static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev) |
775 | { | |
776 | return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; | |
777 | } | |
778 | ||
961d9120 RW |
779 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
780 | { | |
781 | return pci_platform_pm ? | |
782 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
783 | } | |
8f7020d3 | 784 | |
0847684c | 785 | static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
786 | { |
787 | return pci_platform_pm ? | |
0847684c | 788 | pci_platform_pm->set_wakeup(dev, enable) : -ENODEV; |
b67ea761 RW |
789 | } |
790 | ||
bac2a909 RW |
791 | static inline bool platform_pci_need_resume(struct pci_dev *dev) |
792 | { | |
793 | return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; | |
794 | } | |
795 | ||
26ad34d5 MW |
796 | static inline bool platform_pci_bridge_d3(struct pci_dev *dev) |
797 | { | |
798 | return pci_platform_pm ? pci_platform_pm->bridge_d3(dev) : false; | |
799 | } | |
800 | ||
1da177e4 | 801 | /** |
44e4e66e RW |
802 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
803 | * given PCI device | |
804 | * @dev: PCI device to handle. | |
44e4e66e | 805 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 806 | * |
44e4e66e RW |
807 | * RETURN VALUE: |
808 | * -EINVAL if the requested state is invalid. | |
809 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
810 | * wrong version, or device doesn't support the requested state. | |
811 | * 0 if device already is in the requested state. | |
812 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 813 | */ |
f00a20ef | 814 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 815 | { |
337001b6 | 816 | u16 pmcsr; |
44e4e66e | 817 | bool need_restore = false; |
1da177e4 | 818 | |
4a865905 RW |
819 | /* Check if we're already there */ |
820 | if (dev->current_state == state) | |
821 | return 0; | |
822 | ||
337001b6 | 823 | if (!dev->pm_cap) |
cca03dec AL |
824 | return -EIO; |
825 | ||
44e4e66e RW |
826 | if (state < PCI_D0 || state > PCI_D3hot) |
827 | return -EINVAL; | |
828 | ||
1da177e4 | 829 | /* Validate current state: |
f7625980 | 830 | * Can enter D0 from any state, but if we can only go deeper |
1da177e4 LT |
831 | * to sleep if we're already in a low power state |
832 | */ | |
4a865905 | 833 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 834 | && dev->current_state > state) { |
7506dc79 | 835 | pci_err(dev, "invalid power transition (from state %d to %d)\n", |
227f0647 | 836 | dev->current_state, state); |
1da177e4 | 837 | return -EINVAL; |
44e4e66e | 838 | } |
1da177e4 | 839 | |
1da177e4 | 840 | /* check if this device supports the desired state */ |
337001b6 RW |
841 | if ((state == PCI_D1 && !dev->d1_support) |
842 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 843 | return -EIO; |
1da177e4 | 844 | |
337001b6 | 845 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 846 | |
32a36585 | 847 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
848 | * This doesn't affect PME_Status, disables PME_En, and |
849 | * sets PowerState to 0. | |
850 | */ | |
32a36585 | 851 | switch (dev->current_state) { |
d3535fbb JL |
852 | case PCI_D0: |
853 | case PCI_D1: | |
854 | case PCI_D2: | |
855 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
856 | pmcsr |= state; | |
857 | break; | |
f62795f1 RW |
858 | case PCI_D3hot: |
859 | case PCI_D3cold: | |
32a36585 JL |
860 | case PCI_UNKNOWN: /* Boot-up */ |
861 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 862 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 863 | need_restore = true; |
1d09d577 | 864 | /* Fall-through - force to D0 */ |
32a36585 | 865 | default: |
d3535fbb | 866 | pmcsr = 0; |
32a36585 | 867 | break; |
1da177e4 LT |
868 | } |
869 | ||
870 | /* enter specified state */ | |
337001b6 | 871 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
872 | |
873 | /* Mandatory power management transition delays */ | |
874 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
875 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 876 | pci_dev_d3_sleep(dev); |
1da177e4 | 877 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 878 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 879 | |
e13cdbd7 RW |
880 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
881 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
882 | if (dev->current_state != state && printk_ratelimit()) | |
7506dc79 | 883 | pci_info(dev, "Refused to change power state, currently in D%d\n", |
227f0647 | 884 | dev->current_state); |
064b53db | 885 | |
448bd857 HY |
886 | /* |
887 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
888 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
889 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
890 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
891 | * For example, at least some versions of the 3c905B and the | |
892 | * 3c556B exhibit this behaviour. | |
893 | * | |
894 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
895 | * devices in a D3hot state at boot. Consequently, we need to | |
896 | * restore at least the BARs so that the device will be | |
897 | * accessible to its driver. | |
898 | */ | |
899 | if (need_restore) | |
900 | pci_restore_bars(dev); | |
901 | ||
f00a20ef | 902 | if (dev->bus->self) |
7d715a6c SL |
903 | pcie_aspm_pm_state_change(dev->bus->self); |
904 | ||
1da177e4 LT |
905 | return 0; |
906 | } | |
907 | ||
44e4e66e | 908 | /** |
a6a64026 | 909 | * pci_update_current_state - Read power state of given device and cache it |
44e4e66e | 910 | * @dev: PCI device to handle. |
f06fc0b6 | 911 | * @state: State to cache in case the device doesn't have the PM capability |
a6a64026 LW |
912 | * |
913 | * The power state is read from the PMCSR register, which however is | |
914 | * inaccessible in D3cold. The platform firmware is therefore queried first | |
915 | * to detect accessibility of the register. In case the platform firmware | |
916 | * reports an incorrect state or the device isn't power manageable by the | |
917 | * platform at all, we try to detect D3cold by testing accessibility of the | |
918 | * vendor ID in config space. | |
44e4e66e | 919 | */ |
73410429 | 920 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 921 | { |
a6a64026 LW |
922 | if (platform_pci_get_power_state(dev) == PCI_D3cold || |
923 | !pci_device_is_present(dev)) { | |
924 | dev->current_state = PCI_D3cold; | |
925 | } else if (dev->pm_cap) { | |
44e4e66e RW |
926 | u16 pmcsr; |
927 | ||
337001b6 | 928 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 929 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
930 | } else { |
931 | dev->current_state = state; | |
44e4e66e RW |
932 | } |
933 | } | |
934 | ||
db288c9c RW |
935 | /** |
936 | * pci_power_up - Put the given device into D0 forcibly | |
937 | * @dev: PCI device to power up | |
938 | */ | |
939 | void pci_power_up(struct pci_dev *dev) | |
940 | { | |
941 | if (platform_pci_power_manageable(dev)) | |
942 | platform_pci_set_power_state(dev, PCI_D0); | |
943 | ||
944 | pci_raw_set_power_state(dev, PCI_D0); | |
945 | pci_update_current_state(dev, PCI_D0); | |
946 | } | |
947 | ||
0e5dd46b RW |
948 | /** |
949 | * pci_platform_power_transition - Use platform to change device power state | |
950 | * @dev: PCI device to handle. | |
951 | * @state: State to put the device into. | |
952 | */ | |
953 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
954 | { | |
955 | int error; | |
956 | ||
957 | if (platform_pci_power_manageable(dev)) { | |
958 | error = platform_pci_set_power_state(dev, state); | |
959 | if (!error) | |
960 | pci_update_current_state(dev, state); | |
769ba721 | 961 | } else |
0e5dd46b | 962 | error = -ENODEV; |
769ba721 RW |
963 | |
964 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
965 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
966 | |
967 | return error; | |
968 | } | |
969 | ||
0b950f0f SH |
970 | /** |
971 | * pci_wakeup - Wake up a PCI device | |
972 | * @pci_dev: Device to handle. | |
973 | * @ign: ignored parameter | |
974 | */ | |
975 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
976 | { | |
977 | pci_wakeup_event(pci_dev); | |
978 | pm_request_resume(&pci_dev->dev); | |
979 | return 0; | |
980 | } | |
981 | ||
982 | /** | |
983 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
984 | * @bus: Top bus of the subtree to walk. | |
985 | */ | |
2a4d2c42 | 986 | void pci_wakeup_bus(struct pci_bus *bus) |
0b950f0f SH |
987 | { |
988 | if (bus) | |
989 | pci_walk_bus(bus, pci_wakeup, NULL); | |
990 | } | |
991 | ||
0e5dd46b RW |
992 | /** |
993 | * __pci_start_power_transition - Start power transition of a PCI device | |
994 | * @dev: PCI device to handle. | |
995 | * @state: State to put the device into. | |
996 | */ | |
997 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
998 | { | |
448bd857 | 999 | if (state == PCI_D0) { |
0e5dd46b | 1000 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
1001 | /* |
1002 | * Mandatory power management transition delays, see | |
1003 | * PCI Express Base Specification Revision 2.0 Section | |
1004 | * 6.6.1: Conventional Reset. Do not delay for | |
1005 | * devices powered on/off by corresponding bridge, | |
1006 | * because have already delayed for the bridge. | |
1007 | */ | |
1008 | if (dev->runtime_d3cold) { | |
d6112f8d | 1009 | if (dev->d3cold_delay && !dev->imm_ready) |
50b2b540 | 1010 | msleep(dev->d3cold_delay); |
448bd857 HY |
1011 | /* |
1012 | * When powering on a bridge from D3cold, the | |
1013 | * whole hierarchy may be powered on into | |
1014 | * D0uninitialized state, resume them to give | |
1015 | * them a chance to suspend again | |
1016 | */ | |
1017 | pci_wakeup_bus(dev->subordinate); | |
1018 | } | |
1019 | } | |
1020 | } | |
1021 | ||
1022 | /** | |
1023 | * __pci_dev_set_current_state - Set current state of a PCI device | |
1024 | * @dev: Device to handle | |
1025 | * @data: pointer to state to be set | |
1026 | */ | |
1027 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
1028 | { | |
1029 | pci_power_t state = *(pci_power_t *)data; | |
1030 | ||
1031 | dev->current_state = state; | |
1032 | return 0; | |
1033 | } | |
1034 | ||
1035 | /** | |
2a4d2c42 | 1036 | * pci_bus_set_current_state - Walk given bus and set current state of devices |
448bd857 HY |
1037 | * @bus: Top bus of the subtree to walk. |
1038 | * @state: state to be set | |
1039 | */ | |
2a4d2c42 | 1040 | void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) |
448bd857 HY |
1041 | { |
1042 | if (bus) | |
1043 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
1044 | } |
1045 | ||
1046 | /** | |
1047 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
1048 | * @dev: PCI device to handle. | |
1049 | * @state: State to put the device into. | |
1050 | * | |
1051 | * This function should not be called directly by device drivers. | |
1052 | */ | |
1053 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
1054 | { | |
448bd857 HY |
1055 | int ret; |
1056 | ||
db288c9c | 1057 | if (state <= PCI_D0) |
448bd857 HY |
1058 | return -EINVAL; |
1059 | ret = pci_platform_power_transition(dev, state); | |
1060 | /* Power off the bridge may power off the whole hierarchy */ | |
1061 | if (!ret && state == PCI_D3cold) | |
2a4d2c42 | 1062 | pci_bus_set_current_state(dev->subordinate, PCI_D3cold); |
448bd857 | 1063 | return ret; |
0e5dd46b RW |
1064 | } |
1065 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
1066 | ||
44e4e66e RW |
1067 | /** |
1068 | * pci_set_power_state - Set the power state of a PCI device | |
1069 | * @dev: PCI device to handle. | |
1070 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
1071 | * | |
877d0310 | 1072 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
1073 | * the device's PCI PM registers. |
1074 | * | |
1075 | * RETURN VALUE: | |
1076 | * -EINVAL if the requested state is invalid. | |
1077 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
1078 | * wrong version, or device doesn't support the requested state. | |
ab4b8a47 | 1079 | * 0 if the transition is to D1 or D2 but D1 and D2 are not supported. |
44e4e66e | 1080 | * 0 if device already is in the requested state. |
ab4b8a47 | 1081 | * 0 if the transition is to D3 but D3 is not supported. |
44e4e66e RW |
1082 | * 0 if device's power state has been successfully changed. |
1083 | */ | |
1084 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
1085 | { | |
337001b6 | 1086 | int error; |
44e4e66e RW |
1087 | |
1088 | /* bound the state we're entering */ | |
448bd857 HY |
1089 | if (state > PCI_D3cold) |
1090 | state = PCI_D3cold; | |
44e4e66e RW |
1091 | else if (state < PCI_D0) |
1092 | state = PCI_D0; | |
1093 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
1094 | /* | |
1095 | * If the device or the parent bridge do not support PCI PM, | |
1096 | * ignore the request if we're doing anything other than putting | |
1097 | * it into D0 (which would only happen on boot). | |
1098 | */ | |
1099 | return 0; | |
1100 | ||
db288c9c RW |
1101 | /* Check if we're already there */ |
1102 | if (dev->current_state == state) | |
1103 | return 0; | |
1104 | ||
0e5dd46b RW |
1105 | __pci_start_power_transition(dev, state); |
1106 | ||
979b1791 AC |
1107 | /* This device is quirked not to be put into D3, so |
1108 | don't put it in D3 */ | |
448bd857 | 1109 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 1110 | return 0; |
44e4e66e | 1111 | |
448bd857 HY |
1112 | /* |
1113 | * To put device in D3cold, we put device into D3hot in native | |
1114 | * way, then put device into D3cold with platform ops | |
1115 | */ | |
1116 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
1117 | PCI_D3hot : state); | |
44e4e66e | 1118 | |
0e5dd46b RW |
1119 | if (!__pci_complete_power_transition(dev, state)) |
1120 | error = 0; | |
44e4e66e RW |
1121 | |
1122 | return error; | |
1123 | } | |
b7fe9434 | 1124 | EXPORT_SYMBOL(pci_set_power_state); |
44e4e66e | 1125 | |
1da177e4 LT |
1126 | /** |
1127 | * pci_choose_state - Choose the power state of a PCI device | |
1128 | * @dev: PCI device to be suspended | |
1129 | * @state: target sleep state for the whole system. This is the value | |
1130 | * that is passed to suspend() function. | |
1131 | * | |
1132 | * Returns PCI power state suitable for given device and given system | |
1133 | * message. | |
1134 | */ | |
1135 | ||
1136 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
1137 | { | |
ab826ca4 | 1138 | pci_power_t ret; |
0f64474b | 1139 | |
728cdb75 | 1140 | if (!dev->pm_cap) |
1da177e4 LT |
1141 | return PCI_D0; |
1142 | ||
961d9120 RW |
1143 | ret = platform_pci_choose_state(dev); |
1144 | if (ret != PCI_POWER_ERROR) | |
1145 | return ret; | |
ca078bae PM |
1146 | |
1147 | switch (state.event) { | |
1148 | case PM_EVENT_ON: | |
1149 | return PCI_D0; | |
1150 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
1151 | case PM_EVENT_PRETHAW: |
1152 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 1153 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 1154 | case PM_EVENT_HIBERNATE: |
ca078bae | 1155 | return PCI_D3hot; |
1da177e4 | 1156 | default: |
7506dc79 | 1157 | pci_info(dev, "unrecognized suspend event %d\n", |
80ccba11 | 1158 | state.event); |
1da177e4 LT |
1159 | BUG(); |
1160 | } | |
1161 | return PCI_D0; | |
1162 | } | |
1da177e4 LT |
1163 | EXPORT_SYMBOL(pci_choose_state); |
1164 | ||
89858517 YZ |
1165 | #define PCI_EXP_SAVE_REGS 7 |
1166 | ||
fd0f7f73 AW |
1167 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
1168 | u16 cap, bool extended) | |
34a4876e YL |
1169 | { |
1170 | struct pci_cap_saved_state *tmp; | |
34a4876e | 1171 | |
b67bfe0d | 1172 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 1173 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
1174 | return tmp; |
1175 | } | |
1176 | return NULL; | |
1177 | } | |
1178 | ||
fd0f7f73 AW |
1179 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
1180 | { | |
1181 | return _pci_find_saved_cap(dev, cap, false); | |
1182 | } | |
1183 | ||
1184 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
1185 | { | |
1186 | return _pci_find_saved_cap(dev, cap, true); | |
1187 | } | |
1188 | ||
b56a5a23 MT |
1189 | static int pci_save_pcie_state(struct pci_dev *dev) |
1190 | { | |
59875ae4 | 1191 | int i = 0; |
b56a5a23 MT |
1192 | struct pci_cap_saved_state *save_state; |
1193 | u16 *cap; | |
1194 | ||
59875ae4 | 1195 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
1196 | return 0; |
1197 | ||
9f35575d | 1198 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 1199 | if (!save_state) { |
7506dc79 | 1200 | pci_err(dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
1201 | return -ENOMEM; |
1202 | } | |
63f4898a | 1203 | |
59875ae4 JL |
1204 | cap = (u16 *)&save_state->cap.data[0]; |
1205 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
1206 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
1207 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
1208 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
1209 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
1210 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
1211 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 1212 | |
b56a5a23 MT |
1213 | return 0; |
1214 | } | |
1215 | ||
1216 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
1217 | { | |
59875ae4 | 1218 | int i = 0; |
b56a5a23 MT |
1219 | struct pci_cap_saved_state *save_state; |
1220 | u16 *cap; | |
1221 | ||
1222 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 1223 | if (!save_state) |
9cb604ed MS |
1224 | return; |
1225 | ||
59875ae4 JL |
1226 | cap = (u16 *)&save_state->cap.data[0]; |
1227 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
1228 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
1229 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
1230 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
1231 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
1232 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
1233 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
1234 | } |
1235 | ||
cc692a5f SH |
1236 | static int pci_save_pcix_state(struct pci_dev *dev) |
1237 | { | |
63f4898a | 1238 | int pos; |
cc692a5f | 1239 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
1240 | |
1241 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1242 | if (!pos) |
cc692a5f SH |
1243 | return 0; |
1244 | ||
f34303de | 1245 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 1246 | if (!save_state) { |
7506dc79 | 1247 | pci_err(dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
1248 | return -ENOMEM; |
1249 | } | |
cc692a5f | 1250 | |
24a4742f AW |
1251 | pci_read_config_word(dev, pos + PCI_X_CMD, |
1252 | (u16 *)save_state->cap.data); | |
63f4898a | 1253 | |
cc692a5f SH |
1254 | return 0; |
1255 | } | |
1256 | ||
1257 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
1258 | { | |
1259 | int i = 0, pos; | |
1260 | struct pci_cap_saved_state *save_state; | |
1261 | u16 *cap; | |
1262 | ||
1263 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
1264 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1265 | if (!save_state || !pos) |
cc692a5f | 1266 | return; |
24a4742f | 1267 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
1268 | |
1269 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
1270 | } |
1271 | ||
dbbfadf2 BH |
1272 | static void pci_save_ltr_state(struct pci_dev *dev) |
1273 | { | |
1274 | int ltr; | |
1275 | struct pci_cap_saved_state *save_state; | |
1276 | u16 *cap; | |
1277 | ||
1278 | if (!pci_is_pcie(dev)) | |
1279 | return; | |
1280 | ||
1281 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1282 | if (!ltr) | |
1283 | return; | |
1284 | ||
1285 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1286 | if (!save_state) { | |
1287 | pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n"); | |
1288 | return; | |
1289 | } | |
1290 | ||
1291 | cap = (u16 *)&save_state->cap.data[0]; | |
1292 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++); | |
1293 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++); | |
1294 | } | |
1295 | ||
1296 | static void pci_restore_ltr_state(struct pci_dev *dev) | |
1297 | { | |
1298 | struct pci_cap_saved_state *save_state; | |
1299 | int ltr; | |
1300 | u16 *cap; | |
1301 | ||
1302 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1303 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1304 | if (!save_state || !ltr) | |
1305 | return; | |
1306 | ||
1307 | cap = (u16 *)&save_state->cap.data[0]; | |
1308 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++); | |
1309 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++); | |
1310 | } | |
cc692a5f | 1311 | |
1da177e4 LT |
1312 | /** |
1313 | * pci_save_state - save the PCI configuration space of a device before suspending | |
1314 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1315 | */ |
3c78bc61 | 1316 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1317 | { |
1318 | int i; | |
1319 | /* XXX: 100% dword access ok here? */ | |
1320 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 1321 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 1322 | dev->state_saved = true; |
79e50e72 QL |
1323 | |
1324 | i = pci_save_pcie_state(dev); | |
1325 | if (i != 0) | |
b56a5a23 | 1326 | return i; |
79e50e72 QL |
1327 | |
1328 | i = pci_save_pcix_state(dev); | |
1329 | if (i != 0) | |
cc692a5f | 1330 | return i; |
79e50e72 | 1331 | |
dbbfadf2 | 1332 | pci_save_ltr_state(dev); |
4f802170 | 1333 | pci_save_dpc_state(dev); |
754834b9 | 1334 | return pci_save_vc_state(dev); |
1da177e4 | 1335 | } |
b7fe9434 | 1336 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1337 | |
ebfc5b80 | 1338 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
08387454 | 1339 | u32 saved_val, int retry, bool force) |
ebfc5b80 RW |
1340 | { |
1341 | u32 val; | |
1342 | ||
1343 | pci_read_config_dword(pdev, offset, &val); | |
08387454 | 1344 | if (!force && val == saved_val) |
ebfc5b80 RW |
1345 | return; |
1346 | ||
1347 | for (;;) { | |
7506dc79 | 1348 | pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
227f0647 | 1349 | offset, val, saved_val); |
ebfc5b80 RW |
1350 | pci_write_config_dword(pdev, offset, saved_val); |
1351 | if (retry-- <= 0) | |
1352 | return; | |
1353 | ||
1354 | pci_read_config_dword(pdev, offset, &val); | |
1355 | if (val == saved_val) | |
1356 | return; | |
1357 | ||
1358 | mdelay(1); | |
1359 | } | |
1360 | } | |
1361 | ||
a6cb9ee7 | 1362 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
08387454 DD |
1363 | int start, int end, int retry, |
1364 | bool force) | |
ebfc5b80 RW |
1365 | { |
1366 | int index; | |
1367 | ||
1368 | for (index = end; index >= start; index--) | |
1369 | pci_restore_config_dword(pdev, 4 * index, | |
1370 | pdev->saved_config_space[index], | |
08387454 | 1371 | retry, force); |
ebfc5b80 RW |
1372 | } |
1373 | ||
a6cb9ee7 RW |
1374 | static void pci_restore_config_space(struct pci_dev *pdev) |
1375 | { | |
1376 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
08387454 | 1377 | pci_restore_config_space_range(pdev, 10, 15, 0, false); |
a6cb9ee7 | 1378 | /* Restore BARs before the command register. */ |
08387454 DD |
1379 | pci_restore_config_space_range(pdev, 4, 9, 10, false); |
1380 | pci_restore_config_space_range(pdev, 0, 3, 0, false); | |
1381 | } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1382 | pci_restore_config_space_range(pdev, 12, 15, 0, false); | |
1383 | ||
1384 | /* | |
1385 | * Force rewriting of prefetch registers to avoid S3 resume | |
1386 | * issues on Intel PCI bridges that occur when these | |
1387 | * registers are not explicitly written. | |
1388 | */ | |
1389 | pci_restore_config_space_range(pdev, 9, 11, 0, true); | |
1390 | pci_restore_config_space_range(pdev, 0, 8, 0, false); | |
a6cb9ee7 | 1391 | } else { |
08387454 | 1392 | pci_restore_config_space_range(pdev, 0, 15, 0, false); |
a6cb9ee7 RW |
1393 | } |
1394 | } | |
1395 | ||
d3252ace CK |
1396 | static void pci_restore_rebar_state(struct pci_dev *pdev) |
1397 | { | |
1398 | unsigned int pos, nbars, i; | |
1399 | u32 ctrl; | |
1400 | ||
1401 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
1402 | if (!pos) | |
1403 | return; | |
1404 | ||
1405 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1406 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
1407 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
1408 | ||
1409 | for (i = 0; i < nbars; i++, pos += 8) { | |
1410 | struct resource *res; | |
1411 | int bar_idx, size; | |
1412 | ||
1413 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1414 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
1415 | res = pdev->resource + bar_idx; | |
1416 | size = order_base_2((resource_size(res) >> 20) | 1) - 1; | |
1417 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; | |
b1277a22 | 1418 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
d3252ace CK |
1419 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
1420 | } | |
1421 | } | |
1422 | ||
f7625980 | 1423 | /** |
1da177e4 LT |
1424 | * pci_restore_state - Restore the saved state of a PCI device |
1425 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1426 | */ |
1d3c16a8 | 1427 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1428 | { |
c82f63e4 | 1429 | if (!dev->state_saved) |
1d3c16a8 | 1430 | return; |
4b77b0a2 | 1431 | |
dbbfadf2 BH |
1432 | /* |
1433 | * Restore max latencies (in the LTR capability) before enabling | |
1434 | * LTR itself (in the PCIe capability). | |
1435 | */ | |
1436 | pci_restore_ltr_state(dev); | |
1437 | ||
b56a5a23 | 1438 | pci_restore_pcie_state(dev); |
4ebeb1ec CT |
1439 | pci_restore_pasid_state(dev); |
1440 | pci_restore_pri_state(dev); | |
1900ca13 | 1441 | pci_restore_ats_state(dev); |
425c1b22 | 1442 | pci_restore_vc_state(dev); |
d3252ace | 1443 | pci_restore_rebar_state(dev); |
4f802170 | 1444 | pci_restore_dpc_state(dev); |
b56a5a23 | 1445 | |
b07461a8 TI |
1446 | pci_cleanup_aer_error_status_regs(dev); |
1447 | ||
a6cb9ee7 | 1448 | pci_restore_config_space(dev); |
ebfc5b80 | 1449 | |
cc692a5f | 1450 | pci_restore_pcix_state(dev); |
41017f0c | 1451 | pci_restore_msi_state(dev); |
ccbc175a AD |
1452 | |
1453 | /* Restore ACS and IOV configuration state */ | |
1454 | pci_enable_acs(dev); | |
8c5cdb6a | 1455 | pci_restore_iov_state(dev); |
8fed4b65 | 1456 | |
4b77b0a2 | 1457 | dev->state_saved = false; |
1da177e4 | 1458 | } |
b7fe9434 | 1459 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1460 | |
ffbdd3f7 AW |
1461 | struct pci_saved_state { |
1462 | u32 config_space[16]; | |
1463 | struct pci_cap_saved_data cap[0]; | |
1464 | }; | |
1465 | ||
1466 | /** | |
1467 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1468 | * the device saved state. | |
1469 | * @dev: PCI device that we're dealing with | |
1470 | * | |
f7625980 | 1471 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1472 | */ |
1473 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1474 | { | |
1475 | struct pci_saved_state *state; | |
1476 | struct pci_cap_saved_state *tmp; | |
1477 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1478 | size_t size; |
1479 | ||
1480 | if (!dev->state_saved) | |
1481 | return NULL; | |
1482 | ||
1483 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1484 | ||
b67bfe0d | 1485 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1486 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1487 | ||
1488 | state = kzalloc(size, GFP_KERNEL); | |
1489 | if (!state) | |
1490 | return NULL; | |
1491 | ||
1492 | memcpy(state->config_space, dev->saved_config_space, | |
1493 | sizeof(state->config_space)); | |
1494 | ||
1495 | cap = state->cap; | |
b67bfe0d | 1496 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1497 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1498 | memcpy(cap, &tmp->cap, len); | |
1499 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1500 | } | |
1501 | /* Empty cap_save terminates list */ | |
1502 | ||
1503 | return state; | |
1504 | } | |
1505 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1506 | ||
1507 | /** | |
1508 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1509 | * @dev: PCI device that we're dealing with | |
1510 | * @state: Saved state returned from pci_store_saved_state() | |
1511 | */ | |
98d9b271 KRW |
1512 | int pci_load_saved_state(struct pci_dev *dev, |
1513 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1514 | { |
1515 | struct pci_cap_saved_data *cap; | |
1516 | ||
1517 | dev->state_saved = false; | |
1518 | ||
1519 | if (!state) | |
1520 | return 0; | |
1521 | ||
1522 | memcpy(dev->saved_config_space, state->config_space, | |
1523 | sizeof(state->config_space)); | |
1524 | ||
1525 | cap = state->cap; | |
1526 | while (cap->size) { | |
1527 | struct pci_cap_saved_state *tmp; | |
1528 | ||
fd0f7f73 | 1529 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1530 | if (!tmp || tmp->cap.size != cap->size) |
1531 | return -EINVAL; | |
1532 | ||
1533 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1534 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1535 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1536 | } | |
1537 | ||
1538 | dev->state_saved = true; | |
1539 | return 0; | |
1540 | } | |
98d9b271 | 1541 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1542 | |
1543 | /** | |
1544 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1545 | * and free the memory allocated for it. | |
1546 | * @dev: PCI device that we're dealing with | |
1547 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1548 | */ | |
1549 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1550 | struct pci_saved_state **state) | |
1551 | { | |
1552 | int ret = pci_load_saved_state(dev, *state); | |
1553 | kfree(*state); | |
1554 | *state = NULL; | |
1555 | return ret; | |
1556 | } | |
1557 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1558 | ||
8a9d5609 BH |
1559 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1560 | { | |
1561 | return pci_enable_resources(dev, bars); | |
1562 | } | |
1563 | ||
38cc1302 HS |
1564 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1565 | { | |
1566 | int err; | |
1f6ae47e | 1567 | struct pci_dev *bridge; |
1e2571a7 BH |
1568 | u16 cmd; |
1569 | u8 pin; | |
38cc1302 HS |
1570 | |
1571 | err = pci_set_power_state(dev, PCI_D0); | |
1572 | if (err < 0 && err != -EIO) | |
1573 | return err; | |
1f6ae47e VS |
1574 | |
1575 | bridge = pci_upstream_bridge(dev); | |
1576 | if (bridge) | |
1577 | pcie_aspm_powersave_config_link(bridge); | |
1578 | ||
38cc1302 HS |
1579 | err = pcibios_enable_device(dev, bars); |
1580 | if (err < 0) | |
1581 | return err; | |
1582 | pci_fixup_device(pci_fixup_enable, dev); | |
1583 | ||
866d5417 BH |
1584 | if (dev->msi_enabled || dev->msix_enabled) |
1585 | return 0; | |
1586 | ||
1e2571a7 BH |
1587 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1588 | if (pin) { | |
1589 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1590 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1591 | pci_write_config_word(dev, PCI_COMMAND, | |
1592 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1593 | } | |
1594 | ||
38cc1302 HS |
1595 | return 0; |
1596 | } | |
1597 | ||
1598 | /** | |
0b62e13b | 1599 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1600 | * @dev: PCI device to be resumed |
1601 | * | |
1602 | * Note this function is a backend of pci_default_resume and is not supposed | |
1603 | * to be called by normal code, write proper resume handler and use it instead. | |
1604 | */ | |
0b62e13b | 1605 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1606 | { |
296ccb08 | 1607 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1608 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1609 | return 0; | |
1610 | } | |
b7fe9434 | 1611 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1612 | |
928bea96 YL |
1613 | static void pci_enable_bridge(struct pci_dev *dev) |
1614 | { | |
79272138 | 1615 | struct pci_dev *bridge; |
928bea96 YL |
1616 | int retval; |
1617 | ||
79272138 BH |
1618 | bridge = pci_upstream_bridge(dev); |
1619 | if (bridge) | |
1620 | pci_enable_bridge(bridge); | |
928bea96 | 1621 | |
cf3e1feb | 1622 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1623 | if (!dev->is_busmaster) |
cf3e1feb | 1624 | pci_set_master(dev); |
0f50a49e | 1625 | return; |
cf3e1feb YL |
1626 | } |
1627 | ||
928bea96 YL |
1628 | retval = pci_enable_device(dev); |
1629 | if (retval) | |
7506dc79 | 1630 | pci_err(dev, "Error enabling bridge (%d), continuing\n", |
928bea96 YL |
1631 | retval); |
1632 | pci_set_master(dev); | |
1633 | } | |
1634 | ||
b4b4fbba | 1635 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1636 | { |
79272138 | 1637 | struct pci_dev *bridge; |
1da177e4 | 1638 | int err; |
b718989d | 1639 | int i, bars = 0; |
1da177e4 | 1640 | |
97c145f7 JB |
1641 | /* |
1642 | * Power state could be unknown at this point, either due to a fresh | |
1643 | * boot or a device removal call. So get the current power state | |
1644 | * so that things like MSI message writing will behave as expected | |
1645 | * (e.g. if the device really is in D0 at enable time). | |
1646 | */ | |
1647 | if (dev->pm_cap) { | |
1648 | u16 pmcsr; | |
1649 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1650 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1651 | } | |
1652 | ||
cc7ba39b | 1653 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1654 | return 0; /* already enabled */ |
1655 | ||
79272138 | 1656 | bridge = pci_upstream_bridge(dev); |
0f50a49e | 1657 | if (bridge) |
79272138 | 1658 | pci_enable_bridge(bridge); |
928bea96 | 1659 | |
497f16f2 YL |
1660 | /* only skip sriov related */ |
1661 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1662 | if (dev->resource[i].flags & flags) | |
1663 | bars |= (1 << i); | |
1664 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1665 | if (dev->resource[i].flags & flags) |
1666 | bars |= (1 << i); | |
1667 | ||
38cc1302 | 1668 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1669 | if (err < 0) |
38cc1302 | 1670 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1671 | return err; |
1da177e4 LT |
1672 | } |
1673 | ||
b718989d BH |
1674 | /** |
1675 | * pci_enable_device_io - Initialize a device for use with IO space | |
1676 | * @dev: PCI device to be initialized | |
1677 | * | |
1678 | * Initialize device before it's used by a driver. Ask low-level code | |
1679 | * to enable I/O resources. Wake up the device if it was suspended. | |
1680 | * Beware, this function can fail. | |
1681 | */ | |
1682 | int pci_enable_device_io(struct pci_dev *dev) | |
1683 | { | |
b4b4fbba | 1684 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1685 | } |
b7fe9434 | 1686 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1687 | |
1688 | /** | |
1689 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1690 | * @dev: PCI device to be initialized | |
1691 | * | |
1692 | * Initialize device before it's used by a driver. Ask low-level code | |
1693 | * to enable Memory resources. Wake up the device if it was suspended. | |
1694 | * Beware, this function can fail. | |
1695 | */ | |
1696 | int pci_enable_device_mem(struct pci_dev *dev) | |
1697 | { | |
b4b4fbba | 1698 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1699 | } |
b7fe9434 | 1700 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1701 | |
bae94d02 IPG |
1702 | /** |
1703 | * pci_enable_device - Initialize device before it's used by a driver. | |
1704 | * @dev: PCI device to be initialized | |
1705 | * | |
1706 | * Initialize device before it's used by a driver. Ask low-level code | |
1707 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1708 | * Beware, this function can fail. | |
1709 | * | |
1710 | * Note we don't actually enable the device many times if we call | |
1711 | * this function repeatedly (we just increment the count). | |
1712 | */ | |
1713 | int pci_enable_device(struct pci_dev *dev) | |
1714 | { | |
b4b4fbba | 1715 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1716 | } |
b7fe9434 | 1717 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1718 | |
9ac7849e TH |
1719 | /* |
1720 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1721 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1722 | * there's no need to track it separately. pci_devres is initialized | |
1723 | * when a device is enabled using managed PCI device enable interface. | |
1724 | */ | |
1725 | struct pci_devres { | |
7f375f32 TH |
1726 | unsigned int enabled:1; |
1727 | unsigned int pinned:1; | |
9ac7849e TH |
1728 | unsigned int orig_intx:1; |
1729 | unsigned int restore_intx:1; | |
fc0f9f4d | 1730 | unsigned int mwi:1; |
9ac7849e TH |
1731 | u32 region_mask; |
1732 | }; | |
1733 | ||
1734 | static void pcim_release(struct device *gendev, void *res) | |
1735 | { | |
f3d2f165 | 1736 | struct pci_dev *dev = to_pci_dev(gendev); |
9ac7849e TH |
1737 | struct pci_devres *this = res; |
1738 | int i; | |
1739 | ||
1740 | if (dev->msi_enabled) | |
1741 | pci_disable_msi(dev); | |
1742 | if (dev->msix_enabled) | |
1743 | pci_disable_msix(dev); | |
1744 | ||
1745 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1746 | if (this->region_mask & (1 << i)) | |
1747 | pci_release_region(dev, i); | |
1748 | ||
fc0f9f4d HK |
1749 | if (this->mwi) |
1750 | pci_clear_mwi(dev); | |
1751 | ||
9ac7849e TH |
1752 | if (this->restore_intx) |
1753 | pci_intx(dev, this->orig_intx); | |
1754 | ||
7f375f32 | 1755 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1756 | pci_disable_device(dev); |
1757 | } | |
1758 | ||
07656d83 | 1759 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1760 | { |
1761 | struct pci_devres *dr, *new_dr; | |
1762 | ||
1763 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1764 | if (dr) | |
1765 | return dr; | |
1766 | ||
1767 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1768 | if (!new_dr) | |
1769 | return NULL; | |
1770 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1771 | } | |
1772 | ||
07656d83 | 1773 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1774 | { |
1775 | if (pci_is_managed(pdev)) | |
1776 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1777 | return NULL; | |
1778 | } | |
1779 | ||
1780 | /** | |
1781 | * pcim_enable_device - Managed pci_enable_device() | |
1782 | * @pdev: PCI device to be initialized | |
1783 | * | |
1784 | * Managed pci_enable_device(). | |
1785 | */ | |
1786 | int pcim_enable_device(struct pci_dev *pdev) | |
1787 | { | |
1788 | struct pci_devres *dr; | |
1789 | int rc; | |
1790 | ||
1791 | dr = get_pci_dr(pdev); | |
1792 | if (unlikely(!dr)) | |
1793 | return -ENOMEM; | |
b95d58ea TH |
1794 | if (dr->enabled) |
1795 | return 0; | |
9ac7849e TH |
1796 | |
1797 | rc = pci_enable_device(pdev); | |
1798 | if (!rc) { | |
1799 | pdev->is_managed = 1; | |
7f375f32 | 1800 | dr->enabled = 1; |
9ac7849e TH |
1801 | } |
1802 | return rc; | |
1803 | } | |
b7fe9434 | 1804 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
1805 | |
1806 | /** | |
1807 | * pcim_pin_device - Pin managed PCI device | |
1808 | * @pdev: PCI device to pin | |
1809 | * | |
1810 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1811 | * driver detach. @pdev must have been enabled with | |
1812 | * pcim_enable_device(). | |
1813 | */ | |
1814 | void pcim_pin_device(struct pci_dev *pdev) | |
1815 | { | |
1816 | struct pci_devres *dr; | |
1817 | ||
1818 | dr = find_pci_dr(pdev); | |
7f375f32 | 1819 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1820 | if (dr) |
7f375f32 | 1821 | dr->pinned = 1; |
9ac7849e | 1822 | } |
b7fe9434 | 1823 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 1824 | |
eca0d467 MG |
1825 | /* |
1826 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1827 | * @dev: the PCI device being added | |
1828 | * | |
1829 | * Permits the platform to provide architecture specific functionality when | |
1830 | * devices are added. This is the default implementation. Architecture | |
1831 | * implementations can override this. | |
1832 | */ | |
3c78bc61 | 1833 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
1834 | { |
1835 | return 0; | |
1836 | } | |
1837 | ||
6ae32c53 SO |
1838 | /** |
1839 | * pcibios_release_device - provide arch specific hooks when releasing device dev | |
1840 | * @dev: the PCI device being released | |
1841 | * | |
1842 | * Permits the platform to provide architecture specific functionality when | |
1843 | * devices are released. This is the default implementation. Architecture | |
1844 | * implementations can override this. | |
1845 | */ | |
1846 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1847 | ||
1da177e4 LT |
1848 | /** |
1849 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1850 | * @dev: the PCI device to disable | |
1851 | * | |
1852 | * Disables architecture specific PCI resources for the device. This | |
1853 | * is the default implementation. Architecture implementations can | |
1854 | * override this. | |
1855 | */ | |
ff3ce480 | 1856 | void __weak pcibios_disable_device(struct pci_dev *dev) {} |
1da177e4 | 1857 | |
a43ae58c HG |
1858 | /** |
1859 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
1860 | * @irq: ISA IRQ to penalize | |
1861 | * @active: IRQ active or not | |
1862 | * | |
1863 | * Permits the platform to provide architecture-specific functionality when | |
1864 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
1865 | * implementations can override this. | |
1866 | */ | |
1867 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
1868 | ||
fa58d305 RW |
1869 | static void do_pci_disable_device(struct pci_dev *dev) |
1870 | { | |
1871 | u16 pci_command; | |
1872 | ||
1873 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1874 | if (pci_command & PCI_COMMAND_MASTER) { | |
1875 | pci_command &= ~PCI_COMMAND_MASTER; | |
1876 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1877 | } | |
1878 | ||
1879 | pcibios_disable_device(dev); | |
1880 | } | |
1881 | ||
1882 | /** | |
1883 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1884 | * @dev: PCI device to disable | |
1885 | * | |
1886 | * NOTE: This function is a backend of PCI power management routines and is | |
1887 | * not supposed to be called drivers. | |
1888 | */ | |
1889 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1890 | { | |
296ccb08 | 1891 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1892 | do_pci_disable_device(dev); |
1893 | } | |
1894 | ||
1da177e4 LT |
1895 | /** |
1896 | * pci_disable_device - Disable PCI device after use | |
1897 | * @dev: PCI device to be disabled | |
1898 | * | |
1899 | * Signal to the system that the PCI device is not in use by the system | |
1900 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1901 | * |
1902 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1903 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 1904 | */ |
3c78bc61 | 1905 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 1906 | { |
9ac7849e | 1907 | struct pci_devres *dr; |
99dc804d | 1908 | |
9ac7849e TH |
1909 | dr = find_pci_dr(dev); |
1910 | if (dr) | |
7f375f32 | 1911 | dr->enabled = 0; |
9ac7849e | 1912 | |
fd6dceab KK |
1913 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1914 | "disabling already-disabled device"); | |
1915 | ||
cc7ba39b | 1916 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1917 | return; |
1918 | ||
fa58d305 | 1919 | do_pci_disable_device(dev); |
1da177e4 | 1920 | |
fa58d305 | 1921 | dev->is_busmaster = 0; |
1da177e4 | 1922 | } |
b7fe9434 | 1923 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 1924 | |
f7bdd12d BK |
1925 | /** |
1926 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1927 | * @dev: the PCIe device reset |
f7bdd12d BK |
1928 | * @state: Reset state to enter into |
1929 | * | |
1930 | * | |
45e829ea | 1931 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1932 | * implementation. Architecture implementations can override this. |
1933 | */ | |
d6d88c83 BH |
1934 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1935 | enum pcie_reset_state state) | |
f7bdd12d BK |
1936 | { |
1937 | return -EINVAL; | |
1938 | } | |
1939 | ||
1940 | /** | |
1941 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1942 | * @dev: the PCIe device reset |
f7bdd12d BK |
1943 | * @state: Reset state to enter into |
1944 | * | |
1945 | * | |
1946 | * Sets the PCI reset state for the device. | |
1947 | */ | |
1948 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1949 | { | |
1950 | return pcibios_set_pcie_reset_state(dev, state); | |
1951 | } | |
b7fe9434 | 1952 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 1953 | |
dcb0453d BH |
1954 | /** |
1955 | * pcie_clear_root_pme_status - Clear root port PME interrupt status. | |
1956 | * @dev: PCIe root port or event collector. | |
1957 | */ | |
1958 | void pcie_clear_root_pme_status(struct pci_dev *dev) | |
1959 | { | |
1960 | pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME); | |
1961 | } | |
1962 | ||
58ff4633 RW |
1963 | /** |
1964 | * pci_check_pme_status - Check if given device has generated PME. | |
1965 | * @dev: Device to check. | |
1966 | * | |
1967 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1968 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1969 | * 'false' otherwise. | |
1970 | */ | |
1971 | bool pci_check_pme_status(struct pci_dev *dev) | |
1972 | { | |
1973 | int pmcsr_pos; | |
1974 | u16 pmcsr; | |
1975 | bool ret = false; | |
1976 | ||
1977 | if (!dev->pm_cap) | |
1978 | return false; | |
1979 | ||
1980 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1981 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1982 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1983 | return false; | |
1984 | ||
1985 | /* Clear PME status. */ | |
1986 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1987 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1988 | /* Disable PME to avoid interrupt flood. */ | |
1989 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1990 | ret = true; | |
1991 | } | |
1992 | ||
1993 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1994 | ||
1995 | return ret; | |
1996 | } | |
1997 | ||
b67ea761 RW |
1998 | /** |
1999 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
2000 | * @dev: Device to handle. | |
379021d5 | 2001 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
2002 | * |
2003 | * Check if @dev has generated PME and queue a resume request for it in that | |
2004 | * case. | |
2005 | */ | |
379021d5 | 2006 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 2007 | { |
379021d5 RW |
2008 | if (pme_poll_reset && dev->pme_poll) |
2009 | dev->pme_poll = false; | |
2010 | ||
c125e96f | 2011 | if (pci_check_pme_status(dev)) { |
c125e96f | 2012 | pci_wakeup_event(dev); |
0f953bf6 | 2013 | pm_request_resume(&dev->dev); |
c125e96f | 2014 | } |
b67ea761 RW |
2015 | return 0; |
2016 | } | |
2017 | ||
2018 | /** | |
2019 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
2020 | * @bus: Top bus of the subtree to walk. | |
2021 | */ | |
2022 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
2023 | { | |
2024 | if (bus) | |
379021d5 | 2025 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
2026 | } |
2027 | ||
448bd857 | 2028 | |
eb9d0fe4 RW |
2029 | /** |
2030 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
2031 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
2032 | * @state: PCI state from which device will issue PME#. |
2033 | */ | |
e5899e1b | 2034 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 2035 | { |
337001b6 | 2036 | if (!dev->pm_cap) |
eb9d0fe4 RW |
2037 | return false; |
2038 | ||
337001b6 | 2039 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 2040 | } |
b7fe9434 | 2041 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 2042 | |
df17e62e MG |
2043 | static void pci_pme_list_scan(struct work_struct *work) |
2044 | { | |
379021d5 | 2045 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
2046 | |
2047 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
2048 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
2049 | if (pme_dev->dev->pme_poll) { | |
2050 | struct pci_dev *bridge; | |
2051 | ||
2052 | bridge = pme_dev->dev->bus->self; | |
2053 | /* | |
2054 | * If bridge is in low power state, the | |
2055 | * configuration space of subordinate devices | |
2056 | * may be not accessible | |
2057 | */ | |
2058 | if (bridge && bridge->current_state != PCI_D0) | |
2059 | continue; | |
2060 | pci_pme_wakeup(pme_dev->dev, NULL); | |
2061 | } else { | |
2062 | list_del(&pme_dev->list); | |
2063 | kfree(pme_dev); | |
379021d5 | 2064 | } |
df17e62e | 2065 | } |
ce300008 | 2066 | if (!list_empty(&pci_pme_list)) |
ea00353f LW |
2067 | queue_delayed_work(system_freezable_wq, &pci_pme_work, |
2068 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2069 | mutex_unlock(&pci_pme_list_mutex); |
2070 | } | |
2071 | ||
2cef548a | 2072 | static void __pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
2073 | { |
2074 | u16 pmcsr; | |
2075 | ||
ffaddbe8 | 2076 | if (!dev->pme_support) |
eb9d0fe4 RW |
2077 | return; |
2078 | ||
337001b6 | 2079 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
2080 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
2081 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
2082 | if (!enable) | |
2083 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2084 | ||
337001b6 | 2085 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
2cef548a RW |
2086 | } |
2087 | ||
0ce3fcaf RW |
2088 | /** |
2089 | * pci_pme_restore - Restore PME configuration after config space restore. | |
2090 | * @dev: PCI device to update. | |
2091 | */ | |
2092 | void pci_pme_restore(struct pci_dev *dev) | |
dc15e71e RW |
2093 | { |
2094 | u16 pmcsr; | |
2095 | ||
2096 | if (!dev->pme_support) | |
2097 | return; | |
2098 | ||
2099 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
2100 | if (dev->wakeup_prepared) { | |
2101 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
0ce3fcaf | 2102 | pmcsr &= ~PCI_PM_CTRL_PME_STATUS; |
dc15e71e RW |
2103 | } else { |
2104 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2105 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
2106 | } | |
2107 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); | |
2108 | } | |
2109 | ||
2cef548a RW |
2110 | /** |
2111 | * pci_pme_active - enable or disable PCI device's PME# function | |
2112 | * @dev: PCI device to handle. | |
2113 | * @enable: 'true' to enable PME# generation; 'false' to disable it. | |
2114 | * | |
2115 | * The caller must verify that the device is capable of generating PME# before | |
2116 | * calling this function with @enable equal to 'true'. | |
2117 | */ | |
2118 | void pci_pme_active(struct pci_dev *dev, bool enable) | |
2119 | { | |
2120 | __pci_pme_active(dev, enable); | |
eb9d0fe4 | 2121 | |
6e965e0d HY |
2122 | /* |
2123 | * PCI (as opposed to PCIe) PME requires that the device have | |
2124 | * its PME# line hooked up correctly. Not all hardware vendors | |
2125 | * do this, so the PME never gets delivered and the device | |
2126 | * remains asleep. The easiest way around this is to | |
2127 | * periodically walk the list of suspended devices and check | |
2128 | * whether any have their PME flag set. The assumption is that | |
2129 | * we'll wake up often enough anyway that this won't be a huge | |
2130 | * hit, and the power savings from the devices will still be a | |
2131 | * win. | |
2132 | * | |
2133 | * Although PCIe uses in-band PME message instead of PME# line | |
2134 | * to report PME, PME does not work for some PCIe devices in | |
2135 | * reality. For example, there are devices that set their PME | |
2136 | * status bits, but don't really bother to send a PME message; | |
2137 | * there are PCI Express Root Ports that don't bother to | |
2138 | * trigger interrupts when they receive PME messages from the | |
2139 | * devices below. So PME poll is used for PCIe devices too. | |
2140 | */ | |
df17e62e | 2141 | |
379021d5 | 2142 | if (dev->pme_poll) { |
df17e62e MG |
2143 | struct pci_pme_device *pme_dev; |
2144 | if (enable) { | |
2145 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
2146 | GFP_KERNEL); | |
0394cb19 | 2147 | if (!pme_dev) { |
7506dc79 | 2148 | pci_warn(dev, "can't enable PME#\n"); |
0394cb19 BH |
2149 | return; |
2150 | } | |
df17e62e MG |
2151 | pme_dev->dev = dev; |
2152 | mutex_lock(&pci_pme_list_mutex); | |
2153 | list_add(&pme_dev->list, &pci_pme_list); | |
2154 | if (list_is_singular(&pci_pme_list)) | |
ea00353f LW |
2155 | queue_delayed_work(system_freezable_wq, |
2156 | &pci_pme_work, | |
2157 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2158 | mutex_unlock(&pci_pme_list_mutex); |
2159 | } else { | |
2160 | mutex_lock(&pci_pme_list_mutex); | |
2161 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
2162 | if (pme_dev->dev == dev) { | |
2163 | list_del(&pme_dev->list); | |
2164 | kfree(pme_dev); | |
2165 | break; | |
2166 | } | |
2167 | } | |
2168 | mutex_unlock(&pci_pme_list_mutex); | |
2169 | } | |
2170 | } | |
2171 | ||
7506dc79 | 2172 | pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 2173 | } |
b7fe9434 | 2174 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 2175 | |
1da177e4 | 2176 | /** |
cfcadfaa | 2177 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
2178 | * @dev: PCI device affected |
2179 | * @state: PCI state from which device will issue wakeup events | |
2180 | * @enable: True to enable event generation; false to disable | |
2181 | * | |
2182 | * This enables the device as a wakeup event source, or disables it. | |
2183 | * When such events involves platform-specific hooks, those hooks are | |
2184 | * called automatically by this routine. | |
2185 | * | |
2186 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 2187 | * always require such platform hooks. |
075c1771 | 2188 | * |
eb9d0fe4 RW |
2189 | * RETURN VALUE: |
2190 | * 0 is returned on success | |
2191 | * -EINVAL is returned if device is not supposed to wake up the system | |
2192 | * Error code depending on the platform is returned if both the platform and | |
2193 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 2194 | */ |
cfcadfaa | 2195 | static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) |
1da177e4 | 2196 | { |
5bcc2fb4 | 2197 | int ret = 0; |
075c1771 | 2198 | |
baecc470 | 2199 | /* |
ac86e8ee MW |
2200 | * Bridges that are not power-manageable directly only signal |
2201 | * wakeup on behalf of subordinate devices which is set up | |
2202 | * elsewhere, so skip them. However, bridges that are | |
2203 | * power-manageable may signal wakeup for themselves (for example, | |
2204 | * on a hotplug event) and they need to be covered here. | |
baecc470 | 2205 | */ |
ac86e8ee | 2206 | if (!pci_power_manageable(dev)) |
baecc470 RW |
2207 | return 0; |
2208 | ||
0ce3fcaf RW |
2209 | /* Don't do the same thing twice in a row for one device. */ |
2210 | if (!!enable == !!dev->wakeup_prepared) | |
e80bb09d RW |
2211 | return 0; |
2212 | ||
eb9d0fe4 RW |
2213 | /* |
2214 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
2215 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
2216 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 2217 | */ |
1da177e4 | 2218 | |
5bcc2fb4 RW |
2219 | if (enable) { |
2220 | int error; | |
1da177e4 | 2221 | |
5bcc2fb4 RW |
2222 | if (pci_pme_capable(dev, state)) |
2223 | pci_pme_active(dev, true); | |
2224 | else | |
2225 | ret = 1; | |
0847684c | 2226 | error = platform_pci_set_wakeup(dev, true); |
5bcc2fb4 RW |
2227 | if (ret) |
2228 | ret = error; | |
e80bb09d RW |
2229 | if (!ret) |
2230 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 2231 | } else { |
0847684c | 2232 | platform_pci_set_wakeup(dev, false); |
5bcc2fb4 | 2233 | pci_pme_active(dev, false); |
e80bb09d | 2234 | dev->wakeup_prepared = false; |
5bcc2fb4 | 2235 | } |
1da177e4 | 2236 | |
5bcc2fb4 | 2237 | return ret; |
eb9d0fe4 | 2238 | } |
cfcadfaa RW |
2239 | |
2240 | /** | |
2241 | * pci_enable_wake - change wakeup settings for a PCI device | |
2242 | * @pci_dev: Target device | |
2243 | * @state: PCI state from which device will issue wakeup events | |
2244 | * @enable: Whether or not to enable event generation | |
2245 | * | |
2246 | * If @enable is set, check device_may_wakeup() for the device before calling | |
2247 | * __pci_enable_wake() for it. | |
2248 | */ | |
2249 | int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable) | |
2250 | { | |
2251 | if (enable && !device_may_wakeup(&pci_dev->dev)) | |
2252 | return -EINVAL; | |
2253 | ||
2254 | return __pci_enable_wake(pci_dev, state, enable); | |
2255 | } | |
0847684c | 2256 | EXPORT_SYMBOL(pci_enable_wake); |
1da177e4 | 2257 | |
0235c4fc RW |
2258 | /** |
2259 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
2260 | * @dev: PCI device to prepare | |
2261 | * @enable: True to enable wake-up event generation; false to disable | |
2262 | * | |
2263 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
2264 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
2265 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
2266 | * ordering constraints. | |
2267 | * | |
cfcadfaa RW |
2268 | * This function only returns error code if the device is not allowed to wake |
2269 | * up the system from sleep or it is not capable of generating PME# from both | |
2270 | * D3_hot and D3_cold and the platform is unable to enable wake-up power for it. | |
0235c4fc RW |
2271 | */ |
2272 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
2273 | { | |
2274 | return pci_pme_capable(dev, PCI_D3cold) ? | |
2275 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
2276 | pci_enable_wake(dev, PCI_D3hot, enable); | |
2277 | } | |
b7fe9434 | 2278 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 2279 | |
404cc2d8 | 2280 | /** |
37139074 JB |
2281 | * pci_target_state - find an appropriate low power state for a given PCI dev |
2282 | * @dev: PCI device | |
666ff6f8 | 2283 | * @wakeup: Whether or not wakeup functionality will be enabled for the device. |
37139074 JB |
2284 | * |
2285 | * Use underlying platform code to find a supported low power state for @dev. | |
2286 | * If the platform can't manage @dev, return the deepest state from which it | |
2287 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 2288 | */ |
666ff6f8 | 2289 | static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup) |
404cc2d8 RW |
2290 | { |
2291 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
2292 | |
2293 | if (platform_pci_power_manageable(dev)) { | |
2294 | /* | |
60ee031a | 2295 | * Call the platform to find the target state for the device. |
404cc2d8 RW |
2296 | */ |
2297 | pci_power_t state = platform_pci_choose_state(dev); | |
2298 | ||
2299 | switch (state) { | |
2300 | case PCI_POWER_ERROR: | |
2301 | case PCI_UNKNOWN: | |
2302 | break; | |
2303 | case PCI_D1: | |
2304 | case PCI_D2: | |
2305 | if (pci_no_d1d2(dev)) | |
2306 | break; | |
1d09d577 | 2307 | /* else, fall through */ |
404cc2d8 RW |
2308 | default: |
2309 | target_state = state; | |
404cc2d8 | 2310 | } |
4132a577 LW |
2311 | |
2312 | return target_state; | |
2313 | } | |
2314 | ||
2315 | if (!dev->pm_cap) | |
d2abdf62 | 2316 | target_state = PCI_D0; |
4132a577 LW |
2317 | |
2318 | /* | |
2319 | * If the device is in D3cold even though it's not power-manageable by | |
2320 | * the platform, it may have been powered down by non-standard means. | |
2321 | * Best to let it slumber. | |
2322 | */ | |
2323 | if (dev->current_state == PCI_D3cold) | |
2324 | target_state = PCI_D3cold; | |
2325 | ||
666ff6f8 | 2326 | if (wakeup) { |
404cc2d8 RW |
2327 | /* |
2328 | * Find the deepest state from which the device can generate | |
60ee031a | 2329 | * PME#. |
404cc2d8 | 2330 | */ |
337001b6 RW |
2331 | if (dev->pme_support) { |
2332 | while (target_state | |
2333 | && !(dev->pme_support & (1 << target_state))) | |
2334 | target_state--; | |
404cc2d8 RW |
2335 | } |
2336 | } | |
2337 | ||
e5899e1b RW |
2338 | return target_state; |
2339 | } | |
2340 | ||
2341 | /** | |
2342 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
2343 | * @dev: Device to handle. | |
2344 | * | |
2345 | * Choose the power state appropriate for the device depending on whether | |
2346 | * it can wake up the system and/or is power manageable by the platform | |
2347 | * (PCI_D3hot is the default) and put the device into that state. | |
2348 | */ | |
2349 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
2350 | { | |
666ff6f8 RW |
2351 | bool wakeup = device_may_wakeup(&dev->dev); |
2352 | pci_power_t target_state = pci_target_state(dev, wakeup); | |
e5899e1b RW |
2353 | int error; |
2354 | ||
2355 | if (target_state == PCI_POWER_ERROR) | |
2356 | return -EIO; | |
2357 | ||
666ff6f8 | 2358 | pci_enable_wake(dev, target_state, wakeup); |
c157dfa3 | 2359 | |
404cc2d8 RW |
2360 | error = pci_set_power_state(dev, target_state); |
2361 | ||
2362 | if (error) | |
2363 | pci_enable_wake(dev, target_state, false); | |
2364 | ||
2365 | return error; | |
2366 | } | |
b7fe9434 | 2367 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
2368 | |
2369 | /** | |
443bd1c4 | 2370 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
2371 | * @dev: Device to handle. |
2372 | * | |
88393161 | 2373 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
2374 | */ |
2375 | int pci_back_from_sleep(struct pci_dev *dev) | |
2376 | { | |
2377 | pci_enable_wake(dev, PCI_D0, false); | |
2378 | return pci_set_power_state(dev, PCI_D0); | |
2379 | } | |
b7fe9434 | 2380 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 2381 | |
6cbf8214 RW |
2382 | /** |
2383 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
2384 | * @dev: PCI device being suspended. | |
2385 | * | |
2386 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
2387 | * power state. | |
2388 | */ | |
2389 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
2390 | { | |
666ff6f8 | 2391 | pci_power_t target_state; |
6cbf8214 RW |
2392 | int error; |
2393 | ||
666ff6f8 | 2394 | target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); |
6cbf8214 RW |
2395 | if (target_state == PCI_POWER_ERROR) |
2396 | return -EIO; | |
2397 | ||
448bd857 HY |
2398 | dev->runtime_d3cold = target_state == PCI_D3cold; |
2399 | ||
cfcadfaa | 2400 | __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev)); |
6cbf8214 RW |
2401 | |
2402 | error = pci_set_power_state(dev, target_state); | |
2403 | ||
448bd857 | 2404 | if (error) { |
0847684c | 2405 | pci_enable_wake(dev, target_state, false); |
448bd857 HY |
2406 | dev->runtime_d3cold = false; |
2407 | } | |
6cbf8214 RW |
2408 | |
2409 | return error; | |
2410 | } | |
2411 | ||
b67ea761 RW |
2412 | /** |
2413 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
2414 | * @dev: Device to check. | |
2415 | * | |
f7625980 | 2416 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
2417 | * (through the platform or using the native PCIe PME) or if the device supports |
2418 | * PME and one of its upstream bridges can generate wake-up events. | |
2419 | */ | |
2420 | bool pci_dev_run_wake(struct pci_dev *dev) | |
2421 | { | |
2422 | struct pci_bus *bus = dev->bus; | |
2423 | ||
b67ea761 RW |
2424 | if (!dev->pme_support) |
2425 | return false; | |
2426 | ||
666ff6f8 | 2427 | /* PME-capable in principle, but not from the target power state */ |
8feaec33 | 2428 | if (!pci_pme_capable(dev, pci_target_state(dev, true))) |
6496ebd7 AS |
2429 | return false; |
2430 | ||
8feaec33 KHF |
2431 | if (device_can_wakeup(&dev->dev)) |
2432 | return true; | |
2433 | ||
b67ea761 RW |
2434 | while (bus->parent) { |
2435 | struct pci_dev *bridge = bus->self; | |
2436 | ||
de3ef1eb | 2437 | if (device_can_wakeup(&bridge->dev)) |
b67ea761 RW |
2438 | return true; |
2439 | ||
2440 | bus = bus->parent; | |
2441 | } | |
2442 | ||
2443 | /* We have reached the root bus. */ | |
2444 | if (bus->bridge) | |
de3ef1eb | 2445 | return device_can_wakeup(bus->bridge); |
b67ea761 RW |
2446 | |
2447 | return false; | |
2448 | } | |
2449 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2450 | ||
bac2a909 RW |
2451 | /** |
2452 | * pci_dev_keep_suspended - Check if the device can stay in the suspended state. | |
2453 | * @pci_dev: Device to check. | |
2454 | * | |
2455 | * Return 'true' if the device is runtime-suspended, it doesn't have to be | |
2456 | * reconfigured due to wakeup settings difference between system and runtime | |
2457 | * suspend and the current power state of it is suitable for the upcoming | |
2458 | * (system) transition. | |
2cef548a RW |
2459 | * |
2460 | * If the device is not configured for system wakeup, disable PME for it before | |
2461 | * returning 'true' to prevent it from waking up the system unnecessarily. | |
bac2a909 RW |
2462 | */ |
2463 | bool pci_dev_keep_suspended(struct pci_dev *pci_dev) | |
2464 | { | |
2465 | struct device *dev = &pci_dev->dev; | |
666ff6f8 | 2466 | bool wakeup = device_may_wakeup(dev); |
bac2a909 RW |
2467 | |
2468 | if (!pm_runtime_suspended(dev) | |
666ff6f8 | 2469 | || pci_target_state(pci_dev, wakeup) != pci_dev->current_state |
c2eac4d3 | 2470 | || platform_pci_need_resume(pci_dev)) |
bac2a909 RW |
2471 | return false; |
2472 | ||
2cef548a RW |
2473 | /* |
2474 | * At this point the device is good to go unless it's been configured | |
2475 | * to generate PME at the runtime suspend time, but it is not supposed | |
2476 | * to wake up the system. In that case, simply disable PME for it | |
2477 | * (it will have to be re-enabled on exit from system resume). | |
2478 | * | |
2479 | * If the device's power state is D3cold and the platform check above | |
2480 | * hasn't triggered, the device's configuration is suitable and we don't | |
2481 | * need to manipulate it at all. | |
2482 | */ | |
2483 | spin_lock_irq(&dev->power.lock); | |
2484 | ||
2485 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold && | |
666ff6f8 | 2486 | !wakeup) |
2cef548a RW |
2487 | __pci_pme_active(pci_dev, false); |
2488 | ||
2489 | spin_unlock_irq(&dev->power.lock); | |
2490 | return true; | |
2491 | } | |
2492 | ||
2493 | /** | |
2494 | * pci_dev_complete_resume - Finalize resume from system sleep for a device. | |
2495 | * @pci_dev: Device to handle. | |
2496 | * | |
2497 | * If the device is runtime suspended and wakeup-capable, enable PME for it as | |
2498 | * it might have been disabled during the prepare phase of system suspend if | |
2499 | * the device was not configured for system wakeup. | |
2500 | */ | |
2501 | void pci_dev_complete_resume(struct pci_dev *pci_dev) | |
2502 | { | |
2503 | struct device *dev = &pci_dev->dev; | |
2504 | ||
2505 | if (!pci_dev_run_wake(pci_dev)) | |
2506 | return; | |
2507 | ||
2508 | spin_lock_irq(&dev->power.lock); | |
2509 | ||
2510 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) | |
2511 | __pci_pme_active(pci_dev, true); | |
2512 | ||
2513 | spin_unlock_irq(&dev->power.lock); | |
bac2a909 RW |
2514 | } |
2515 | ||
b3c32c4f HY |
2516 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2517 | { | |
2518 | struct device *dev = &pdev->dev; | |
2519 | struct device *parent = dev->parent; | |
2520 | ||
2521 | if (parent) | |
2522 | pm_runtime_get_sync(parent); | |
2523 | pm_runtime_get_noresume(dev); | |
2524 | /* | |
2525 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2526 | * so wait until suspending completes | |
2527 | */ | |
2528 | pm_runtime_barrier(dev); | |
2529 | /* | |
2530 | * Only need to resume devices in D3cold, because config | |
2531 | * registers are still accessible for devices suspended but | |
2532 | * not in D3cold. | |
2533 | */ | |
2534 | if (pdev->current_state == PCI_D3cold) | |
2535 | pm_runtime_resume(dev); | |
2536 | } | |
2537 | ||
2538 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2539 | { | |
2540 | struct device *dev = &pdev->dev; | |
2541 | struct device *parent = dev->parent; | |
2542 | ||
2543 | pm_runtime_put(dev); | |
2544 | if (parent) | |
2545 | pm_runtime_put_sync(parent); | |
2546 | } | |
2547 | ||
85b0cae8 MW |
2548 | static const struct dmi_system_id bridge_d3_blacklist[] = { |
2549 | #ifdef CONFIG_X86 | |
2550 | { | |
2551 | /* | |
2552 | * Gigabyte X299 root port is not marked as hotplug capable | |
2553 | * which allows Linux to power manage it. However, this | |
2554 | * confuses the BIOS SMI handler so don't power manage root | |
2555 | * ports on that system. | |
2556 | */ | |
2557 | .ident = "X299 DESIGNARE EX-CF", | |
2558 | .matches = { | |
2559 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
2560 | DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"), | |
2561 | }, | |
2562 | }, | |
2563 | #endif | |
2564 | { } | |
2565 | }; | |
2566 | ||
9d26d3a8 MW |
2567 | /** |
2568 | * pci_bridge_d3_possible - Is it possible to put the bridge into D3 | |
2569 | * @bridge: Bridge to check | |
2570 | * | |
2571 | * This function checks if it is possible to move the bridge to D3. | |
47a8e237 | 2572 | * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt. |
9d26d3a8 | 2573 | */ |
c6a63307 | 2574 | bool pci_bridge_d3_possible(struct pci_dev *bridge) |
9d26d3a8 | 2575 | { |
9d26d3a8 MW |
2576 | if (!pci_is_pcie(bridge)) |
2577 | return false; | |
2578 | ||
2579 | switch (pci_pcie_type(bridge)) { | |
2580 | case PCI_EXP_TYPE_ROOT_PORT: | |
2581 | case PCI_EXP_TYPE_UPSTREAM: | |
2582 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2583 | if (pci_bridge_d3_disable) | |
2584 | return false; | |
97a90aee LW |
2585 | |
2586 | /* | |
eb3b5bf1 | 2587 | * Hotplug ports handled by firmware in System Management Mode |
97a90aee | 2588 | * may not be put into D3 by the OS (Thunderbolt on non-Macs). |
97a90aee | 2589 | */ |
eb3b5bf1 | 2590 | if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) |
97a90aee LW |
2591 | return false; |
2592 | ||
9d26d3a8 MW |
2593 | if (pci_bridge_d3_force) |
2594 | return true; | |
2595 | ||
47a8e237 LW |
2596 | /* Even the oldest 2010 Thunderbolt controller supports D3. */ |
2597 | if (bridge->is_thunderbolt) | |
2598 | return true; | |
2599 | ||
26ad34d5 MW |
2600 | /* Platform might know better if the bridge supports D3 */ |
2601 | if (platform_pci_bridge_d3(bridge)) | |
2602 | return true; | |
2603 | ||
eb3b5bf1 LW |
2604 | /* |
2605 | * Hotplug ports handled natively by the OS were not validated | |
2606 | * by vendors for runtime D3 at least until 2018 because there | |
2607 | * was no OS support. | |
2608 | */ | |
2609 | if (bridge->is_hotplug_bridge) | |
2610 | return false; | |
2611 | ||
85b0cae8 MW |
2612 | if (dmi_check_system(bridge_d3_blacklist)) |
2613 | return false; | |
2614 | ||
9d26d3a8 MW |
2615 | /* |
2616 | * It should be safe to put PCIe ports from 2015 or newer | |
2617 | * to D3. | |
2618 | */ | |
ac95090a | 2619 | if (dmi_get_bios_year() >= 2015) |
9d26d3a8 | 2620 | return true; |
9d26d3a8 MW |
2621 | break; |
2622 | } | |
2623 | ||
2624 | return false; | |
2625 | } | |
2626 | ||
2627 | static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) | |
2628 | { | |
2629 | bool *d3cold_ok = data; | |
9d26d3a8 | 2630 | |
718a0609 LW |
2631 | if (/* The device needs to be allowed to go D3cold ... */ |
2632 | dev->no_d3cold || !dev->d3cold_allowed || | |
2633 | ||
2634 | /* ... and if it is wakeup capable to do so from D3cold. */ | |
2635 | (device_may_wakeup(&dev->dev) && | |
2636 | !pci_pme_capable(dev, PCI_D3cold)) || | |
2637 | ||
2638 | /* If it is a bridge it must be allowed to go to D3. */ | |
d98e0929 | 2639 | !pci_power_manageable(dev)) |
9d26d3a8 | 2640 | |
718a0609 | 2641 | *d3cold_ok = false; |
9d26d3a8 | 2642 | |
718a0609 | 2643 | return !*d3cold_ok; |
9d26d3a8 MW |
2644 | } |
2645 | ||
2646 | /* | |
2647 | * pci_bridge_d3_update - Update bridge D3 capabilities | |
2648 | * @dev: PCI device which is changed | |
9d26d3a8 MW |
2649 | * |
2650 | * Update upstream bridge PM capabilities accordingly depending on if the | |
2651 | * device PM configuration was changed or the device is being removed. The | |
2652 | * change is also propagated upstream. | |
2653 | */ | |
1ed276a7 | 2654 | void pci_bridge_d3_update(struct pci_dev *dev) |
9d26d3a8 | 2655 | { |
1ed276a7 | 2656 | bool remove = !device_is_registered(&dev->dev); |
9d26d3a8 MW |
2657 | struct pci_dev *bridge; |
2658 | bool d3cold_ok = true; | |
2659 | ||
2660 | bridge = pci_upstream_bridge(dev); | |
2661 | if (!bridge || !pci_bridge_d3_possible(bridge)) | |
2662 | return; | |
2663 | ||
9d26d3a8 | 2664 | /* |
e8559b71 LW |
2665 | * If D3 is currently allowed for the bridge, removing one of its |
2666 | * children won't change that. | |
2667 | */ | |
2668 | if (remove && bridge->bridge_d3) | |
2669 | return; | |
2670 | ||
2671 | /* | |
2672 | * If D3 is currently allowed for the bridge and a child is added or | |
2673 | * changed, disallowance of D3 can only be caused by that child, so | |
2674 | * we only need to check that single device, not any of its siblings. | |
2675 | * | |
2676 | * If D3 is currently not allowed for the bridge, checking the device | |
2677 | * first may allow us to skip checking its siblings. | |
9d26d3a8 MW |
2678 | */ |
2679 | if (!remove) | |
2680 | pci_dev_check_d3cold(dev, &d3cold_ok); | |
2681 | ||
e8559b71 LW |
2682 | /* |
2683 | * If D3 is currently not allowed for the bridge, this may be caused | |
2684 | * either by the device being changed/removed or any of its siblings, | |
2685 | * so we need to go through all children to find out if one of them | |
2686 | * continues to block D3. | |
2687 | */ | |
2688 | if (d3cold_ok && !bridge->bridge_d3) | |
9d26d3a8 MW |
2689 | pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, |
2690 | &d3cold_ok); | |
9d26d3a8 MW |
2691 | |
2692 | if (bridge->bridge_d3 != d3cold_ok) { | |
2693 | bridge->bridge_d3 = d3cold_ok; | |
2694 | /* Propagate change to upstream bridges */ | |
1ed276a7 | 2695 | pci_bridge_d3_update(bridge); |
9d26d3a8 | 2696 | } |
9d26d3a8 MW |
2697 | } |
2698 | ||
9d26d3a8 MW |
2699 | /** |
2700 | * pci_d3cold_enable - Enable D3cold for device | |
2701 | * @dev: PCI device to handle | |
2702 | * | |
2703 | * This function can be used in drivers to enable D3cold from the device | |
2704 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2705 | * accordingly. | |
2706 | */ | |
2707 | void pci_d3cold_enable(struct pci_dev *dev) | |
2708 | { | |
2709 | if (dev->no_d3cold) { | |
2710 | dev->no_d3cold = false; | |
1ed276a7 | 2711 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2712 | } |
2713 | } | |
2714 | EXPORT_SYMBOL_GPL(pci_d3cold_enable); | |
2715 | ||
2716 | /** | |
2717 | * pci_d3cold_disable - Disable D3cold for device | |
2718 | * @dev: PCI device to handle | |
2719 | * | |
2720 | * This function can be used in drivers to disable D3cold from the device | |
2721 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2722 | * accordingly. | |
2723 | */ | |
2724 | void pci_d3cold_disable(struct pci_dev *dev) | |
2725 | { | |
2726 | if (!dev->no_d3cold) { | |
2727 | dev->no_d3cold = true; | |
1ed276a7 | 2728 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2729 | } |
2730 | } | |
2731 | EXPORT_SYMBOL_GPL(pci_d3cold_disable); | |
2732 | ||
eb9d0fe4 RW |
2733 | /** |
2734 | * pci_pm_init - Initialize PM functions of given PCI device | |
2735 | * @dev: PCI device to handle. | |
2736 | */ | |
2737 | void pci_pm_init(struct pci_dev *dev) | |
2738 | { | |
2739 | int pm; | |
d6112f8d | 2740 | u16 status; |
eb9d0fe4 | 2741 | u16 pmc; |
1da177e4 | 2742 | |
bb910a70 | 2743 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2744 | pm_runtime_set_active(&dev->dev); |
2745 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2746 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2747 | dev->wakeup_prepared = false; |
bb910a70 | 2748 | |
337001b6 | 2749 | dev->pm_cap = 0; |
ffaddbe8 | 2750 | dev->pme_support = 0; |
337001b6 | 2751 | |
eb9d0fe4 RW |
2752 | /* find PCI PM capability in list */ |
2753 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
2754 | if (!pm) | |
50246dd4 | 2755 | return; |
eb9d0fe4 RW |
2756 | /* Check device's ability to generate PME# */ |
2757 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 2758 | |
eb9d0fe4 | 2759 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
7506dc79 | 2760 | pci_err(dev, "unsupported PM cap regs version (%u)\n", |
eb9d0fe4 | 2761 | pmc & PCI_PM_CAP_VER_MASK); |
50246dd4 | 2762 | return; |
eb9d0fe4 RW |
2763 | } |
2764 | ||
337001b6 | 2765 | dev->pm_cap = pm; |
1ae861e6 | 2766 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 2767 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
9d26d3a8 | 2768 | dev->bridge_d3 = pci_bridge_d3_possible(dev); |
4f9c1397 | 2769 | dev->d3cold_allowed = true; |
337001b6 RW |
2770 | |
2771 | dev->d1_support = false; | |
2772 | dev->d2_support = false; | |
2773 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 2774 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 2775 | dev->d1_support = true; |
c9ed77ee | 2776 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 2777 | dev->d2_support = true; |
c9ed77ee BH |
2778 | |
2779 | if (dev->d1_support || dev->d2_support) | |
7506dc79 | 2780 | pci_printk(KERN_DEBUG, dev, "supports%s%s\n", |
ec84f126 JB |
2781 | dev->d1_support ? " D1" : "", |
2782 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
2783 | } |
2784 | ||
2785 | pmc &= PCI_PM_CAP_PME_MASK; | |
2786 | if (pmc) { | |
7506dc79 | 2787 | pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n", |
c9ed77ee BH |
2788 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
2789 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
2790 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2791 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2792 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2793 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2794 | dev->pme_poll = true; |
eb9d0fe4 RW |
2795 | /* |
2796 | * Make device's PM flags reflect the wake-up capability, but | |
2797 | * let the user space enable it to wake up the system as needed. | |
2798 | */ | |
2799 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2800 | /* Disable the PME# generation functionality */ |
337001b6 | 2801 | pci_pme_active(dev, false); |
eb9d0fe4 | 2802 | } |
d6112f8d FB |
2803 | |
2804 | pci_read_config_word(dev, PCI_STATUS, &status); | |
2805 | if (status & PCI_STATUS_IMM_READY) | |
2806 | dev->imm_ready = 1; | |
1da177e4 LT |
2807 | } |
2808 | ||
938174e5 SS |
2809 | static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) |
2810 | { | |
92efb1bd | 2811 | unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; |
938174e5 SS |
2812 | |
2813 | switch (prop) { | |
2814 | case PCI_EA_P_MEM: | |
2815 | case PCI_EA_P_VF_MEM: | |
2816 | flags |= IORESOURCE_MEM; | |
2817 | break; | |
2818 | case PCI_EA_P_MEM_PREFETCH: | |
2819 | case PCI_EA_P_VF_MEM_PREFETCH: | |
2820 | flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
2821 | break; | |
2822 | case PCI_EA_P_IO: | |
2823 | flags |= IORESOURCE_IO; | |
2824 | break; | |
2825 | default: | |
2826 | return 0; | |
2827 | } | |
2828 | ||
2829 | return flags; | |
2830 | } | |
2831 | ||
2832 | static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, | |
2833 | u8 prop) | |
2834 | { | |
2835 | if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) | |
2836 | return &dev->resource[bei]; | |
11183991 DD |
2837 | #ifdef CONFIG_PCI_IOV |
2838 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && | |
2839 | (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) | |
2840 | return &dev->resource[PCI_IOV_RESOURCES + | |
2841 | bei - PCI_EA_BEI_VF_BAR0]; | |
2842 | #endif | |
938174e5 SS |
2843 | else if (bei == PCI_EA_BEI_ROM) |
2844 | return &dev->resource[PCI_ROM_RESOURCE]; | |
2845 | else | |
2846 | return NULL; | |
2847 | } | |
2848 | ||
2849 | /* Read an Enhanced Allocation (EA) entry */ | |
2850 | static int pci_ea_read(struct pci_dev *dev, int offset) | |
2851 | { | |
2852 | struct resource *res; | |
2853 | int ent_size, ent_offset = offset; | |
2854 | resource_size_t start, end; | |
2855 | unsigned long flags; | |
26635112 | 2856 | u32 dw0, bei, base, max_offset; |
938174e5 SS |
2857 | u8 prop; |
2858 | bool support_64 = (sizeof(resource_size_t) >= 8); | |
2859 | ||
2860 | pci_read_config_dword(dev, ent_offset, &dw0); | |
2861 | ent_offset += 4; | |
2862 | ||
2863 | /* Entry size field indicates DWORDs after 1st */ | |
2864 | ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; | |
2865 | ||
2866 | if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ | |
2867 | goto out; | |
2868 | ||
26635112 BH |
2869 | bei = (dw0 & PCI_EA_BEI) >> 4; |
2870 | prop = (dw0 & PCI_EA_PP) >> 8; | |
2871 | ||
938174e5 SS |
2872 | /* |
2873 | * If the Property is in the reserved range, try the Secondary | |
2874 | * Property instead. | |
2875 | */ | |
2876 | if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) | |
26635112 | 2877 | prop = (dw0 & PCI_EA_SP) >> 16; |
938174e5 SS |
2878 | if (prop > PCI_EA_P_BRIDGE_IO) |
2879 | goto out; | |
2880 | ||
26635112 | 2881 | res = pci_ea_get_resource(dev, bei, prop); |
938174e5 | 2882 | if (!res) { |
7506dc79 | 2883 | pci_err(dev, "Unsupported EA entry BEI: %u\n", bei); |
938174e5 SS |
2884 | goto out; |
2885 | } | |
2886 | ||
2887 | flags = pci_ea_flags(dev, prop); | |
2888 | if (!flags) { | |
7506dc79 | 2889 | pci_err(dev, "Unsupported EA properties: %#x\n", prop); |
938174e5 SS |
2890 | goto out; |
2891 | } | |
2892 | ||
2893 | /* Read Base */ | |
2894 | pci_read_config_dword(dev, ent_offset, &base); | |
2895 | start = (base & PCI_EA_FIELD_MASK); | |
2896 | ent_offset += 4; | |
2897 | ||
2898 | /* Read MaxOffset */ | |
2899 | pci_read_config_dword(dev, ent_offset, &max_offset); | |
2900 | ent_offset += 4; | |
2901 | ||
2902 | /* Read Base MSBs (if 64-bit entry) */ | |
2903 | if (base & PCI_EA_IS_64) { | |
2904 | u32 base_upper; | |
2905 | ||
2906 | pci_read_config_dword(dev, ent_offset, &base_upper); | |
2907 | ent_offset += 4; | |
2908 | ||
2909 | flags |= IORESOURCE_MEM_64; | |
2910 | ||
2911 | /* entry starts above 32-bit boundary, can't use */ | |
2912 | if (!support_64 && base_upper) | |
2913 | goto out; | |
2914 | ||
2915 | if (support_64) | |
2916 | start |= ((u64)base_upper << 32); | |
2917 | } | |
2918 | ||
2919 | end = start + (max_offset | 0x03); | |
2920 | ||
2921 | /* Read MaxOffset MSBs (if 64-bit entry) */ | |
2922 | if (max_offset & PCI_EA_IS_64) { | |
2923 | u32 max_offset_upper; | |
2924 | ||
2925 | pci_read_config_dword(dev, ent_offset, &max_offset_upper); | |
2926 | ent_offset += 4; | |
2927 | ||
2928 | flags |= IORESOURCE_MEM_64; | |
2929 | ||
2930 | /* entry too big, can't use */ | |
2931 | if (!support_64 && max_offset_upper) | |
2932 | goto out; | |
2933 | ||
2934 | if (support_64) | |
2935 | end += ((u64)max_offset_upper << 32); | |
2936 | } | |
2937 | ||
2938 | if (end < start) { | |
7506dc79 | 2939 | pci_err(dev, "EA Entry crosses address boundary\n"); |
938174e5 SS |
2940 | goto out; |
2941 | } | |
2942 | ||
2943 | if (ent_size != ent_offset - offset) { | |
7506dc79 | 2944 | pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n", |
938174e5 SS |
2945 | ent_size, ent_offset - offset); |
2946 | goto out; | |
2947 | } | |
2948 | ||
2949 | res->name = pci_name(dev); | |
2950 | res->start = start; | |
2951 | res->end = end; | |
2952 | res->flags = flags; | |
597becb4 BH |
2953 | |
2954 | if (bei <= PCI_EA_BEI_BAR5) | |
7506dc79 | 2955 | pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
2956 | bei, res, prop); |
2957 | else if (bei == PCI_EA_BEI_ROM) | |
7506dc79 | 2958 | pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
2959 | res, prop); |
2960 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) | |
7506dc79 | 2961 | pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
2962 | bei - PCI_EA_BEI_VF_BAR0, res, prop); |
2963 | else | |
7506dc79 | 2964 | pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
2965 | bei, res, prop); |
2966 | ||
938174e5 SS |
2967 | out: |
2968 | return offset + ent_size; | |
2969 | } | |
2970 | ||
dcbb408a | 2971 | /* Enhanced Allocation Initialization */ |
938174e5 SS |
2972 | void pci_ea_init(struct pci_dev *dev) |
2973 | { | |
2974 | int ea; | |
2975 | u8 num_ent; | |
2976 | int offset; | |
2977 | int i; | |
2978 | ||
2979 | /* find PCI EA capability in list */ | |
2980 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
2981 | if (!ea) | |
2982 | return; | |
2983 | ||
2984 | /* determine the number of entries */ | |
2985 | pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, | |
2986 | &num_ent); | |
2987 | num_ent &= PCI_EA_NUM_ENT_MASK; | |
2988 | ||
2989 | offset = ea + PCI_EA_FIRST_ENT; | |
2990 | ||
2991 | /* Skip DWORD 2 for type 1 functions */ | |
2992 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
2993 | offset += 4; | |
2994 | ||
2995 | /* parse each EA entry */ | |
2996 | for (i = 0; i < num_ent; ++i) | |
2997 | offset = pci_ea_read(dev, offset); | |
2998 | } | |
2999 | ||
34a4876e YL |
3000 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
3001 | struct pci_cap_saved_state *new_cap) | |
3002 | { | |
3003 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
3004 | } | |
3005 | ||
63f4898a | 3006 | /** |
fd0f7f73 AW |
3007 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
3008 | * capability registers | |
63f4898a RW |
3009 | * @dev: the PCI device |
3010 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 3011 | * @extended: Standard or Extended capability ID |
63f4898a RW |
3012 | * @size: requested size of the buffer |
3013 | */ | |
fd0f7f73 AW |
3014 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
3015 | bool extended, unsigned int size) | |
63f4898a RW |
3016 | { |
3017 | int pos; | |
3018 | struct pci_cap_saved_state *save_state; | |
3019 | ||
fd0f7f73 AW |
3020 | if (extended) |
3021 | pos = pci_find_ext_capability(dev, cap); | |
3022 | else | |
3023 | pos = pci_find_capability(dev, cap); | |
3024 | ||
0a1a9b49 | 3025 | if (!pos) |
63f4898a RW |
3026 | return 0; |
3027 | ||
3028 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
3029 | if (!save_state) | |
3030 | return -ENOMEM; | |
3031 | ||
24a4742f | 3032 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 3033 | save_state->cap.cap_extended = extended; |
24a4742f | 3034 | save_state->cap.size = size; |
63f4898a RW |
3035 | pci_add_saved_cap(dev, save_state); |
3036 | ||
3037 | return 0; | |
3038 | } | |
3039 | ||
fd0f7f73 AW |
3040 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
3041 | { | |
3042 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
3043 | } | |
3044 | ||
3045 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
3046 | { | |
3047 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
3048 | } | |
3049 | ||
63f4898a RW |
3050 | /** |
3051 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
3052 | * @dev: the PCI device | |
3053 | */ | |
3054 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
3055 | { | |
3056 | int error; | |
3057 | ||
89858517 YZ |
3058 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
3059 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a | 3060 | if (error) |
7506dc79 | 3061 | pci_err(dev, "unable to preallocate PCI Express save buffer\n"); |
63f4898a RW |
3062 | |
3063 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
3064 | if (error) | |
7506dc79 | 3065 | pci_err(dev, "unable to preallocate PCI-X save buffer\n"); |
425c1b22 | 3066 | |
dbbfadf2 BH |
3067 | error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR, |
3068 | 2 * sizeof(u16)); | |
3069 | if (error) | |
3070 | pci_err(dev, "unable to allocate suspend buffer for LTR\n"); | |
3071 | ||
425c1b22 | 3072 | pci_allocate_vc_save_buffers(dev); |
63f4898a RW |
3073 | } |
3074 | ||
f796841e YL |
3075 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
3076 | { | |
3077 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 3078 | struct hlist_node *n; |
f796841e | 3079 | |
b67bfe0d | 3080 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
3081 | kfree(tmp); |
3082 | } | |
3083 | ||
58c3a727 | 3084 | /** |
31ab2476 | 3085 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 3086 | * @dev: the PCI device |
b0cc6020 YW |
3087 | * |
3088 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
3089 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 3090 | */ |
31ab2476 | 3091 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 3092 | { |
58c3a727 | 3093 | u32 cap; |
8113587c | 3094 | struct pci_dev *bridge; |
58c3a727 | 3095 | |
6748dcc2 | 3096 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
3097 | return; |
3098 | ||
8113587c | 3099 | bridge = dev->bus->self; |
cb97ae34 | 3100 | if (!bridge) |
8113587c ZY |
3101 | return; |
3102 | ||
59875ae4 | 3103 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
3104 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
3105 | return; | |
3106 | ||
b0cc6020 YW |
3107 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
3108 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
3109 | PCI_EXP_DEVCTL2_ARI); | |
3110 | bridge->ari_enabled = 1; | |
3111 | } else { | |
3112 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
3113 | PCI_EXP_DEVCTL2_ARI); | |
3114 | bridge->ari_enabled = 0; | |
3115 | } | |
58c3a727 YZ |
3116 | } |
3117 | ||
5d990b62 CW |
3118 | static int pci_acs_enable; |
3119 | ||
3120 | /** | |
3121 | * pci_request_acs - ask for ACS to be enabled if supported | |
3122 | */ | |
3123 | void pci_request_acs(void) | |
3124 | { | |
3125 | pci_acs_enable = 1; | |
3126 | } | |
3127 | ||
aaca43fd LG |
3128 | static const char *disable_acs_redir_param; |
3129 | ||
3130 | /** | |
3131 | * pci_disable_acs_redir - disable ACS redirect capabilities | |
3132 | * @dev: the PCI device | |
3133 | * | |
3134 | * For only devices specified in the disable_acs_redir parameter. | |
3135 | */ | |
3136 | static void pci_disable_acs_redir(struct pci_dev *dev) | |
3137 | { | |
3138 | int ret = 0; | |
3139 | const char *p; | |
3140 | int pos; | |
3141 | u16 ctrl; | |
3142 | ||
3143 | if (!disable_acs_redir_param) | |
3144 | return; | |
3145 | ||
3146 | p = disable_acs_redir_param; | |
3147 | while (*p) { | |
3148 | ret = pci_dev_str_match(dev, p, &p); | |
3149 | if (ret < 0) { | |
3150 | pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n", | |
3151 | disable_acs_redir_param); | |
3152 | ||
3153 | break; | |
3154 | } else if (ret == 1) { | |
3155 | /* Found a match */ | |
3156 | break; | |
3157 | } | |
3158 | ||
3159 | if (*p != ';' && *p != ',') { | |
3160 | /* End of param or invalid format */ | |
3161 | break; | |
3162 | } | |
3163 | p++; | |
3164 | } | |
3165 | ||
3166 | if (ret != 1) | |
3167 | return; | |
3168 | ||
73c47dde LG |
3169 | if (!pci_dev_specific_disable_acs_redir(dev)) |
3170 | return; | |
3171 | ||
aaca43fd LG |
3172 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
3173 | if (!pos) { | |
3174 | pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n"); | |
3175 | return; | |
3176 | } | |
3177 | ||
3178 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
3179 | ||
3180 | /* P2P Request & Completion Redirect */ | |
3181 | ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); | |
3182 | ||
3183 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
3184 | ||
3185 | pci_info(dev, "disabled ACS redirect\n"); | |
3186 | } | |
3187 | ||
ae21ee65 | 3188 | /** |
2c744244 | 3189 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites |
ae21ee65 AK |
3190 | * @dev: the PCI device |
3191 | */ | |
c1d61c9b | 3192 | static void pci_std_enable_acs(struct pci_dev *dev) |
ae21ee65 AK |
3193 | { |
3194 | int pos; | |
3195 | u16 cap; | |
3196 | u16 ctrl; | |
3197 | ||
ae21ee65 AK |
3198 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
3199 | if (!pos) | |
c1d61c9b | 3200 | return; |
ae21ee65 AK |
3201 | |
3202 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
3203 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
3204 | ||
3205 | /* Source Validation */ | |
3206 | ctrl |= (cap & PCI_ACS_SV); | |
3207 | ||
3208 | /* P2P Request Redirect */ | |
3209 | ctrl |= (cap & PCI_ACS_RR); | |
3210 | ||
3211 | /* P2P Completion Redirect */ | |
3212 | ctrl |= (cap & PCI_ACS_CR); | |
3213 | ||
3214 | /* Upstream Forwarding */ | |
3215 | ctrl |= (cap & PCI_ACS_UF); | |
3216 | ||
3217 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2c744244 AW |
3218 | } |
3219 | ||
3220 | /** | |
3221 | * pci_enable_acs - enable ACS if hardware support it | |
3222 | * @dev: the PCI device | |
3223 | */ | |
3224 | void pci_enable_acs(struct pci_dev *dev) | |
3225 | { | |
3226 | if (!pci_acs_enable) | |
aaca43fd | 3227 | goto disable_acs_redir; |
2c744244 | 3228 | |
c1d61c9b | 3229 | if (!pci_dev_specific_enable_acs(dev)) |
aaca43fd | 3230 | goto disable_acs_redir; |
2c744244 | 3231 | |
c1d61c9b | 3232 | pci_std_enable_acs(dev); |
aaca43fd LG |
3233 | |
3234 | disable_acs_redir: | |
3235 | /* | |
3236 | * Note: pci_disable_acs_redir() must be called even if ACS was not | |
3237 | * enabled by the kernel because it may have been enabled by | |
3238 | * platform firmware. So if we are told to disable it, we should | |
3239 | * always disable it after setting the kernel's default | |
3240 | * preferences. | |
3241 | */ | |
3242 | pci_disable_acs_redir(dev); | |
ae21ee65 AK |
3243 | } |
3244 | ||
0a67119f AW |
3245 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
3246 | { | |
3247 | int pos; | |
83db7e0b | 3248 | u16 cap, ctrl; |
0a67119f AW |
3249 | |
3250 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
3251 | if (!pos) | |
3252 | return false; | |
3253 | ||
83db7e0b AW |
3254 | /* |
3255 | * Except for egress control, capabilities are either required | |
3256 | * or only required if controllable. Features missing from the | |
3257 | * capability field can therefore be assumed as hard-wired enabled. | |
3258 | */ | |
3259 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
3260 | acs_flags &= (cap | PCI_ACS_EC); | |
3261 | ||
0a67119f AW |
3262 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
3263 | return (ctrl & acs_flags) == acs_flags; | |
3264 | } | |
3265 | ||
ad805758 AW |
3266 | /** |
3267 | * pci_acs_enabled - test ACS against required flags for a given device | |
3268 | * @pdev: device to test | |
3269 | * @acs_flags: required PCI ACS flags | |
3270 | * | |
3271 | * Return true if the device supports the provided flags. Automatically | |
3272 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
3273 | * |
3274 | * Note that this interface checks the effective ACS capabilities of the | |
3275 | * device rather than the actual capabilities. For instance, most single | |
3276 | * function endpoints are not required to support ACS because they have no | |
3277 | * opportunity for peer-to-peer access. We therefore return 'true' | |
3278 | * regardless of whether the device exposes an ACS capability. This makes | |
3279 | * it much easier for callers of this function to ignore the actual type | |
3280 | * or topology of the device when testing ACS support. | |
ad805758 AW |
3281 | */ |
3282 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
3283 | { | |
0a67119f | 3284 | int ret; |
ad805758 AW |
3285 | |
3286 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
3287 | if (ret >= 0) | |
3288 | return ret > 0; | |
3289 | ||
0a67119f AW |
3290 | /* |
3291 | * Conventional PCI and PCI-X devices never support ACS, either | |
3292 | * effectively or actually. The shared bus topology implies that | |
3293 | * any device on the bus can receive or snoop DMA. | |
3294 | */ | |
ad805758 AW |
3295 | if (!pci_is_pcie(pdev)) |
3296 | return false; | |
3297 | ||
0a67119f AW |
3298 | switch (pci_pcie_type(pdev)) { |
3299 | /* | |
3300 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 3301 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
3302 | * handle them as we would a non-PCIe device. |
3303 | */ | |
3304 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
3305 | /* | |
3306 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
3307 | * applicable... must never implement an ACS Extended Capability...". | |
3308 | * This seems arbitrary, but we take a conservative interpretation | |
3309 | * of this statement. | |
3310 | */ | |
3311 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
3312 | case PCI_EXP_TYPE_RC_EC: | |
3313 | return false; | |
3314 | /* | |
3315 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
3316 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
3317 | * regardless of whether they are single- or multi-function devices. | |
3318 | */ | |
3319 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3320 | case PCI_EXP_TYPE_ROOT_PORT: | |
3321 | return pci_acs_flags_enabled(pdev, acs_flags); | |
3322 | /* | |
3323 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
3324 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 3325 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
3326 | * device. The footnote for section 6.12 indicates the specific |
3327 | * PCIe types included here. | |
3328 | */ | |
3329 | case PCI_EXP_TYPE_ENDPOINT: | |
3330 | case PCI_EXP_TYPE_UPSTREAM: | |
3331 | case PCI_EXP_TYPE_LEG_END: | |
3332 | case PCI_EXP_TYPE_RC_END: | |
3333 | if (!pdev->multifunction) | |
3334 | break; | |
3335 | ||
0a67119f | 3336 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
3337 | } |
3338 | ||
0a67119f | 3339 | /* |
f7625980 | 3340 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
3341 | * to single function devices with the exception of downstream ports. |
3342 | */ | |
ad805758 AW |
3343 | return true; |
3344 | } | |
3345 | ||
3346 | /** | |
3347 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
3348 | * @start: starting downstream device | |
3349 | * @end: ending upstream device or NULL to search to the root bus | |
3350 | * @acs_flags: required flags | |
3351 | * | |
3352 | * Walk up a device tree from start to end testing PCI ACS support. If | |
3353 | * any step along the way does not support the required flags, return false. | |
3354 | */ | |
3355 | bool pci_acs_path_enabled(struct pci_dev *start, | |
3356 | struct pci_dev *end, u16 acs_flags) | |
3357 | { | |
3358 | struct pci_dev *pdev, *parent = start; | |
3359 | ||
3360 | do { | |
3361 | pdev = parent; | |
3362 | ||
3363 | if (!pci_acs_enabled(pdev, acs_flags)) | |
3364 | return false; | |
3365 | ||
3366 | if (pci_is_root_bus(pdev->bus)) | |
3367 | return (end == NULL); | |
3368 | ||
3369 | parent = pdev->bus->self; | |
3370 | } while (pdev != end); | |
3371 | ||
3372 | return true; | |
3373 | } | |
3374 | ||
276b738d CK |
3375 | /** |
3376 | * pci_rebar_find_pos - find position of resize ctrl reg for BAR | |
3377 | * @pdev: PCI device | |
3378 | * @bar: BAR to find | |
3379 | * | |
3380 | * Helper to find the position of the ctrl register for a BAR. | |
3381 | * Returns -ENOTSUPP if resizable BARs are not supported at all. | |
3382 | * Returns -ENOENT if no ctrl register for the BAR could be found. | |
3383 | */ | |
3384 | static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) | |
3385 | { | |
3386 | unsigned int pos, nbars, i; | |
3387 | u32 ctrl; | |
3388 | ||
3389 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
3390 | if (!pos) | |
3391 | return -ENOTSUPP; | |
3392 | ||
3393 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3394 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
3395 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
3396 | ||
3397 | for (i = 0; i < nbars; i++, pos += 8) { | |
3398 | int bar_idx; | |
3399 | ||
3400 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3401 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
3402 | if (bar_idx == bar) | |
3403 | return pos; | |
3404 | } | |
3405 | ||
3406 | return -ENOENT; | |
3407 | } | |
3408 | ||
3409 | /** | |
3410 | * pci_rebar_get_possible_sizes - get possible sizes for BAR | |
3411 | * @pdev: PCI device | |
3412 | * @bar: BAR to query | |
3413 | * | |
3414 | * Get the possible sizes of a resizable BAR as bitmask defined in the spec | |
3415 | * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable. | |
3416 | */ | |
3417 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) | |
3418 | { | |
3419 | int pos; | |
3420 | u32 cap; | |
3421 | ||
3422 | pos = pci_rebar_find_pos(pdev, bar); | |
3423 | if (pos < 0) | |
3424 | return 0; | |
3425 | ||
3426 | pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); | |
3427 | return (cap & PCI_REBAR_CAP_SIZES) >> 4; | |
3428 | } | |
3429 | ||
3430 | /** | |
3431 | * pci_rebar_get_current_size - get the current size of a BAR | |
3432 | * @pdev: PCI device | |
3433 | * @bar: BAR to set size to | |
3434 | * | |
3435 | * Read the size of a BAR from the resizable BAR config. | |
3436 | * Returns size if found or negative error code. | |
3437 | */ | |
3438 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) | |
3439 | { | |
3440 | int pos; | |
3441 | u32 ctrl; | |
3442 | ||
3443 | pos = pci_rebar_find_pos(pdev, bar); | |
3444 | if (pos < 0) | |
3445 | return pos; | |
3446 | ||
3447 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
b1277a22 | 3448 | return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3449 | } |
3450 | ||
3451 | /** | |
3452 | * pci_rebar_set_size - set a new size for a BAR | |
3453 | * @pdev: PCI device | |
3454 | * @bar: BAR to set size to | |
3455 | * @size: new size as defined in the spec (0=1MB, 19=512GB) | |
3456 | * | |
3457 | * Set the new size of a BAR as defined in the spec. | |
3458 | * Returns zero if resizing was successful, error code otherwise. | |
3459 | */ | |
3460 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) | |
3461 | { | |
3462 | int pos; | |
3463 | u32 ctrl; | |
3464 | ||
3465 | pos = pci_rebar_find_pos(pdev, bar); | |
3466 | if (pos < 0) | |
3467 | return pos; | |
3468 | ||
3469 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3470 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; | |
b1277a22 | 3471 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3472 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
3473 | return 0; | |
3474 | } | |
3475 | ||
430a2368 JC |
3476 | /** |
3477 | * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port | |
3478 | * @dev: the PCI device | |
3479 | * @cap_mask: mask of desired AtomicOp sizes, including one or more of: | |
3480 | * PCI_EXP_DEVCAP2_ATOMIC_COMP32 | |
3481 | * PCI_EXP_DEVCAP2_ATOMIC_COMP64 | |
3482 | * PCI_EXP_DEVCAP2_ATOMIC_COMP128 | |
3483 | * | |
3484 | * Return 0 if all upstream bridges support AtomicOp routing, egress | |
3485 | * blocking is disabled on all upstream ports, and the root port supports | |
3486 | * the requested completion capabilities (32-bit, 64-bit and/or 128-bit | |
3487 | * AtomicOp completion), or negative otherwise. | |
3488 | */ | |
3489 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) | |
3490 | { | |
3491 | struct pci_bus *bus = dev->bus; | |
3492 | struct pci_dev *bridge; | |
3493 | u32 cap, ctl2; | |
3494 | ||
3495 | if (!pci_is_pcie(dev)) | |
3496 | return -EINVAL; | |
3497 | ||
3498 | /* | |
3499 | * Per PCIe r4.0, sec 6.15, endpoints and root ports may be | |
3500 | * AtomicOp requesters. For now, we only support endpoints as | |
3501 | * requesters and root ports as completers. No endpoints as | |
3502 | * completers, and no peer-to-peer. | |
3503 | */ | |
3504 | ||
3505 | switch (pci_pcie_type(dev)) { | |
3506 | case PCI_EXP_TYPE_ENDPOINT: | |
3507 | case PCI_EXP_TYPE_LEG_END: | |
3508 | case PCI_EXP_TYPE_RC_END: | |
3509 | break; | |
3510 | default: | |
3511 | return -EINVAL; | |
3512 | } | |
3513 | ||
3514 | while (bus->parent) { | |
3515 | bridge = bus->self; | |
3516 | ||
3517 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); | |
3518 | ||
3519 | switch (pci_pcie_type(bridge)) { | |
3520 | /* Ensure switch ports support AtomicOp routing */ | |
3521 | case PCI_EXP_TYPE_UPSTREAM: | |
3522 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3523 | if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) | |
3524 | return -EINVAL; | |
3525 | break; | |
3526 | ||
3527 | /* Ensure root port supports all the sizes we care about */ | |
3528 | case PCI_EXP_TYPE_ROOT_PORT: | |
3529 | if ((cap & cap_mask) != cap_mask) | |
3530 | return -EINVAL; | |
3531 | break; | |
3532 | } | |
3533 | ||
3534 | /* Ensure upstream ports don't block AtomicOps on egress */ | |
3535 | if (!bridge->has_secondary_link) { | |
3536 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, | |
3537 | &ctl2); | |
3538 | if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) | |
3539 | return -EINVAL; | |
3540 | } | |
3541 | ||
3542 | bus = bus->parent; | |
3543 | } | |
3544 | ||
3545 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, | |
3546 | PCI_EXP_DEVCTL2_ATOMIC_REQ); | |
3547 | return 0; | |
3548 | } | |
3549 | EXPORT_SYMBOL(pci_enable_atomic_ops_to_root); | |
3550 | ||
57c2cf71 BH |
3551 | /** |
3552 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
3553 | * @dev: the PCI device | |
bb5c2de2 | 3554 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
3555 | * |
3556 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
3557 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
3558 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
3559 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
3560 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 3561 | */ |
3df425f3 | 3562 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 3563 | { |
46b952a3 MW |
3564 | int slot; |
3565 | ||
3566 | if (pci_ari_enabled(dev->bus)) | |
3567 | slot = 0; | |
3568 | else | |
3569 | slot = PCI_SLOT(dev->devfn); | |
3570 | ||
3571 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
3572 | } |
3573 | ||
3c78bc61 | 3574 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
3575 | { |
3576 | u8 pin; | |
3577 | ||
514d207d | 3578 | pin = dev->pin; |
1da177e4 LT |
3579 | if (!pin) |
3580 | return -1; | |
878f2e50 | 3581 | |
8784fd4d | 3582 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 3583 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
3584 | dev = dev->bus->self; |
3585 | } | |
3586 | *bridge = dev; | |
3587 | return pin; | |
3588 | } | |
3589 | ||
68feac87 BH |
3590 | /** |
3591 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
3592 | * @dev: the PCI device | |
3593 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
3594 | * | |
3595 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
3596 | * bridges all the way up to a PCI root bus. | |
3597 | */ | |
3598 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
3599 | { | |
3600 | u8 pin = *pinp; | |
3601 | ||
1eb39487 | 3602 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
3603 | pin = pci_swizzle_interrupt_pin(dev, pin); |
3604 | dev = dev->bus->self; | |
3605 | } | |
3606 | *pinp = pin; | |
3607 | return PCI_SLOT(dev->devfn); | |
3608 | } | |
e6b29dea | 3609 | EXPORT_SYMBOL_GPL(pci_common_swizzle); |
68feac87 | 3610 | |
1da177e4 LT |
3611 | /** |
3612 | * pci_release_region - Release a PCI bar | |
3613 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
3614 | * @bar: BAR to release | |
3615 | * | |
3616 | * Releases the PCI I/O and memory resources previously reserved by a | |
3617 | * successful call to pci_request_region. Call this function only | |
3618 | * after all use of the PCI regions has ceased. | |
3619 | */ | |
3620 | void pci_release_region(struct pci_dev *pdev, int bar) | |
3621 | { | |
9ac7849e TH |
3622 | struct pci_devres *dr; |
3623 | ||
1da177e4 LT |
3624 | if (pci_resource_len(pdev, bar) == 0) |
3625 | return; | |
3626 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
3627 | release_region(pci_resource_start(pdev, bar), | |
3628 | pci_resource_len(pdev, bar)); | |
3629 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
3630 | release_mem_region(pci_resource_start(pdev, bar), | |
3631 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
3632 | |
3633 | dr = find_pci_dr(pdev); | |
3634 | if (dr) | |
3635 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 3636 | } |
b7fe9434 | 3637 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
3638 | |
3639 | /** | |
f5ddcac4 | 3640 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
3641 | * @pdev: PCI device whose resources are to be reserved |
3642 | * @bar: BAR to be reserved | |
3643 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 3644 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
3645 | * |
3646 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
3647 | * being reserved by owner @res_name. Do not access any | |
3648 | * address inside the PCI regions unless this call returns | |
3649 | * successfully. | |
3650 | * | |
f5ddcac4 RD |
3651 | * If @exclusive is set, then the region is marked so that userspace |
3652 | * is explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 3653 | * sysfs MMIO access. |
f5ddcac4 | 3654 | * |
1da177e4 LT |
3655 | * Returns 0 on success, or %EBUSY on error. A warning |
3656 | * message is also printed on failure. | |
3657 | */ | |
3c78bc61 RD |
3658 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
3659 | const char *res_name, int exclusive) | |
1da177e4 | 3660 | { |
9ac7849e TH |
3661 | struct pci_devres *dr; |
3662 | ||
1da177e4 LT |
3663 | if (pci_resource_len(pdev, bar) == 0) |
3664 | return 0; | |
f7625980 | 3665 | |
1da177e4 LT |
3666 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
3667 | if (!request_region(pci_resource_start(pdev, bar), | |
3668 | pci_resource_len(pdev, bar), res_name)) | |
3669 | goto err_out; | |
3c78bc61 | 3670 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
3671 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
3672 | pci_resource_len(pdev, bar), res_name, | |
3673 | exclusive)) | |
1da177e4 LT |
3674 | goto err_out; |
3675 | } | |
9ac7849e TH |
3676 | |
3677 | dr = find_pci_dr(pdev); | |
3678 | if (dr) | |
3679 | dr->region_mask |= 1 << bar; | |
3680 | ||
1da177e4 LT |
3681 | return 0; |
3682 | ||
3683 | err_out: | |
7506dc79 | 3684 | pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 3685 | &pdev->resource[bar]); |
1da177e4 LT |
3686 | return -EBUSY; |
3687 | } | |
3688 | ||
e8de1481 | 3689 | /** |
f5ddcac4 | 3690 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
3691 | * @pdev: PCI device whose resources are to be reserved |
3692 | * @bar: BAR to be reserved | |
f5ddcac4 | 3693 | * @res_name: Name to be associated with resource |
e8de1481 | 3694 | * |
f5ddcac4 | 3695 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
3696 | * being reserved by owner @res_name. Do not access any |
3697 | * address inside the PCI regions unless this call returns | |
3698 | * successfully. | |
3699 | * | |
3700 | * Returns 0 on success, or %EBUSY on error. A warning | |
3701 | * message is also printed on failure. | |
3702 | */ | |
3703 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
3704 | { | |
3705 | return __pci_request_region(pdev, bar, res_name, 0); | |
3706 | } | |
b7fe9434 | 3707 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 AV |
3708 | |
3709 | /** | |
3710 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
3711 | * @pdev: PCI device whose resources are to be reserved | |
3712 | * @bar: BAR to be reserved | |
3713 | * @res_name: Name to be associated with resource. | |
3714 | * | |
3715 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
3716 | * being reserved by owner @res_name. Do not access any | |
3717 | * address inside the PCI regions unless this call returns | |
3718 | * successfully. | |
3719 | * | |
3720 | * Returns 0 on success, or %EBUSY on error. A warning | |
3721 | * message is also printed on failure. | |
3722 | * | |
3723 | * The key difference that _exclusive makes it that userspace is | |
3724 | * explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 3725 | * sysfs. |
e8de1481 | 3726 | */ |
3c78bc61 RD |
3727 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, |
3728 | const char *res_name) | |
e8de1481 AV |
3729 | { |
3730 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
3731 | } | |
b7fe9434 RD |
3732 | EXPORT_SYMBOL(pci_request_region_exclusive); |
3733 | ||
c87deff7 HS |
3734 | /** |
3735 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
3736 | * @pdev: PCI device whose resources were previously reserved | |
3737 | * @bars: Bitmask of BARs to be released | |
3738 | * | |
3739 | * Release selected PCI I/O and memory resources previously reserved. | |
3740 | * Call this function only after all use of the PCI regions has ceased. | |
3741 | */ | |
3742 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
3743 | { | |
3744 | int i; | |
3745 | ||
3746 | for (i = 0; i < 6; i++) | |
3747 | if (bars & (1 << i)) | |
3748 | pci_release_region(pdev, i); | |
3749 | } | |
b7fe9434 | 3750 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 3751 | |
9738abed | 3752 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 3753 | const char *res_name, int excl) |
c87deff7 HS |
3754 | { |
3755 | int i; | |
3756 | ||
3757 | for (i = 0; i < 6; i++) | |
3758 | if (bars & (1 << i)) | |
e8de1481 | 3759 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
3760 | goto err_out; |
3761 | return 0; | |
3762 | ||
3763 | err_out: | |
3c78bc61 | 3764 | while (--i >= 0) |
c87deff7 HS |
3765 | if (bars & (1 << i)) |
3766 | pci_release_region(pdev, i); | |
3767 | ||
3768 | return -EBUSY; | |
3769 | } | |
1da177e4 | 3770 | |
e8de1481 AV |
3771 | |
3772 | /** | |
3773 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
3774 | * @pdev: PCI device whose resources are to be reserved | |
3775 | * @bars: Bitmask of BARs to be requested | |
3776 | * @res_name: Name to be associated with resource | |
3777 | */ | |
3778 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
3779 | const char *res_name) | |
3780 | { | |
3781 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
3782 | } | |
b7fe9434 | 3783 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 3784 | |
3c78bc61 RD |
3785 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
3786 | const char *res_name) | |
e8de1481 AV |
3787 | { |
3788 | return __pci_request_selected_regions(pdev, bars, res_name, | |
3789 | IORESOURCE_EXCLUSIVE); | |
3790 | } | |
b7fe9434 | 3791 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 3792 | |
1da177e4 LT |
3793 | /** |
3794 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
3795 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
3796 | * | |
3797 | * Releases all PCI I/O and memory resources previously reserved by a | |
3798 | * successful call to pci_request_regions. Call this function only | |
3799 | * after all use of the PCI regions has ceased. | |
3800 | */ | |
3801 | ||
3802 | void pci_release_regions(struct pci_dev *pdev) | |
3803 | { | |
c87deff7 | 3804 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 | 3805 | } |
b7fe9434 | 3806 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
3807 | |
3808 | /** | |
3809 | * pci_request_regions - Reserved PCI I/O and memory resources | |
3810 | * @pdev: PCI device whose resources are to be reserved | |
3811 | * @res_name: Name to be associated with resource. | |
3812 | * | |
3813 | * Mark all PCI regions associated with PCI device @pdev as | |
3814 | * being reserved by owner @res_name. Do not access any | |
3815 | * address inside the PCI regions unless this call returns | |
3816 | * successfully. | |
3817 | * | |
3818 | * Returns 0 on success, or %EBUSY on error. A warning | |
3819 | * message is also printed on failure. | |
3820 | */ | |
3c990e92 | 3821 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 3822 | { |
c87deff7 | 3823 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 | 3824 | } |
b7fe9434 | 3825 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 3826 | |
e8de1481 AV |
3827 | /** |
3828 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
3829 | * @pdev: PCI device whose resources are to be reserved | |
3830 | * @res_name: Name to be associated with resource. | |
3831 | * | |
3832 | * Mark all PCI regions associated with PCI device @pdev as | |
3833 | * being reserved by owner @res_name. Do not access any | |
3834 | * address inside the PCI regions unless this call returns | |
3835 | * successfully. | |
3836 | * | |
3837 | * pci_request_regions_exclusive() will mark the region so that | |
f7625980 | 3838 | * /dev/mem and the sysfs MMIO access will not be allowed. |
e8de1481 AV |
3839 | * |
3840 | * Returns 0 on success, or %EBUSY on error. A warning | |
3841 | * message is also printed on failure. | |
3842 | */ | |
3843 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
3844 | { | |
3845 | return pci_request_selected_regions_exclusive(pdev, | |
3846 | ((1 << 6) - 1), res_name); | |
3847 | } | |
b7fe9434 | 3848 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 3849 | |
c5076cfe TN |
3850 | /* |
3851 | * Record the PCI IO range (expressed as CPU physical address + size). | |
3852 | * Return a negative value if an error has occured, zero otherwise | |
3853 | */ | |
fcfaab30 GP |
3854 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
3855 | resource_size_t size) | |
c5076cfe | 3856 | { |
5745392e | 3857 | int ret = 0; |
c5076cfe | 3858 | #ifdef PCI_IOBASE |
5745392e | 3859 | struct logic_pio_hwaddr *range; |
c5076cfe | 3860 | |
5745392e ZY |
3861 | if (!size || addr + size < addr) |
3862 | return -EINVAL; | |
c5076cfe | 3863 | |
c5076cfe | 3864 | range = kzalloc(sizeof(*range), GFP_ATOMIC); |
5745392e ZY |
3865 | if (!range) |
3866 | return -ENOMEM; | |
c5076cfe | 3867 | |
5745392e | 3868 | range->fwnode = fwnode; |
c5076cfe | 3869 | range->size = size; |
5745392e ZY |
3870 | range->hw_start = addr; |
3871 | range->flags = LOGIC_PIO_CPU_MMIO; | |
c5076cfe | 3872 | |
5745392e ZY |
3873 | ret = logic_pio_register_range(range); |
3874 | if (ret) | |
3875 | kfree(range); | |
c5076cfe TN |
3876 | #endif |
3877 | ||
5745392e | 3878 | return ret; |
c5076cfe TN |
3879 | } |
3880 | ||
3881 | phys_addr_t pci_pio_to_address(unsigned long pio) | |
3882 | { | |
3883 | phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; | |
3884 | ||
3885 | #ifdef PCI_IOBASE | |
5745392e | 3886 | if (pio >= MMIO_UPPER_LIMIT) |
c5076cfe TN |
3887 | return address; |
3888 | ||
5745392e | 3889 | address = logic_pio_to_hwaddr(pio); |
c5076cfe TN |
3890 | #endif |
3891 | ||
3892 | return address; | |
3893 | } | |
3894 | ||
3895 | unsigned long __weak pci_address_to_pio(phys_addr_t address) | |
3896 | { | |
3897 | #ifdef PCI_IOBASE | |
5745392e | 3898 | return logic_pio_trans_cpuaddr(address); |
c5076cfe TN |
3899 | #else |
3900 | if (address > IO_SPACE_LIMIT) | |
3901 | return (unsigned long)-1; | |
3902 | ||
3903 | return (unsigned long) address; | |
3904 | #endif | |
3905 | } | |
3906 | ||
8b921acf LD |
3907 | /** |
3908 | * pci_remap_iospace - Remap the memory mapped I/O space | |
3909 | * @res: Resource describing the I/O space | |
3910 | * @phys_addr: physical address of range to be mapped | |
3911 | * | |
3912 | * Remap the memory mapped I/O space described by the @res | |
3913 | * and the CPU physical address @phys_addr into virtual address space. | |
3914 | * Only architectures that have memory mapped IO functions defined | |
3915 | * (and the PCI_IOBASE value defined) should call this function. | |
3916 | */ | |
7b309aef | 3917 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) |
8b921acf LD |
3918 | { |
3919 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3920 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3921 | ||
3922 | if (!(res->flags & IORESOURCE_IO)) | |
3923 | return -EINVAL; | |
3924 | ||
3925 | if (res->end > IO_SPACE_LIMIT) | |
3926 | return -EINVAL; | |
3927 | ||
3928 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
3929 | pgprot_device(PAGE_KERNEL)); | |
3930 | #else | |
3931 | /* this architecture does not have memory mapped I/O space, | |
3932 | so this function should never be called */ | |
3933 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); | |
3934 | return -ENODEV; | |
3935 | #endif | |
3936 | } | |
f90b0875 | 3937 | EXPORT_SYMBOL(pci_remap_iospace); |
8b921acf | 3938 | |
4d3f1384 SK |
3939 | /** |
3940 | * pci_unmap_iospace - Unmap the memory mapped I/O space | |
3941 | * @res: resource to be unmapped | |
3942 | * | |
3943 | * Unmap the CPU virtual address @res from virtual address space. | |
3944 | * Only architectures that have memory mapped IO functions defined | |
3945 | * (and the PCI_IOBASE value defined) should call this function. | |
3946 | */ | |
3947 | void pci_unmap_iospace(struct resource *res) | |
3948 | { | |
3949 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3950 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3951 | ||
3952 | unmap_kernel_range(vaddr, resource_size(res)); | |
3953 | #endif | |
3954 | } | |
f90b0875 | 3955 | EXPORT_SYMBOL(pci_unmap_iospace); |
4d3f1384 | 3956 | |
a5fb9fb0 SS |
3957 | static void devm_pci_unmap_iospace(struct device *dev, void *ptr) |
3958 | { | |
3959 | struct resource **res = ptr; | |
3960 | ||
3961 | pci_unmap_iospace(*res); | |
3962 | } | |
3963 | ||
3964 | /** | |
3965 | * devm_pci_remap_iospace - Managed pci_remap_iospace() | |
3966 | * @dev: Generic device to remap IO address for | |
3967 | * @res: Resource describing the I/O space | |
3968 | * @phys_addr: physical address of range to be mapped | |
3969 | * | |
3970 | * Managed pci_remap_iospace(). Map is automatically unmapped on driver | |
3971 | * detach. | |
3972 | */ | |
3973 | int devm_pci_remap_iospace(struct device *dev, const struct resource *res, | |
3974 | phys_addr_t phys_addr) | |
3975 | { | |
3976 | const struct resource **ptr; | |
3977 | int error; | |
3978 | ||
3979 | ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL); | |
3980 | if (!ptr) | |
3981 | return -ENOMEM; | |
3982 | ||
3983 | error = pci_remap_iospace(res, phys_addr); | |
3984 | if (error) { | |
3985 | devres_free(ptr); | |
3986 | } else { | |
3987 | *ptr = res; | |
3988 | devres_add(dev, ptr); | |
3989 | } | |
3990 | ||
3991 | return error; | |
3992 | } | |
3993 | EXPORT_SYMBOL(devm_pci_remap_iospace); | |
3994 | ||
490cb6dd LP |
3995 | /** |
3996 | * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace() | |
3997 | * @dev: Generic device to remap IO address for | |
3998 | * @offset: Resource address to map | |
3999 | * @size: Size of map | |
4000 | * | |
4001 | * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver | |
4002 | * detach. | |
4003 | */ | |
4004 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, | |
4005 | resource_size_t offset, | |
4006 | resource_size_t size) | |
4007 | { | |
4008 | void __iomem **ptr, *addr; | |
4009 | ||
4010 | ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL); | |
4011 | if (!ptr) | |
4012 | return NULL; | |
4013 | ||
4014 | addr = pci_remap_cfgspace(offset, size); | |
4015 | if (addr) { | |
4016 | *ptr = addr; | |
4017 | devres_add(dev, ptr); | |
4018 | } else | |
4019 | devres_free(ptr); | |
4020 | ||
4021 | return addr; | |
4022 | } | |
4023 | EXPORT_SYMBOL(devm_pci_remap_cfgspace); | |
4024 | ||
4025 | /** | |
4026 | * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource | |
4027 | * @dev: generic device to handle the resource for | |
4028 | * @res: configuration space resource to be handled | |
4029 | * | |
4030 | * Checks that a resource is a valid memory region, requests the memory | |
4031 | * region and ioremaps with pci_remap_cfgspace() API that ensures the | |
4032 | * proper PCI configuration space memory attributes are guaranteed. | |
4033 | * | |
4034 | * All operations are managed and will be undone on driver detach. | |
4035 | * | |
4036 | * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code | |
505fb746 | 4037 | * on failure. Usage example:: |
490cb6dd LP |
4038 | * |
4039 | * res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
4040 | * base = devm_pci_remap_cfg_resource(&pdev->dev, res); | |
4041 | * if (IS_ERR(base)) | |
4042 | * return PTR_ERR(base); | |
4043 | */ | |
4044 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
4045 | struct resource *res) | |
4046 | { | |
4047 | resource_size_t size; | |
4048 | const char *name; | |
4049 | void __iomem *dest_ptr; | |
4050 | ||
4051 | BUG_ON(!dev); | |
4052 | ||
4053 | if (!res || resource_type(res) != IORESOURCE_MEM) { | |
4054 | dev_err(dev, "invalid resource\n"); | |
4055 | return IOMEM_ERR_PTR(-EINVAL); | |
4056 | } | |
4057 | ||
4058 | size = resource_size(res); | |
4059 | name = res->name ?: dev_name(dev); | |
4060 | ||
4061 | if (!devm_request_mem_region(dev, res->start, size, name)) { | |
4062 | dev_err(dev, "can't request region for resource %pR\n", res); | |
4063 | return IOMEM_ERR_PTR(-EBUSY); | |
4064 | } | |
4065 | ||
4066 | dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); | |
4067 | if (!dest_ptr) { | |
4068 | dev_err(dev, "ioremap failed for resource %pR\n", res); | |
4069 | devm_release_mem_region(dev, res->start, size); | |
4070 | dest_ptr = IOMEM_ERR_PTR(-ENOMEM); | |
4071 | } | |
4072 | ||
4073 | return dest_ptr; | |
4074 | } | |
4075 | EXPORT_SYMBOL(devm_pci_remap_cfg_resource); | |
4076 | ||
6a479079 BH |
4077 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
4078 | { | |
4079 | u16 old_cmd, cmd; | |
4080 | ||
4081 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
4082 | if (enable) | |
4083 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
4084 | else | |
4085 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
4086 | if (cmd != old_cmd) { | |
7506dc79 | 4087 | pci_dbg(dev, "%s bus mastering\n", |
6a479079 BH |
4088 | enable ? "enabling" : "disabling"); |
4089 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4090 | } | |
4091 | dev->is_busmaster = enable; | |
4092 | } | |
e8de1481 | 4093 | |
2b6f2c35 MS |
4094 | /** |
4095 | * pcibios_setup - process "pci=" kernel boot arguments | |
4096 | * @str: string used to pass in "pci=" kernel boot arguments | |
4097 | * | |
4098 | * Process kernel boot arguments. This is the default implementation. | |
4099 | * Architecture specific implementations can override this as necessary. | |
4100 | */ | |
4101 | char * __weak __init pcibios_setup(char *str) | |
4102 | { | |
4103 | return str; | |
4104 | } | |
4105 | ||
96c55900 MS |
4106 | /** |
4107 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
4108 | * @dev: the PCI device to enable | |
4109 | * | |
4110 | * Enables PCI bus-mastering for the device. This is the default | |
4111 | * implementation. Architecture specific implementations can override | |
4112 | * this if necessary. | |
4113 | */ | |
4114 | void __weak pcibios_set_master(struct pci_dev *dev) | |
4115 | { | |
4116 | u8 lat; | |
4117 | ||
f676678f MS |
4118 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
4119 | if (pci_is_pcie(dev)) | |
4120 | return; | |
4121 | ||
96c55900 MS |
4122 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
4123 | if (lat < 16) | |
4124 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
4125 | else if (lat > pcibios_max_latency) | |
4126 | lat = pcibios_max_latency; | |
4127 | else | |
4128 | return; | |
a006482b | 4129 | |
96c55900 MS |
4130 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
4131 | } | |
4132 | ||
1da177e4 LT |
4133 | /** |
4134 | * pci_set_master - enables bus-mastering for device dev | |
4135 | * @dev: the PCI device to enable | |
4136 | * | |
4137 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
4138 | * to do the needed arch specific settings. | |
4139 | */ | |
6a479079 | 4140 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 4141 | { |
6a479079 | 4142 | __pci_set_master(dev, true); |
1da177e4 LT |
4143 | pcibios_set_master(dev); |
4144 | } | |
b7fe9434 | 4145 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 4146 | |
6a479079 BH |
4147 | /** |
4148 | * pci_clear_master - disables bus-mastering for device dev | |
4149 | * @dev: the PCI device to disable | |
4150 | */ | |
4151 | void pci_clear_master(struct pci_dev *dev) | |
4152 | { | |
4153 | __pci_set_master(dev, false); | |
4154 | } | |
b7fe9434 | 4155 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 4156 | |
1da177e4 | 4157 | /** |
edb2d97e MW |
4158 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
4159 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 4160 | * |
edb2d97e MW |
4161 | * Helper function for pci_set_mwi. |
4162 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
4163 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
4164 | * | |
4165 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4166 | */ | |
15ea76d4 | 4167 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
4168 | { |
4169 | u8 cacheline_size; | |
4170 | ||
4171 | if (!pci_cache_line_size) | |
15ea76d4 | 4172 | return -EINVAL; |
1da177e4 LT |
4173 | |
4174 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
4175 | equal to or multiple of the right value. */ | |
4176 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4177 | if (cacheline_size >= pci_cache_line_size && | |
4178 | (cacheline_size % pci_cache_line_size) == 0) | |
4179 | return 0; | |
4180 | ||
4181 | /* Write the correct value. */ | |
4182 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
4183 | /* Read it back. */ | |
4184 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4185 | if (cacheline_size == pci_cache_line_size) | |
4186 | return 0; | |
4187 | ||
7506dc79 | 4188 | pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n", |
227f0647 | 4189 | pci_cache_line_size << 2); |
1da177e4 LT |
4190 | |
4191 | return -EINVAL; | |
4192 | } | |
15ea76d4 TH |
4193 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
4194 | ||
1da177e4 LT |
4195 | /** |
4196 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
4197 | * @dev: the PCI device for which MWI is enabled | |
4198 | * | |
694625c0 | 4199 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
4200 | * |
4201 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4202 | */ | |
3c78bc61 | 4203 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 4204 | { |
b7fe9434 RD |
4205 | #ifdef PCI_DISABLE_MWI |
4206 | return 0; | |
4207 | #else | |
1da177e4 LT |
4208 | int rc; |
4209 | u16 cmd; | |
4210 | ||
edb2d97e | 4211 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
4212 | if (rc) |
4213 | return rc; | |
4214 | ||
4215 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 4216 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
7506dc79 | 4217 | pci_dbg(dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
4218 | cmd |= PCI_COMMAND_INVALIDATE; |
4219 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4220 | } | |
1da177e4 | 4221 | return 0; |
b7fe9434 | 4222 | #endif |
1da177e4 | 4223 | } |
b7fe9434 | 4224 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 4225 | |
fc0f9f4d HK |
4226 | /** |
4227 | * pcim_set_mwi - a device-managed pci_set_mwi() | |
4228 | * @dev: the PCI device for which MWI is enabled | |
4229 | * | |
4230 | * Managed pci_set_mwi(). | |
4231 | * | |
4232 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4233 | */ | |
4234 | int pcim_set_mwi(struct pci_dev *dev) | |
4235 | { | |
4236 | struct pci_devres *dr; | |
4237 | ||
4238 | dr = find_pci_dr(dev); | |
4239 | if (!dr) | |
4240 | return -ENOMEM; | |
4241 | ||
4242 | dr->mwi = 1; | |
4243 | return pci_set_mwi(dev); | |
4244 | } | |
4245 | EXPORT_SYMBOL(pcim_set_mwi); | |
4246 | ||
694625c0 RD |
4247 | /** |
4248 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
4249 | * @dev: the PCI device for which MWI is enabled | |
4250 | * | |
4251 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
4252 | * Callers are not required to check the return value. | |
4253 | * | |
4254 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4255 | */ | |
4256 | int pci_try_set_mwi(struct pci_dev *dev) | |
4257 | { | |
b7fe9434 RD |
4258 | #ifdef PCI_DISABLE_MWI |
4259 | return 0; | |
4260 | #else | |
4261 | return pci_set_mwi(dev); | |
4262 | #endif | |
694625c0 | 4263 | } |
b7fe9434 | 4264 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 4265 | |
1da177e4 LT |
4266 | /** |
4267 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
4268 | * @dev: the PCI device to disable | |
4269 | * | |
4270 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
4271 | */ | |
3c78bc61 | 4272 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 4273 | { |
b7fe9434 | 4274 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
4275 | u16 cmd; |
4276 | ||
4277 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4278 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
4279 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
4280 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4281 | } | |
b7fe9434 | 4282 | #endif |
1da177e4 | 4283 | } |
b7fe9434 | 4284 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 4285 | |
a04ce0ff BR |
4286 | /** |
4287 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
4288 | * @pdev: the PCI device to operate on |
4289 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
4290 | * |
4291 | * Enables/disables PCI INTx for device dev | |
4292 | */ | |
3c78bc61 | 4293 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
4294 | { |
4295 | u16 pci_command, new; | |
4296 | ||
4297 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
4298 | ||
3c78bc61 | 4299 | if (enable) |
a04ce0ff | 4300 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 4301 | else |
a04ce0ff | 4302 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
4303 | |
4304 | if (new != pci_command) { | |
9ac7849e TH |
4305 | struct pci_devres *dr; |
4306 | ||
2fd9d74b | 4307 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
4308 | |
4309 | dr = find_pci_dr(pdev); | |
4310 | if (dr && !dr->restore_intx) { | |
4311 | dr->restore_intx = 1; | |
4312 | dr->orig_intx = !enable; | |
4313 | } | |
a04ce0ff BR |
4314 | } |
4315 | } | |
b7fe9434 | 4316 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 4317 | |
a2e27787 JK |
4318 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) |
4319 | { | |
4320 | struct pci_bus *bus = dev->bus; | |
4321 | bool mask_updated = true; | |
4322 | u32 cmd_status_dword; | |
4323 | u16 origcmd, newcmd; | |
4324 | unsigned long flags; | |
4325 | bool irq_pending; | |
4326 | ||
4327 | /* | |
4328 | * We do a single dword read to retrieve both command and status. | |
4329 | * Document assumptions that make this possible. | |
4330 | */ | |
4331 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
4332 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
4333 | ||
4334 | raw_spin_lock_irqsave(&pci_lock, flags); | |
4335 | ||
4336 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
4337 | ||
4338 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
4339 | ||
4340 | /* | |
4341 | * Check interrupt status register to see whether our device | |
4342 | * triggered the interrupt (when masking) or the next IRQ is | |
4343 | * already pending (when unmasking). | |
4344 | */ | |
4345 | if (mask != irq_pending) { | |
4346 | mask_updated = false; | |
4347 | goto done; | |
4348 | } | |
4349 | ||
4350 | origcmd = cmd_status_dword; | |
4351 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
4352 | if (mask) | |
4353 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
4354 | if (newcmd != origcmd) | |
4355 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
4356 | ||
4357 | done: | |
4358 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
4359 | ||
4360 | return mask_updated; | |
4361 | } | |
4362 | ||
4363 | /** | |
4364 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 4365 | * @dev: the PCI device to operate on |
a2e27787 JK |
4366 | * |
4367 | * Check if the device dev has its INTx line asserted, mask it and | |
99b3c58f | 4368 | * return true in that case. False is returned if no interrupt was |
a2e27787 JK |
4369 | * pending. |
4370 | */ | |
4371 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
4372 | { | |
4373 | return pci_check_and_set_intx_mask(dev, true); | |
4374 | } | |
4375 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
4376 | ||
4377 | /** | |
ebd50b93 | 4378 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 4379 | * @dev: the PCI device to operate on |
a2e27787 JK |
4380 | * |
4381 | * Check if the device dev has its INTx line asserted, unmask it if not | |
4382 | * and return true. False is returned and the mask remains active if | |
4383 | * there was still an interrupt pending. | |
4384 | */ | |
4385 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
4386 | { | |
4387 | return pci_check_and_set_intx_mask(dev, false); | |
4388 | } | |
4389 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
4390 | ||
3775a209 CL |
4391 | /** |
4392 | * pci_wait_for_pending_transaction - waits for pending transaction | |
4393 | * @dev: the PCI device to operate on | |
4394 | * | |
4395 | * Return 0 if transaction is pending 1 otherwise. | |
4396 | */ | |
4397 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 4398 | { |
157e876f AW |
4399 | if (!pci_is_pcie(dev)) |
4400 | return 1; | |
8c1c699f | 4401 | |
d0b4cc4e GS |
4402 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
4403 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
4404 | } |
4405 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
4406 | ||
a2758b6b | 4407 | static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) |
5adecf81 | 4408 | { |
a2758b6b | 4409 | int delay = 1; |
5adecf81 AW |
4410 | u32 id; |
4411 | ||
821cdad5 | 4412 | /* |
a2758b6b | 4413 | * After reset, the device should not silently discard config |
821cdad5 SK |
4414 | * requests, but it may still indicate that it needs more time by |
4415 | * responding to them with CRS completions. The Root Port will | |
4416 | * generally synthesize ~0 data to complete the read (except when | |
4417 | * CRS SV is enabled and the read was for the Vendor ID; in that | |
4418 | * case it synthesizes 0x0001 data). | |
4419 | * | |
4420 | * Wait for the device to return a non-CRS completion. Read the | |
4421 | * Command register instead of Vendor ID so we don't have to | |
4422 | * contend with the CRS SV value. | |
4423 | */ | |
4424 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
4425 | while (id == ~0) { | |
4426 | if (delay > timeout) { | |
a2758b6b SK |
4427 | pci_warn(dev, "not ready %dms after %s; giving up\n", |
4428 | delay - 1, reset_type); | |
91295d79 | 4429 | return -ENOTTY; |
821cdad5 SK |
4430 | } |
4431 | ||
4432 | if (delay > 1000) | |
a2758b6b SK |
4433 | pci_info(dev, "not ready %dms after %s; waiting\n", |
4434 | delay - 1, reset_type); | |
821cdad5 SK |
4435 | |
4436 | msleep(delay); | |
4437 | delay *= 2; | |
5adecf81 | 4438 | pci_read_config_dword(dev, PCI_COMMAND, &id); |
821cdad5 | 4439 | } |
5adecf81 | 4440 | |
821cdad5 | 4441 | if (delay > 1000) |
a2758b6b SK |
4442 | pci_info(dev, "ready %dms after %s\n", delay - 1, |
4443 | reset_type); | |
91295d79 SK |
4444 | |
4445 | return 0; | |
5adecf81 AW |
4446 | } |
4447 | ||
a60a2b73 CH |
4448 | /** |
4449 | * pcie_has_flr - check if a device supports function level resets | |
4450 | * @dev: device to check | |
4451 | * | |
4452 | * Returns true if the device advertises support for PCIe function level | |
4453 | * resets. | |
4454 | */ | |
2d2917f7 | 4455 | bool pcie_has_flr(struct pci_dev *dev) |
3775a209 CL |
4456 | { |
4457 | u32 cap; | |
4458 | ||
f65fd1aa | 4459 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
a60a2b73 | 4460 | return false; |
3775a209 | 4461 | |
a60a2b73 CH |
4462 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
4463 | return cap & PCI_EXP_DEVCAP_FLR; | |
4464 | } | |
2d2917f7 | 4465 | EXPORT_SYMBOL_GPL(pcie_has_flr); |
3775a209 | 4466 | |
a60a2b73 CH |
4467 | /** |
4468 | * pcie_flr - initiate a PCIe function level reset | |
4469 | * @dev: device to reset | |
4470 | * | |
4471 | * Initiate a function level reset on @dev. The caller should ensure the | |
4472 | * device supports FLR before calling this function, e.g. by using the | |
4473 | * pcie_has_flr() helper. | |
4474 | */ | |
91295d79 | 4475 | int pcie_flr(struct pci_dev *dev) |
a60a2b73 | 4476 | { |
3775a209 | 4477 | if (!pci_wait_for_pending_transaction(dev)) |
7506dc79 | 4478 | pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 4479 | |
59875ae4 | 4480 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
a2758b6b | 4481 | |
d6112f8d FB |
4482 | if (dev->imm_ready) |
4483 | return 0; | |
4484 | ||
a2758b6b SK |
4485 | /* |
4486 | * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within | |
4487 | * 100ms, but may silently discard requests while the FLR is in | |
4488 | * progress. Wait 100ms before trying to access the device. | |
4489 | */ | |
4490 | msleep(100); | |
4491 | ||
4492 | return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); | |
8dd7f803 | 4493 | } |
a60a2b73 | 4494 | EXPORT_SYMBOL_GPL(pcie_flr); |
d91cdc74 | 4495 | |
8c1c699f | 4496 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 4497 | { |
8c1c699f | 4498 | int pos; |
1ca88797 SY |
4499 | u8 cap; |
4500 | ||
8c1c699f YZ |
4501 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
4502 | if (!pos) | |
1ca88797 | 4503 | return -ENOTTY; |
8c1c699f | 4504 | |
f65fd1aa SN |
4505 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
4506 | return -ENOTTY; | |
4507 | ||
8c1c699f | 4508 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); |
1ca88797 SY |
4509 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
4510 | return -ENOTTY; | |
4511 | ||
4512 | if (probe) | |
4513 | return 0; | |
4514 | ||
d066c946 AW |
4515 | /* |
4516 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
4517 | * is used, so we use the conrol offset rather than status and shift | |
4518 | * the test bit to match. | |
4519 | */ | |
bb383e28 | 4520 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 4521 | PCI_AF_STATUS_TP << 8)) |
7506dc79 | 4522 | pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 4523 | |
8c1c699f | 4524 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
a2758b6b | 4525 | |
d6112f8d FB |
4526 | if (dev->imm_ready) |
4527 | return 0; | |
4528 | ||
a2758b6b SK |
4529 | /* |
4530 | * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, | |
4531 | * updated 27 July 2006; a device must complete an FLR within | |
4532 | * 100ms, but may silently discard requests while the FLR is in | |
4533 | * progress. Wait 100ms before trying to access the device. | |
4534 | */ | |
4535 | msleep(100); | |
4536 | ||
4537 | return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); | |
1ca88797 SY |
4538 | } |
4539 | ||
83d74e03 RW |
4540 | /** |
4541 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
4542 | * @dev: Device to reset. | |
4543 | * @probe: If set, only check if the device can be reset this way. | |
4544 | * | |
4545 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
4546 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
4547 | * PCI_D0. If that's the case and the device is not in a low-power state | |
4548 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
4549 | * | |
4550 | * NOTE: This causes the caller to sleep for twice the device power transition | |
4551 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 4552 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
4553 | * Moreover, only devices in D0 can be reset by this function. |
4554 | */ | |
f85876ba | 4555 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 4556 | { |
f85876ba YZ |
4557 | u16 csr; |
4558 | ||
51e53738 | 4559 | if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) |
f85876ba | 4560 | return -ENOTTY; |
d91cdc74 | 4561 | |
f85876ba YZ |
4562 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
4563 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
4564 | return -ENOTTY; | |
d91cdc74 | 4565 | |
f85876ba YZ |
4566 | if (probe) |
4567 | return 0; | |
1ca88797 | 4568 | |
f85876ba YZ |
4569 | if (dev->current_state != PCI_D0) |
4570 | return -EINVAL; | |
4571 | ||
4572 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4573 | csr |= PCI_D3hot; | |
4574 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4575 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
4576 | |
4577 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4578 | csr |= PCI_D0; | |
4579 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4580 | pci_dev_d3_sleep(dev); |
f85876ba | 4581 | |
abbcf0e2 | 4582 | return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS); |
f85876ba | 4583 | } |
9f5a70f1 OP |
4584 | /** |
4585 | * pcie_wait_for_link - Wait until link is active or inactive | |
4586 | * @pdev: Bridge device | |
4587 | * @active: waiting for active or inactive? | |
4588 | * | |
4589 | * Use this to wait till link becomes active or inactive. | |
4590 | */ | |
4591 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active) | |
4592 | { | |
4593 | int timeout = 1000; | |
4594 | bool ret; | |
4595 | u16 lnk_status; | |
4596 | ||
f0157160 KB |
4597 | /* |
4598 | * Some controllers might not implement link active reporting. In this | |
4599 | * case, we wait for 1000 + 100 ms. | |
4600 | */ | |
4601 | if (!pdev->link_active_reporting) { | |
4602 | msleep(1100); | |
4603 | return true; | |
4604 | } | |
4605 | ||
4606 | /* | |
4607 | * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms, | |
4608 | * after which we should expect an link active if the reset was | |
4609 | * successful. If so, software must wait a minimum 100ms before sending | |
4610 | * configuration requests to devices downstream this port. | |
4611 | * | |
4612 | * If the link fails to activate, either the device was physically | |
4613 | * removed or the link is permanently failed. | |
4614 | */ | |
4615 | if (active) | |
4616 | msleep(20); | |
9f5a70f1 OP |
4617 | for (;;) { |
4618 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); | |
4619 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); | |
4620 | if (ret == active) | |
f0157160 | 4621 | break; |
9f5a70f1 OP |
4622 | if (timeout <= 0) |
4623 | break; | |
4624 | msleep(10); | |
4625 | timeout -= 10; | |
4626 | } | |
f0157160 KB |
4627 | if (active && ret) |
4628 | msleep(100); | |
4629 | else if (ret != active) | |
4630 | pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n", | |
4631 | active ? "set" : "cleared"); | |
4632 | return ret == active; | |
9f5a70f1 | 4633 | } |
f85876ba | 4634 | |
9e33002f | 4635 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
4636 | { |
4637 | u16 ctrl; | |
64e8674f AW |
4638 | |
4639 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
4640 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
4641 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
df62ab5e | 4642 | |
de0c548c AW |
4643 | /* |
4644 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 4645 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
4646 | */ |
4647 | msleep(2); | |
64e8674f AW |
4648 | |
4649 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
4650 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
4651 | |
4652 | /* | |
4653 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
4654 | * Assuming a minimum 33MHz clock this results in a 1s | |
4655 | * delay before we can consider subordinate devices to | |
4656 | * be re-initialized. PCIe has some ways to shorten this, | |
4657 | * but we don't make use of them yet. | |
4658 | */ | |
4659 | ssleep(1); | |
64e8674f | 4660 | } |
d92a208d | 4661 | |
9e33002f GS |
4662 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
4663 | { | |
4664 | pci_reset_secondary_bus(dev); | |
4665 | } | |
4666 | ||
d92a208d | 4667 | /** |
381634ca | 4668 | * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge. |
d92a208d GS |
4669 | * @dev: Bridge device |
4670 | * | |
4671 | * Use the bridge control register to assert reset on the secondary bus. | |
4672 | * Devices on the secondary bus are left in power-on state. | |
4673 | */ | |
381634ca | 4674 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev) |
d92a208d GS |
4675 | { |
4676 | pcibios_reset_secondary_bus(dev); | |
01fd61c0 | 4677 | |
6b2f1351 | 4678 | return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS); |
d92a208d | 4679 | } |
bfc45606 | 4680 | EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); |
64e8674f AW |
4681 | |
4682 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
4683 | { | |
c12ff1df YZ |
4684 | struct pci_dev *pdev; |
4685 | ||
f331a859 AW |
4686 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
4687 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
4688 | return -ENOTTY; |
4689 | ||
4690 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4691 | if (pdev != dev) | |
4692 | return -ENOTTY; | |
4693 | ||
4694 | if (probe) | |
4695 | return 0; | |
4696 | ||
381634ca | 4697 | return pci_bridge_secondary_bus_reset(dev->bus->self); |
c12ff1df YZ |
4698 | } |
4699 | ||
608c3881 AW |
4700 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
4701 | { | |
4702 | int rc = -ENOTTY; | |
4703 | ||
81c4b5bf | 4704 | if (!hotplug || !try_module_get(hotplug->owner)) |
608c3881 AW |
4705 | return rc; |
4706 | ||
4707 | if (hotplug->ops->reset_slot) | |
4708 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
4709 | ||
81c4b5bf | 4710 | module_put(hotplug->owner); |
608c3881 AW |
4711 | |
4712 | return rc; | |
4713 | } | |
4714 | ||
4715 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
4716 | { | |
4717 | struct pci_dev *pdev; | |
4718 | ||
f331a859 AW |
4719 | if (dev->subordinate || !dev->slot || |
4720 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
608c3881 AW |
4721 | return -ENOTTY; |
4722 | ||
4723 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4724 | if (pdev != dev && pdev->slot == dev->slot) | |
4725 | return -ENOTTY; | |
4726 | ||
4727 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
4728 | } | |
4729 | ||
77cb985a AW |
4730 | static void pci_dev_lock(struct pci_dev *dev) |
4731 | { | |
4732 | pci_cfg_access_lock(dev); | |
4733 | /* block PM suspend, driver probe, etc. */ | |
4734 | device_lock(&dev->dev); | |
4735 | } | |
4736 | ||
61cf16d8 AW |
4737 | /* Return 1 on successful lock, 0 on contention */ |
4738 | static int pci_dev_trylock(struct pci_dev *dev) | |
4739 | { | |
4740 | if (pci_cfg_access_trylock(dev)) { | |
4741 | if (device_trylock(&dev->dev)) | |
4742 | return 1; | |
4743 | pci_cfg_access_unlock(dev); | |
4744 | } | |
4745 | ||
4746 | return 0; | |
4747 | } | |
4748 | ||
77cb985a AW |
4749 | static void pci_dev_unlock(struct pci_dev *dev) |
4750 | { | |
4751 | device_unlock(&dev->dev); | |
4752 | pci_cfg_access_unlock(dev); | |
4753 | } | |
4754 | ||
775755ed | 4755 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
3ebe7f9f KB |
4756 | { |
4757 | const struct pci_error_handlers *err_handler = | |
4758 | dev->driver ? dev->driver->err_handler : NULL; | |
3ebe7f9f | 4759 | |
b014e96d | 4760 | /* |
775755ed | 4761 | * dev->driver->err_handler->reset_prepare() is protected against |
b014e96d CH |
4762 | * races with ->remove() by the device lock, which must be held by |
4763 | * the caller. | |
4764 | */ | |
775755ed CH |
4765 | if (err_handler && err_handler->reset_prepare) |
4766 | err_handler->reset_prepare(dev); | |
3ebe7f9f | 4767 | |
a6cbaade AW |
4768 | /* |
4769 | * Wake-up device prior to save. PM registers default to D0 after | |
4770 | * reset and a simple register restore doesn't reliably return | |
4771 | * to a non-D0 state anyway. | |
4772 | */ | |
4773 | pci_set_power_state(dev, PCI_D0); | |
4774 | ||
77cb985a AW |
4775 | pci_save_state(dev); |
4776 | /* | |
4777 | * Disable the device by clearing the Command register, except for | |
4778 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
4779 | * BARs, but also prevents the device from being Bus Master, preventing | |
4780 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
4781 | * compliant devices, INTx-disable prevents legacy interrupts. | |
4782 | */ | |
4783 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
4784 | } | |
4785 | ||
4786 | static void pci_dev_restore(struct pci_dev *dev) | |
4787 | { | |
775755ed CH |
4788 | const struct pci_error_handlers *err_handler = |
4789 | dev->driver ? dev->driver->err_handler : NULL; | |
977f857c | 4790 | |
77cb985a | 4791 | pci_restore_state(dev); |
77cb985a | 4792 | |
775755ed CH |
4793 | /* |
4794 | * dev->driver->err_handler->reset_done() is protected against | |
4795 | * races with ->remove() by the device lock, which must be held by | |
4796 | * the caller. | |
4797 | */ | |
4798 | if (err_handler && err_handler->reset_done) | |
4799 | err_handler->reset_done(dev); | |
d91cdc74 | 4800 | } |
3ebe7f9f | 4801 | |
6fbf9e7a KRW |
4802 | /** |
4803 | * __pci_reset_function_locked - reset a PCI device function while holding | |
4804 | * the @dev mutex lock. | |
4805 | * @dev: PCI device to reset | |
4806 | * | |
4807 | * Some devices allow an individual function to be reset without affecting | |
4808 | * other functions in the same device. The PCI device must be responsive | |
4809 | * to PCI config space in order to use this function. | |
4810 | * | |
4811 | * The device function is presumed to be unused and the caller is holding | |
4812 | * the device mutex lock when this function is called. | |
4813 | * Resetting the device will make the contents of PCI configuration space | |
4814 | * random, so any caller of this must be prepared to reinitialise the | |
4815 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
4816 | * etc. | |
4817 | * | |
4818 | * Returns 0 if the device function was successfully reset or negative if the | |
4819 | * device doesn't support resetting a single function. | |
4820 | */ | |
4821 | int __pci_reset_function_locked(struct pci_dev *dev) | |
4822 | { | |
52354b9d CH |
4823 | int rc; |
4824 | ||
4825 | might_sleep(); | |
4826 | ||
832c418a BH |
4827 | /* |
4828 | * A reset method returns -ENOTTY if it doesn't support this device | |
4829 | * and we should try the next method. | |
4830 | * | |
4831 | * If it returns 0 (success), we're finished. If it returns any | |
4832 | * other error, we're also finished: this indicates that further | |
4833 | * reset mechanisms might be broken on the device. | |
4834 | */ | |
52354b9d CH |
4835 | rc = pci_dev_specific_reset(dev, 0); |
4836 | if (rc != -ENOTTY) | |
4837 | return rc; | |
4838 | if (pcie_has_flr(dev)) { | |
91295d79 SK |
4839 | rc = pcie_flr(dev); |
4840 | if (rc != -ENOTTY) | |
4841 | return rc; | |
52354b9d CH |
4842 | } |
4843 | rc = pci_af_flr(dev, 0); | |
4844 | if (rc != -ENOTTY) | |
4845 | return rc; | |
4846 | rc = pci_pm_reset(dev, 0); | |
4847 | if (rc != -ENOTTY) | |
4848 | return rc; | |
4849 | rc = pci_dev_reset_slot_function(dev, 0); | |
4850 | if (rc != -ENOTTY) | |
4851 | return rc; | |
4852 | return pci_parent_bus_reset(dev, 0); | |
6fbf9e7a KRW |
4853 | } |
4854 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
4855 | ||
711d5779 MT |
4856 | /** |
4857 | * pci_probe_reset_function - check whether the device can be safely reset | |
4858 | * @dev: PCI device to reset | |
4859 | * | |
4860 | * Some devices allow an individual function to be reset without affecting | |
4861 | * other functions in the same device. The PCI device must be responsive | |
4862 | * to PCI config space in order to use this function. | |
4863 | * | |
4864 | * Returns 0 if the device function can be reset or negative if the | |
4865 | * device doesn't support resetting a single function. | |
4866 | */ | |
4867 | int pci_probe_reset_function(struct pci_dev *dev) | |
4868 | { | |
52354b9d CH |
4869 | int rc; |
4870 | ||
4871 | might_sleep(); | |
4872 | ||
4873 | rc = pci_dev_specific_reset(dev, 1); | |
4874 | if (rc != -ENOTTY) | |
4875 | return rc; | |
4876 | if (pcie_has_flr(dev)) | |
4877 | return 0; | |
4878 | rc = pci_af_flr(dev, 1); | |
4879 | if (rc != -ENOTTY) | |
4880 | return rc; | |
4881 | rc = pci_pm_reset(dev, 1); | |
4882 | if (rc != -ENOTTY) | |
4883 | return rc; | |
4884 | rc = pci_dev_reset_slot_function(dev, 1); | |
4885 | if (rc != -ENOTTY) | |
4886 | return rc; | |
4887 | ||
4888 | return pci_parent_bus_reset(dev, 1); | |
711d5779 MT |
4889 | } |
4890 | ||
8dd7f803 | 4891 | /** |
8c1c699f YZ |
4892 | * pci_reset_function - quiesce and reset a PCI device function |
4893 | * @dev: PCI device to reset | |
8dd7f803 SY |
4894 | * |
4895 | * Some devices allow an individual function to be reset without affecting | |
4896 | * other functions in the same device. The PCI device must be responsive | |
4897 | * to PCI config space in order to use this function. | |
4898 | * | |
4899 | * This function does not just reset the PCI portion of a device, but | |
4900 | * clears all the state associated with the device. This function differs | |
79e699b6 JS |
4901 | * from __pci_reset_function_locked() in that it saves and restores device state |
4902 | * over the reset and takes the PCI device lock. | |
8dd7f803 | 4903 | * |
8c1c699f | 4904 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
4905 | * device doesn't support resetting a single function. |
4906 | */ | |
4907 | int pci_reset_function(struct pci_dev *dev) | |
4908 | { | |
8c1c699f | 4909 | int rc; |
8dd7f803 | 4910 | |
204f4afa BH |
4911 | if (!dev->reset_fn) |
4912 | return -ENOTTY; | |
8dd7f803 | 4913 | |
b014e96d | 4914 | pci_dev_lock(dev); |
77cb985a | 4915 | pci_dev_save_and_disable(dev); |
8dd7f803 | 4916 | |
52354b9d | 4917 | rc = __pci_reset_function_locked(dev); |
8dd7f803 | 4918 | |
77cb985a | 4919 | pci_dev_restore(dev); |
b014e96d | 4920 | pci_dev_unlock(dev); |
8dd7f803 | 4921 | |
8c1c699f | 4922 | return rc; |
8dd7f803 SY |
4923 | } |
4924 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
4925 | ||
a477b9cd MZ |
4926 | /** |
4927 | * pci_reset_function_locked - quiesce and reset a PCI device function | |
4928 | * @dev: PCI device to reset | |
4929 | * | |
4930 | * Some devices allow an individual function to be reset without affecting | |
4931 | * other functions in the same device. The PCI device must be responsive | |
4932 | * to PCI config space in order to use this function. | |
4933 | * | |
4934 | * This function does not just reset the PCI portion of a device, but | |
4935 | * clears all the state associated with the device. This function differs | |
79e699b6 | 4936 | * from __pci_reset_function_locked() in that it saves and restores device state |
a477b9cd MZ |
4937 | * over the reset. It also differs from pci_reset_function() in that it |
4938 | * requires the PCI device lock to be held. | |
4939 | * | |
4940 | * Returns 0 if the device function was successfully reset or negative if the | |
4941 | * device doesn't support resetting a single function. | |
4942 | */ | |
4943 | int pci_reset_function_locked(struct pci_dev *dev) | |
4944 | { | |
4945 | int rc; | |
4946 | ||
204f4afa BH |
4947 | if (!dev->reset_fn) |
4948 | return -ENOTTY; | |
a477b9cd MZ |
4949 | |
4950 | pci_dev_save_and_disable(dev); | |
4951 | ||
4952 | rc = __pci_reset_function_locked(dev); | |
4953 | ||
4954 | pci_dev_restore(dev); | |
4955 | ||
4956 | return rc; | |
4957 | } | |
4958 | EXPORT_SYMBOL_GPL(pci_reset_function_locked); | |
4959 | ||
61cf16d8 AW |
4960 | /** |
4961 | * pci_try_reset_function - quiesce and reset a PCI device function | |
4962 | * @dev: PCI device to reset | |
4963 | * | |
4964 | * Same as above, except return -EAGAIN if unable to lock device. | |
4965 | */ | |
4966 | int pci_try_reset_function(struct pci_dev *dev) | |
4967 | { | |
4968 | int rc; | |
4969 | ||
204f4afa BH |
4970 | if (!dev->reset_fn) |
4971 | return -ENOTTY; | |
61cf16d8 | 4972 | |
b014e96d CH |
4973 | if (!pci_dev_trylock(dev)) |
4974 | return -EAGAIN; | |
61cf16d8 | 4975 | |
b014e96d | 4976 | pci_dev_save_and_disable(dev); |
52354b9d | 4977 | rc = __pci_reset_function_locked(dev); |
cb5e0d06 | 4978 | pci_dev_restore(dev); |
b014e96d | 4979 | pci_dev_unlock(dev); |
61cf16d8 | 4980 | |
61cf16d8 AW |
4981 | return rc; |
4982 | } | |
4983 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
4984 | ||
f331a859 AW |
4985 | /* Do any devices on or below this bus prevent a bus reset? */ |
4986 | static bool pci_bus_resetable(struct pci_bus *bus) | |
4987 | { | |
4988 | struct pci_dev *dev; | |
4989 | ||
35702778 DD |
4990 | |
4991 | if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
4992 | return false; | |
4993 | ||
f331a859 AW |
4994 | list_for_each_entry(dev, &bus->devices, bus_list) { |
4995 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
4996 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
4997 | return false; | |
4998 | } | |
4999 | ||
5000 | return true; | |
5001 | } | |
5002 | ||
090a3c53 AW |
5003 | /* Lock devices from the top of the tree down */ |
5004 | static void pci_bus_lock(struct pci_bus *bus) | |
5005 | { | |
5006 | struct pci_dev *dev; | |
5007 | ||
5008 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5009 | pci_dev_lock(dev); | |
5010 | if (dev->subordinate) | |
5011 | pci_bus_lock(dev->subordinate); | |
5012 | } | |
5013 | } | |
5014 | ||
5015 | /* Unlock devices from the bottom of the tree up */ | |
5016 | static void pci_bus_unlock(struct pci_bus *bus) | |
5017 | { | |
5018 | struct pci_dev *dev; | |
5019 | ||
5020 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5021 | if (dev->subordinate) | |
5022 | pci_bus_unlock(dev->subordinate); | |
5023 | pci_dev_unlock(dev); | |
5024 | } | |
5025 | } | |
5026 | ||
61cf16d8 AW |
5027 | /* Return 1 on successful lock, 0 on contention */ |
5028 | static int pci_bus_trylock(struct pci_bus *bus) | |
5029 | { | |
5030 | struct pci_dev *dev; | |
5031 | ||
5032 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5033 | if (!pci_dev_trylock(dev)) | |
5034 | goto unlock; | |
5035 | if (dev->subordinate) { | |
5036 | if (!pci_bus_trylock(dev->subordinate)) { | |
5037 | pci_dev_unlock(dev); | |
5038 | goto unlock; | |
5039 | } | |
5040 | } | |
5041 | } | |
5042 | return 1; | |
5043 | ||
5044 | unlock: | |
5045 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
5046 | if (dev->subordinate) | |
5047 | pci_bus_unlock(dev->subordinate); | |
5048 | pci_dev_unlock(dev); | |
5049 | } | |
5050 | return 0; | |
5051 | } | |
5052 | ||
f331a859 AW |
5053 | /* Do any devices on or below this slot prevent a bus reset? */ |
5054 | static bool pci_slot_resetable(struct pci_slot *slot) | |
5055 | { | |
5056 | struct pci_dev *dev; | |
5057 | ||
33ba90aa JG |
5058 | if (slot->bus->self && |
5059 | (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
5060 | return false; | |
5061 | ||
f331a859 AW |
5062 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { |
5063 | if (!dev->slot || dev->slot != slot) | |
5064 | continue; | |
5065 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
5066 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
5067 | return false; | |
5068 | } | |
5069 | ||
5070 | return true; | |
5071 | } | |
5072 | ||
090a3c53 AW |
5073 | /* Lock devices from the top of the tree down */ |
5074 | static void pci_slot_lock(struct pci_slot *slot) | |
5075 | { | |
5076 | struct pci_dev *dev; | |
5077 | ||
5078 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5079 | if (!dev->slot || dev->slot != slot) | |
5080 | continue; | |
5081 | pci_dev_lock(dev); | |
5082 | if (dev->subordinate) | |
5083 | pci_bus_lock(dev->subordinate); | |
5084 | } | |
5085 | } | |
5086 | ||
5087 | /* Unlock devices from the bottom of the tree up */ | |
5088 | static void pci_slot_unlock(struct pci_slot *slot) | |
5089 | { | |
5090 | struct pci_dev *dev; | |
5091 | ||
5092 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5093 | if (!dev->slot || dev->slot != slot) | |
5094 | continue; | |
5095 | if (dev->subordinate) | |
5096 | pci_bus_unlock(dev->subordinate); | |
5097 | pci_dev_unlock(dev); | |
5098 | } | |
5099 | } | |
5100 | ||
61cf16d8 AW |
5101 | /* Return 1 on successful lock, 0 on contention */ |
5102 | static int pci_slot_trylock(struct pci_slot *slot) | |
5103 | { | |
5104 | struct pci_dev *dev; | |
5105 | ||
5106 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5107 | if (!dev->slot || dev->slot != slot) | |
5108 | continue; | |
5109 | if (!pci_dev_trylock(dev)) | |
5110 | goto unlock; | |
5111 | if (dev->subordinate) { | |
5112 | if (!pci_bus_trylock(dev->subordinate)) { | |
5113 | pci_dev_unlock(dev); | |
5114 | goto unlock; | |
5115 | } | |
5116 | } | |
5117 | } | |
5118 | return 1; | |
5119 | ||
5120 | unlock: | |
5121 | list_for_each_entry_continue_reverse(dev, | |
5122 | &slot->bus->devices, bus_list) { | |
5123 | if (!dev->slot || dev->slot != slot) | |
5124 | continue; | |
5125 | if (dev->subordinate) | |
5126 | pci_bus_unlock(dev->subordinate); | |
5127 | pci_dev_unlock(dev); | |
5128 | } | |
5129 | return 0; | |
5130 | } | |
5131 | ||
ddefc033 AW |
5132 | /* |
5133 | * Save and disable devices from the top of the tree down while holding | |
5134 | * the @dev mutex lock for the entire tree. | |
5135 | */ | |
5136 | static void pci_bus_save_and_disable_locked(struct pci_bus *bus) | |
090a3c53 AW |
5137 | { |
5138 | struct pci_dev *dev; | |
5139 | ||
5140 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5141 | pci_dev_save_and_disable(dev); | |
5142 | if (dev->subordinate) | |
ddefc033 | 5143 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5144 | } |
5145 | } | |
5146 | ||
5147 | /* | |
ddefc033 AW |
5148 | * Restore devices from top of the tree down while holding @dev mutex lock |
5149 | * for the entire tree. Parent bridges need to be restored before we can | |
5150 | * get to subordinate devices. | |
090a3c53 | 5151 | */ |
ddefc033 | 5152 | static void pci_bus_restore_locked(struct pci_bus *bus) |
090a3c53 AW |
5153 | { |
5154 | struct pci_dev *dev; | |
5155 | ||
5156 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5157 | pci_dev_restore(dev); | |
5158 | if (dev->subordinate) | |
ddefc033 | 5159 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5160 | } |
5161 | } | |
5162 | ||
ddefc033 AW |
5163 | /* |
5164 | * Save and disable devices from the top of the tree down while holding | |
5165 | * the @dev mutex lock for the entire tree. | |
5166 | */ | |
5167 | static void pci_slot_save_and_disable_locked(struct pci_slot *slot) | |
090a3c53 AW |
5168 | { |
5169 | struct pci_dev *dev; | |
5170 | ||
5171 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5172 | if (!dev->slot || dev->slot != slot) | |
5173 | continue; | |
5174 | pci_dev_save_and_disable(dev); | |
5175 | if (dev->subordinate) | |
ddefc033 | 5176 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5177 | } |
5178 | } | |
5179 | ||
5180 | /* | |
ddefc033 AW |
5181 | * Restore devices from top of the tree down while holding @dev mutex lock |
5182 | * for the entire tree. Parent bridges need to be restored before we can | |
5183 | * get to subordinate devices. | |
090a3c53 | 5184 | */ |
ddefc033 | 5185 | static void pci_slot_restore_locked(struct pci_slot *slot) |
090a3c53 AW |
5186 | { |
5187 | struct pci_dev *dev; | |
5188 | ||
5189 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5190 | if (!dev->slot || dev->slot != slot) | |
5191 | continue; | |
5192 | pci_dev_restore(dev); | |
5193 | if (dev->subordinate) | |
ddefc033 | 5194 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5195 | } |
5196 | } | |
5197 | ||
5198 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
5199 | { | |
5200 | int rc; | |
5201 | ||
f331a859 | 5202 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
5203 | return -ENOTTY; |
5204 | ||
5205 | if (!probe) | |
5206 | pci_slot_lock(slot); | |
5207 | ||
5208 | might_sleep(); | |
5209 | ||
5210 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
5211 | ||
5212 | if (!probe) | |
5213 | pci_slot_unlock(slot); | |
5214 | ||
5215 | return rc; | |
5216 | } | |
5217 | ||
9a3d2b9b AW |
5218 | /** |
5219 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
5220 | * @slot: PCI slot to probe | |
5221 | * | |
5222 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
5223 | */ | |
5224 | int pci_probe_reset_slot(struct pci_slot *slot) | |
5225 | { | |
5226 | return pci_slot_reset(slot, 1); | |
5227 | } | |
5228 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
5229 | ||
090a3c53 | 5230 | /** |
c6a44ba9 | 5231 | * __pci_reset_slot - Try to reset a PCI slot |
090a3c53 AW |
5232 | * @slot: PCI slot to reset |
5233 | * | |
5234 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
5235 | * independent of other slots. For instance, some slots may support slot power | |
5236 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
5237 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
5238 | * Generally a slot reset should be attempted before a bus reset. All of the | |
5239 | * function of the slot and any subordinate buses behind the slot are reset | |
5240 | * through this function. PCI config space of all devices in the slot and | |
5241 | * behind the slot is saved before and restored after reset. | |
5242 | * | |
61cf16d8 AW |
5243 | * Same as above except return -EAGAIN if the slot cannot be locked |
5244 | */ | |
c6a44ba9 | 5245 | static int __pci_reset_slot(struct pci_slot *slot) |
61cf16d8 AW |
5246 | { |
5247 | int rc; | |
5248 | ||
5249 | rc = pci_slot_reset(slot, 1); | |
5250 | if (rc) | |
5251 | return rc; | |
5252 | ||
61cf16d8 | 5253 | if (pci_slot_trylock(slot)) { |
ddefc033 | 5254 | pci_slot_save_and_disable_locked(slot); |
61cf16d8 AW |
5255 | might_sleep(); |
5256 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
ddefc033 | 5257 | pci_slot_restore_locked(slot); |
61cf16d8 AW |
5258 | pci_slot_unlock(slot); |
5259 | } else | |
5260 | rc = -EAGAIN; | |
5261 | ||
61cf16d8 AW |
5262 | return rc; |
5263 | } | |
61cf16d8 | 5264 | |
090a3c53 AW |
5265 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
5266 | { | |
18426238 SK |
5267 | int ret; |
5268 | ||
f331a859 | 5269 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
5270 | return -ENOTTY; |
5271 | ||
5272 | if (probe) | |
5273 | return 0; | |
5274 | ||
5275 | pci_bus_lock(bus); | |
5276 | ||
5277 | might_sleep(); | |
5278 | ||
381634ca | 5279 | ret = pci_bridge_secondary_bus_reset(bus->self); |
090a3c53 AW |
5280 | |
5281 | pci_bus_unlock(bus); | |
5282 | ||
18426238 | 5283 | return ret; |
090a3c53 AW |
5284 | } |
5285 | ||
c4eed62a KB |
5286 | /** |
5287 | * pci_bus_error_reset - reset the bridge's subordinate bus | |
5288 | * @bridge: The parent device that connects to the bus to reset | |
5289 | * | |
5290 | * This function will first try to reset the slots on this bus if the method is | |
5291 | * available. If slot reset fails or is not available, this will fall back to a | |
5292 | * secondary bus reset. | |
5293 | */ | |
5294 | int pci_bus_error_reset(struct pci_dev *bridge) | |
5295 | { | |
5296 | struct pci_bus *bus = bridge->subordinate; | |
5297 | struct pci_slot *slot; | |
5298 | ||
5299 | if (!bus) | |
5300 | return -ENOTTY; | |
5301 | ||
5302 | mutex_lock(&pci_slot_mutex); | |
5303 | if (list_empty(&bus->slots)) | |
5304 | goto bus_reset; | |
5305 | ||
5306 | list_for_each_entry(slot, &bus->slots, list) | |
5307 | if (pci_probe_reset_slot(slot)) | |
5308 | goto bus_reset; | |
5309 | ||
5310 | list_for_each_entry(slot, &bus->slots, list) | |
5311 | if (pci_slot_reset(slot, 0)) | |
5312 | goto bus_reset; | |
5313 | ||
5314 | mutex_unlock(&pci_slot_mutex); | |
5315 | return 0; | |
5316 | bus_reset: | |
5317 | mutex_unlock(&pci_slot_mutex); | |
5318 | return pci_bus_reset(bridge->subordinate, 0); | |
5319 | } | |
5320 | ||
9a3d2b9b AW |
5321 | /** |
5322 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
5323 | * @bus: PCI bus to probe | |
5324 | * | |
5325 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
5326 | */ | |
5327 | int pci_probe_reset_bus(struct pci_bus *bus) | |
5328 | { | |
5329 | return pci_bus_reset(bus, 1); | |
5330 | } | |
5331 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
5332 | ||
090a3c53 | 5333 | /** |
c6a44ba9 | 5334 | * __pci_reset_bus - Try to reset a PCI bus |
090a3c53 AW |
5335 | * @bus: top level PCI bus to reset |
5336 | * | |
61cf16d8 | 5337 | * Same as above except return -EAGAIN if the bus cannot be locked |
090a3c53 | 5338 | */ |
c6a44ba9 | 5339 | static int __pci_reset_bus(struct pci_bus *bus) |
090a3c53 AW |
5340 | { |
5341 | int rc; | |
5342 | ||
5343 | rc = pci_bus_reset(bus, 1); | |
5344 | if (rc) | |
5345 | return rc; | |
5346 | ||
61cf16d8 | 5347 | if (pci_bus_trylock(bus)) { |
ddefc033 | 5348 | pci_bus_save_and_disable_locked(bus); |
61cf16d8 | 5349 | might_sleep(); |
381634ca | 5350 | rc = pci_bridge_secondary_bus_reset(bus->self); |
ddefc033 | 5351 | pci_bus_restore_locked(bus); |
61cf16d8 AW |
5352 | pci_bus_unlock(bus); |
5353 | } else | |
5354 | rc = -EAGAIN; | |
090a3c53 | 5355 | |
090a3c53 AW |
5356 | return rc; |
5357 | } | |
090a3c53 | 5358 | |
61cf16d8 | 5359 | /** |
c6a44ba9 | 5360 | * pci_reset_bus - Try to reset a PCI bus |
811c5cb3 | 5361 | * @pdev: top level PCI device to reset via slot/bus |
61cf16d8 AW |
5362 | * |
5363 | * Same as above except return -EAGAIN if the bus cannot be locked | |
5364 | */ | |
c6a44ba9 | 5365 | int pci_reset_bus(struct pci_dev *pdev) |
61cf16d8 | 5366 | { |
d8a52810 | 5367 | return (!pci_probe_reset_slot(pdev->slot)) ? |
c6a44ba9 | 5368 | __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); |
61cf16d8 | 5369 | } |
c6a44ba9 | 5370 | EXPORT_SYMBOL_GPL(pci_reset_bus); |
61cf16d8 | 5371 | |
d556ad4b PO |
5372 | /** |
5373 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
5374 | * @dev: PCI device to query | |
5375 | * | |
5376 | * Returns mmrbc: maximum designed memory read count in bytes | |
5377 | * or appropriate error value. | |
5378 | */ | |
5379 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
5380 | { | |
7c9e2b1c | 5381 | int cap; |
d556ad4b PO |
5382 | u32 stat; |
5383 | ||
5384 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5385 | if (!cap) | |
5386 | return -EINVAL; | |
5387 | ||
7c9e2b1c | 5388 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
5389 | return -EINVAL; |
5390 | ||
25daeb55 | 5391 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
5392 | } |
5393 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
5394 | ||
5395 | /** | |
5396 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
5397 | * @dev: PCI device to query | |
5398 | * | |
5399 | * Returns mmrbc: maximum memory read count in bytes | |
5400 | * or appropriate error value. | |
5401 | */ | |
5402 | int pcix_get_mmrbc(struct pci_dev *dev) | |
5403 | { | |
7c9e2b1c | 5404 | int cap; |
bdc2bda7 | 5405 | u16 cmd; |
d556ad4b PO |
5406 | |
5407 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5408 | if (!cap) | |
5409 | return -EINVAL; | |
5410 | ||
7c9e2b1c DN |
5411 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5412 | return -EINVAL; | |
d556ad4b | 5413 | |
7c9e2b1c | 5414 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
5415 | } |
5416 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
5417 | ||
5418 | /** | |
5419 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
5420 | * @dev: PCI device to query | |
5421 | * @mmrbc: maximum memory read count in bytes | |
5422 | * valid values are 512, 1024, 2048, 4096 | |
5423 | * | |
5424 | * If possible sets maximum memory read byte count, some bridges have erratas | |
5425 | * that prevent this. | |
5426 | */ | |
5427 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
5428 | { | |
7c9e2b1c | 5429 | int cap; |
bdc2bda7 DN |
5430 | u32 stat, v, o; |
5431 | u16 cmd; | |
d556ad4b | 5432 | |
229f5afd | 5433 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 5434 | return -EINVAL; |
d556ad4b PO |
5435 | |
5436 | v = ffs(mmrbc) - 10; | |
5437 | ||
5438 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5439 | if (!cap) | |
7c9e2b1c | 5440 | return -EINVAL; |
d556ad4b | 5441 | |
7c9e2b1c DN |
5442 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
5443 | return -EINVAL; | |
d556ad4b PO |
5444 | |
5445 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
5446 | return -E2BIG; | |
5447 | ||
7c9e2b1c DN |
5448 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5449 | return -EINVAL; | |
d556ad4b PO |
5450 | |
5451 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
5452 | if (o != v) { | |
809a3bf9 | 5453 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
5454 | return -EIO; |
5455 | ||
5456 | cmd &= ~PCI_X_CMD_MAX_READ; | |
5457 | cmd |= v << 2; | |
7c9e2b1c DN |
5458 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
5459 | return -EIO; | |
d556ad4b | 5460 | } |
7c9e2b1c | 5461 | return 0; |
d556ad4b PO |
5462 | } |
5463 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
5464 | ||
5465 | /** | |
5466 | * pcie_get_readrq - get PCI Express read request size | |
5467 | * @dev: PCI device to query | |
5468 | * | |
5469 | * Returns maximum memory read request in bytes | |
5470 | * or appropriate error value. | |
5471 | */ | |
5472 | int pcie_get_readrq(struct pci_dev *dev) | |
5473 | { | |
d556ad4b PO |
5474 | u16 ctl; |
5475 | ||
59875ae4 | 5476 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 5477 | |
59875ae4 | 5478 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
5479 | } |
5480 | EXPORT_SYMBOL(pcie_get_readrq); | |
5481 | ||
5482 | /** | |
5483 | * pcie_set_readrq - set PCI Express maximum memory read request | |
5484 | * @dev: PCI device to query | |
42e61f4a | 5485 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
5486 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5487 | * | |
c9b378c7 | 5488 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
5489 | */ |
5490 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
5491 | { | |
59875ae4 | 5492 | u16 v; |
d556ad4b | 5493 | |
229f5afd | 5494 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 5495 | return -EINVAL; |
d556ad4b | 5496 | |
a1c473aa BH |
5497 | /* |
5498 | * If using the "performance" PCIe config, we clamp the | |
5499 | * read rq size to the max packet size to prevent the | |
5500 | * host bridge generating requests larger than we can | |
5501 | * cope with | |
5502 | */ | |
5503 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
5504 | int mps = pcie_get_mps(dev); | |
5505 | ||
a1c473aa BH |
5506 | if (mps < rq) |
5507 | rq = mps; | |
5508 | } | |
5509 | ||
5510 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 5511 | |
59875ae4 JL |
5512 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
5513 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
5514 | } |
5515 | EXPORT_SYMBOL(pcie_set_readrq); | |
5516 | ||
b03e7495 JM |
5517 | /** |
5518 | * pcie_get_mps - get PCI Express maximum payload size | |
5519 | * @dev: PCI device to query | |
5520 | * | |
5521 | * Returns maximum payload size in bytes | |
b03e7495 JM |
5522 | */ |
5523 | int pcie_get_mps(struct pci_dev *dev) | |
5524 | { | |
b03e7495 JM |
5525 | u16 ctl; |
5526 | ||
59875ae4 | 5527 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 5528 | |
59875ae4 | 5529 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 5530 | } |
f1c66c46 | 5531 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
5532 | |
5533 | /** | |
5534 | * pcie_set_mps - set PCI Express maximum payload size | |
5535 | * @dev: PCI device to query | |
47c08f31 | 5536 | * @mps: maximum payload size in bytes |
b03e7495 JM |
5537 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5538 | * | |
5539 | * If possible sets maximum payload size | |
5540 | */ | |
5541 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
5542 | { | |
59875ae4 | 5543 | u16 v; |
b03e7495 JM |
5544 | |
5545 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 5546 | return -EINVAL; |
b03e7495 JM |
5547 | |
5548 | v = ffs(mps) - 8; | |
f7625980 | 5549 | if (v > dev->pcie_mpss) |
59875ae4 | 5550 | return -EINVAL; |
b03e7495 JM |
5551 | v <<= 5; |
5552 | ||
59875ae4 JL |
5553 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
5554 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 | 5555 | } |
f1c66c46 | 5556 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 5557 | |
6db79a88 TG |
5558 | /** |
5559 | * pcie_bandwidth_available - determine minimum link settings of a PCIe | |
5560 | * device and its bandwidth limitation | |
5561 | * @dev: PCI device to query | |
5562 | * @limiting_dev: storage for device causing the bandwidth limitation | |
5563 | * @speed: storage for speed of limiting device | |
5564 | * @width: storage for width of limiting device | |
5565 | * | |
5566 | * Walk up the PCI device chain and find the point where the minimum | |
5567 | * bandwidth is available. Return the bandwidth available there and (if | |
5568 | * limiting_dev, speed, and width pointers are supplied) information about | |
5569 | * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of | |
5570 | * raw bandwidth. | |
5571 | */ | |
5572 | u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, | |
5573 | enum pci_bus_speed *speed, | |
5574 | enum pcie_link_width *width) | |
5575 | { | |
5576 | u16 lnksta; | |
5577 | enum pci_bus_speed next_speed; | |
5578 | enum pcie_link_width next_width; | |
5579 | u32 bw, next_bw; | |
5580 | ||
5581 | if (speed) | |
5582 | *speed = PCI_SPEED_UNKNOWN; | |
5583 | if (width) | |
5584 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
5585 | ||
5586 | bw = 0; | |
5587 | ||
5588 | while (dev) { | |
5589 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
5590 | ||
5591 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
5592 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
5593 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
5594 | ||
5595 | next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); | |
5596 | ||
5597 | /* Check if current device limits the total bandwidth */ | |
5598 | if (!bw || next_bw <= bw) { | |
5599 | bw = next_bw; | |
5600 | ||
5601 | if (limiting_dev) | |
5602 | *limiting_dev = dev; | |
5603 | if (speed) | |
5604 | *speed = next_speed; | |
5605 | if (width) | |
5606 | *width = next_width; | |
5607 | } | |
5608 | ||
5609 | dev = pci_upstream_bridge(dev); | |
5610 | } | |
5611 | ||
5612 | return bw; | |
5613 | } | |
5614 | EXPORT_SYMBOL(pcie_bandwidth_available); | |
5615 | ||
6cf57be0 TG |
5616 | /** |
5617 | * pcie_get_speed_cap - query for the PCI device's link speed capability | |
5618 | * @dev: PCI device to query | |
5619 | * | |
5620 | * Query the PCI device speed capability. Return the maximum link speed | |
5621 | * supported by the device. | |
5622 | */ | |
5623 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) | |
5624 | { | |
5625 | u32 lnkcap2, lnkcap; | |
5626 | ||
5627 | /* | |
f1f90e25 MP |
5628 | * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The |
5629 | * implementation note there recommends using the Supported Link | |
5630 | * Speeds Vector in Link Capabilities 2 when supported. | |
5631 | * | |
5632 | * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software | |
5633 | * should use the Supported Link Speeds field in Link Capabilities, | |
5634 | * where only 2.5 GT/s and 5.0 GT/s speeds were defined. | |
6cf57be0 TG |
5635 | */ |
5636 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); | |
5637 | if (lnkcap2) { /* PCIe r3.0-compliant */ | |
5638 | if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) | |
5639 | return PCIE_SPEED_16_0GT; | |
5640 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
5641 | return PCIE_SPEED_8_0GT; | |
5642 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
5643 | return PCIE_SPEED_5_0GT; | |
5644 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
5645 | return PCIE_SPEED_2_5GT; | |
5646 | return PCI_SPEED_UNKNOWN; | |
5647 | } | |
5648 | ||
5649 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
f1f90e25 MP |
5650 | if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) |
5651 | return PCIE_SPEED_5_0GT; | |
5652 | else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) | |
5653 | return PCIE_SPEED_2_5GT; | |
6cf57be0 TG |
5654 | |
5655 | return PCI_SPEED_UNKNOWN; | |
5656 | } | |
576c7218 | 5657 | EXPORT_SYMBOL(pcie_get_speed_cap); |
6cf57be0 | 5658 | |
c70b65fb TG |
5659 | /** |
5660 | * pcie_get_width_cap - query for the PCI device's link width capability | |
5661 | * @dev: PCI device to query | |
5662 | * | |
5663 | * Query the PCI device width capability. Return the maximum link width | |
5664 | * supported by the device. | |
5665 | */ | |
5666 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) | |
5667 | { | |
5668 | u32 lnkcap; | |
5669 | ||
5670 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
5671 | if (lnkcap) | |
5672 | return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; | |
5673 | ||
5674 | return PCIE_LNK_WIDTH_UNKNOWN; | |
5675 | } | |
576c7218 | 5676 | EXPORT_SYMBOL(pcie_get_width_cap); |
c70b65fb | 5677 | |
b852f63a TG |
5678 | /** |
5679 | * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability | |
5680 | * @dev: PCI device | |
5681 | * @speed: storage for link speed | |
5682 | * @width: storage for link width | |
5683 | * | |
5684 | * Calculate a PCI device's link bandwidth by querying for its link speed | |
5685 | * and width, multiplying them, and applying encoding overhead. The result | |
5686 | * is in Mb/s, i.e., megabits/second of raw bandwidth. | |
5687 | */ | |
5688 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, | |
5689 | enum pcie_link_width *width) | |
5690 | { | |
5691 | *speed = pcie_get_speed_cap(dev); | |
5692 | *width = pcie_get_width_cap(dev); | |
5693 | ||
5694 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
5695 | return 0; | |
5696 | ||
5697 | return *width * PCIE_SPEED2MBS_ENC(*speed); | |
5698 | } | |
5699 | ||
9e506a7b | 5700 | /** |
2d1ce5ec | 5701 | * __pcie_print_link_status - Report the PCI device's link speed and width |
9e506a7b | 5702 | * @dev: PCI device to query |
2d1ce5ec | 5703 | * @verbose: Print info even when enough bandwidth is available |
9e506a7b | 5704 | * |
2d1ce5ec AG |
5705 | * If the available bandwidth at the device is less than the device is |
5706 | * capable of, report the device's maximum possible bandwidth and the | |
5707 | * upstream link that limits its performance. If @verbose, always print | |
5708 | * the available bandwidth, even if the device isn't constrained. | |
9e506a7b | 5709 | */ |
2d1ce5ec | 5710 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose) |
9e506a7b TG |
5711 | { |
5712 | enum pcie_link_width width, width_cap; | |
5713 | enum pci_bus_speed speed, speed_cap; | |
5714 | struct pci_dev *limiting_dev = NULL; | |
5715 | u32 bw_avail, bw_cap; | |
5716 | ||
5717 | bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap); | |
5718 | bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width); | |
5719 | ||
2d1ce5ec | 5720 | if (bw_avail >= bw_cap && verbose) |
0cf22d6b | 5721 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n", |
9e506a7b TG |
5722 | bw_cap / 1000, bw_cap % 1000, |
5723 | PCIE_SPEED2STR(speed_cap), width_cap); | |
2d1ce5ec | 5724 | else if (bw_avail < bw_cap) |
0cf22d6b | 5725 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n", |
9e506a7b TG |
5726 | bw_avail / 1000, bw_avail % 1000, |
5727 | PCIE_SPEED2STR(speed), width, | |
5728 | limiting_dev ? pci_name(limiting_dev) : "<unknown>", | |
5729 | bw_cap / 1000, bw_cap % 1000, | |
5730 | PCIE_SPEED2STR(speed_cap), width_cap); | |
5731 | } | |
2d1ce5ec AG |
5732 | |
5733 | /** | |
5734 | * pcie_print_link_status - Report the PCI device's link speed and width | |
5735 | * @dev: PCI device to query | |
5736 | * | |
5737 | * Report the available bandwidth at the device. | |
5738 | */ | |
5739 | void pcie_print_link_status(struct pci_dev *dev) | |
5740 | { | |
5741 | __pcie_print_link_status(dev, true); | |
5742 | } | |
9e506a7b TG |
5743 | EXPORT_SYMBOL(pcie_print_link_status); |
5744 | ||
c87deff7 HS |
5745 | /** |
5746 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 5747 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
5748 | * @flags: resource type mask to be selected |
5749 | * | |
5750 | * This helper routine makes bar mask from the type of resource. | |
5751 | */ | |
5752 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
5753 | { | |
5754 | int i, bars = 0; | |
5755 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
5756 | if (pci_resource_flags(dev, i) & flags) | |
5757 | bars |= (1 << i); | |
5758 | return bars; | |
5759 | } | |
b7fe9434 | 5760 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 5761 | |
95a8b6ef MT |
5762 | /* Some architectures require additional programming to enable VGA */ |
5763 | static arch_set_vga_state_t arch_set_vga_state; | |
5764 | ||
5765 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
5766 | { | |
5767 | arch_set_vga_state = func; /* NULL disables */ | |
5768 | } | |
5769 | ||
5770 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 5771 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
5772 | { |
5773 | if (arch_set_vga_state) | |
5774 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 5775 | flags); |
95a8b6ef MT |
5776 | return 0; |
5777 | } | |
5778 | ||
deb2d2ec BH |
5779 | /** |
5780 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
5781 | * @dev: the PCI device |
5782 | * @decode: true = enable decoding, false = disable decoding | |
5783 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 5784 | * @flags: traverse ancestors and change bridges |
3448a19d | 5785 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
5786 | */ |
5787 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 5788 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
5789 | { |
5790 | struct pci_bus *bus; | |
5791 | struct pci_dev *bridge; | |
5792 | u16 cmd; | |
95a8b6ef | 5793 | int rc; |
deb2d2ec | 5794 | |
67ebd814 | 5795 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 5796 | |
95a8b6ef | 5797 | /* ARCH specific VGA enables */ |
3448a19d | 5798 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
5799 | if (rc) |
5800 | return rc; | |
5801 | ||
3448a19d DA |
5802 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
5803 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
5804 | if (decode == true) | |
5805 | cmd |= command_bits; | |
5806 | else | |
5807 | cmd &= ~command_bits; | |
5808 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
5809 | } | |
deb2d2ec | 5810 | |
3448a19d | 5811 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
5812 | return 0; |
5813 | ||
5814 | bus = dev->bus; | |
5815 | while (bus) { | |
5816 | bridge = bus->self; | |
5817 | if (bridge) { | |
5818 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
5819 | &cmd); | |
5820 | if (decode == true) | |
5821 | cmd |= PCI_BRIDGE_CTL_VGA; | |
5822 | else | |
5823 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
5824 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
5825 | cmd); | |
5826 | } | |
5827 | bus = bus->parent; | |
5828 | } | |
5829 | return 0; | |
5830 | } | |
5831 | ||
f0af9593 BH |
5832 | /** |
5833 | * pci_add_dma_alias - Add a DMA devfn alias for a device | |
5834 | * @dev: the PCI device for which alias is added | |
5835 | * @devfn: alias slot and function | |
5836 | * | |
f778a0d2 LG |
5837 | * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask |
5838 | * which is used to program permissible bus-devfn source addresses for DMA | |
5839 | * requests in an IOMMU. These aliases factor into IOMMU group creation | |
5840 | * and are useful for devices generating DMA requests beyond or different | |
5841 | * from their logical bus-devfn. Examples include device quirks where the | |
5842 | * device simply uses the wrong devfn, as well as non-transparent bridges | |
5843 | * where the alias may be a proxy for devices in another domain. | |
5844 | * | |
5845 | * IOMMU group creation is performed during device discovery or addition, | |
5846 | * prior to any potential DMA mapping and therefore prior to driver probing | |
5847 | * (especially for userspace assigned devices where IOMMU group definition | |
5848 | * cannot be left as a userspace activity). DMA aliases should therefore | |
5849 | * be configured via quirks, such as the PCI fixup header quirk. | |
f0af9593 BH |
5850 | */ |
5851 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn) | |
5852 | { | |
338c3149 | 5853 | if (!dev->dma_alias_mask) |
c6635792 | 5854 | dev->dma_alias_mask = bitmap_zalloc(U8_MAX, GFP_KERNEL); |
338c3149 | 5855 | if (!dev->dma_alias_mask) { |
7506dc79 | 5856 | pci_warn(dev, "Unable to allocate DMA alias mask\n"); |
338c3149 JL |
5857 | return; |
5858 | } | |
5859 | ||
5860 | set_bit(devfn, dev->dma_alias_mask); | |
7506dc79 | 5861 | pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n", |
48c83080 | 5862 | PCI_SLOT(devfn), PCI_FUNC(devfn)); |
f0af9593 BH |
5863 | } |
5864 | ||
338c3149 JL |
5865 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) |
5866 | { | |
5867 | return (dev1->dma_alias_mask && | |
5868 | test_bit(dev2->devfn, dev1->dma_alias_mask)) || | |
5869 | (dev2->dma_alias_mask && | |
5870 | test_bit(dev1->devfn, dev2->dma_alias_mask)); | |
5871 | } | |
5872 | ||
8496e85c RW |
5873 | bool pci_device_is_present(struct pci_dev *pdev) |
5874 | { | |
5875 | u32 v; | |
5876 | ||
fe2bd75b KB |
5877 | if (pci_dev_is_disconnected(pdev)) |
5878 | return false; | |
8496e85c RW |
5879 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); |
5880 | } | |
5881 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
5882 | ||
08249651 RW |
5883 | void pci_ignore_hotplug(struct pci_dev *dev) |
5884 | { | |
5885 | struct pci_dev *bridge = dev->bus->self; | |
5886 | ||
5887 | dev->ignore_hotplug = 1; | |
5888 | /* Propagate the "ignore hotplug" setting to the parent bridge. */ | |
5889 | if (bridge) | |
5890 | bridge->ignore_hotplug = 1; | |
5891 | } | |
5892 | EXPORT_SYMBOL_GPL(pci_ignore_hotplug); | |
5893 | ||
0a701aa6 YX |
5894 | resource_size_t __weak pcibios_default_alignment(void) |
5895 | { | |
5896 | return 0; | |
5897 | } | |
5898 | ||
32a9a682 YS |
5899 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
5900 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 5901 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
5902 | |
5903 | /** | |
5904 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
5905 | * @dev: the PCI device to get | |
e3adec72 | 5906 | * @resize: whether or not to change resources' size when reassigning alignment |
32a9a682 YS |
5907 | * |
5908 | * RETURNS: Resource alignment if it is specified. | |
5909 | * Zero if it is not specified. | |
5910 | */ | |
e3adec72 YX |
5911 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, |
5912 | bool *resize) | |
32a9a682 | 5913 | { |
07d8d7e5 | 5914 | int align_order, count; |
0a701aa6 | 5915 | resource_size_t align = pcibios_default_alignment(); |
07d8d7e5 LG |
5916 | const char *p; |
5917 | int ret; | |
32a9a682 YS |
5918 | |
5919 | spin_lock(&resource_alignment_lock); | |
5920 | p = resource_alignment_param; | |
0a701aa6 | 5921 | if (!*p && !align) |
f0b99f70 YX |
5922 | goto out; |
5923 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
0a701aa6 | 5924 | align = 0; |
f0b99f70 YX |
5925 | pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n"); |
5926 | goto out; | |
5927 | } | |
5928 | ||
32a9a682 YS |
5929 | while (*p) { |
5930 | count = 0; | |
5931 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
5932 | p[count] == '@') { | |
5933 | p += count + 1; | |
5934 | } else { | |
5935 | align_order = -1; | |
5936 | } | |
07d8d7e5 LG |
5937 | |
5938 | ret = pci_dev_str_match(dev, p, &p); | |
5939 | if (ret == 1) { | |
5940 | *resize = true; | |
5941 | if (align_order == -1) | |
5942 | align = PAGE_SIZE; | |
5943 | else | |
5944 | align = 1 << align_order; | |
5945 | break; | |
5946 | } else if (ret < 0) { | |
5947 | pr_err("PCI: Can't parse resource_alignment parameter: %s\n", | |
5948 | p); | |
5949 | break; | |
32a9a682 | 5950 | } |
07d8d7e5 | 5951 | |
32a9a682 YS |
5952 | if (*p != ';' && *p != ',') { |
5953 | /* End of param or invalid format */ | |
5954 | break; | |
5955 | } | |
5956 | p++; | |
5957 | } | |
f0b99f70 | 5958 | out: |
32a9a682 YS |
5959 | spin_unlock(&resource_alignment_lock); |
5960 | return align; | |
5961 | } | |
5962 | ||
81a5e70e | 5963 | static void pci_request_resource_alignment(struct pci_dev *dev, int bar, |
e3adec72 | 5964 | resource_size_t align, bool resize) |
81a5e70e BH |
5965 | { |
5966 | struct resource *r = &dev->resource[bar]; | |
5967 | resource_size_t size; | |
5968 | ||
5969 | if (!(r->flags & IORESOURCE_MEM)) | |
5970 | return; | |
5971 | ||
5972 | if (r->flags & IORESOURCE_PCI_FIXED) { | |
7506dc79 | 5973 | pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n", |
81a5e70e BH |
5974 | bar, r, (unsigned long long)align); |
5975 | return; | |
5976 | } | |
5977 | ||
5978 | size = resource_size(r); | |
0dde1c08 BH |
5979 | if (size >= align) |
5980 | return; | |
81a5e70e | 5981 | |
0dde1c08 | 5982 | /* |
e3adec72 YX |
5983 | * Increase the alignment of the resource. There are two ways we |
5984 | * can do this: | |
0dde1c08 | 5985 | * |
e3adec72 YX |
5986 | * 1) Increase the size of the resource. BARs are aligned on their |
5987 | * size, so when we reallocate space for this resource, we'll | |
5988 | * allocate it with the larger alignment. This also prevents | |
5989 | * assignment of any other BARs inside the alignment region, so | |
5990 | * if we're requesting page alignment, this means no other BARs | |
5991 | * will share the page. | |
5992 | * | |
5993 | * The disadvantage is that this makes the resource larger than | |
5994 | * the hardware BAR, which may break drivers that compute things | |
5995 | * based on the resource size, e.g., to find registers at a | |
5996 | * fixed offset before the end of the BAR. | |
5997 | * | |
5998 | * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and | |
5999 | * set r->start to the desired alignment. By itself this | |
6000 | * doesn't prevent other BARs being put inside the alignment | |
6001 | * region, but if we realign *every* resource of every device in | |
6002 | * the system, none of them will share an alignment region. | |
6003 | * | |
6004 | * When the user has requested alignment for only some devices via | |
6005 | * the "pci=resource_alignment" argument, "resize" is true and we | |
6006 | * use the first method. Otherwise we assume we're aligning all | |
6007 | * devices and we use the second. | |
0dde1c08 | 6008 | */ |
e3adec72 | 6009 | |
7506dc79 | 6010 | pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n", |
0dde1c08 | 6011 | bar, r, (unsigned long long)align); |
81a5e70e | 6012 | |
e3adec72 YX |
6013 | if (resize) { |
6014 | r->start = 0; | |
6015 | r->end = align - 1; | |
6016 | } else { | |
6017 | r->flags &= ~IORESOURCE_SIZEALIGN; | |
6018 | r->flags |= IORESOURCE_STARTALIGN; | |
6019 | r->start = align; | |
6020 | r->end = r->start + size - 1; | |
6021 | } | |
0dde1c08 | 6022 | r->flags |= IORESOURCE_UNSET; |
81a5e70e BH |
6023 | } |
6024 | ||
2069ecfb YL |
6025 | /* |
6026 | * This function disables memory decoding and releases memory resources | |
6027 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
6028 | * It also rounds up size to specified alignment. | |
6029 | * Later on, the kernel will assign page-aligned memory resource back | |
6030 | * to the device. | |
6031 | */ | |
6032 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
6033 | { | |
6034 | int i; | |
6035 | struct resource *r; | |
81a5e70e | 6036 | resource_size_t align; |
2069ecfb | 6037 | u16 command; |
e3adec72 | 6038 | bool resize = false; |
2069ecfb | 6039 | |
62d9a78f YX |
6040 | /* |
6041 | * VF BARs are read-only zero according to SR-IOV spec r1.1, sec | |
6042 | * 3.4.1.11. Their resources are allocated from the space | |
6043 | * described by the VF BARx register in the PF's SR-IOV capability. | |
6044 | * We can't influence their alignment here. | |
6045 | */ | |
6046 | if (dev->is_virtfn) | |
6047 | return; | |
6048 | ||
10c463a7 | 6049 | /* check if specified PCI is target device to reassign */ |
e3adec72 | 6050 | align = pci_specified_resource_alignment(dev, &resize); |
10c463a7 | 6051 | if (!align) |
2069ecfb YL |
6052 | return; |
6053 | ||
6054 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
6055 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
7506dc79 | 6056 | pci_warn(dev, "Can't reassign resources to host bridge\n"); |
2069ecfb YL |
6057 | return; |
6058 | } | |
6059 | ||
2069ecfb YL |
6060 | pci_read_config_word(dev, PCI_COMMAND, &command); |
6061 | command &= ~PCI_COMMAND_MEMORY; | |
6062 | pci_write_config_word(dev, PCI_COMMAND, command); | |
6063 | ||
81a5e70e | 6064 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) |
e3adec72 | 6065 | pci_request_resource_alignment(dev, i, align, resize); |
f0b99f70 | 6066 | |
81a5e70e BH |
6067 | /* |
6068 | * Need to disable bridge's resource window, | |
2069ecfb YL |
6069 | * to enable the kernel to reassign new resource |
6070 | * window later on. | |
6071 | */ | |
b2fb5cc5 | 6072 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { |
2069ecfb YL |
6073 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { |
6074 | r = &dev->resource[i]; | |
6075 | if (!(r->flags & IORESOURCE_MEM)) | |
6076 | continue; | |
bd064f0a | 6077 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
6078 | r->end = resource_size(r) - 1; |
6079 | r->start = 0; | |
6080 | } | |
6081 | pci_disable_bridge_window(dev); | |
6082 | } | |
6083 | } | |
6084 | ||
9738abed | 6085 | static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
32a9a682 YS |
6086 | { |
6087 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
6088 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
6089 | spin_lock(&resource_alignment_lock); | |
6090 | strncpy(resource_alignment_param, buf, count); | |
6091 | resource_alignment_param[count] = '\0'; | |
6092 | spin_unlock(&resource_alignment_lock); | |
6093 | return count; | |
6094 | } | |
6095 | ||
9738abed | 6096 | static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
32a9a682 YS |
6097 | { |
6098 | size_t count; | |
6099 | spin_lock(&resource_alignment_lock); | |
6100 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
6101 | spin_unlock(&resource_alignment_lock); | |
6102 | return count; | |
6103 | } | |
6104 | ||
d61dfafc | 6105 | static ssize_t resource_alignment_show(struct bus_type *bus, char *buf) |
32a9a682 YS |
6106 | { |
6107 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
6108 | } | |
6109 | ||
d61dfafc | 6110 | static ssize_t resource_alignment_store(struct bus_type *bus, |
32a9a682 YS |
6111 | const char *buf, size_t count) |
6112 | { | |
6113 | return pci_set_resource_alignment_param(buf, count); | |
6114 | } | |
6115 | ||
d61dfafc | 6116 | static BUS_ATTR_RW(resource_alignment); |
32a9a682 YS |
6117 | |
6118 | static int __init pci_resource_alignment_sysfs_init(void) | |
6119 | { | |
6120 | return bus_create_file(&pci_bus_type, | |
6121 | &bus_attr_resource_alignment); | |
6122 | } | |
32a9a682 YS |
6123 | late_initcall(pci_resource_alignment_sysfs_init); |
6124 | ||
15856ad5 | 6125 | static void pci_no_domains(void) |
32a2eea7 JG |
6126 | { |
6127 | #ifdef CONFIG_PCI_DOMAINS | |
6128 | pci_domains_supported = 0; | |
6129 | #endif | |
6130 | } | |
6131 | ||
ae07b786 | 6132 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
41e5c0f8 LD |
6133 | static atomic_t __domain_nr = ATOMIC_INIT(-1); |
6134 | ||
ae07b786 | 6135 | static int pci_get_new_domain_nr(void) |
41e5c0f8 LD |
6136 | { |
6137 | return atomic_inc_return(&__domain_nr); | |
6138 | } | |
7c674700 | 6139 | |
1a4f93f7 | 6140 | static int of_pci_bus_find_domain_nr(struct device *parent) |
7c674700 LP |
6141 | { |
6142 | static int use_dt_domains = -1; | |
54c6e2dd | 6143 | int domain = -1; |
7c674700 | 6144 | |
54c6e2dd KHC |
6145 | if (parent) |
6146 | domain = of_get_pci_domain_nr(parent->of_node); | |
7c674700 LP |
6147 | /* |
6148 | * Check DT domain and use_dt_domains values. | |
6149 | * | |
6150 | * If DT domain property is valid (domain >= 0) and | |
6151 | * use_dt_domains != 0, the DT assignment is valid since this means | |
6152 | * we have not previously allocated a domain number by using | |
6153 | * pci_get_new_domain_nr(); we should also update use_dt_domains to | |
6154 | * 1, to indicate that we have just assigned a domain number from | |
6155 | * DT. | |
6156 | * | |
6157 | * If DT domain property value is not valid (ie domain < 0), and we | |
6158 | * have not previously assigned a domain number from DT | |
6159 | * (use_dt_domains != 1) we should assign a domain number by | |
6160 | * using the: | |
6161 | * | |
6162 | * pci_get_new_domain_nr() | |
6163 | * | |
6164 | * API and update the use_dt_domains value to keep track of method we | |
6165 | * are using to assign domain numbers (use_dt_domains = 0). | |
6166 | * | |
6167 | * All other combinations imply we have a platform that is trying | |
6168 | * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), | |
6169 | * which is a recipe for domain mishandling and it is prevented by | |
6170 | * invalidating the domain value (domain = -1) and printing a | |
6171 | * corresponding error. | |
6172 | */ | |
6173 | if (domain >= 0 && use_dt_domains) { | |
6174 | use_dt_domains = 1; | |
6175 | } else if (domain < 0 && use_dt_domains != 1) { | |
6176 | use_dt_domains = 0; | |
6177 | domain = pci_get_new_domain_nr(); | |
6178 | } else { | |
9df1c6ec SL |
6179 | if (parent) |
6180 | pr_err("Node %pOF has ", parent->of_node); | |
6181 | pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); | |
7c674700 LP |
6182 | domain = -1; |
6183 | } | |
6184 | ||
9c7cb891 | 6185 | return domain; |
7c674700 | 6186 | } |
1a4f93f7 TN |
6187 | |
6188 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) | |
6189 | { | |
2ab51dde TN |
6190 | return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : |
6191 | acpi_pci_bus_find_domain_nr(bus); | |
7c674700 LP |
6192 | } |
6193 | #endif | |
41e5c0f8 | 6194 | |
0ef5f8f6 | 6195 | /** |
642c92da | 6196 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
6197 | * |
6198 | * Returns 1 if we can access PCI extended config space (offsets | |
6199 | * greater than 0xff). This is the default implementation. Architecture | |
6200 | * implementations can override this. | |
6201 | */ | |
642c92da | 6202 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
6203 | { |
6204 | return 1; | |
6205 | } | |
6206 | ||
2d1c8618 BH |
6207 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
6208 | { | |
6209 | } | |
6210 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
6211 | ||
ad04d31e | 6212 | static int __init pci_setup(char *str) |
1da177e4 LT |
6213 | { |
6214 | while (str) { | |
6215 | char *k = strchr(str, ','); | |
6216 | if (k) | |
6217 | *k++ = 0; | |
6218 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
6219 | if (!strcmp(str, "nomsi")) { |
6220 | pci_no_msi(); | |
cef74409 GK |
6221 | } else if (!strncmp(str, "noats", 5)) { |
6222 | pr_info("PCIe: ATS is disabled\n"); | |
6223 | pcie_ats_disabled = true; | |
7f785763 RD |
6224 | } else if (!strcmp(str, "noaer")) { |
6225 | pci_no_aer(); | |
11eb0e0e SK |
6226 | } else if (!strcmp(str, "earlydump")) { |
6227 | pci_early_dump = true; | |
b55438fd YL |
6228 | } else if (!strncmp(str, "realloc=", 8)) { |
6229 | pci_realloc_get_opt(str + 8); | |
f483d392 | 6230 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 6231 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
6232 | } else if (!strcmp(str, "nodomains")) { |
6233 | pci_no_domains(); | |
6748dcc2 RW |
6234 | } else if (!strncmp(str, "noari", 5)) { |
6235 | pcie_ari_disabled = true; | |
4516a618 AN |
6236 | } else if (!strncmp(str, "cbiosize=", 9)) { |
6237 | pci_cardbus_io_size = memparse(str + 9, &str); | |
6238 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
6239 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
6240 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
6241 | pci_set_resource_alignment_param(str + 19, | |
6242 | strlen(str + 19)); | |
43c16408 AP |
6243 | } else if (!strncmp(str, "ecrc=", 5)) { |
6244 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
6245 | } else if (!strncmp(str, "hpiosize=", 9)) { |
6246 | pci_hotplug_io_size = memparse(str + 9, &str); | |
6247 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
6248 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
e16b4660 KB |
6249 | } else if (!strncmp(str, "hpbussize=", 10)) { |
6250 | pci_hotplug_bus_size = | |
6251 | simple_strtoul(str + 10, &str, 0); | |
6252 | if (pci_hotplug_bus_size > 0xff) | |
6253 | pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
5f39e670 JM |
6254 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
6255 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
6256 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
6257 | pcie_bus_config = PCIE_BUS_SAFE; | |
6258 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
6259 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
6260 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
6261 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
6262 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
6263 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
aaca43fd | 6264 | } else if (!strncmp(str, "disable_acs_redir=", 18)) { |
d2fd6e81 LG |
6265 | disable_acs_redir_param = |
6266 | kstrdup(str + 18, GFP_KERNEL); | |
309e57df | 6267 | } else { |
25da8dba | 6268 | pr_err("PCI: Unknown option `%s'\n", str); |
309e57df | 6269 | } |
1da177e4 LT |
6270 | } |
6271 | str = k; | |
6272 | } | |
0637a70a | 6273 | return 0; |
1da177e4 | 6274 | } |
0637a70a | 6275 | early_param("pci", pci_setup); |