Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ | |
3 | * | |
4 | * PCI Bus Services, see include/linux/pci.h for further explanation. | |
5 | * | |
6 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
7 | * David Mosberger-Tang | |
8 | * | |
9 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/spinlock.h> | |
4e57b681 | 18 | #include <linux/string.h> |
1da177e4 | 19 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 20 | #include "pci.h" |
1da177e4 | 21 | |
ffadcc2f | 22 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 LT |
23 | |
24 | /** | |
25 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
26 | * @bus: pointer to PCI bus structure to search | |
27 | * | |
28 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
29 | * including the given PCI bus and its list of child PCI buses. | |
30 | */ | |
31 | unsigned char __devinit | |
32 | pci_bus_max_busnr(struct pci_bus* bus) | |
33 | { | |
34 | struct list_head *tmp; | |
35 | unsigned char max, n; | |
36 | ||
b82db5ce | 37 | max = bus->subordinate; |
1da177e4 LT |
38 | list_for_each(tmp, &bus->children) { |
39 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
40 | if(n > max) | |
41 | max = n; | |
42 | } | |
43 | return max; | |
44 | } | |
b82db5ce | 45 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 46 | |
b82db5ce | 47 | #if 0 |
1da177e4 LT |
48 | /** |
49 | * pci_max_busnr - returns maximum PCI bus number | |
50 | * | |
51 | * Returns the highest PCI bus number present in the system global list of | |
52 | * PCI buses. | |
53 | */ | |
54 | unsigned char __devinit | |
55 | pci_max_busnr(void) | |
56 | { | |
57 | struct pci_bus *bus = NULL; | |
58 | unsigned char max, n; | |
59 | ||
60 | max = 0; | |
61 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
62 | n = pci_bus_max_busnr(bus); | |
63 | if(n > max) | |
64 | max = n; | |
65 | } | |
66 | return max; | |
67 | } | |
68 | ||
54c762fe AB |
69 | #endif /* 0 */ |
70 | ||
687d5fe3 ME |
71 | #define PCI_FIND_CAP_TTL 48 |
72 | ||
73 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
74 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
75 | { |
76 | u8 id; | |
24a4e377 | 77 | |
687d5fe3 | 78 | while ((*ttl)--) { |
24a4e377 RD |
79 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
80 | if (pos < 0x40) | |
81 | break; | |
82 | pos &= ~3; | |
83 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
84 | &id); | |
85 | if (id == 0xff) | |
86 | break; | |
87 | if (id == cap) | |
88 | return pos; | |
89 | pos += PCI_CAP_LIST_NEXT; | |
90 | } | |
91 | return 0; | |
92 | } | |
93 | ||
687d5fe3 ME |
94 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
95 | u8 pos, int cap) | |
96 | { | |
97 | int ttl = PCI_FIND_CAP_TTL; | |
98 | ||
99 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
100 | } | |
101 | ||
24a4e377 RD |
102 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
103 | { | |
104 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
105 | pos + PCI_CAP_LIST_NEXT, cap); | |
106 | } | |
107 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
108 | ||
d3bac118 ME |
109 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
110 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
111 | { |
112 | u16 status; | |
1da177e4 LT |
113 | |
114 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
115 | if (!(status & PCI_STATUS_CAP_LIST)) | |
116 | return 0; | |
117 | ||
118 | switch (hdr_type) { | |
119 | case PCI_HEADER_TYPE_NORMAL: | |
120 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 121 | return PCI_CAPABILITY_LIST; |
1da177e4 | 122 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 123 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
124 | default: |
125 | return 0; | |
126 | } | |
d3bac118 ME |
127 | |
128 | return 0; | |
1da177e4 LT |
129 | } |
130 | ||
131 | /** | |
132 | * pci_find_capability - query for devices' capabilities | |
133 | * @dev: PCI device to query | |
134 | * @cap: capability code | |
135 | * | |
136 | * Tell if a device supports a given PCI capability. | |
137 | * Returns the address of the requested capability structure within the | |
138 | * device's PCI configuration space or 0 in case the device does not | |
139 | * support it. Possible values for @cap: | |
140 | * | |
141 | * %PCI_CAP_ID_PM Power Management | |
142 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
143 | * %PCI_CAP_ID_VPD Vital Product Data | |
144 | * %PCI_CAP_ID_SLOTID Slot Identification | |
145 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
146 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
147 | * %PCI_CAP_ID_PCIX PCI-X | |
148 | * %PCI_CAP_ID_EXP PCI Express | |
149 | */ | |
150 | int pci_find_capability(struct pci_dev *dev, int cap) | |
151 | { | |
d3bac118 ME |
152 | int pos; |
153 | ||
154 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
155 | if (pos) | |
156 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
157 | ||
158 | return pos; | |
1da177e4 LT |
159 | } |
160 | ||
161 | /** | |
162 | * pci_bus_find_capability - query for devices' capabilities | |
163 | * @bus: the PCI bus to query | |
164 | * @devfn: PCI device to query | |
165 | * @cap: capability code | |
166 | * | |
167 | * Like pci_find_capability() but works for pci devices that do not have a | |
168 | * pci_dev structure set up yet. | |
169 | * | |
170 | * Returns the address of the requested capability structure within the | |
171 | * device's PCI configuration space or 0 in case the device does not | |
172 | * support it. | |
173 | */ | |
174 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
175 | { | |
d3bac118 | 176 | int pos; |
1da177e4 LT |
177 | u8 hdr_type; |
178 | ||
179 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
180 | ||
d3bac118 ME |
181 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
182 | if (pos) | |
183 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
184 | ||
185 | return pos; | |
1da177e4 LT |
186 | } |
187 | ||
188 | /** | |
189 | * pci_find_ext_capability - Find an extended capability | |
190 | * @dev: PCI device to query | |
191 | * @cap: capability code | |
192 | * | |
193 | * Returns the address of the requested extended capability structure | |
194 | * within the device's PCI configuration space or 0 if the device does | |
195 | * not support it. Possible values for @cap: | |
196 | * | |
197 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
198 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
199 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
200 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
201 | */ | |
202 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
203 | { | |
204 | u32 header; | |
205 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
206 | int pos = 0x100; | |
207 | ||
208 | if (dev->cfg_size <= 256) | |
209 | return 0; | |
210 | ||
211 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
212 | return 0; | |
213 | ||
214 | /* | |
215 | * If we have no capabilities, this is indicated by cap ID, | |
216 | * cap version and next pointer all being 0. | |
217 | */ | |
218 | if (header == 0) | |
219 | return 0; | |
220 | ||
221 | while (ttl-- > 0) { | |
222 | if (PCI_EXT_CAP_ID(header) == cap) | |
223 | return pos; | |
224 | ||
225 | pos = PCI_EXT_CAP_NEXT(header); | |
226 | if (pos < 0x100) | |
227 | break; | |
228 | ||
229 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
230 | break; | |
231 | } | |
232 | ||
233 | return 0; | |
234 | } | |
3a720d72 | 235 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 236 | |
687d5fe3 ME |
237 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
238 | { | |
239 | int rc, ttl = PCI_FIND_CAP_TTL; | |
240 | u8 cap, mask; | |
241 | ||
242 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
243 | mask = HT_3BIT_CAP_MASK; | |
244 | else | |
245 | mask = HT_5BIT_CAP_MASK; | |
246 | ||
247 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
248 | PCI_CAP_ID_HT, &ttl); | |
249 | while (pos) { | |
250 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
251 | if (rc != PCIBIOS_SUCCESSFUL) | |
252 | return 0; | |
253 | ||
254 | if ((cap & mask) == ht_cap) | |
255 | return pos; | |
256 | ||
47a4d5be BG |
257 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
258 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
259 | PCI_CAP_ID_HT, &ttl); |
260 | } | |
261 | ||
262 | return 0; | |
263 | } | |
264 | /** | |
265 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
266 | * @dev: PCI device to query | |
267 | * @pos: Position from which to continue searching | |
268 | * @ht_cap: Hypertransport capability code | |
269 | * | |
270 | * To be used in conjunction with pci_find_ht_capability() to search for | |
271 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
272 | * from pci_find_ht_capability(). | |
273 | * | |
274 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
275 | * steps to avoid an infinite loop. | |
276 | */ | |
277 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
278 | { | |
279 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
280 | } | |
281 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
282 | ||
283 | /** | |
284 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
285 | * @dev: PCI device to query | |
286 | * @ht_cap: Hypertransport capability code | |
287 | * | |
288 | * Tell if a device supports a given Hypertransport capability. | |
289 | * Returns an address within the device's PCI configuration space | |
290 | * or 0 in case the device does not support the request capability. | |
291 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
292 | * which has a Hypertransport capability matching @ht_cap. | |
293 | */ | |
294 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
295 | { | |
296 | int pos; | |
297 | ||
298 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
299 | if (pos) | |
300 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
301 | ||
302 | return pos; | |
303 | } | |
304 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
305 | ||
1da177e4 LT |
306 | /** |
307 | * pci_find_parent_resource - return resource region of parent bus of given region | |
308 | * @dev: PCI device structure contains resources to be searched | |
309 | * @res: child resource record for which parent is sought | |
310 | * | |
311 | * For given resource region of given device, return the resource | |
312 | * region of parent bus the given region is contained in or where | |
313 | * it should be allocated from. | |
314 | */ | |
315 | struct resource * | |
316 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
317 | { | |
318 | const struct pci_bus *bus = dev->bus; | |
319 | int i; | |
320 | struct resource *best = NULL; | |
321 | ||
322 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
323 | struct resource *r = bus->resource[i]; | |
324 | if (!r) | |
325 | continue; | |
326 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
327 | continue; /* Not contained */ | |
328 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
329 | continue; /* Wrong type */ | |
330 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
331 | return r; /* Exact match */ | |
332 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
333 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
334 | } | |
335 | return best; | |
336 | } | |
337 | ||
064b53db JL |
338 | /** |
339 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
340 | * @dev: PCI device to have its BARs restored | |
341 | * | |
342 | * Restore the BAR values for a given device, so as to make it | |
343 | * accessible by its driver. | |
344 | */ | |
345 | void | |
346 | pci_restore_bars(struct pci_dev *dev) | |
347 | { | |
348 | int i, numres; | |
349 | ||
350 | switch (dev->hdr_type) { | |
351 | case PCI_HEADER_TYPE_NORMAL: | |
352 | numres = 6; | |
353 | break; | |
354 | case PCI_HEADER_TYPE_BRIDGE: | |
355 | numres = 2; | |
356 | break; | |
357 | case PCI_HEADER_TYPE_CARDBUS: | |
358 | numres = 1; | |
359 | break; | |
360 | default: | |
361 | /* Should never get here, but just in case... */ | |
362 | return; | |
363 | } | |
364 | ||
365 | for (i = 0; i < numres; i ++) | |
366 | pci_update_resource(dev, &dev->resource[i], i); | |
367 | } | |
368 | ||
8f7020d3 RD |
369 | int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); |
370 | ||
1da177e4 LT |
371 | /** |
372 | * pci_set_power_state - Set the power state of a PCI device | |
373 | * @dev: PCI device to be suspended | |
374 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering | |
375 | * | |
376 | * Transition a device to a new power state, using the Power Management | |
377 | * Capabilities in the device's config space. | |
378 | * | |
379 | * RETURN VALUE: | |
380 | * -EINVAL if trying to enter a lower state than we're already in. | |
381 | * 0 if we're already in the requested state. | |
382 | * -EIO if device does not support PCI PM. | |
383 | * 0 if we can successfully change the power state. | |
384 | */ | |
1da177e4 LT |
385 | int |
386 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
387 | { | |
064b53db | 388 | int pm, need_restore = 0; |
1da177e4 LT |
389 | u16 pmcsr, pmc; |
390 | ||
391 | /* bound the state we're entering */ | |
392 | if (state > PCI_D3hot) | |
393 | state = PCI_D3hot; | |
394 | ||
e36c455c PM |
395 | /* |
396 | * If the device or the parent bridge can't support PCI PM, ignore | |
397 | * the request if we're doing anything besides putting it into D0 | |
398 | * (which would only happen on boot). | |
399 | */ | |
400 | if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
401 | return 0; | |
402 | ||
1da177e4 LT |
403 | /* Validate current state: |
404 | * Can enter D0 from any state, but if we can only go deeper | |
405 | * to sleep if we're already in a low power state | |
406 | */ | |
02669492 AM |
407 | if (state != PCI_D0 && dev->current_state > state) { |
408 | printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", | |
409 | __FUNCTION__, pci_name(dev), state, dev->current_state); | |
1da177e4 | 410 | return -EINVAL; |
02669492 | 411 | } else if (dev->current_state == state) |
1da177e4 LT |
412 | return 0; /* we're already there */ |
413 | ||
ffadcc2f | 414 | |
1da177e4 LT |
415 | /* find PCI PM capability in list */ |
416 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
417 | ||
418 | /* abort if the device doesn't support PM capabilities */ | |
419 | if (!pm) | |
420 | return -EIO; | |
421 | ||
422 | pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); | |
3fe9d19f | 423 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1da177e4 LT |
424 | printk(KERN_DEBUG |
425 | "PCI: %s has unsupported PM cap regs version (%u)\n", | |
426 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); | |
427 | return -EIO; | |
428 | } | |
429 | ||
430 | /* check if this device supports the desired state */ | |
3fe9d19f DR |
431 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
432 | return -EIO; | |
433 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) | |
434 | return -EIO; | |
1da177e4 | 435 | |
064b53db JL |
436 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
437 | ||
32a36585 | 438 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
439 | * This doesn't affect PME_Status, disables PME_En, and |
440 | * sets PowerState to 0. | |
441 | */ | |
32a36585 | 442 | switch (dev->current_state) { |
d3535fbb JL |
443 | case PCI_D0: |
444 | case PCI_D1: | |
445 | case PCI_D2: | |
446 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
447 | pmcsr |= state; | |
448 | break; | |
32a36585 JL |
449 | case PCI_UNKNOWN: /* Boot-up */ |
450 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
451 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
064b53db | 452 | need_restore = 1; |
32a36585 | 453 | /* Fall-through: force to D0 */ |
32a36585 | 454 | default: |
d3535fbb | 455 | pmcsr = 0; |
32a36585 | 456 | break; |
1da177e4 LT |
457 | } |
458 | ||
459 | /* enter specified state */ | |
460 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
461 | ||
462 | /* Mandatory power management transition delays */ | |
463 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
464 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 465 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
466 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
467 | udelay(200); | |
1da177e4 | 468 | |
b913100d DSL |
469 | /* |
470 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx | |
d6e05edc | 471 | * Firmware method after native method ? |
b913100d DSL |
472 | */ |
473 | if (platform_pci_set_power_state) | |
474 | platform_pci_set_power_state(dev, state); | |
475 | ||
476 | dev->current_state = state; | |
064b53db JL |
477 | |
478 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
479 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
480 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
481 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
482 | * For example, at least some versions of the 3c905B and the | |
483 | * 3c556B exhibit this behaviour. | |
484 | * | |
485 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
486 | * devices in a D3hot state at boot. Consequently, we need to | |
487 | * restore at least the BARs so that the device will be | |
488 | * accessible to its driver. | |
489 | */ | |
490 | if (need_restore) | |
491 | pci_restore_bars(dev); | |
492 | ||
1da177e4 LT |
493 | return 0; |
494 | } | |
495 | ||
f165b10f | 496 | int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); |
0f64474b | 497 | |
1da177e4 LT |
498 | /** |
499 | * pci_choose_state - Choose the power state of a PCI device | |
500 | * @dev: PCI device to be suspended | |
501 | * @state: target sleep state for the whole system. This is the value | |
502 | * that is passed to suspend() function. | |
503 | * | |
504 | * Returns PCI power state suitable for given device and given system | |
505 | * message. | |
506 | */ | |
507 | ||
508 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
509 | { | |
0f64474b DSL |
510 | int ret; |
511 | ||
1da177e4 LT |
512 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
513 | return PCI_D0; | |
514 | ||
0f64474b DSL |
515 | if (platform_pci_choose_state) { |
516 | ret = platform_pci_choose_state(dev, state); | |
517 | if (ret >= 0) | |
ca078bae | 518 | state.event = ret; |
0f64474b | 519 | } |
ca078bae PM |
520 | |
521 | switch (state.event) { | |
522 | case PM_EVENT_ON: | |
523 | return PCI_D0; | |
524 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
525 | case PM_EVENT_PRETHAW: |
526 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae PM |
527 | case PM_EVENT_SUSPEND: |
528 | return PCI_D3hot; | |
1da177e4 | 529 | default: |
b887d2e6 | 530 | printk("Unrecognized suspend event %d\n", state.event); |
1da177e4 LT |
531 | BUG(); |
532 | } | |
533 | return PCI_D0; | |
534 | } | |
535 | ||
536 | EXPORT_SYMBOL(pci_choose_state); | |
537 | ||
b56a5a23 MT |
538 | static int pci_save_pcie_state(struct pci_dev *dev) |
539 | { | |
540 | int pos, i = 0; | |
541 | struct pci_cap_saved_state *save_state; | |
542 | u16 *cap; | |
543 | ||
544 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
545 | if (pos <= 0) | |
546 | return 0; | |
547 | ||
548 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
549 | if (!save_state) { | |
550 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
551 | return -ENOMEM; | |
552 | } | |
553 | cap = (u16 *)&save_state->data[0]; | |
554 | ||
555 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
556 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
557 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
558 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
559 | pci_add_saved_cap(dev, save_state); | |
560 | return 0; | |
561 | } | |
562 | ||
563 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
564 | { | |
565 | int i = 0, pos; | |
566 | struct pci_cap_saved_state *save_state; | |
567 | u16 *cap; | |
568 | ||
569 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
570 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
571 | if (!save_state || pos <= 0) | |
572 | return; | |
573 | cap = (u16 *)&save_state->data[0]; | |
574 | ||
575 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
576 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
577 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
578 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
579 | pci_remove_saved_cap(save_state); | |
580 | kfree(save_state); | |
581 | } | |
582 | ||
cc692a5f SH |
583 | |
584 | static int pci_save_pcix_state(struct pci_dev *dev) | |
585 | { | |
586 | int pos, i = 0; | |
587 | struct pci_cap_saved_state *save_state; | |
588 | u16 *cap; | |
589 | ||
590 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
591 | if (pos <= 0) | |
592 | return 0; | |
593 | ||
594 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); | |
595 | if (!save_state) { | |
596 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
597 | return -ENOMEM; | |
598 | } | |
599 | cap = (u16 *)&save_state->data[0]; | |
600 | ||
601 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); | |
602 | pci_add_saved_cap(dev, save_state); | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
607 | { | |
608 | int i = 0, pos; | |
609 | struct pci_cap_saved_state *save_state; | |
610 | u16 *cap; | |
611 | ||
612 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
613 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
614 | if (!save_state || pos <= 0) | |
615 | return; | |
616 | cap = (u16 *)&save_state->data[0]; | |
617 | ||
618 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
619 | pci_remove_saved_cap(save_state); | |
620 | kfree(save_state); | |
621 | } | |
622 | ||
623 | ||
1da177e4 LT |
624 | /** |
625 | * pci_save_state - save the PCI configuration space of a device before suspending | |
626 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
627 | */ |
628 | int | |
629 | pci_save_state(struct pci_dev *dev) | |
630 | { | |
631 | int i; | |
632 | /* XXX: 100% dword access ok here? */ | |
633 | for (i = 0; i < 16; i++) | |
634 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
41017f0c SL |
635 | if ((i = pci_save_msi_state(dev)) != 0) |
636 | return i; | |
637 | if ((i = pci_save_msix_state(dev)) != 0) | |
638 | return i; | |
b56a5a23 MT |
639 | if ((i = pci_save_pcie_state(dev)) != 0) |
640 | return i; | |
cc692a5f SH |
641 | if ((i = pci_save_pcix_state(dev)) != 0) |
642 | return i; | |
1da177e4 LT |
643 | return 0; |
644 | } | |
645 | ||
646 | /** | |
647 | * pci_restore_state - Restore the saved state of a PCI device | |
648 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
649 | */ |
650 | int | |
651 | pci_restore_state(struct pci_dev *dev) | |
652 | { | |
653 | int i; | |
04d9c1a1 | 654 | int val; |
1da177e4 | 655 | |
b56a5a23 MT |
656 | /* PCI Express register must be restored first */ |
657 | pci_restore_pcie_state(dev); | |
658 | ||
8b8c8d28 YL |
659 | /* |
660 | * The Base Address register should be programmed before the command | |
661 | * register(s) | |
662 | */ | |
663 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
664 | pci_read_config_dword(dev, i * 4, &val); |
665 | if (val != dev->saved_config_space[i]) { | |
666 | printk(KERN_DEBUG "PM: Writing back config space on " | |
667 | "device %s at offset %x (was %x, writing %x)\n", | |
668 | pci_name(dev), i, | |
669 | val, (int)dev->saved_config_space[i]); | |
670 | pci_write_config_dword(dev,i * 4, | |
671 | dev->saved_config_space[i]); | |
672 | } | |
673 | } | |
cc692a5f | 674 | pci_restore_pcix_state(dev); |
41017f0c SL |
675 | pci_restore_msi_state(dev); |
676 | pci_restore_msix_state(dev); | |
1da177e4 LT |
677 | return 0; |
678 | } | |
679 | ||
38cc1302 HS |
680 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
681 | { | |
682 | int err; | |
683 | ||
684 | err = pci_set_power_state(dev, PCI_D0); | |
685 | if (err < 0 && err != -EIO) | |
686 | return err; | |
687 | err = pcibios_enable_device(dev, bars); | |
688 | if (err < 0) | |
689 | return err; | |
690 | pci_fixup_device(pci_fixup_enable, dev); | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
695 | /** | |
696 | * __pci_reenable_device - Resume abandoned device | |
697 | * @dev: PCI device to be resumed | |
698 | * | |
699 | * Note this function is a backend of pci_default_resume and is not supposed | |
700 | * to be called by normal code, write proper resume handler and use it instead. | |
701 | */ | |
702 | int | |
703 | __pci_reenable_device(struct pci_dev *dev) | |
704 | { | |
705 | if (atomic_read(&dev->enable_cnt)) | |
706 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
707 | return 0; | |
708 | } | |
709 | ||
1da177e4 LT |
710 | /** |
711 | * pci_enable_device_bars - Initialize some of a device for use | |
712 | * @dev: PCI device to be initialized | |
713 | * @bars: bitmask of BAR's that must be configured | |
714 | * | |
715 | * Initialize device before it's used by a driver. Ask low-level code | |
9fb625c3 | 716 | * to enable selected I/O and memory resources. Wake up the device if it |
1da177e4 LT |
717 | * was suspended. Beware, this function can fail. |
718 | */ | |
1da177e4 LT |
719 | int |
720 | pci_enable_device_bars(struct pci_dev *dev, int bars) | |
721 | { | |
722 | int err; | |
723 | ||
9fb625c3 HS |
724 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
725 | return 0; /* already enabled */ | |
726 | ||
38cc1302 | 727 | err = do_pci_enable_device(dev, bars); |
95a62965 | 728 | if (err < 0) |
38cc1302 | 729 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 730 | return err; |
1da177e4 LT |
731 | } |
732 | ||
bae94d02 IPG |
733 | /** |
734 | * pci_enable_device - Initialize device before it's used by a driver. | |
735 | * @dev: PCI device to be initialized | |
736 | * | |
737 | * Initialize device before it's used by a driver. Ask low-level code | |
738 | * to enable I/O and memory. Wake up the device if it was suspended. | |
739 | * Beware, this function can fail. | |
740 | * | |
741 | * Note we don't actually enable the device many times if we call | |
742 | * this function repeatedly (we just increment the count). | |
743 | */ | |
744 | int pci_enable_device(struct pci_dev *dev) | |
745 | { | |
9fb625c3 | 746 | return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); |
bae94d02 IPG |
747 | } |
748 | ||
1da177e4 LT |
749 | /** |
750 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
751 | * @dev: the PCI device to disable | |
752 | * | |
753 | * Disables architecture specific PCI resources for the device. This | |
754 | * is the default implementation. Architecture implementations can | |
755 | * override this. | |
756 | */ | |
757 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
758 | ||
759 | /** | |
760 | * pci_disable_device - Disable PCI device after use | |
761 | * @dev: PCI device to be disabled | |
762 | * | |
763 | * Signal to the system that the PCI device is not in use by the system | |
764 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
765 | * |
766 | * Note we don't actually disable the device until all callers of | |
767 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
768 | */ |
769 | void | |
770 | pci_disable_device(struct pci_dev *dev) | |
771 | { | |
772 | u16 pci_command; | |
99dc804d | 773 | |
bae94d02 IPG |
774 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
775 | return; | |
776 | ||
99dc804d SL |
777 | if (dev->msi_enabled) |
778 | disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), | |
779 | PCI_CAP_ID_MSI); | |
780 | if (dev->msix_enabled) | |
781 | disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), | |
782 | PCI_CAP_ID_MSIX); | |
783 | ||
1da177e4 LT |
784 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
785 | if (pci_command & PCI_COMMAND_MASTER) { | |
786 | pci_command &= ~PCI_COMMAND_MASTER; | |
787 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
788 | } | |
ceb43744 | 789 | dev->is_busmaster = 0; |
1da177e4 LT |
790 | |
791 | pcibios_disable_device(dev); | |
792 | } | |
793 | ||
794 | /** | |
795 | * pci_enable_wake - enable device to generate PME# when suspended | |
796 | * @dev: - PCI device to operate on | |
797 | * @state: - Current state of device. | |
798 | * @enable: - Flag to enable or disable generation | |
799 | * | |
800 | * Set the bits in the device's PM Capabilities to generate PME# when | |
801 | * the system is suspended. | |
802 | * | |
803 | * -EIO is returned if device doesn't have PM Capabilities. | |
804 | * -EINVAL is returned if device supports it, but can't generate wake events. | |
805 | * 0 if operation is successful. | |
806 | * | |
807 | */ | |
808 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
809 | { | |
810 | int pm; | |
811 | u16 value; | |
812 | ||
813 | /* find PCI PM capability in list */ | |
814 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
815 | ||
816 | /* If device doesn't support PM Capabilities, but request is to disable | |
817 | * wake events, it's a nop; otherwise fail */ | |
818 | if (!pm) | |
819 | return enable ? -EIO : 0; | |
820 | ||
821 | /* Check device's ability to generate PME# */ | |
822 | pci_read_config_word(dev,pm+PCI_PM_PMC,&value); | |
823 | ||
824 | value &= PCI_PM_CAP_PME_MASK; | |
825 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
826 | ||
827 | /* Check if it can generate PME# from requested state. */ | |
828 | if (!value || !(value & (1 << state))) | |
829 | return enable ? -EINVAL : 0; | |
830 | ||
831 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); | |
832 | ||
833 | /* Clear PME_Status by writing 1 to it and enable PME# */ | |
834 | value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
835 | ||
836 | if (!enable) | |
837 | value &= ~PCI_PM_CTRL_PME_ENABLE; | |
838 | ||
839 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
844 | int | |
845 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
846 | { | |
847 | u8 pin; | |
848 | ||
514d207d | 849 | pin = dev->pin; |
1da177e4 LT |
850 | if (!pin) |
851 | return -1; | |
852 | pin--; | |
853 | while (dev->bus->self) { | |
854 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
855 | dev = dev->bus->self; | |
856 | } | |
857 | *bridge = dev; | |
858 | return pin; | |
859 | } | |
860 | ||
861 | /** | |
862 | * pci_release_region - Release a PCI bar | |
863 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
864 | * @bar: BAR to release | |
865 | * | |
866 | * Releases the PCI I/O and memory resources previously reserved by a | |
867 | * successful call to pci_request_region. Call this function only | |
868 | * after all use of the PCI regions has ceased. | |
869 | */ | |
870 | void pci_release_region(struct pci_dev *pdev, int bar) | |
871 | { | |
872 | if (pci_resource_len(pdev, bar) == 0) | |
873 | return; | |
874 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
875 | release_region(pci_resource_start(pdev, bar), | |
876 | pci_resource_len(pdev, bar)); | |
877 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
878 | release_mem_region(pci_resource_start(pdev, bar), | |
879 | pci_resource_len(pdev, bar)); | |
880 | } | |
881 | ||
882 | /** | |
883 | * pci_request_region - Reserved PCI I/O and memory resource | |
884 | * @pdev: PCI device whose resources are to be reserved | |
885 | * @bar: BAR to be reserved | |
886 | * @res_name: Name to be associated with resource. | |
887 | * | |
888 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
889 | * being reserved by owner @res_name. Do not access any | |
890 | * address inside the PCI regions unless this call returns | |
891 | * successfully. | |
892 | * | |
893 | * Returns 0 on success, or %EBUSY on error. A warning | |
894 | * message is also printed on failure. | |
895 | */ | |
3c990e92 | 896 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 LT |
897 | { |
898 | if (pci_resource_len(pdev, bar) == 0) | |
899 | return 0; | |
900 | ||
901 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
902 | if (!request_region(pci_resource_start(pdev, bar), | |
903 | pci_resource_len(pdev, bar), res_name)) | |
904 | goto err_out; | |
905 | } | |
906 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
907 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
908 | pci_resource_len(pdev, bar), res_name)) | |
909 | goto err_out; | |
910 | } | |
911 | ||
912 | return 0; | |
913 | ||
914 | err_out: | |
1396a8c3 GKH |
915 | printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx " |
916 | "for device %s\n", | |
1da177e4 LT |
917 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", |
918 | bar + 1, /* PCI BAR # */ | |
1396a8c3 GKH |
919 | (unsigned long long)pci_resource_len(pdev, bar), |
920 | (unsigned long long)pci_resource_start(pdev, bar), | |
1da177e4 LT |
921 | pci_name(pdev)); |
922 | return -EBUSY; | |
923 | } | |
924 | ||
c87deff7 HS |
925 | /** |
926 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
927 | * @pdev: PCI device whose resources were previously reserved | |
928 | * @bars: Bitmask of BARs to be released | |
929 | * | |
930 | * Release selected PCI I/O and memory resources previously reserved. | |
931 | * Call this function only after all use of the PCI regions has ceased. | |
932 | */ | |
933 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
934 | { | |
935 | int i; | |
936 | ||
937 | for (i = 0; i < 6; i++) | |
938 | if (bars & (1 << i)) | |
939 | pci_release_region(pdev, i); | |
940 | } | |
941 | ||
942 | /** | |
943 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
944 | * @pdev: PCI device whose resources are to be reserved | |
945 | * @bars: Bitmask of BARs to be requested | |
946 | * @res_name: Name to be associated with resource | |
947 | */ | |
948 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
949 | const char *res_name) | |
950 | { | |
951 | int i; | |
952 | ||
953 | for (i = 0; i < 6; i++) | |
954 | if (bars & (1 << i)) | |
955 | if(pci_request_region(pdev, i, res_name)) | |
956 | goto err_out; | |
957 | return 0; | |
958 | ||
959 | err_out: | |
960 | while(--i >= 0) | |
961 | if (bars & (1 << i)) | |
962 | pci_release_region(pdev, i); | |
963 | ||
964 | return -EBUSY; | |
965 | } | |
1da177e4 LT |
966 | |
967 | /** | |
968 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
969 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
970 | * | |
971 | * Releases all PCI I/O and memory resources previously reserved by a | |
972 | * successful call to pci_request_regions. Call this function only | |
973 | * after all use of the PCI regions has ceased. | |
974 | */ | |
975 | ||
976 | void pci_release_regions(struct pci_dev *pdev) | |
977 | { | |
c87deff7 | 978 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
979 | } |
980 | ||
981 | /** | |
982 | * pci_request_regions - Reserved PCI I/O and memory resources | |
983 | * @pdev: PCI device whose resources are to be reserved | |
984 | * @res_name: Name to be associated with resource. | |
985 | * | |
986 | * Mark all PCI regions associated with PCI device @pdev as | |
987 | * being reserved by owner @res_name. Do not access any | |
988 | * address inside the PCI regions unless this call returns | |
989 | * successfully. | |
990 | * | |
991 | * Returns 0 on success, or %EBUSY on error. A warning | |
992 | * message is also printed on failure. | |
993 | */ | |
3c990e92 | 994 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 995 | { |
c87deff7 | 996 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
997 | } |
998 | ||
999 | /** | |
1000 | * pci_set_master - enables bus-mastering for device dev | |
1001 | * @dev: the PCI device to enable | |
1002 | * | |
1003 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1004 | * to do the needed arch specific settings. | |
1005 | */ | |
1006 | void | |
1007 | pci_set_master(struct pci_dev *dev) | |
1008 | { | |
1009 | u16 cmd; | |
1010 | ||
1011 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1012 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
1013 | pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); | |
1014 | cmd |= PCI_COMMAND_MASTER; | |
1015 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1016 | } | |
1017 | dev->is_busmaster = 1; | |
1018 | pcibios_set_master(dev); | |
1019 | } | |
1020 | ||
edb2d97e MW |
1021 | #ifdef PCI_DISABLE_MWI |
1022 | int pci_set_mwi(struct pci_dev *dev) | |
1023 | { | |
1024 | return 0; | |
1025 | } | |
1026 | ||
1027 | void pci_clear_mwi(struct pci_dev *dev) | |
1028 | { | |
1029 | } | |
1030 | ||
1031 | #else | |
ebf5a248 MW |
1032 | |
1033 | #ifndef PCI_CACHE_LINE_BYTES | |
1034 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1035 | #endif | |
1036 | ||
1da177e4 | 1037 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1038 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1039 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1040 | |
1041 | /** | |
edb2d97e MW |
1042 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1043 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1044 | * |
edb2d97e MW |
1045 | * Helper function for pci_set_mwi. |
1046 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1047 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1048 | * | |
1049 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1050 | */ | |
1051 | static int | |
edb2d97e | 1052 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1053 | { |
1054 | u8 cacheline_size; | |
1055 | ||
1056 | if (!pci_cache_line_size) | |
1057 | return -EINVAL; /* The system doesn't support MWI. */ | |
1058 | ||
1059 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1060 | equal to or multiple of the right value. */ | |
1061 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1062 | if (cacheline_size >= pci_cache_line_size && | |
1063 | (cacheline_size % pci_cache_line_size) == 0) | |
1064 | return 0; | |
1065 | ||
1066 | /* Write the correct value. */ | |
1067 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1068 | /* Read it back. */ | |
1069 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1070 | if (cacheline_size == pci_cache_line_size) | |
1071 | return 0; | |
1072 | ||
1073 | printk(KERN_DEBUG "PCI: cache line size of %d is not supported " | |
1074 | "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); | |
1075 | ||
1076 | return -EINVAL; | |
1077 | } | |
1da177e4 LT |
1078 | |
1079 | /** | |
1080 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1081 | * @dev: the PCI device for which MWI is enabled | |
1082 | * | |
1083 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, | |
1084 | * and then calls @pcibios_set_mwi to do the needed arch specific | |
1085 | * operations or a generic mwi-prep function. | |
1086 | * | |
1087 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1088 | */ | |
1089 | int | |
1090 | pci_set_mwi(struct pci_dev *dev) | |
1091 | { | |
1092 | int rc; | |
1093 | u16 cmd; | |
1094 | ||
edb2d97e | 1095 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1096 | if (rc) |
1097 | return rc; | |
1098 | ||
1099 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1100 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
1101 | pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); | |
1102 | cmd |= PCI_COMMAND_INVALIDATE; | |
1103 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1104 | } | |
1105 | ||
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | /** | |
1110 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1111 | * @dev: the PCI device to disable | |
1112 | * | |
1113 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1114 | */ | |
1115 | void | |
1116 | pci_clear_mwi(struct pci_dev *dev) | |
1117 | { | |
1118 | u16 cmd; | |
1119 | ||
1120 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1121 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1122 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1123 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1124 | } | |
1125 | } | |
edb2d97e | 1126 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1127 | |
a04ce0ff BR |
1128 | /** |
1129 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1130 | * @pdev: the PCI device to operate on |
1131 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1132 | * |
1133 | * Enables/disables PCI INTx for device dev | |
1134 | */ | |
1135 | void | |
1136 | pci_intx(struct pci_dev *pdev, int enable) | |
1137 | { | |
1138 | u16 pci_command, new; | |
1139 | ||
1140 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1141 | ||
1142 | if (enable) { | |
1143 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1144 | } else { | |
1145 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1146 | } | |
1147 | ||
1148 | if (new != pci_command) { | |
2fd9d74b | 1149 | pci_write_config_word(pdev, PCI_COMMAND, new); |
a04ce0ff BR |
1150 | } |
1151 | } | |
1152 | ||
1da177e4 LT |
1153 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1154 | /* | |
1155 | * These can be overridden by arch-specific implementations | |
1156 | */ | |
1157 | int | |
1158 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1159 | { | |
1160 | if (!pci_dma_supported(dev, mask)) | |
1161 | return -EIO; | |
1162 | ||
1163 | dev->dma_mask = mask; | |
1164 | ||
1165 | return 0; | |
1166 | } | |
1167 | ||
1da177e4 LT |
1168 | int |
1169 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1170 | { | |
1171 | if (!pci_dma_supported(dev, mask)) | |
1172 | return -EIO; | |
1173 | ||
1174 | dev->dev.coherent_dma_mask = mask; | |
1175 | ||
1176 | return 0; | |
1177 | } | |
1178 | #endif | |
c87deff7 HS |
1179 | |
1180 | /** | |
1181 | * pci_select_bars - Make BAR mask from the type of resource | |
1182 | * @pdev: the PCI device for which BAR mask is made | |
1183 | * @flags: resource type mask to be selected | |
1184 | * | |
1185 | * This helper routine makes bar mask from the type of resource. | |
1186 | */ | |
1187 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
1188 | { | |
1189 | int i, bars = 0; | |
1190 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
1191 | if (pci_resource_flags(dev, i) & flags) | |
1192 | bars |= (1 << i); | |
1193 | return bars; | |
1194 | } | |
1195 | ||
1da177e4 LT |
1196 | static int __devinit pci_init(void) |
1197 | { | |
1198 | struct pci_dev *dev = NULL; | |
1199 | ||
1200 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1201 | pci_fixup_device(pci_fixup_final, dev); | |
1202 | } | |
1203 | return 0; | |
1204 | } | |
1205 | ||
1206 | static int __devinit pci_setup(char *str) | |
1207 | { | |
1208 | while (str) { | |
1209 | char *k = strchr(str, ','); | |
1210 | if (k) | |
1211 | *k++ = 0; | |
1212 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
1213 | if (!strcmp(str, "nomsi")) { |
1214 | pci_no_msi(); | |
1215 | } else { | |
1216 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
1217 | str); | |
1218 | } | |
1da177e4 LT |
1219 | } |
1220 | str = k; | |
1221 | } | |
0637a70a | 1222 | return 0; |
1da177e4 | 1223 | } |
0637a70a | 1224 | early_param("pci", pci_setup); |
1da177e4 LT |
1225 | |
1226 | device_initcall(pci_init); | |
1da177e4 | 1227 | |
064b53db | 1228 | EXPORT_SYMBOL_GPL(pci_restore_bars); |
1da177e4 LT |
1229 | EXPORT_SYMBOL(pci_enable_device_bars); |
1230 | EXPORT_SYMBOL(pci_enable_device); | |
1231 | EXPORT_SYMBOL(pci_disable_device); | |
1da177e4 LT |
1232 | EXPORT_SYMBOL(pci_find_capability); |
1233 | EXPORT_SYMBOL(pci_bus_find_capability); | |
1234 | EXPORT_SYMBOL(pci_release_regions); | |
1235 | EXPORT_SYMBOL(pci_request_regions); | |
1236 | EXPORT_SYMBOL(pci_release_region); | |
1237 | EXPORT_SYMBOL(pci_request_region); | |
c87deff7 HS |
1238 | EXPORT_SYMBOL(pci_release_selected_regions); |
1239 | EXPORT_SYMBOL(pci_request_selected_regions); | |
1da177e4 LT |
1240 | EXPORT_SYMBOL(pci_set_master); |
1241 | EXPORT_SYMBOL(pci_set_mwi); | |
1242 | EXPORT_SYMBOL(pci_clear_mwi); | |
a04ce0ff | 1243 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 1244 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
1245 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
1246 | EXPORT_SYMBOL(pci_assign_resource); | |
1247 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 1248 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
1249 | |
1250 | EXPORT_SYMBOL(pci_set_power_state); | |
1251 | EXPORT_SYMBOL(pci_save_state); | |
1252 | EXPORT_SYMBOL(pci_restore_state); | |
1253 | EXPORT_SYMBOL(pci_enable_wake); | |
1254 |