Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
1da177e4 | 4 | * |
df62ab5e BH |
5 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
6 | * David Mosberger-Tang | |
1da177e4 | 7 | * |
df62ab5e | 8 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> |
1da177e4 LT |
9 | */ |
10 | ||
2ab51dde | 11 | #include <linux/acpi.h> |
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/delay.h> | |
9d26d3a8 | 14 | #include <linux/dmi.h> |
1da177e4 | 15 | #include <linux/init.h> |
bbd8810d | 16 | #include <linux/msi.h> |
7c674700 LP |
17 | #include <linux/of.h> |
18 | #include <linux/of_pci.h> | |
1da177e4 | 19 | #include <linux/pci.h> |
075c1771 | 20 | #include <linux/pm.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/spinlock.h> | |
4e57b681 | 24 | #include <linux/string.h> |
229f5afd | 25 | #include <linux/log2.h> |
5745392e | 26 | #include <linux/logic_pio.h> |
c300bd2f | 27 | #include <linux/pm_wakeup.h> |
8dd7f803 | 28 | #include <linux/interrupt.h> |
32a9a682 | 29 | #include <linux/device.h> |
b67ea761 | 30 | #include <linux/pm_runtime.h> |
608c3881 | 31 | #include <linux/pci_hotplug.h> |
4d3f1384 | 32 | #include <linux/vmalloc.h> |
4ebeb1ec | 33 | #include <linux/pci-ats.h> |
32a9a682 | 34 | #include <asm/setup.h> |
2a2aca31 | 35 | #include <asm/dma.h> |
b07461a8 | 36 | #include <linux/aer.h> |
bc56b9e0 | 37 | #include "pci.h" |
1da177e4 | 38 | |
c4eed62a KB |
39 | DEFINE_MUTEX(pci_slot_mutex); |
40 | ||
00240c38 AS |
41 | const char *pci_power_names[] = { |
42 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
43 | }; | |
44 | EXPORT_SYMBOL_GPL(pci_power_names); | |
45 | ||
93177a74 RW |
46 | int isa_dma_bridge_buggy; |
47 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
48 | ||
49 | int pci_pci_problems; | |
50 | EXPORT_SYMBOL(pci_pci_problems); | |
51 | ||
1ae861e6 RW |
52 | unsigned int pci_pm_d3_delay; |
53 | ||
df17e62e MG |
54 | static void pci_pme_list_scan(struct work_struct *work); |
55 | ||
56 | static LIST_HEAD(pci_pme_list); | |
57 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
58 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
59 | ||
60 | struct pci_pme_device { | |
61 | struct list_head list; | |
62 | struct pci_dev *dev; | |
63 | }; | |
64 | ||
65 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
66 | ||
1ae861e6 RW |
67 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
68 | { | |
69 | unsigned int delay = dev->d3_delay; | |
70 | ||
71 | if (delay < pci_pm_d3_delay) | |
72 | delay = pci_pm_d3_delay; | |
73 | ||
50b2b540 AH |
74 | if (delay) |
75 | msleep(delay); | |
1ae861e6 | 76 | } |
1da177e4 | 77 | |
32a2eea7 JG |
78 | #ifdef CONFIG_PCI_DOMAINS |
79 | int pci_domains_supported = 1; | |
80 | #endif | |
81 | ||
4516a618 AN |
82 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
83 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
84 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
85 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
86 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
87 | ||
28760489 | 88 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
d7b8a217 NJ |
89 | #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024) |
90 | #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024) | |
91 | /* hpiosize=nn can override this */ | |
28760489 | 92 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; |
d7b8a217 NJ |
93 | /* |
94 | * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size, | |
95 | * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size; | |
96 | * pci=hpmemsize=nnM overrides both | |
97 | */ | |
98 | unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE; | |
99 | unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE; | |
28760489 | 100 | |
e16b4660 KB |
101 | #define DEFAULT_HOTPLUG_BUS_SIZE 1 |
102 | unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
103 | ||
27d868b5 | 104 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; |
b03e7495 | 105 | |
ac1aa47b JB |
106 | /* |
107 | * The default CLS is used if arch didn't set CLS explicitly and not | |
108 | * all pci devices agree on the same value. Arch can override either | |
109 | * the dfl or actual value as it sees fit. Don't forget this is | |
110 | * measured in 32-bit words, not bytes. | |
111 | */ | |
15856ad5 | 112 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
113 | u8 pci_cache_line_size; |
114 | ||
96c55900 MS |
115 | /* |
116 | * If we set up a device for bus mastering, we need to check the latency | |
117 | * timer as certain BIOSes forget to set it properly. | |
118 | */ | |
119 | unsigned int pcibios_max_latency = 255; | |
120 | ||
6748dcc2 RW |
121 | /* If set, the PCIe ARI capability will not be used. */ |
122 | static bool pcie_ari_disabled; | |
123 | ||
cef74409 GK |
124 | /* If set, the PCIe ATS capability will not be used. */ |
125 | static bool pcie_ats_disabled; | |
126 | ||
11eb0e0e SK |
127 | /* If set, the PCI config space of each device is printed during boot. */ |
128 | bool pci_early_dump; | |
129 | ||
cef74409 GK |
130 | bool pci_ats_disabled(void) |
131 | { | |
132 | return pcie_ats_disabled; | |
133 | } | |
1a373a78 | 134 | EXPORT_SYMBOL_GPL(pci_ats_disabled); |
cef74409 | 135 | |
9d26d3a8 MW |
136 | /* Disable bridge_d3 for all PCIe ports */ |
137 | static bool pci_bridge_d3_disable; | |
138 | /* Force bridge_d3 for all PCIe ports */ | |
139 | static bool pci_bridge_d3_force; | |
140 | ||
141 | static int __init pcie_port_pm_setup(char *str) | |
142 | { | |
143 | if (!strcmp(str, "off")) | |
144 | pci_bridge_d3_disable = true; | |
145 | else if (!strcmp(str, "force")) | |
146 | pci_bridge_d3_force = true; | |
147 | return 1; | |
148 | } | |
149 | __setup("pcie_port_pm=", pcie_port_pm_setup); | |
150 | ||
a2758b6b SK |
151 | /* Time to wait after a reset for device to become responsive */ |
152 | #define PCIE_RESET_READY_POLL_MS 60000 | |
153 | ||
1da177e4 LT |
154 | /** |
155 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
156 | * @bus: pointer to PCI bus structure to search | |
157 | * | |
158 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
159 | * including the given PCI bus and its list of child PCI buses. | |
160 | */ | |
07656d83 | 161 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 162 | { |
94e6a9b9 | 163 | struct pci_bus *tmp; |
1da177e4 LT |
164 | unsigned char max, n; |
165 | ||
b918c62e | 166 | max = bus->busn_res.end; |
94e6a9b9 YW |
167 | list_for_each_entry(tmp, &bus->children, node) { |
168 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 169 | if (n > max) |
1da177e4 LT |
170 | max = n; |
171 | } | |
172 | return max; | |
173 | } | |
b82db5ce | 174 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 175 | |
ec5d9e87 HK |
176 | /** |
177 | * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS | |
178 | * @pdev: the PCI device | |
179 | * | |
180 | * Returns error bits set in PCI_STATUS and clears them. | |
181 | */ | |
182 | int pci_status_get_and_clear_errors(struct pci_dev *pdev) | |
183 | { | |
184 | u16 status; | |
185 | int ret; | |
186 | ||
187 | ret = pci_read_config_word(pdev, PCI_STATUS, &status); | |
188 | if (ret != PCIBIOS_SUCCESSFUL) | |
189 | return -EIO; | |
190 | ||
191 | status &= PCI_STATUS_ERROR_BITS; | |
192 | if (status) | |
193 | pci_write_config_word(pdev, PCI_STATUS, status); | |
194 | ||
195 | return status; | |
196 | } | |
197 | EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors); | |
198 | ||
1684f5dd AM |
199 | #ifdef CONFIG_HAS_IOMEM |
200 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
201 | { | |
1f7bf3bf BH |
202 | struct resource *res = &pdev->resource[bar]; |
203 | ||
1684f5dd AM |
204 | /* |
205 | * Make sure the BAR is actually a memory resource, not an IO resource | |
206 | */ | |
646c0282 | 207 | if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { |
7506dc79 | 208 | pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res); |
1684f5dd AM |
209 | return NULL; |
210 | } | |
4bdc0d67 | 211 | return ioremap(res->start, resource_size(res)); |
1684f5dd AM |
212 | } |
213 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
c43996f4 LR |
214 | |
215 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) | |
216 | { | |
217 | /* | |
218 | * Make sure the BAR is actually a memory resource, not an IO resource | |
219 | */ | |
220 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
221 | WARN_ON(1); | |
222 | return NULL; | |
223 | } | |
224 | return ioremap_wc(pci_resource_start(pdev, bar), | |
225 | pci_resource_len(pdev, bar)); | |
226 | } | |
227 | EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); | |
1684f5dd AM |
228 | #endif |
229 | ||
45db3370 LG |
230 | /** |
231 | * pci_dev_str_match_path - test if a path string matches a device | |
74356add BH |
232 | * @dev: the PCI device to test |
233 | * @path: string to match the device against | |
45db3370 LG |
234 | * @endptr: pointer to the string after the match |
235 | * | |
236 | * Test if a string (typically from a kernel parameter) formatted as a | |
237 | * path of device/function addresses matches a PCI device. The string must | |
238 | * be of the form: | |
239 | * | |
240 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* | |
241 | * | |
242 | * A path for a device can be obtained using 'lspci -t'. Using a path | |
243 | * is more robust against bus renumbering than using only a single bus, | |
244 | * device and function address. | |
245 | * | |
246 | * Returns 1 if the string matches the device, 0 if it does not and | |
247 | * a negative error code if it fails to parse the string. | |
248 | */ | |
249 | static int pci_dev_str_match_path(struct pci_dev *dev, const char *path, | |
250 | const char **endptr) | |
251 | { | |
252 | int ret; | |
253 | int seg, bus, slot, func; | |
254 | char *wpath, *p; | |
255 | char end; | |
256 | ||
257 | *endptr = strchrnul(path, ';'); | |
258 | ||
259 | wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL); | |
260 | if (!wpath) | |
261 | return -ENOMEM; | |
262 | ||
263 | while (1) { | |
264 | p = strrchr(wpath, '/'); | |
265 | if (!p) | |
266 | break; | |
267 | ret = sscanf(p, "/%x.%x%c", &slot, &func, &end); | |
268 | if (ret != 2) { | |
269 | ret = -EINVAL; | |
270 | goto free_and_exit; | |
271 | } | |
272 | ||
273 | if (dev->devfn != PCI_DEVFN(slot, func)) { | |
274 | ret = 0; | |
275 | goto free_and_exit; | |
276 | } | |
277 | ||
278 | /* | |
279 | * Note: we don't need to get a reference to the upstream | |
280 | * bridge because we hold a reference to the top level | |
281 | * device which should hold a reference to the bridge, | |
282 | * and so on. | |
283 | */ | |
284 | dev = pci_upstream_bridge(dev); | |
285 | if (!dev) { | |
286 | ret = 0; | |
287 | goto free_and_exit; | |
288 | } | |
289 | ||
290 | *p = 0; | |
291 | } | |
292 | ||
293 | ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot, | |
294 | &func, &end); | |
295 | if (ret != 4) { | |
296 | seg = 0; | |
297 | ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end); | |
298 | if (ret != 3) { | |
299 | ret = -EINVAL; | |
300 | goto free_and_exit; | |
301 | } | |
302 | } | |
303 | ||
304 | ret = (seg == pci_domain_nr(dev->bus) && | |
305 | bus == dev->bus->number && | |
306 | dev->devfn == PCI_DEVFN(slot, func)); | |
307 | ||
308 | free_and_exit: | |
309 | kfree(wpath); | |
310 | return ret; | |
311 | } | |
312 | ||
07d8d7e5 LG |
313 | /** |
314 | * pci_dev_str_match - test if a string matches a device | |
74356add BH |
315 | * @dev: the PCI device to test |
316 | * @p: string to match the device against | |
07d8d7e5 LG |
317 | * @endptr: pointer to the string after the match |
318 | * | |
319 | * Test if a string (typically from a kernel parameter) matches a specified | |
320 | * PCI device. The string may be of one of the following formats: | |
321 | * | |
45db3370 | 322 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* |
07d8d7e5 LG |
323 | * pci:<vendor>:<device>[:<subvendor>:<subdevice>] |
324 | * | |
325 | * The first format specifies a PCI bus/device/function address which | |
326 | * may change if new hardware is inserted, if motherboard firmware changes, | |
327 | * or due to changes caused in kernel parameters. If the domain is | |
45db3370 LG |
328 | * left unspecified, it is taken to be 0. In order to be robust against |
329 | * bus renumbering issues, a path of PCI device/function numbers may be used | |
330 | * to address the specific device. The path for a device can be determined | |
331 | * through the use of 'lspci -t'. | |
07d8d7e5 LG |
332 | * |
333 | * The second format matches devices using IDs in the configuration | |
334 | * space which may match multiple devices in the system. A value of 0 | |
335 | * for any field will match all devices. (Note: this differs from | |
336 | * in-kernel code that uses PCI_ANY_ID which is ~0; this is for | |
337 | * legacy reasons and convenience so users don't have to specify | |
338 | * FFFFFFFFs on the command line.) | |
339 | * | |
340 | * Returns 1 if the string matches the device, 0 if it does not and | |
341 | * a negative error code if the string cannot be parsed. | |
342 | */ | |
343 | static int pci_dev_str_match(struct pci_dev *dev, const char *p, | |
344 | const char **endptr) | |
345 | { | |
346 | int ret; | |
45db3370 | 347 | int count; |
07d8d7e5 LG |
348 | unsigned short vendor, device, subsystem_vendor, subsystem_device; |
349 | ||
350 | if (strncmp(p, "pci:", 4) == 0) { | |
351 | /* PCI vendor/device (subvendor/subdevice) IDs are specified */ | |
352 | p += 4; | |
353 | ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device, | |
354 | &subsystem_vendor, &subsystem_device, &count); | |
355 | if (ret != 4) { | |
356 | ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count); | |
357 | if (ret != 2) | |
358 | return -EINVAL; | |
359 | ||
360 | subsystem_vendor = 0; | |
361 | subsystem_device = 0; | |
362 | } | |
363 | ||
364 | p += count; | |
365 | ||
366 | if ((!vendor || vendor == dev->vendor) && | |
367 | (!device || device == dev->device) && | |
368 | (!subsystem_vendor || | |
369 | subsystem_vendor == dev->subsystem_vendor) && | |
370 | (!subsystem_device || | |
371 | subsystem_device == dev->subsystem_device)) | |
372 | goto found; | |
07d8d7e5 | 373 | } else { |
45db3370 LG |
374 | /* |
375 | * PCI Bus, Device, Function IDs are specified | |
74356add | 376 | * (optionally, may include a path of devfns following it) |
45db3370 LG |
377 | */ |
378 | ret = pci_dev_str_match_path(dev, p, &p); | |
379 | if (ret < 0) | |
380 | return ret; | |
381 | else if (ret) | |
07d8d7e5 LG |
382 | goto found; |
383 | } | |
384 | ||
385 | *endptr = p; | |
386 | return 0; | |
387 | ||
388 | found: | |
389 | *endptr = p; | |
390 | return 1; | |
391 | } | |
687d5fe3 ME |
392 | |
393 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
394 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
395 | { |
396 | u8 id; | |
55db3208 SS |
397 | u16 ent; |
398 | ||
399 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
24a4e377 | 400 | |
687d5fe3 | 401 | while ((*ttl)--) { |
24a4e377 RD |
402 | if (pos < 0x40) |
403 | break; | |
404 | pos &= ~3; | |
55db3208 SS |
405 | pci_bus_read_config_word(bus, devfn, pos, &ent); |
406 | ||
407 | id = ent & 0xff; | |
24a4e377 RD |
408 | if (id == 0xff) |
409 | break; | |
410 | if (id == cap) | |
411 | return pos; | |
55db3208 | 412 | pos = (ent >> 8); |
24a4e377 RD |
413 | } |
414 | return 0; | |
415 | } | |
416 | ||
687d5fe3 ME |
417 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
418 | u8 pos, int cap) | |
419 | { | |
420 | int ttl = PCI_FIND_CAP_TTL; | |
421 | ||
422 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
423 | } | |
424 | ||
24a4e377 RD |
425 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
426 | { | |
427 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
428 | pos + PCI_CAP_LIST_NEXT, cap); | |
429 | } | |
430 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
431 | ||
d3bac118 ME |
432 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
433 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
434 | { |
435 | u16 status; | |
1da177e4 LT |
436 | |
437 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
438 | if (!(status & PCI_STATUS_CAP_LIST)) | |
439 | return 0; | |
440 | ||
441 | switch (hdr_type) { | |
442 | case PCI_HEADER_TYPE_NORMAL: | |
443 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 444 | return PCI_CAPABILITY_LIST; |
1da177e4 | 445 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 446 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 | 447 | } |
d3bac118 ME |
448 | |
449 | return 0; | |
1da177e4 LT |
450 | } |
451 | ||
452 | /** | |
f7625980 | 453 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
454 | * @dev: PCI device to query |
455 | * @cap: capability code | |
456 | * | |
457 | * Tell if a device supports a given PCI capability. | |
458 | * Returns the address of the requested capability structure within the | |
459 | * device's PCI configuration space or 0 in case the device does not | |
74356add | 460 | * support it. Possible values for @cap include: |
1da177e4 | 461 | * |
f7625980 BH |
462 | * %PCI_CAP_ID_PM Power Management |
463 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
464 | * %PCI_CAP_ID_VPD Vital Product Data | |
465 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 466 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 467 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
468 | * %PCI_CAP_ID_PCIX PCI-X |
469 | * %PCI_CAP_ID_EXP PCI Express | |
470 | */ | |
471 | int pci_find_capability(struct pci_dev *dev, int cap) | |
472 | { | |
d3bac118 ME |
473 | int pos; |
474 | ||
475 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
476 | if (pos) | |
477 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
478 | ||
479 | return pos; | |
1da177e4 | 480 | } |
b7fe9434 | 481 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
482 | |
483 | /** | |
f7625980 | 484 | * pci_bus_find_capability - query for devices' capabilities |
74356add | 485 | * @bus: the PCI bus to query |
1da177e4 | 486 | * @devfn: PCI device to query |
74356add | 487 | * @cap: capability code |
1da177e4 | 488 | * |
74356add | 489 | * Like pci_find_capability() but works for PCI devices that do not have a |
f7625980 | 490 | * pci_dev structure set up yet. |
1da177e4 LT |
491 | * |
492 | * Returns the address of the requested capability structure within the | |
493 | * device's PCI configuration space or 0 in case the device does not | |
494 | * support it. | |
495 | */ | |
496 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
497 | { | |
d3bac118 | 498 | int pos; |
1da177e4 LT |
499 | u8 hdr_type; |
500 | ||
501 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
502 | ||
d3bac118 ME |
503 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
504 | if (pos) | |
505 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
506 | ||
507 | return pos; | |
1da177e4 | 508 | } |
b7fe9434 | 509 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
510 | |
511 | /** | |
44a9a36f | 512 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 513 | * @dev: PCI device to query |
44a9a36f | 514 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
515 | * @cap: capability code |
516 | * | |
44a9a36f | 517 | * Returns the address of the next matching extended capability structure |
1da177e4 | 518 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
519 | * not support it. Some capabilities can occur several times, e.g., the |
520 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 521 | */ |
44a9a36f | 522 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
523 | { |
524 | u32 header; | |
557848c3 ZY |
525 | int ttl; |
526 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 527 | |
557848c3 ZY |
528 | /* minimum 8 bytes per capability */ |
529 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
530 | ||
531 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
532 | return 0; |
533 | ||
44a9a36f BH |
534 | if (start) |
535 | pos = start; | |
536 | ||
1da177e4 LT |
537 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
538 | return 0; | |
539 | ||
540 | /* | |
541 | * If we have no capabilities, this is indicated by cap ID, | |
542 | * cap version and next pointer all being 0. | |
543 | */ | |
544 | if (header == 0) | |
545 | return 0; | |
546 | ||
547 | while (ttl-- > 0) { | |
44a9a36f | 548 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
549 | return pos; |
550 | ||
551 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 552 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
553 | break; |
554 | ||
555 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
556 | break; | |
557 | } | |
558 | ||
559 | return 0; | |
560 | } | |
44a9a36f BH |
561 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
562 | ||
563 | /** | |
564 | * pci_find_ext_capability - Find an extended capability | |
565 | * @dev: PCI device to query | |
566 | * @cap: capability code | |
567 | * | |
568 | * Returns the address of the requested extended capability structure | |
569 | * within the device's PCI configuration space or 0 if the device does | |
74356add | 570 | * not support it. Possible values for @cap include: |
44a9a36f BH |
571 | * |
572 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
573 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
574 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
575 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
576 | */ | |
577 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
578 | { | |
579 | return pci_find_next_ext_capability(dev, 0, cap); | |
580 | } | |
3a720d72 | 581 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 582 | |
70c0923b JK |
583 | /** |
584 | * pci_get_dsn - Read and return the 8-byte Device Serial Number | |
585 | * @dev: PCI device to query | |
586 | * | |
587 | * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial | |
588 | * Number. | |
589 | * | |
590 | * Returns the DSN, or zero if the capability does not exist. | |
591 | */ | |
592 | u64 pci_get_dsn(struct pci_dev *dev) | |
593 | { | |
594 | u32 dword; | |
595 | u64 dsn; | |
596 | int pos; | |
597 | ||
598 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN); | |
599 | if (!pos) | |
600 | return 0; | |
601 | ||
602 | /* | |
603 | * The Device Serial Number is two dwords offset 4 bytes from the | |
604 | * capability position. The specification says that the first dword is | |
605 | * the lower half, and the second dword is the upper half. | |
606 | */ | |
607 | pos += 4; | |
608 | pci_read_config_dword(dev, pos, &dword); | |
609 | dsn = (u64)dword; | |
610 | pci_read_config_dword(dev, pos + 4, &dword); | |
611 | dsn |= ((u64)dword) << 32; | |
612 | ||
613 | return dsn; | |
614 | } | |
615 | EXPORT_SYMBOL_GPL(pci_get_dsn); | |
616 | ||
687d5fe3 ME |
617 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
618 | { | |
619 | int rc, ttl = PCI_FIND_CAP_TTL; | |
620 | u8 cap, mask; | |
621 | ||
622 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
623 | mask = HT_3BIT_CAP_MASK; | |
624 | else | |
625 | mask = HT_5BIT_CAP_MASK; | |
626 | ||
627 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
628 | PCI_CAP_ID_HT, &ttl); | |
629 | while (pos) { | |
630 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
631 | if (rc != PCIBIOS_SUCCESSFUL) | |
632 | return 0; | |
633 | ||
634 | if ((cap & mask) == ht_cap) | |
635 | return pos; | |
636 | ||
47a4d5be BG |
637 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
638 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
639 | PCI_CAP_ID_HT, &ttl); |
640 | } | |
641 | ||
642 | return 0; | |
643 | } | |
644 | /** | |
645 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
646 | * @dev: PCI device to query | |
647 | * @pos: Position from which to continue searching | |
648 | * @ht_cap: Hypertransport capability code | |
649 | * | |
650 | * To be used in conjunction with pci_find_ht_capability() to search for | |
651 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
652 | * from pci_find_ht_capability(). | |
653 | * | |
654 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
655 | * steps to avoid an infinite loop. | |
656 | */ | |
657 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
658 | { | |
659 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
660 | } | |
661 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
662 | ||
663 | /** | |
664 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
665 | * @dev: PCI device to query | |
666 | * @ht_cap: Hypertransport capability code | |
667 | * | |
668 | * Tell if a device supports a given Hypertransport capability. | |
669 | * Returns an address within the device's PCI configuration space | |
670 | * or 0 in case the device does not support the request capability. | |
671 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
672 | * which has a Hypertransport capability matching @ht_cap. | |
673 | */ | |
674 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
675 | { | |
676 | int pos; | |
677 | ||
678 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
679 | if (pos) | |
680 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
681 | ||
682 | return pos; | |
683 | } | |
684 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
685 | ||
1da177e4 | 686 | /** |
74356add BH |
687 | * pci_find_parent_resource - return resource region of parent bus of given |
688 | * region | |
1da177e4 LT |
689 | * @dev: PCI device structure contains resources to be searched |
690 | * @res: child resource record for which parent is sought | |
691 | * | |
74356add BH |
692 | * For given resource region of given device, return the resource region of |
693 | * parent bus the given region is contained in. | |
1da177e4 | 694 | */ |
3c78bc61 RD |
695 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
696 | struct resource *res) | |
1da177e4 LT |
697 | { |
698 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 699 | struct resource *r; |
1da177e4 | 700 | int i; |
1da177e4 | 701 | |
89a74ecc | 702 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
703 | if (!r) |
704 | continue; | |
31342330 | 705 | if (resource_contains(r, res)) { |
f44116ae BH |
706 | |
707 | /* | |
708 | * If the window is prefetchable but the BAR is | |
709 | * not, the allocator made a mistake. | |
710 | */ | |
711 | if (r->flags & IORESOURCE_PREFETCH && | |
712 | !(res->flags & IORESOURCE_PREFETCH)) | |
713 | return NULL; | |
714 | ||
715 | /* | |
716 | * If we're below a transparent bridge, there may | |
717 | * be both a positively-decoded aperture and a | |
718 | * subtractively-decoded region that contain the BAR. | |
719 | * We want the positively-decoded one, so this depends | |
720 | * on pci_bus_for_each_resource() giving us those | |
721 | * first. | |
722 | */ | |
723 | return r; | |
724 | } | |
1da177e4 | 725 | } |
f44116ae | 726 | return NULL; |
1da177e4 | 727 | } |
b7fe9434 | 728 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 729 | |
afd29f90 MW |
730 | /** |
731 | * pci_find_resource - Return matching PCI device resource | |
732 | * @dev: PCI device to query | |
733 | * @res: Resource to look for | |
734 | * | |
735 | * Goes over standard PCI resources (BARs) and checks if the given resource | |
736 | * is partially or fully contained in any of them. In that case the | |
737 | * matching resource is returned, %NULL otherwise. | |
738 | */ | |
739 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res) | |
740 | { | |
741 | int i; | |
742 | ||
c9c13ba4 | 743 | for (i = 0; i < PCI_STD_NUM_BARS; i++) { |
afd29f90 MW |
744 | struct resource *r = &dev->resource[i]; |
745 | ||
746 | if (r->start && resource_contains(r, res)) | |
747 | return r; | |
748 | } | |
749 | ||
750 | return NULL; | |
751 | } | |
752 | EXPORT_SYMBOL(pci_find_resource); | |
753 | ||
157e876f AW |
754 | /** |
755 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
756 | * @dev: the PCI device to operate on | |
757 | * @pos: config space offset of status word | |
758 | * @mask: mask of bit(s) to care about in status word | |
759 | * | |
760 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
761 | */ | |
762 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
763 | { | |
764 | int i; | |
765 | ||
766 | /* Wait for Transaction Pending bit clean */ | |
767 | for (i = 0; i < 4; i++) { | |
768 | u16 status; | |
769 | if (i) | |
770 | msleep((1 << (i - 1)) * 100); | |
771 | ||
772 | pci_read_config_word(dev, pos, &status); | |
773 | if (!(status & mask)) | |
774 | return 1; | |
775 | } | |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
cbe42036 RJ |
780 | static int pci_acs_enable; |
781 | ||
782 | /** | |
783 | * pci_request_acs - ask for ACS to be enabled if supported | |
784 | */ | |
785 | void pci_request_acs(void) | |
786 | { | |
787 | pci_acs_enable = 1; | |
788 | } | |
789 | ||
790 | static const char *disable_acs_redir_param; | |
791 | ||
792 | /** | |
793 | * pci_disable_acs_redir - disable ACS redirect capabilities | |
794 | * @dev: the PCI device | |
795 | * | |
796 | * For only devices specified in the disable_acs_redir parameter. | |
797 | */ | |
798 | static void pci_disable_acs_redir(struct pci_dev *dev) | |
799 | { | |
800 | int ret = 0; | |
801 | const char *p; | |
802 | int pos; | |
803 | u16 ctrl; | |
804 | ||
805 | if (!disable_acs_redir_param) | |
806 | return; | |
807 | ||
808 | p = disable_acs_redir_param; | |
809 | while (*p) { | |
810 | ret = pci_dev_str_match(dev, p, &p); | |
811 | if (ret < 0) { | |
812 | pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n", | |
813 | disable_acs_redir_param); | |
814 | ||
815 | break; | |
816 | } else if (ret == 1) { | |
817 | /* Found a match */ | |
818 | break; | |
819 | } | |
820 | ||
821 | if (*p != ';' && *p != ',') { | |
822 | /* End of param or invalid format */ | |
823 | break; | |
824 | } | |
825 | p++; | |
826 | } | |
827 | ||
828 | if (ret != 1) | |
829 | return; | |
830 | ||
831 | if (!pci_dev_specific_disable_acs_redir(dev)) | |
832 | return; | |
833 | ||
52fbf5bd | 834 | pos = dev->acs_cap; |
cbe42036 RJ |
835 | if (!pos) { |
836 | pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n"); | |
837 | return; | |
838 | } | |
839 | ||
840 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
841 | ||
842 | /* P2P Request & Completion Redirect */ | |
843 | ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); | |
844 | ||
845 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
846 | ||
847 | pci_info(dev, "disabled ACS redirect\n"); | |
848 | } | |
849 | ||
850 | /** | |
851 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities | |
852 | * @dev: the PCI device | |
853 | */ | |
854 | static void pci_std_enable_acs(struct pci_dev *dev) | |
855 | { | |
856 | int pos; | |
857 | u16 cap; | |
858 | u16 ctrl; | |
859 | ||
52fbf5bd | 860 | pos = dev->acs_cap; |
cbe42036 RJ |
861 | if (!pos) |
862 | return; | |
863 | ||
864 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
865 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
866 | ||
867 | /* Source Validation */ | |
868 | ctrl |= (cap & PCI_ACS_SV); | |
869 | ||
870 | /* P2P Request Redirect */ | |
871 | ctrl |= (cap & PCI_ACS_RR); | |
872 | ||
873 | /* P2P Completion Redirect */ | |
874 | ctrl |= (cap & PCI_ACS_CR); | |
875 | ||
876 | /* Upstream Forwarding */ | |
877 | ctrl |= (cap & PCI_ACS_UF); | |
878 | ||
879 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
880 | } | |
881 | ||
882 | /** | |
883 | * pci_enable_acs - enable ACS if hardware support it | |
884 | * @dev: the PCI device | |
885 | */ | |
52fbf5bd | 886 | static void pci_enable_acs(struct pci_dev *dev) |
cbe42036 RJ |
887 | { |
888 | if (!pci_acs_enable) | |
889 | goto disable_acs_redir; | |
890 | ||
891 | if (!pci_dev_specific_enable_acs(dev)) | |
892 | goto disable_acs_redir; | |
893 | ||
894 | pci_std_enable_acs(dev); | |
895 | ||
896 | disable_acs_redir: | |
897 | /* | |
898 | * Note: pci_disable_acs_redir() must be called even if ACS was not | |
899 | * enabled by the kernel because it may have been enabled by | |
900 | * platform firmware. So if we are told to disable it, we should | |
901 | * always disable it after setting the kernel's default | |
902 | * preferences. | |
903 | */ | |
904 | pci_disable_acs_redir(dev); | |
905 | } | |
906 | ||
064b53db | 907 | /** |
70675e0b | 908 | * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) |
064b53db JL |
909 | * @dev: PCI device to have its BARs restored |
910 | * | |
911 | * Restore the BAR values for a given device, so as to make it | |
912 | * accessible by its driver. | |
913 | */ | |
3c78bc61 | 914 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 915 | { |
bc5f5a82 | 916 | int i; |
064b53db | 917 | |
bc5f5a82 | 918 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 919 | pci_update_resource(dev, i); |
064b53db JL |
920 | } |
921 | ||
299f2ffe | 922 | static const struct pci_platform_pm_ops *pci_platform_pm; |
961d9120 | 923 | |
299f2ffe | 924 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) |
961d9120 | 925 | { |
cc7cc02b | 926 | if (!ops->is_manageable || !ops->set_state || !ops->get_state || |
0847684c | 927 | !ops->choose_state || !ops->set_wakeup || !ops->need_resume) |
961d9120 RW |
928 | return -EINVAL; |
929 | pci_platform_pm = ops; | |
930 | return 0; | |
931 | } | |
932 | ||
933 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
934 | { | |
935 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
936 | } | |
937 | ||
938 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 939 | pci_power_t t) |
961d9120 RW |
940 | { |
941 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
942 | } | |
943 | ||
cc7cc02b LW |
944 | static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev) |
945 | { | |
946 | return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; | |
947 | } | |
948 | ||
b51033e0 RW |
949 | static inline void platform_pci_refresh_power_state(struct pci_dev *dev) |
950 | { | |
951 | if (pci_platform_pm && pci_platform_pm->refresh_state) | |
952 | pci_platform_pm->refresh_state(dev); | |
953 | } | |
954 | ||
961d9120 RW |
955 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
956 | { | |
957 | return pci_platform_pm ? | |
958 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
959 | } | |
8f7020d3 | 960 | |
0847684c | 961 | static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
962 | { |
963 | return pci_platform_pm ? | |
0847684c | 964 | pci_platform_pm->set_wakeup(dev, enable) : -ENODEV; |
b67ea761 RW |
965 | } |
966 | ||
bac2a909 RW |
967 | static inline bool platform_pci_need_resume(struct pci_dev *dev) |
968 | { | |
969 | return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; | |
970 | } | |
971 | ||
26ad34d5 MW |
972 | static inline bool platform_pci_bridge_d3(struct pci_dev *dev) |
973 | { | |
c3aaf086 BH |
974 | if (pci_platform_pm && pci_platform_pm->bridge_d3) |
975 | return pci_platform_pm->bridge_d3(dev); | |
976 | return false; | |
26ad34d5 MW |
977 | } |
978 | ||
1da177e4 | 979 | /** |
44e4e66e | 980 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
74356add | 981 | * given PCI device |
44e4e66e | 982 | * @dev: PCI device to handle. |
44e4e66e | 983 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 984 | * |
44e4e66e RW |
985 | * RETURN VALUE: |
986 | * -EINVAL if the requested state is invalid. | |
987 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
988 | * wrong version, or device doesn't support the requested state. | |
989 | * 0 if device already is in the requested state. | |
990 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 991 | */ |
f00a20ef | 992 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 993 | { |
337001b6 | 994 | u16 pmcsr; |
44e4e66e | 995 | bool need_restore = false; |
1da177e4 | 996 | |
4a865905 RW |
997 | /* Check if we're already there */ |
998 | if (dev->current_state == state) | |
999 | return 0; | |
1000 | ||
337001b6 | 1001 | if (!dev->pm_cap) |
cca03dec AL |
1002 | return -EIO; |
1003 | ||
44e4e66e RW |
1004 | if (state < PCI_D0 || state > PCI_D3hot) |
1005 | return -EINVAL; | |
1006 | ||
74356add | 1007 | /* |
e43f15ea BH |
1008 | * Validate transition: We can enter D0 from any state, but if |
1009 | * we're already in a low-power state, we can only go deeper. E.g., | |
1010 | * we can go from D1 to D3, but we can't go directly from D3 to D1; | |
1011 | * we'd have to go from D3 to D0, then to D1. | |
1da177e4 | 1012 | */ |
4a865905 | 1013 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 1014 | && dev->current_state > state) { |
e43f15ea BH |
1015 | pci_err(dev, "invalid power transition (from %s to %s)\n", |
1016 | pci_power_name(dev->current_state), | |
1017 | pci_power_name(state)); | |
1da177e4 | 1018 | return -EINVAL; |
44e4e66e | 1019 | } |
1da177e4 | 1020 | |
74356add | 1021 | /* Check if this device supports the desired state */ |
337001b6 RW |
1022 | if ((state == PCI_D1 && !dev->d1_support) |
1023 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 1024 | return -EIO; |
1da177e4 | 1025 | |
337001b6 | 1026 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
327ccbbc BH |
1027 | if (pmcsr == (u16) ~0) { |
1028 | pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n", | |
1029 | pci_power_name(dev->current_state), | |
1030 | pci_power_name(state)); | |
1031 | return -EIO; | |
1032 | } | |
064b53db | 1033 | |
74356add BH |
1034 | /* |
1035 | * If we're (effectively) in D3, force entire word to 0. | |
1da177e4 LT |
1036 | * This doesn't affect PME_Status, disables PME_En, and |
1037 | * sets PowerState to 0. | |
1038 | */ | |
32a36585 | 1039 | switch (dev->current_state) { |
d3535fbb JL |
1040 | case PCI_D0: |
1041 | case PCI_D1: | |
1042 | case PCI_D2: | |
1043 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
1044 | pmcsr |= state; | |
1045 | break; | |
f62795f1 RW |
1046 | case PCI_D3hot: |
1047 | case PCI_D3cold: | |
32a36585 JL |
1048 | case PCI_UNKNOWN: /* Boot-up */ |
1049 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 1050 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 1051 | need_restore = true; |
df561f66 | 1052 | fallthrough; /* force to D0 */ |
32a36585 | 1053 | default: |
d3535fbb | 1054 | pmcsr = 0; |
32a36585 | 1055 | break; |
1da177e4 LT |
1056 | } |
1057 | ||
74356add | 1058 | /* Enter specified state */ |
337001b6 | 1059 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 | 1060 | |
74356add BH |
1061 | /* |
1062 | * Mandatory power management transition delays; see PCI PM 1.1 | |
1063 | * 5.6.1 table 18 | |
1064 | */ | |
1da177e4 | 1065 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
1ae861e6 | 1066 | pci_dev_d3_sleep(dev); |
1da177e4 | 1067 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
7e24bc34 | 1068 | msleep(PCI_PM_D2_DELAY); |
1da177e4 | 1069 | |
e13cdbd7 RW |
1070 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
1071 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
7f1c62c4 | 1072 | if (dev->current_state != state) |
e43f15ea BH |
1073 | pci_info_ratelimited(dev, "refused to change power state from %s to %s\n", |
1074 | pci_power_name(dev->current_state), | |
1075 | pci_power_name(state)); | |
064b53db | 1076 | |
448bd857 HY |
1077 | /* |
1078 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
1079 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
1080 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
1081 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
1082 | * For example, at least some versions of the 3c905B and the | |
1083 | * 3c556B exhibit this behaviour. | |
1084 | * | |
1085 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
1086 | * devices in a D3hot state at boot. Consequently, we need to | |
1087 | * restore at least the BARs so that the device will be | |
1088 | * accessible to its driver. | |
1089 | */ | |
1090 | if (need_restore) | |
1091 | pci_restore_bars(dev); | |
1092 | ||
f00a20ef | 1093 | if (dev->bus->self) |
7d715a6c SL |
1094 | pcie_aspm_pm_state_change(dev->bus->self); |
1095 | ||
1da177e4 LT |
1096 | return 0; |
1097 | } | |
1098 | ||
44e4e66e | 1099 | /** |
a6a64026 | 1100 | * pci_update_current_state - Read power state of given device and cache it |
44e4e66e | 1101 | * @dev: PCI device to handle. |
f06fc0b6 | 1102 | * @state: State to cache in case the device doesn't have the PM capability |
a6a64026 LW |
1103 | * |
1104 | * The power state is read from the PMCSR register, which however is | |
1105 | * inaccessible in D3cold. The platform firmware is therefore queried first | |
1106 | * to detect accessibility of the register. In case the platform firmware | |
1107 | * reports an incorrect state or the device isn't power manageable by the | |
1108 | * platform at all, we try to detect D3cold by testing accessibility of the | |
1109 | * vendor ID in config space. | |
44e4e66e | 1110 | */ |
73410429 | 1111 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 1112 | { |
a6a64026 LW |
1113 | if (platform_pci_get_power_state(dev) == PCI_D3cold || |
1114 | !pci_device_is_present(dev)) { | |
1115 | dev->current_state = PCI_D3cold; | |
1116 | } else if (dev->pm_cap) { | |
44e4e66e RW |
1117 | u16 pmcsr; |
1118 | ||
337001b6 | 1119 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 1120 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
1121 | } else { |
1122 | dev->current_state = state; | |
44e4e66e RW |
1123 | } |
1124 | } | |
1125 | ||
b51033e0 RW |
1126 | /** |
1127 | * pci_refresh_power_state - Refresh the given device's power state data | |
1128 | * @dev: Target PCI device. | |
1129 | * | |
1130 | * Ask the platform to refresh the devices power state information and invoke | |
1131 | * pci_update_current_state() to update its current PCI power state. | |
1132 | */ | |
1133 | void pci_refresh_power_state(struct pci_dev *dev) | |
1134 | { | |
1135 | if (platform_pci_power_manageable(dev)) | |
1136 | platform_pci_refresh_power_state(dev); | |
1137 | ||
1138 | pci_update_current_state(dev, dev->current_state); | |
1139 | } | |
1140 | ||
0e5dd46b RW |
1141 | /** |
1142 | * pci_platform_power_transition - Use platform to change device power state | |
1143 | * @dev: PCI device to handle. | |
1144 | * @state: State to put the device into. | |
1145 | */ | |
d6aa37cd | 1146 | int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) |
0e5dd46b RW |
1147 | { |
1148 | int error; | |
1149 | ||
1150 | if (platform_pci_power_manageable(dev)) { | |
1151 | error = platform_pci_set_power_state(dev, state); | |
1152 | if (!error) | |
1153 | pci_update_current_state(dev, state); | |
769ba721 | 1154 | } else |
0e5dd46b | 1155 | error = -ENODEV; |
769ba721 RW |
1156 | |
1157 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
1158 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
1159 | |
1160 | return error; | |
1161 | } | |
d6aa37cd | 1162 | EXPORT_SYMBOL_GPL(pci_platform_power_transition); |
0e5dd46b | 1163 | |
0b950f0f SH |
1164 | /** |
1165 | * pci_wakeup - Wake up a PCI device | |
1166 | * @pci_dev: Device to handle. | |
1167 | * @ign: ignored parameter | |
1168 | */ | |
1169 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
1170 | { | |
1171 | pci_wakeup_event(pci_dev); | |
1172 | pm_request_resume(&pci_dev->dev); | |
1173 | return 0; | |
1174 | } | |
1175 | ||
1176 | /** | |
1177 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
1178 | * @bus: Top bus of the subtree to walk. | |
1179 | */ | |
2a4d2c42 | 1180 | void pci_wakeup_bus(struct pci_bus *bus) |
0b950f0f SH |
1181 | { |
1182 | if (bus) | |
1183 | pci_walk_bus(bus, pci_wakeup, NULL); | |
1184 | } | |
1185 | ||
bae26849 VS |
1186 | static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) |
1187 | { | |
1188 | int delay = 1; | |
1189 | u32 id; | |
1190 | ||
1191 | /* | |
1192 | * After reset, the device should not silently discard config | |
1193 | * requests, but it may still indicate that it needs more time by | |
1194 | * responding to them with CRS completions. The Root Port will | |
1195 | * generally synthesize ~0 data to complete the read (except when | |
1196 | * CRS SV is enabled and the read was for the Vendor ID; in that | |
1197 | * case it synthesizes 0x0001 data). | |
1198 | * | |
1199 | * Wait for the device to return a non-CRS completion. Read the | |
1200 | * Command register instead of Vendor ID so we don't have to | |
1201 | * contend with the CRS SV value. | |
1202 | */ | |
1203 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
1204 | while (id == ~0) { | |
1205 | if (delay > timeout) { | |
1206 | pci_warn(dev, "not ready %dms after %s; giving up\n", | |
1207 | delay - 1, reset_type); | |
1208 | return -ENOTTY; | |
1209 | } | |
1210 | ||
1211 | if (delay > 1000) | |
1212 | pci_info(dev, "not ready %dms after %s; waiting\n", | |
1213 | delay - 1, reset_type); | |
1214 | ||
1215 | msleep(delay); | |
1216 | delay *= 2; | |
1217 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
1218 | } | |
1219 | ||
1220 | if (delay > 1000) | |
1221 | pci_info(dev, "ready %dms after %s\n", delay - 1, | |
1222 | reset_type); | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
0e5dd46b | 1227 | /** |
dc2256b0 RW |
1228 | * pci_power_up - Put the given device into D0 |
1229 | * @dev: PCI device to power up | |
0e5dd46b | 1230 | */ |
dc2256b0 | 1231 | int pci_power_up(struct pci_dev *dev) |
0e5dd46b | 1232 | { |
dc2256b0 RW |
1233 | pci_platform_power_transition(dev, PCI_D0); |
1234 | ||
1235 | /* | |
ad9001f2 MW |
1236 | * Mandatory power management transition delays are handled in |
1237 | * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the | |
1238 | * corresponding bridge. | |
dc2256b0 RW |
1239 | */ |
1240 | if (dev->runtime_d3cold) { | |
448bd857 | 1241 | /* |
dc2256b0 RW |
1242 | * When powering on a bridge from D3cold, the whole hierarchy |
1243 | * may be powered on into D0uninitialized state, resume them to | |
1244 | * give them a chance to suspend again | |
448bd857 | 1245 | */ |
dc2256b0 | 1246 | pci_wakeup_bus(dev->subordinate); |
448bd857 | 1247 | } |
448bd857 | 1248 | |
adfac8f6 | 1249 | return pci_raw_set_power_state(dev, PCI_D0); |
448bd857 HY |
1250 | } |
1251 | ||
1252 | /** | |
1253 | * __pci_dev_set_current_state - Set current state of a PCI device | |
1254 | * @dev: Device to handle | |
1255 | * @data: pointer to state to be set | |
1256 | */ | |
1257 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
1258 | { | |
1259 | pci_power_t state = *(pci_power_t *)data; | |
1260 | ||
1261 | dev->current_state = state; | |
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | /** | |
2a4d2c42 | 1266 | * pci_bus_set_current_state - Walk given bus and set current state of devices |
448bd857 HY |
1267 | * @bus: Top bus of the subtree to walk. |
1268 | * @state: state to be set | |
1269 | */ | |
2a4d2c42 | 1270 | void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) |
448bd857 HY |
1271 | { |
1272 | if (bus) | |
1273 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
1274 | } |
1275 | ||
44e4e66e RW |
1276 | /** |
1277 | * pci_set_power_state - Set the power state of a PCI device | |
1278 | * @dev: PCI device to handle. | |
1279 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
1280 | * | |
877d0310 | 1281 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
1282 | * the device's PCI PM registers. |
1283 | * | |
1284 | * RETURN VALUE: | |
1285 | * -EINVAL if the requested state is invalid. | |
1286 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
1287 | * wrong version, or device doesn't support the requested state. | |
ab4b8a47 | 1288 | * 0 if the transition is to D1 or D2 but D1 and D2 are not supported. |
44e4e66e | 1289 | * 0 if device already is in the requested state. |
ab4b8a47 | 1290 | * 0 if the transition is to D3 but D3 is not supported. |
44e4e66e RW |
1291 | * 0 if device's power state has been successfully changed. |
1292 | */ | |
1293 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
1294 | { | |
337001b6 | 1295 | int error; |
44e4e66e | 1296 | |
74356add | 1297 | /* Bound the state we're entering */ |
448bd857 HY |
1298 | if (state > PCI_D3cold) |
1299 | state = PCI_D3cold; | |
44e4e66e RW |
1300 | else if (state < PCI_D0) |
1301 | state = PCI_D0; | |
1302 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
74356add | 1303 | |
44e4e66e | 1304 | /* |
74356add BH |
1305 | * If the device or the parent bridge do not support PCI |
1306 | * PM, ignore the request if we're doing anything other | |
1307 | * than putting it into D0 (which would only happen on | |
1308 | * boot). | |
44e4e66e RW |
1309 | */ |
1310 | return 0; | |
1311 | ||
db288c9c RW |
1312 | /* Check if we're already there */ |
1313 | if (dev->current_state == state) | |
1314 | return 0; | |
1315 | ||
adfac8f6 RW |
1316 | if (state == PCI_D0) |
1317 | return pci_power_up(dev); | |
0e5dd46b | 1318 | |
74356add BH |
1319 | /* |
1320 | * This device is quirked not to be put into D3, so don't put it in | |
1321 | * D3 | |
1322 | */ | |
448bd857 | 1323 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 1324 | return 0; |
44e4e66e | 1325 | |
448bd857 HY |
1326 | /* |
1327 | * To put device in D3cold, we put device into D3hot in native | |
1328 | * way, then put device into D3cold with platform ops | |
1329 | */ | |
1330 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
1331 | PCI_D3hot : state); | |
44e4e66e | 1332 | |
9c77e63b RW |
1333 | if (pci_platform_power_transition(dev, state)) |
1334 | return error; | |
44e4e66e | 1335 | |
9c77e63b RW |
1336 | /* Powering off a bridge may power off the whole hierarchy */ |
1337 | if (state == PCI_D3cold) | |
1338 | pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
44e4e66e | 1339 | |
9c77e63b | 1340 | return 0; |
45144d42 | 1341 | } |
b7fe9434 | 1342 | EXPORT_SYMBOL(pci_set_power_state); |
45144d42 | 1343 | |
1da177e4 LT |
1344 | /** |
1345 | * pci_choose_state - Choose the power state of a PCI device | |
1346 | * @dev: PCI device to be suspended | |
1347 | * @state: target sleep state for the whole system. This is the value | |
74356add | 1348 | * that is passed to suspend() function. |
1da177e4 LT |
1349 | * |
1350 | * Returns PCI power state suitable for given device and given system | |
1351 | * message. | |
1352 | */ | |
1da177e4 LT |
1353 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) |
1354 | { | |
ab826ca4 | 1355 | pci_power_t ret; |
0f64474b | 1356 | |
728cdb75 | 1357 | if (!dev->pm_cap) |
1da177e4 LT |
1358 | return PCI_D0; |
1359 | ||
961d9120 RW |
1360 | ret = platform_pci_choose_state(dev); |
1361 | if (ret != PCI_POWER_ERROR) | |
1362 | return ret; | |
ca078bae PM |
1363 | |
1364 | switch (state.event) { | |
1365 | case PM_EVENT_ON: | |
1366 | return PCI_D0; | |
1367 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
1368 | case PM_EVENT_PRETHAW: |
1369 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 1370 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 1371 | case PM_EVENT_HIBERNATE: |
ca078bae | 1372 | return PCI_D3hot; |
1da177e4 | 1373 | default: |
7506dc79 | 1374 | pci_info(dev, "unrecognized suspend event %d\n", |
80ccba11 | 1375 | state.event); |
1da177e4 LT |
1376 | BUG(); |
1377 | } | |
1378 | return PCI_D0; | |
1379 | } | |
1da177e4 LT |
1380 | EXPORT_SYMBOL(pci_choose_state); |
1381 | ||
89858517 YZ |
1382 | #define PCI_EXP_SAVE_REGS 7 |
1383 | ||
fd0f7f73 AW |
1384 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
1385 | u16 cap, bool extended) | |
34a4876e YL |
1386 | { |
1387 | struct pci_cap_saved_state *tmp; | |
34a4876e | 1388 | |
b67bfe0d | 1389 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 1390 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
1391 | return tmp; |
1392 | } | |
1393 | return NULL; | |
1394 | } | |
1395 | ||
fd0f7f73 AW |
1396 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
1397 | { | |
1398 | return _pci_find_saved_cap(dev, cap, false); | |
1399 | } | |
1400 | ||
1401 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
1402 | { | |
1403 | return _pci_find_saved_cap(dev, cap, true); | |
1404 | } | |
1405 | ||
b56a5a23 MT |
1406 | static int pci_save_pcie_state(struct pci_dev *dev) |
1407 | { | |
59875ae4 | 1408 | int i = 0; |
b56a5a23 MT |
1409 | struct pci_cap_saved_state *save_state; |
1410 | u16 *cap; | |
1411 | ||
59875ae4 | 1412 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
1413 | return 0; |
1414 | ||
9f35575d | 1415 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 1416 | if (!save_state) { |
7506dc79 | 1417 | pci_err(dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
1418 | return -ENOMEM; |
1419 | } | |
63f4898a | 1420 | |
59875ae4 JL |
1421 | cap = (u16 *)&save_state->cap.data[0]; |
1422 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
1423 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
1424 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
1425 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
1426 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
1427 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
1428 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 1429 | |
b56a5a23 MT |
1430 | return 0; |
1431 | } | |
1432 | ||
1433 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
1434 | { | |
59875ae4 | 1435 | int i = 0; |
b56a5a23 MT |
1436 | struct pci_cap_saved_state *save_state; |
1437 | u16 *cap; | |
1438 | ||
1439 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 1440 | if (!save_state) |
9cb604ed MS |
1441 | return; |
1442 | ||
59875ae4 JL |
1443 | cap = (u16 *)&save_state->cap.data[0]; |
1444 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
1445 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
1446 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
1447 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
1448 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
1449 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
1450 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
1451 | } |
1452 | ||
cc692a5f SH |
1453 | static int pci_save_pcix_state(struct pci_dev *dev) |
1454 | { | |
63f4898a | 1455 | int pos; |
cc692a5f | 1456 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
1457 | |
1458 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1459 | if (!pos) |
cc692a5f SH |
1460 | return 0; |
1461 | ||
f34303de | 1462 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 1463 | if (!save_state) { |
7506dc79 | 1464 | pci_err(dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
1465 | return -ENOMEM; |
1466 | } | |
cc692a5f | 1467 | |
24a4742f AW |
1468 | pci_read_config_word(dev, pos + PCI_X_CMD, |
1469 | (u16 *)save_state->cap.data); | |
63f4898a | 1470 | |
cc692a5f SH |
1471 | return 0; |
1472 | } | |
1473 | ||
1474 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
1475 | { | |
1476 | int i = 0, pos; | |
1477 | struct pci_cap_saved_state *save_state; | |
1478 | u16 *cap; | |
1479 | ||
1480 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
1481 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1482 | if (!save_state || !pos) |
cc692a5f | 1483 | return; |
24a4742f | 1484 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
1485 | |
1486 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
1487 | } |
1488 | ||
dbbfadf2 BH |
1489 | static void pci_save_ltr_state(struct pci_dev *dev) |
1490 | { | |
1491 | int ltr; | |
1492 | struct pci_cap_saved_state *save_state; | |
1493 | u16 *cap; | |
1494 | ||
1495 | if (!pci_is_pcie(dev)) | |
1496 | return; | |
1497 | ||
1498 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1499 | if (!ltr) | |
1500 | return; | |
1501 | ||
1502 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1503 | if (!save_state) { | |
1504 | pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n"); | |
1505 | return; | |
1506 | } | |
1507 | ||
1508 | cap = (u16 *)&save_state->cap.data[0]; | |
1509 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++); | |
1510 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++); | |
1511 | } | |
1512 | ||
1513 | static void pci_restore_ltr_state(struct pci_dev *dev) | |
1514 | { | |
1515 | struct pci_cap_saved_state *save_state; | |
1516 | int ltr; | |
1517 | u16 *cap; | |
1518 | ||
1519 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1520 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1521 | if (!save_state || !ltr) | |
1522 | return; | |
1523 | ||
1524 | cap = (u16 *)&save_state->cap.data[0]; | |
1525 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++); | |
1526 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++); | |
1527 | } | |
cc692a5f | 1528 | |
1da177e4 | 1529 | /** |
74356add BH |
1530 | * pci_save_state - save the PCI configuration space of a device before |
1531 | * suspending | |
1532 | * @dev: PCI device that we're dealing with | |
1da177e4 | 1533 | */ |
3c78bc61 | 1534 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1535 | { |
1536 | int i; | |
1537 | /* XXX: 100% dword access ok here? */ | |
47b802d5 | 1538 | for (i = 0; i < 16; i++) { |
9e0b5b2c | 1539 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
47b802d5 CY |
1540 | pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n", |
1541 | i * 4, dev->saved_config_space[i]); | |
1542 | } | |
aa8c6c93 | 1543 | dev->state_saved = true; |
79e50e72 QL |
1544 | |
1545 | i = pci_save_pcie_state(dev); | |
1546 | if (i != 0) | |
b56a5a23 | 1547 | return i; |
79e50e72 QL |
1548 | |
1549 | i = pci_save_pcix_state(dev); | |
1550 | if (i != 0) | |
cc692a5f | 1551 | return i; |
79e50e72 | 1552 | |
dbbfadf2 | 1553 | pci_save_ltr_state(dev); |
4f802170 | 1554 | pci_save_dpc_state(dev); |
af65d1ad | 1555 | pci_save_aer_state(dev); |
754834b9 | 1556 | return pci_save_vc_state(dev); |
1da177e4 | 1557 | } |
b7fe9434 | 1558 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1559 | |
ebfc5b80 | 1560 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
08387454 | 1561 | u32 saved_val, int retry, bool force) |
ebfc5b80 RW |
1562 | { |
1563 | u32 val; | |
1564 | ||
1565 | pci_read_config_dword(pdev, offset, &val); | |
08387454 | 1566 | if (!force && val == saved_val) |
ebfc5b80 RW |
1567 | return; |
1568 | ||
1569 | for (;;) { | |
7506dc79 | 1570 | pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
227f0647 | 1571 | offset, val, saved_val); |
ebfc5b80 RW |
1572 | pci_write_config_dword(pdev, offset, saved_val); |
1573 | if (retry-- <= 0) | |
1574 | return; | |
1575 | ||
1576 | pci_read_config_dword(pdev, offset, &val); | |
1577 | if (val == saved_val) | |
1578 | return; | |
1579 | ||
1580 | mdelay(1); | |
1581 | } | |
1582 | } | |
1583 | ||
a6cb9ee7 | 1584 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
08387454 DD |
1585 | int start, int end, int retry, |
1586 | bool force) | |
ebfc5b80 RW |
1587 | { |
1588 | int index; | |
1589 | ||
1590 | for (index = end; index >= start; index--) | |
1591 | pci_restore_config_dword(pdev, 4 * index, | |
1592 | pdev->saved_config_space[index], | |
08387454 | 1593 | retry, force); |
ebfc5b80 RW |
1594 | } |
1595 | ||
a6cb9ee7 RW |
1596 | static void pci_restore_config_space(struct pci_dev *pdev) |
1597 | { | |
1598 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
08387454 | 1599 | pci_restore_config_space_range(pdev, 10, 15, 0, false); |
a6cb9ee7 | 1600 | /* Restore BARs before the command register. */ |
08387454 DD |
1601 | pci_restore_config_space_range(pdev, 4, 9, 10, false); |
1602 | pci_restore_config_space_range(pdev, 0, 3, 0, false); | |
1603 | } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1604 | pci_restore_config_space_range(pdev, 12, 15, 0, false); | |
1605 | ||
1606 | /* | |
1607 | * Force rewriting of prefetch registers to avoid S3 resume | |
1608 | * issues on Intel PCI bridges that occur when these | |
1609 | * registers are not explicitly written. | |
1610 | */ | |
1611 | pci_restore_config_space_range(pdev, 9, 11, 0, true); | |
1612 | pci_restore_config_space_range(pdev, 0, 8, 0, false); | |
a6cb9ee7 | 1613 | } else { |
08387454 | 1614 | pci_restore_config_space_range(pdev, 0, 15, 0, false); |
a6cb9ee7 RW |
1615 | } |
1616 | } | |
1617 | ||
d3252ace CK |
1618 | static void pci_restore_rebar_state(struct pci_dev *pdev) |
1619 | { | |
1620 | unsigned int pos, nbars, i; | |
1621 | u32 ctrl; | |
1622 | ||
1623 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
1624 | if (!pos) | |
1625 | return; | |
1626 | ||
1627 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1628 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
1629 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
1630 | ||
1631 | for (i = 0; i < nbars; i++, pos += 8) { | |
1632 | struct resource *res; | |
1633 | int bar_idx, size; | |
1634 | ||
1635 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1636 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
1637 | res = pdev->resource + bar_idx; | |
d2182b2d | 1638 | size = ilog2(resource_size(res)) - 20; |
d3252ace | 1639 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; |
b1277a22 | 1640 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
d3252ace CK |
1641 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
1642 | } | |
1643 | } | |
1644 | ||
f7625980 | 1645 | /** |
1da177e4 | 1646 | * pci_restore_state - Restore the saved state of a PCI device |
74356add | 1647 | * @dev: PCI device that we're dealing with |
1da177e4 | 1648 | */ |
1d3c16a8 | 1649 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1650 | { |
c82f63e4 | 1651 | if (!dev->state_saved) |
1d3c16a8 | 1652 | return; |
4b77b0a2 | 1653 | |
dbbfadf2 BH |
1654 | /* |
1655 | * Restore max latencies (in the LTR capability) before enabling | |
1656 | * LTR itself (in the PCIe capability). | |
1657 | */ | |
1658 | pci_restore_ltr_state(dev); | |
1659 | ||
b56a5a23 | 1660 | pci_restore_pcie_state(dev); |
4ebeb1ec CT |
1661 | pci_restore_pasid_state(dev); |
1662 | pci_restore_pri_state(dev); | |
1900ca13 | 1663 | pci_restore_ats_state(dev); |
425c1b22 | 1664 | pci_restore_vc_state(dev); |
d3252ace | 1665 | pci_restore_rebar_state(dev); |
4f802170 | 1666 | pci_restore_dpc_state(dev); |
b56a5a23 | 1667 | |
894020fd | 1668 | pci_aer_clear_status(dev); |
af65d1ad | 1669 | pci_restore_aer_state(dev); |
b07461a8 | 1670 | |
a6cb9ee7 | 1671 | pci_restore_config_space(dev); |
ebfc5b80 | 1672 | |
cc692a5f | 1673 | pci_restore_pcix_state(dev); |
41017f0c | 1674 | pci_restore_msi_state(dev); |
ccbc175a AD |
1675 | |
1676 | /* Restore ACS and IOV configuration state */ | |
1677 | pci_enable_acs(dev); | |
8c5cdb6a | 1678 | pci_restore_iov_state(dev); |
8fed4b65 | 1679 | |
4b77b0a2 | 1680 | dev->state_saved = false; |
1da177e4 | 1681 | } |
b7fe9434 | 1682 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1683 | |
ffbdd3f7 AW |
1684 | struct pci_saved_state { |
1685 | u32 config_space[16]; | |
914a1951 | 1686 | struct pci_cap_saved_data cap[]; |
ffbdd3f7 AW |
1687 | }; |
1688 | ||
1689 | /** | |
1690 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1691 | * the device saved state. | |
1692 | * @dev: PCI device that we're dealing with | |
1693 | * | |
f7625980 | 1694 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1695 | */ |
1696 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1697 | { | |
1698 | struct pci_saved_state *state; | |
1699 | struct pci_cap_saved_state *tmp; | |
1700 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1701 | size_t size; |
1702 | ||
1703 | if (!dev->state_saved) | |
1704 | return NULL; | |
1705 | ||
1706 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1707 | ||
b67bfe0d | 1708 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1709 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1710 | ||
1711 | state = kzalloc(size, GFP_KERNEL); | |
1712 | if (!state) | |
1713 | return NULL; | |
1714 | ||
1715 | memcpy(state->config_space, dev->saved_config_space, | |
1716 | sizeof(state->config_space)); | |
1717 | ||
1718 | cap = state->cap; | |
b67bfe0d | 1719 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1720 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1721 | memcpy(cap, &tmp->cap, len); | |
1722 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1723 | } | |
1724 | /* Empty cap_save terminates list */ | |
1725 | ||
1726 | return state; | |
1727 | } | |
1728 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1729 | ||
1730 | /** | |
1731 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1732 | * @dev: PCI device that we're dealing with | |
1733 | * @state: Saved state returned from pci_store_saved_state() | |
1734 | */ | |
98d9b271 KRW |
1735 | int pci_load_saved_state(struct pci_dev *dev, |
1736 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1737 | { |
1738 | struct pci_cap_saved_data *cap; | |
1739 | ||
1740 | dev->state_saved = false; | |
1741 | ||
1742 | if (!state) | |
1743 | return 0; | |
1744 | ||
1745 | memcpy(dev->saved_config_space, state->config_space, | |
1746 | sizeof(state->config_space)); | |
1747 | ||
1748 | cap = state->cap; | |
1749 | while (cap->size) { | |
1750 | struct pci_cap_saved_state *tmp; | |
1751 | ||
fd0f7f73 | 1752 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1753 | if (!tmp || tmp->cap.size != cap->size) |
1754 | return -EINVAL; | |
1755 | ||
1756 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1757 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1758 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1759 | } | |
1760 | ||
1761 | dev->state_saved = true; | |
1762 | return 0; | |
1763 | } | |
98d9b271 | 1764 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1765 | |
1766 | /** | |
1767 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1768 | * and free the memory allocated for it. | |
1769 | * @dev: PCI device that we're dealing with | |
1770 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1771 | */ | |
1772 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1773 | struct pci_saved_state **state) | |
1774 | { | |
1775 | int ret = pci_load_saved_state(dev, *state); | |
1776 | kfree(*state); | |
1777 | *state = NULL; | |
1778 | return ret; | |
1779 | } | |
1780 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1781 | ||
8a9d5609 BH |
1782 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1783 | { | |
1784 | return pci_enable_resources(dev, bars); | |
1785 | } | |
1786 | ||
38cc1302 HS |
1787 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1788 | { | |
1789 | int err; | |
1f6ae47e | 1790 | struct pci_dev *bridge; |
1e2571a7 BH |
1791 | u16 cmd; |
1792 | u8 pin; | |
38cc1302 HS |
1793 | |
1794 | err = pci_set_power_state(dev, PCI_D0); | |
1795 | if (err < 0 && err != -EIO) | |
1796 | return err; | |
1f6ae47e VS |
1797 | |
1798 | bridge = pci_upstream_bridge(dev); | |
1799 | if (bridge) | |
1800 | pcie_aspm_powersave_config_link(bridge); | |
1801 | ||
38cc1302 HS |
1802 | err = pcibios_enable_device(dev, bars); |
1803 | if (err < 0) | |
1804 | return err; | |
1805 | pci_fixup_device(pci_fixup_enable, dev); | |
1806 | ||
866d5417 BH |
1807 | if (dev->msi_enabled || dev->msix_enabled) |
1808 | return 0; | |
1809 | ||
1e2571a7 BH |
1810 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1811 | if (pin) { | |
1812 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1813 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1814 | pci_write_config_word(dev, PCI_COMMAND, | |
1815 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1816 | } | |
1817 | ||
38cc1302 HS |
1818 | return 0; |
1819 | } | |
1820 | ||
1821 | /** | |
0b62e13b | 1822 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1823 | * @dev: PCI device to be resumed |
1824 | * | |
74356add BH |
1825 | * NOTE: This function is a backend of pci_default_resume() and is not supposed |
1826 | * to be called by normal code, write proper resume handler and use it instead. | |
38cc1302 | 1827 | */ |
0b62e13b | 1828 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1829 | { |
296ccb08 | 1830 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1831 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1832 | return 0; | |
1833 | } | |
b7fe9434 | 1834 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1835 | |
928bea96 YL |
1836 | static void pci_enable_bridge(struct pci_dev *dev) |
1837 | { | |
79272138 | 1838 | struct pci_dev *bridge; |
928bea96 YL |
1839 | int retval; |
1840 | ||
79272138 BH |
1841 | bridge = pci_upstream_bridge(dev); |
1842 | if (bridge) | |
1843 | pci_enable_bridge(bridge); | |
928bea96 | 1844 | |
cf3e1feb | 1845 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1846 | if (!dev->is_busmaster) |
cf3e1feb | 1847 | pci_set_master(dev); |
0f50a49e | 1848 | return; |
cf3e1feb YL |
1849 | } |
1850 | ||
928bea96 YL |
1851 | retval = pci_enable_device(dev); |
1852 | if (retval) | |
7506dc79 | 1853 | pci_err(dev, "Error enabling bridge (%d), continuing\n", |
928bea96 YL |
1854 | retval); |
1855 | pci_set_master(dev); | |
1856 | } | |
1857 | ||
b4b4fbba | 1858 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1859 | { |
79272138 | 1860 | struct pci_dev *bridge; |
1da177e4 | 1861 | int err; |
b718989d | 1862 | int i, bars = 0; |
1da177e4 | 1863 | |
97c145f7 JB |
1864 | /* |
1865 | * Power state could be unknown at this point, either due to a fresh | |
1866 | * boot or a device removal call. So get the current power state | |
1867 | * so that things like MSI message writing will behave as expected | |
1868 | * (e.g. if the device really is in D0 at enable time). | |
1869 | */ | |
1870 | if (dev->pm_cap) { | |
1871 | u16 pmcsr; | |
1872 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1873 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1874 | } | |
1875 | ||
cc7ba39b | 1876 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1877 | return 0; /* already enabled */ |
1878 | ||
79272138 | 1879 | bridge = pci_upstream_bridge(dev); |
0f50a49e | 1880 | if (bridge) |
79272138 | 1881 | pci_enable_bridge(bridge); |
928bea96 | 1882 | |
497f16f2 YL |
1883 | /* only skip sriov related */ |
1884 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1885 | if (dev->resource[i].flags & flags) | |
1886 | bars |= (1 << i); | |
1887 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1888 | if (dev->resource[i].flags & flags) |
1889 | bars |= (1 << i); | |
1890 | ||
38cc1302 | 1891 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1892 | if (err < 0) |
38cc1302 | 1893 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1894 | return err; |
1da177e4 LT |
1895 | } |
1896 | ||
b718989d BH |
1897 | /** |
1898 | * pci_enable_device_io - Initialize a device for use with IO space | |
1899 | * @dev: PCI device to be initialized | |
1900 | * | |
74356add BH |
1901 | * Initialize device before it's used by a driver. Ask low-level code |
1902 | * to enable I/O resources. Wake up the device if it was suspended. | |
1903 | * Beware, this function can fail. | |
b718989d BH |
1904 | */ |
1905 | int pci_enable_device_io(struct pci_dev *dev) | |
1906 | { | |
b4b4fbba | 1907 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1908 | } |
b7fe9434 | 1909 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1910 | |
1911 | /** | |
1912 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1913 | * @dev: PCI device to be initialized | |
1914 | * | |
74356add BH |
1915 | * Initialize device before it's used by a driver. Ask low-level code |
1916 | * to enable Memory resources. Wake up the device if it was suspended. | |
1917 | * Beware, this function can fail. | |
b718989d BH |
1918 | */ |
1919 | int pci_enable_device_mem(struct pci_dev *dev) | |
1920 | { | |
b4b4fbba | 1921 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1922 | } |
b7fe9434 | 1923 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1924 | |
bae94d02 IPG |
1925 | /** |
1926 | * pci_enable_device - Initialize device before it's used by a driver. | |
1927 | * @dev: PCI device to be initialized | |
1928 | * | |
74356add BH |
1929 | * Initialize device before it's used by a driver. Ask low-level code |
1930 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1931 | * Beware, this function can fail. | |
bae94d02 | 1932 | * |
74356add BH |
1933 | * Note we don't actually enable the device many times if we call |
1934 | * this function repeatedly (we just increment the count). | |
bae94d02 IPG |
1935 | */ |
1936 | int pci_enable_device(struct pci_dev *dev) | |
1937 | { | |
b4b4fbba | 1938 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1939 | } |
b7fe9434 | 1940 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1941 | |
9ac7849e | 1942 | /* |
74356add BH |
1943 | * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X |
1944 | * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so | |
9ac7849e TH |
1945 | * there's no need to track it separately. pci_devres is initialized |
1946 | * when a device is enabled using managed PCI device enable interface. | |
1947 | */ | |
1948 | struct pci_devres { | |
7f375f32 TH |
1949 | unsigned int enabled:1; |
1950 | unsigned int pinned:1; | |
9ac7849e TH |
1951 | unsigned int orig_intx:1; |
1952 | unsigned int restore_intx:1; | |
fc0f9f4d | 1953 | unsigned int mwi:1; |
9ac7849e TH |
1954 | u32 region_mask; |
1955 | }; | |
1956 | ||
1957 | static void pcim_release(struct device *gendev, void *res) | |
1958 | { | |
f3d2f165 | 1959 | struct pci_dev *dev = to_pci_dev(gendev); |
9ac7849e TH |
1960 | struct pci_devres *this = res; |
1961 | int i; | |
1962 | ||
1963 | if (dev->msi_enabled) | |
1964 | pci_disable_msi(dev); | |
1965 | if (dev->msix_enabled) | |
1966 | pci_disable_msix(dev); | |
1967 | ||
1968 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1969 | if (this->region_mask & (1 << i)) | |
1970 | pci_release_region(dev, i); | |
1971 | ||
fc0f9f4d HK |
1972 | if (this->mwi) |
1973 | pci_clear_mwi(dev); | |
1974 | ||
9ac7849e TH |
1975 | if (this->restore_intx) |
1976 | pci_intx(dev, this->orig_intx); | |
1977 | ||
7f375f32 | 1978 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1979 | pci_disable_device(dev); |
1980 | } | |
1981 | ||
07656d83 | 1982 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1983 | { |
1984 | struct pci_devres *dr, *new_dr; | |
1985 | ||
1986 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1987 | if (dr) | |
1988 | return dr; | |
1989 | ||
1990 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1991 | if (!new_dr) | |
1992 | return NULL; | |
1993 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1994 | } | |
1995 | ||
07656d83 | 1996 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1997 | { |
1998 | if (pci_is_managed(pdev)) | |
1999 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
2000 | return NULL; | |
2001 | } | |
2002 | ||
2003 | /** | |
2004 | * pcim_enable_device - Managed pci_enable_device() | |
2005 | * @pdev: PCI device to be initialized | |
2006 | * | |
2007 | * Managed pci_enable_device(). | |
2008 | */ | |
2009 | int pcim_enable_device(struct pci_dev *pdev) | |
2010 | { | |
2011 | struct pci_devres *dr; | |
2012 | int rc; | |
2013 | ||
2014 | dr = get_pci_dr(pdev); | |
2015 | if (unlikely(!dr)) | |
2016 | return -ENOMEM; | |
b95d58ea TH |
2017 | if (dr->enabled) |
2018 | return 0; | |
9ac7849e TH |
2019 | |
2020 | rc = pci_enable_device(pdev); | |
2021 | if (!rc) { | |
2022 | pdev->is_managed = 1; | |
7f375f32 | 2023 | dr->enabled = 1; |
9ac7849e TH |
2024 | } |
2025 | return rc; | |
2026 | } | |
b7fe9434 | 2027 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
2028 | |
2029 | /** | |
2030 | * pcim_pin_device - Pin managed PCI device | |
2031 | * @pdev: PCI device to pin | |
2032 | * | |
2033 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
2034 | * driver detach. @pdev must have been enabled with | |
2035 | * pcim_enable_device(). | |
2036 | */ | |
2037 | void pcim_pin_device(struct pci_dev *pdev) | |
2038 | { | |
2039 | struct pci_devres *dr; | |
2040 | ||
2041 | dr = find_pci_dr(pdev); | |
7f375f32 | 2042 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 2043 | if (dr) |
7f375f32 | 2044 | dr->pinned = 1; |
9ac7849e | 2045 | } |
b7fe9434 | 2046 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 2047 | |
eca0d467 MG |
2048 | /* |
2049 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
2050 | * @dev: the PCI device being added | |
2051 | * | |
2052 | * Permits the platform to provide architecture specific functionality when | |
2053 | * devices are added. This is the default implementation. Architecture | |
2054 | * implementations can override this. | |
2055 | */ | |
3c78bc61 | 2056 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
2057 | { |
2058 | return 0; | |
2059 | } | |
2060 | ||
6ae32c53 | 2061 | /** |
74356add BH |
2062 | * pcibios_release_device - provide arch specific hooks when releasing |
2063 | * device dev | |
6ae32c53 SO |
2064 | * @dev: the PCI device being released |
2065 | * | |
2066 | * Permits the platform to provide architecture specific functionality when | |
2067 | * devices are released. This is the default implementation. Architecture | |
2068 | * implementations can override this. | |
2069 | */ | |
2070 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
2071 | ||
1da177e4 LT |
2072 | /** |
2073 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
2074 | * @dev: the PCI device to disable | |
2075 | * | |
2076 | * Disables architecture specific PCI resources for the device. This | |
2077 | * is the default implementation. Architecture implementations can | |
2078 | * override this. | |
2079 | */ | |
ff3ce480 | 2080 | void __weak pcibios_disable_device(struct pci_dev *dev) {} |
1da177e4 | 2081 | |
a43ae58c HG |
2082 | /** |
2083 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
2084 | * @irq: ISA IRQ to penalize | |
2085 | * @active: IRQ active or not | |
2086 | * | |
2087 | * Permits the platform to provide architecture-specific functionality when | |
2088 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
2089 | * implementations can override this. | |
2090 | */ | |
2091 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
2092 | ||
fa58d305 RW |
2093 | static void do_pci_disable_device(struct pci_dev *dev) |
2094 | { | |
2095 | u16 pci_command; | |
2096 | ||
2097 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
2098 | if (pci_command & PCI_COMMAND_MASTER) { | |
2099 | pci_command &= ~PCI_COMMAND_MASTER; | |
2100 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
2101 | } | |
2102 | ||
2103 | pcibios_disable_device(dev); | |
2104 | } | |
2105 | ||
2106 | /** | |
2107 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
2108 | * @dev: PCI device to disable | |
2109 | * | |
2110 | * NOTE: This function is a backend of PCI power management routines and is | |
2111 | * not supposed to be called drivers. | |
2112 | */ | |
2113 | void pci_disable_enabled_device(struct pci_dev *dev) | |
2114 | { | |
296ccb08 | 2115 | if (pci_is_enabled(dev)) |
fa58d305 RW |
2116 | do_pci_disable_device(dev); |
2117 | } | |
2118 | ||
1da177e4 LT |
2119 | /** |
2120 | * pci_disable_device - Disable PCI device after use | |
2121 | * @dev: PCI device to be disabled | |
2122 | * | |
2123 | * Signal to the system that the PCI device is not in use by the system | |
2124 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
2125 | * |
2126 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 2127 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 2128 | */ |
3c78bc61 | 2129 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 2130 | { |
9ac7849e | 2131 | struct pci_devres *dr; |
99dc804d | 2132 | |
9ac7849e TH |
2133 | dr = find_pci_dr(dev); |
2134 | if (dr) | |
7f375f32 | 2135 | dr->enabled = 0; |
9ac7849e | 2136 | |
fd6dceab KK |
2137 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
2138 | "disabling already-disabled device"); | |
2139 | ||
cc7ba39b | 2140 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
2141 | return; |
2142 | ||
fa58d305 | 2143 | do_pci_disable_device(dev); |
1da177e4 | 2144 | |
fa58d305 | 2145 | dev->is_busmaster = 0; |
1da177e4 | 2146 | } |
b7fe9434 | 2147 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 2148 | |
f7bdd12d BK |
2149 | /** |
2150 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 2151 | * @dev: the PCIe device reset |
f7bdd12d BK |
2152 | * @state: Reset state to enter into |
2153 | * | |
74356add | 2154 | * Set the PCIe reset state for the device. This is the default |
f7bdd12d BK |
2155 | * implementation. Architecture implementations can override this. |
2156 | */ | |
d6d88c83 BH |
2157 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
2158 | enum pcie_reset_state state) | |
f7bdd12d BK |
2159 | { |
2160 | return -EINVAL; | |
2161 | } | |
2162 | ||
2163 | /** | |
2164 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 2165 | * @dev: the PCIe device reset |
f7bdd12d BK |
2166 | * @state: Reset state to enter into |
2167 | * | |
f7bdd12d BK |
2168 | * Sets the PCI reset state for the device. |
2169 | */ | |
2170 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
2171 | { | |
2172 | return pcibios_set_pcie_reset_state(dev, state); | |
2173 | } | |
b7fe9434 | 2174 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 2175 | |
600a5b4f BH |
2176 | void pcie_clear_device_status(struct pci_dev *dev) |
2177 | { | |
2178 | u16 sta; | |
2179 | ||
2180 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta); | |
2181 | pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta); | |
2182 | } | |
2183 | ||
dcb0453d BH |
2184 | /** |
2185 | * pcie_clear_root_pme_status - Clear root port PME interrupt status. | |
2186 | * @dev: PCIe root port or event collector. | |
2187 | */ | |
2188 | void pcie_clear_root_pme_status(struct pci_dev *dev) | |
2189 | { | |
2190 | pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME); | |
2191 | } | |
2192 | ||
58ff4633 RW |
2193 | /** |
2194 | * pci_check_pme_status - Check if given device has generated PME. | |
2195 | * @dev: Device to check. | |
2196 | * | |
2197 | * Check the PME status of the device and if set, clear it and clear PME enable | |
2198 | * (if set). Return 'true' if PME status and PME enable were both set or | |
2199 | * 'false' otherwise. | |
2200 | */ | |
2201 | bool pci_check_pme_status(struct pci_dev *dev) | |
2202 | { | |
2203 | int pmcsr_pos; | |
2204 | u16 pmcsr; | |
2205 | bool ret = false; | |
2206 | ||
2207 | if (!dev->pm_cap) | |
2208 | return false; | |
2209 | ||
2210 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
2211 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
2212 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
2213 | return false; | |
2214 | ||
2215 | /* Clear PME status. */ | |
2216 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
2217 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
2218 | /* Disable PME to avoid interrupt flood. */ | |
2219 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2220 | ret = true; | |
2221 | } | |
2222 | ||
2223 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
2224 | ||
2225 | return ret; | |
2226 | } | |
2227 | ||
b67ea761 RW |
2228 | /** |
2229 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
2230 | * @dev: Device to handle. | |
379021d5 | 2231 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
2232 | * |
2233 | * Check if @dev has generated PME and queue a resume request for it in that | |
2234 | * case. | |
2235 | */ | |
379021d5 | 2236 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 2237 | { |
379021d5 RW |
2238 | if (pme_poll_reset && dev->pme_poll) |
2239 | dev->pme_poll = false; | |
2240 | ||
c125e96f | 2241 | if (pci_check_pme_status(dev)) { |
c125e96f | 2242 | pci_wakeup_event(dev); |
0f953bf6 | 2243 | pm_request_resume(&dev->dev); |
c125e96f | 2244 | } |
b67ea761 RW |
2245 | return 0; |
2246 | } | |
2247 | ||
2248 | /** | |
2249 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
2250 | * @bus: Top bus of the subtree to walk. | |
2251 | */ | |
2252 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
2253 | { | |
2254 | if (bus) | |
379021d5 | 2255 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
2256 | } |
2257 | ||
448bd857 | 2258 | |
eb9d0fe4 RW |
2259 | /** |
2260 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
2261 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
2262 | * @state: PCI state from which device will issue PME#. |
2263 | */ | |
e5899e1b | 2264 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 2265 | { |
337001b6 | 2266 | if (!dev->pm_cap) |
eb9d0fe4 RW |
2267 | return false; |
2268 | ||
337001b6 | 2269 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 2270 | } |
b7fe9434 | 2271 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 2272 | |
df17e62e MG |
2273 | static void pci_pme_list_scan(struct work_struct *work) |
2274 | { | |
379021d5 | 2275 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
2276 | |
2277 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
2278 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
2279 | if (pme_dev->dev->pme_poll) { | |
2280 | struct pci_dev *bridge; | |
2281 | ||
2282 | bridge = pme_dev->dev->bus->self; | |
2283 | /* | |
2284 | * If bridge is in low power state, the | |
2285 | * configuration space of subordinate devices | |
2286 | * may be not accessible | |
2287 | */ | |
2288 | if (bridge && bridge->current_state != PCI_D0) | |
2289 | continue; | |
000dd531 MW |
2290 | /* |
2291 | * If the device is in D3cold it should not be | |
2292 | * polled either. | |
2293 | */ | |
2294 | if (pme_dev->dev->current_state == PCI_D3cold) | |
2295 | continue; | |
2296 | ||
ce300008 BH |
2297 | pci_pme_wakeup(pme_dev->dev, NULL); |
2298 | } else { | |
2299 | list_del(&pme_dev->list); | |
2300 | kfree(pme_dev); | |
379021d5 | 2301 | } |
df17e62e | 2302 | } |
ce300008 | 2303 | if (!list_empty(&pci_pme_list)) |
ea00353f LW |
2304 | queue_delayed_work(system_freezable_wq, &pci_pme_work, |
2305 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2306 | mutex_unlock(&pci_pme_list_mutex); |
2307 | } | |
2308 | ||
2cef548a | 2309 | static void __pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
2310 | { |
2311 | u16 pmcsr; | |
2312 | ||
ffaddbe8 | 2313 | if (!dev->pme_support) |
eb9d0fe4 RW |
2314 | return; |
2315 | ||
337001b6 | 2316 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
2317 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
2318 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
2319 | if (!enable) | |
2320 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2321 | ||
337001b6 | 2322 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
2cef548a RW |
2323 | } |
2324 | ||
0ce3fcaf RW |
2325 | /** |
2326 | * pci_pme_restore - Restore PME configuration after config space restore. | |
2327 | * @dev: PCI device to update. | |
2328 | */ | |
2329 | void pci_pme_restore(struct pci_dev *dev) | |
dc15e71e RW |
2330 | { |
2331 | u16 pmcsr; | |
2332 | ||
2333 | if (!dev->pme_support) | |
2334 | return; | |
2335 | ||
2336 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
2337 | if (dev->wakeup_prepared) { | |
2338 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
0ce3fcaf | 2339 | pmcsr &= ~PCI_PM_CTRL_PME_STATUS; |
dc15e71e RW |
2340 | } else { |
2341 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2342 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
2343 | } | |
2344 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); | |
2345 | } | |
2346 | ||
2cef548a RW |
2347 | /** |
2348 | * pci_pme_active - enable or disable PCI device's PME# function | |
2349 | * @dev: PCI device to handle. | |
2350 | * @enable: 'true' to enable PME# generation; 'false' to disable it. | |
2351 | * | |
2352 | * The caller must verify that the device is capable of generating PME# before | |
2353 | * calling this function with @enable equal to 'true'. | |
2354 | */ | |
2355 | void pci_pme_active(struct pci_dev *dev, bool enable) | |
2356 | { | |
2357 | __pci_pme_active(dev, enable); | |
eb9d0fe4 | 2358 | |
6e965e0d HY |
2359 | /* |
2360 | * PCI (as opposed to PCIe) PME requires that the device have | |
2361 | * its PME# line hooked up correctly. Not all hardware vendors | |
2362 | * do this, so the PME never gets delivered and the device | |
2363 | * remains asleep. The easiest way around this is to | |
2364 | * periodically walk the list of suspended devices and check | |
2365 | * whether any have their PME flag set. The assumption is that | |
2366 | * we'll wake up often enough anyway that this won't be a huge | |
2367 | * hit, and the power savings from the devices will still be a | |
2368 | * win. | |
2369 | * | |
2370 | * Although PCIe uses in-band PME message instead of PME# line | |
2371 | * to report PME, PME does not work for some PCIe devices in | |
2372 | * reality. For example, there are devices that set their PME | |
2373 | * status bits, but don't really bother to send a PME message; | |
2374 | * there are PCI Express Root Ports that don't bother to | |
2375 | * trigger interrupts when they receive PME messages from the | |
2376 | * devices below. So PME poll is used for PCIe devices too. | |
2377 | */ | |
df17e62e | 2378 | |
379021d5 | 2379 | if (dev->pme_poll) { |
df17e62e MG |
2380 | struct pci_pme_device *pme_dev; |
2381 | if (enable) { | |
2382 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
2383 | GFP_KERNEL); | |
0394cb19 | 2384 | if (!pme_dev) { |
7506dc79 | 2385 | pci_warn(dev, "can't enable PME#\n"); |
0394cb19 BH |
2386 | return; |
2387 | } | |
df17e62e MG |
2388 | pme_dev->dev = dev; |
2389 | mutex_lock(&pci_pme_list_mutex); | |
2390 | list_add(&pme_dev->list, &pci_pme_list); | |
2391 | if (list_is_singular(&pci_pme_list)) | |
ea00353f LW |
2392 | queue_delayed_work(system_freezable_wq, |
2393 | &pci_pme_work, | |
2394 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2395 | mutex_unlock(&pci_pme_list_mutex); |
2396 | } else { | |
2397 | mutex_lock(&pci_pme_list_mutex); | |
2398 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
2399 | if (pme_dev->dev == dev) { | |
2400 | list_del(&pme_dev->list); | |
2401 | kfree(pme_dev); | |
2402 | break; | |
2403 | } | |
2404 | } | |
2405 | mutex_unlock(&pci_pme_list_mutex); | |
2406 | } | |
2407 | } | |
2408 | ||
7506dc79 | 2409 | pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 2410 | } |
b7fe9434 | 2411 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 2412 | |
1da177e4 | 2413 | /** |
cfcadfaa | 2414 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
2415 | * @dev: PCI device affected |
2416 | * @state: PCI state from which device will issue wakeup events | |
2417 | * @enable: True to enable event generation; false to disable | |
2418 | * | |
2419 | * This enables the device as a wakeup event source, or disables it. | |
2420 | * When such events involves platform-specific hooks, those hooks are | |
2421 | * called automatically by this routine. | |
2422 | * | |
2423 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 2424 | * always require such platform hooks. |
075c1771 | 2425 | * |
eb9d0fe4 RW |
2426 | * RETURN VALUE: |
2427 | * 0 is returned on success | |
2428 | * -EINVAL is returned if device is not supposed to wake up the system | |
2429 | * Error code depending on the platform is returned if both the platform and | |
2430 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 2431 | */ |
cfcadfaa | 2432 | static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) |
1da177e4 | 2433 | { |
5bcc2fb4 | 2434 | int ret = 0; |
075c1771 | 2435 | |
baecc470 | 2436 | /* |
ac86e8ee MW |
2437 | * Bridges that are not power-manageable directly only signal |
2438 | * wakeup on behalf of subordinate devices which is set up | |
2439 | * elsewhere, so skip them. However, bridges that are | |
2440 | * power-manageable may signal wakeup for themselves (for example, | |
2441 | * on a hotplug event) and they need to be covered here. | |
baecc470 | 2442 | */ |
ac86e8ee | 2443 | if (!pci_power_manageable(dev)) |
baecc470 RW |
2444 | return 0; |
2445 | ||
0ce3fcaf RW |
2446 | /* Don't do the same thing twice in a row for one device. */ |
2447 | if (!!enable == !!dev->wakeup_prepared) | |
e80bb09d RW |
2448 | return 0; |
2449 | ||
eb9d0fe4 RW |
2450 | /* |
2451 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
2452 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
2453 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 2454 | */ |
1da177e4 | 2455 | |
5bcc2fb4 RW |
2456 | if (enable) { |
2457 | int error; | |
1da177e4 | 2458 | |
5bcc2fb4 RW |
2459 | if (pci_pme_capable(dev, state)) |
2460 | pci_pme_active(dev, true); | |
2461 | else | |
2462 | ret = 1; | |
0847684c | 2463 | error = platform_pci_set_wakeup(dev, true); |
5bcc2fb4 RW |
2464 | if (ret) |
2465 | ret = error; | |
e80bb09d RW |
2466 | if (!ret) |
2467 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 2468 | } else { |
0847684c | 2469 | platform_pci_set_wakeup(dev, false); |
5bcc2fb4 | 2470 | pci_pme_active(dev, false); |
e80bb09d | 2471 | dev->wakeup_prepared = false; |
5bcc2fb4 | 2472 | } |
1da177e4 | 2473 | |
5bcc2fb4 | 2474 | return ret; |
eb9d0fe4 | 2475 | } |
cfcadfaa RW |
2476 | |
2477 | /** | |
2478 | * pci_enable_wake - change wakeup settings for a PCI device | |
2479 | * @pci_dev: Target device | |
2480 | * @state: PCI state from which device will issue wakeup events | |
2481 | * @enable: Whether or not to enable event generation | |
2482 | * | |
2483 | * If @enable is set, check device_may_wakeup() for the device before calling | |
2484 | * __pci_enable_wake() for it. | |
2485 | */ | |
2486 | int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable) | |
2487 | { | |
2488 | if (enable && !device_may_wakeup(&pci_dev->dev)) | |
2489 | return -EINVAL; | |
2490 | ||
2491 | return __pci_enable_wake(pci_dev, state, enable); | |
2492 | } | |
0847684c | 2493 | EXPORT_SYMBOL(pci_enable_wake); |
1da177e4 | 2494 | |
0235c4fc RW |
2495 | /** |
2496 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
2497 | * @dev: PCI device to prepare | |
2498 | * @enable: True to enable wake-up event generation; false to disable | |
2499 | * | |
2500 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
2501 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
2502 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
2503 | * ordering constraints. | |
2504 | * | |
cfcadfaa RW |
2505 | * This function only returns error code if the device is not allowed to wake |
2506 | * up the system from sleep or it is not capable of generating PME# from both | |
2507 | * D3_hot and D3_cold and the platform is unable to enable wake-up power for it. | |
0235c4fc RW |
2508 | */ |
2509 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
2510 | { | |
2511 | return pci_pme_capable(dev, PCI_D3cold) ? | |
2512 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
2513 | pci_enable_wake(dev, PCI_D3hot, enable); | |
2514 | } | |
b7fe9434 | 2515 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 2516 | |
404cc2d8 | 2517 | /** |
37139074 JB |
2518 | * pci_target_state - find an appropriate low power state for a given PCI dev |
2519 | * @dev: PCI device | |
666ff6f8 | 2520 | * @wakeup: Whether or not wakeup functionality will be enabled for the device. |
37139074 JB |
2521 | * |
2522 | * Use underlying platform code to find a supported low power state for @dev. | |
2523 | * If the platform can't manage @dev, return the deepest state from which it | |
2524 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 2525 | */ |
666ff6f8 | 2526 | static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup) |
404cc2d8 RW |
2527 | { |
2528 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
2529 | |
2530 | if (platform_pci_power_manageable(dev)) { | |
2531 | /* | |
60ee031a | 2532 | * Call the platform to find the target state for the device. |
404cc2d8 RW |
2533 | */ |
2534 | pci_power_t state = platform_pci_choose_state(dev); | |
2535 | ||
2536 | switch (state) { | |
2537 | case PCI_POWER_ERROR: | |
2538 | case PCI_UNKNOWN: | |
2539 | break; | |
2540 | case PCI_D1: | |
2541 | case PCI_D2: | |
2542 | if (pci_no_d1d2(dev)) | |
2543 | break; | |
df561f66 | 2544 | fallthrough; |
404cc2d8 RW |
2545 | default: |
2546 | target_state = state; | |
404cc2d8 | 2547 | } |
4132a577 LW |
2548 | |
2549 | return target_state; | |
2550 | } | |
2551 | ||
2552 | if (!dev->pm_cap) | |
d2abdf62 | 2553 | target_state = PCI_D0; |
4132a577 LW |
2554 | |
2555 | /* | |
2556 | * If the device is in D3cold even though it's not power-manageable by | |
2557 | * the platform, it may have been powered down by non-standard means. | |
2558 | * Best to let it slumber. | |
2559 | */ | |
2560 | if (dev->current_state == PCI_D3cold) | |
2561 | target_state = PCI_D3cold; | |
2562 | ||
666ff6f8 | 2563 | if (wakeup) { |
404cc2d8 RW |
2564 | /* |
2565 | * Find the deepest state from which the device can generate | |
60ee031a | 2566 | * PME#. |
404cc2d8 | 2567 | */ |
337001b6 RW |
2568 | if (dev->pme_support) { |
2569 | while (target_state | |
2570 | && !(dev->pme_support & (1 << target_state))) | |
2571 | target_state--; | |
404cc2d8 RW |
2572 | } |
2573 | } | |
2574 | ||
e5899e1b RW |
2575 | return target_state; |
2576 | } | |
2577 | ||
2578 | /** | |
74356add BH |
2579 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition |
2580 | * into a sleep state | |
e5899e1b RW |
2581 | * @dev: Device to handle. |
2582 | * | |
2583 | * Choose the power state appropriate for the device depending on whether | |
2584 | * it can wake up the system and/or is power manageable by the platform | |
2585 | * (PCI_D3hot is the default) and put the device into that state. | |
2586 | */ | |
2587 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
2588 | { | |
666ff6f8 RW |
2589 | bool wakeup = device_may_wakeup(&dev->dev); |
2590 | pci_power_t target_state = pci_target_state(dev, wakeup); | |
e5899e1b RW |
2591 | int error; |
2592 | ||
2593 | if (target_state == PCI_POWER_ERROR) | |
2594 | return -EIO; | |
2595 | ||
666ff6f8 | 2596 | pci_enable_wake(dev, target_state, wakeup); |
c157dfa3 | 2597 | |
404cc2d8 RW |
2598 | error = pci_set_power_state(dev, target_state); |
2599 | ||
2600 | if (error) | |
2601 | pci_enable_wake(dev, target_state, false); | |
2602 | ||
2603 | return error; | |
2604 | } | |
b7fe9434 | 2605 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
2606 | |
2607 | /** | |
74356add BH |
2608 | * pci_back_from_sleep - turn PCI device on during system-wide transition |
2609 | * into working state | |
404cc2d8 RW |
2610 | * @dev: Device to handle. |
2611 | * | |
88393161 | 2612 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
2613 | */ |
2614 | int pci_back_from_sleep(struct pci_dev *dev) | |
2615 | { | |
2616 | pci_enable_wake(dev, PCI_D0, false); | |
2617 | return pci_set_power_state(dev, PCI_D0); | |
2618 | } | |
b7fe9434 | 2619 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 2620 | |
6cbf8214 RW |
2621 | /** |
2622 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
2623 | * @dev: PCI device being suspended. | |
2624 | * | |
2625 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
2626 | * power state. | |
2627 | */ | |
2628 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
2629 | { | |
666ff6f8 | 2630 | pci_power_t target_state; |
6cbf8214 RW |
2631 | int error; |
2632 | ||
666ff6f8 | 2633 | target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); |
6cbf8214 RW |
2634 | if (target_state == PCI_POWER_ERROR) |
2635 | return -EIO; | |
2636 | ||
448bd857 HY |
2637 | dev->runtime_d3cold = target_state == PCI_D3cold; |
2638 | ||
cfcadfaa | 2639 | __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev)); |
6cbf8214 RW |
2640 | |
2641 | error = pci_set_power_state(dev, target_state); | |
2642 | ||
448bd857 | 2643 | if (error) { |
0847684c | 2644 | pci_enable_wake(dev, target_state, false); |
448bd857 HY |
2645 | dev->runtime_d3cold = false; |
2646 | } | |
6cbf8214 RW |
2647 | |
2648 | return error; | |
2649 | } | |
2650 | ||
b67ea761 RW |
2651 | /** |
2652 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
2653 | * @dev: Device to check. | |
2654 | * | |
f7625980 | 2655 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
2656 | * (through the platform or using the native PCIe PME) or if the device supports |
2657 | * PME and one of its upstream bridges can generate wake-up events. | |
2658 | */ | |
2659 | bool pci_dev_run_wake(struct pci_dev *dev) | |
2660 | { | |
2661 | struct pci_bus *bus = dev->bus; | |
2662 | ||
b67ea761 RW |
2663 | if (!dev->pme_support) |
2664 | return false; | |
2665 | ||
666ff6f8 | 2666 | /* PME-capable in principle, but not from the target power state */ |
8feaec33 | 2667 | if (!pci_pme_capable(dev, pci_target_state(dev, true))) |
6496ebd7 AS |
2668 | return false; |
2669 | ||
8feaec33 KHF |
2670 | if (device_can_wakeup(&dev->dev)) |
2671 | return true; | |
2672 | ||
b67ea761 RW |
2673 | while (bus->parent) { |
2674 | struct pci_dev *bridge = bus->self; | |
2675 | ||
de3ef1eb | 2676 | if (device_can_wakeup(&bridge->dev)) |
b67ea761 RW |
2677 | return true; |
2678 | ||
2679 | bus = bus->parent; | |
2680 | } | |
2681 | ||
2682 | /* We have reached the root bus. */ | |
2683 | if (bus->bridge) | |
de3ef1eb | 2684 | return device_can_wakeup(bus->bridge); |
b67ea761 RW |
2685 | |
2686 | return false; | |
2687 | } | |
2688 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2689 | ||
bac2a909 | 2690 | /** |
0c7376ad | 2691 | * pci_dev_need_resume - Check if it is necessary to resume the device. |
bac2a909 RW |
2692 | * @pci_dev: Device to check. |
2693 | * | |
0c7376ad | 2694 | * Return 'true' if the device is not runtime-suspended or it has to be |
bac2a909 | 2695 | * reconfigured due to wakeup settings difference between system and runtime |
0c7376ad RW |
2696 | * suspend, or the current power state of it is not suitable for the upcoming |
2697 | * (system-wide) transition. | |
bac2a909 | 2698 | */ |
0c7376ad | 2699 | bool pci_dev_need_resume(struct pci_dev *pci_dev) |
bac2a909 RW |
2700 | { |
2701 | struct device *dev = &pci_dev->dev; | |
234f223d RW |
2702 | pci_power_t target_state; |
2703 | ||
2704 | if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev)) | |
0c7376ad | 2705 | return true; |
bac2a909 | 2706 | |
0c7376ad | 2707 | target_state = pci_target_state(pci_dev, device_may_wakeup(dev)); |
234f223d RW |
2708 | |
2709 | /* | |
2710 | * If the earlier platform check has not triggered, D3cold is just power | |
2711 | * removal on top of D3hot, so no need to resume the device in that | |
2712 | * case. | |
2713 | */ | |
0c7376ad RW |
2714 | return target_state != pci_dev->current_state && |
2715 | target_state != PCI_D3cold && | |
2716 | pci_dev->current_state != PCI_D3hot; | |
2717 | } | |
2718 | ||
2719 | /** | |
2720 | * pci_dev_adjust_pme - Adjust PME setting for a suspended device. | |
2721 | * @pci_dev: Device to check. | |
2722 | * | |
2723 | * If the device is suspended and it is not configured for system wakeup, | |
2724 | * disable PME for it to prevent it from waking up the system unnecessarily. | |
2725 | * | |
2726 | * Note that if the device's power state is D3cold and the platform check in | |
2727 | * pci_dev_need_resume() has not triggered, the device's configuration need not | |
2728 | * be changed. | |
2729 | */ | |
2730 | void pci_dev_adjust_pme(struct pci_dev *pci_dev) | |
2731 | { | |
2732 | struct device *dev = &pci_dev->dev; | |
bac2a909 | 2733 | |
2cef548a RW |
2734 | spin_lock_irq(&dev->power.lock); |
2735 | ||
0c7376ad RW |
2736 | if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) && |
2737 | pci_dev->current_state < PCI_D3cold) | |
2cef548a RW |
2738 | __pci_pme_active(pci_dev, false); |
2739 | ||
2740 | spin_unlock_irq(&dev->power.lock); | |
2cef548a RW |
2741 | } |
2742 | ||
2743 | /** | |
2744 | * pci_dev_complete_resume - Finalize resume from system sleep for a device. | |
2745 | * @pci_dev: Device to handle. | |
2746 | * | |
2747 | * If the device is runtime suspended and wakeup-capable, enable PME for it as | |
2748 | * it might have been disabled during the prepare phase of system suspend if | |
2749 | * the device was not configured for system wakeup. | |
2750 | */ | |
2751 | void pci_dev_complete_resume(struct pci_dev *pci_dev) | |
2752 | { | |
2753 | struct device *dev = &pci_dev->dev; | |
2754 | ||
2755 | if (!pci_dev_run_wake(pci_dev)) | |
2756 | return; | |
2757 | ||
2758 | spin_lock_irq(&dev->power.lock); | |
2759 | ||
2760 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) | |
2761 | __pci_pme_active(pci_dev, true); | |
2762 | ||
2763 | spin_unlock_irq(&dev->power.lock); | |
bac2a909 RW |
2764 | } |
2765 | ||
b3c32c4f HY |
2766 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2767 | { | |
2768 | struct device *dev = &pdev->dev; | |
2769 | struct device *parent = dev->parent; | |
2770 | ||
2771 | if (parent) | |
2772 | pm_runtime_get_sync(parent); | |
2773 | pm_runtime_get_noresume(dev); | |
2774 | /* | |
2775 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2776 | * so wait until suspending completes | |
2777 | */ | |
2778 | pm_runtime_barrier(dev); | |
2779 | /* | |
2780 | * Only need to resume devices in D3cold, because config | |
2781 | * registers are still accessible for devices suspended but | |
2782 | * not in D3cold. | |
2783 | */ | |
2784 | if (pdev->current_state == PCI_D3cold) | |
2785 | pm_runtime_resume(dev); | |
2786 | } | |
2787 | ||
2788 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2789 | { | |
2790 | struct device *dev = &pdev->dev; | |
2791 | struct device *parent = dev->parent; | |
2792 | ||
2793 | pm_runtime_put(dev); | |
2794 | if (parent) | |
2795 | pm_runtime_put_sync(parent); | |
2796 | } | |
2797 | ||
85b0cae8 MW |
2798 | static const struct dmi_system_id bridge_d3_blacklist[] = { |
2799 | #ifdef CONFIG_X86 | |
2800 | { | |
2801 | /* | |
2802 | * Gigabyte X299 root port is not marked as hotplug capable | |
2803 | * which allows Linux to power manage it. However, this | |
2804 | * confuses the BIOS SMI handler so don't power manage root | |
2805 | * ports on that system. | |
2806 | */ | |
2807 | .ident = "X299 DESIGNARE EX-CF", | |
2808 | .matches = { | |
2809 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
2810 | DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"), | |
2811 | }, | |
2812 | }, | |
2813 | #endif | |
2814 | { } | |
2815 | }; | |
2816 | ||
9d26d3a8 MW |
2817 | /** |
2818 | * pci_bridge_d3_possible - Is it possible to put the bridge into D3 | |
2819 | * @bridge: Bridge to check | |
2820 | * | |
2821 | * This function checks if it is possible to move the bridge to D3. | |
47a8e237 | 2822 | * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt. |
9d26d3a8 | 2823 | */ |
c6a63307 | 2824 | bool pci_bridge_d3_possible(struct pci_dev *bridge) |
9d26d3a8 | 2825 | { |
9d26d3a8 MW |
2826 | if (!pci_is_pcie(bridge)) |
2827 | return false; | |
2828 | ||
2829 | switch (pci_pcie_type(bridge)) { | |
2830 | case PCI_EXP_TYPE_ROOT_PORT: | |
2831 | case PCI_EXP_TYPE_UPSTREAM: | |
2832 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2833 | if (pci_bridge_d3_disable) | |
2834 | return false; | |
97a90aee LW |
2835 | |
2836 | /* | |
eb3b5bf1 | 2837 | * Hotplug ports handled by firmware in System Management Mode |
97a90aee | 2838 | * may not be put into D3 by the OS (Thunderbolt on non-Macs). |
97a90aee | 2839 | */ |
eb3b5bf1 | 2840 | if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) |
97a90aee LW |
2841 | return false; |
2842 | ||
9d26d3a8 MW |
2843 | if (pci_bridge_d3_force) |
2844 | return true; | |
2845 | ||
47a8e237 LW |
2846 | /* Even the oldest 2010 Thunderbolt controller supports D3. */ |
2847 | if (bridge->is_thunderbolt) | |
2848 | return true; | |
2849 | ||
26ad34d5 MW |
2850 | /* Platform might know better if the bridge supports D3 */ |
2851 | if (platform_pci_bridge_d3(bridge)) | |
2852 | return true; | |
2853 | ||
eb3b5bf1 LW |
2854 | /* |
2855 | * Hotplug ports handled natively by the OS were not validated | |
2856 | * by vendors for runtime D3 at least until 2018 because there | |
2857 | * was no OS support. | |
2858 | */ | |
2859 | if (bridge->is_hotplug_bridge) | |
2860 | return false; | |
2861 | ||
85b0cae8 MW |
2862 | if (dmi_check_system(bridge_d3_blacklist)) |
2863 | return false; | |
2864 | ||
9d26d3a8 MW |
2865 | /* |
2866 | * It should be safe to put PCIe ports from 2015 or newer | |
2867 | * to D3. | |
2868 | */ | |
ac95090a | 2869 | if (dmi_get_bios_year() >= 2015) |
9d26d3a8 | 2870 | return true; |
9d26d3a8 MW |
2871 | break; |
2872 | } | |
2873 | ||
2874 | return false; | |
2875 | } | |
2876 | ||
2877 | static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) | |
2878 | { | |
2879 | bool *d3cold_ok = data; | |
9d26d3a8 | 2880 | |
718a0609 LW |
2881 | if (/* The device needs to be allowed to go D3cold ... */ |
2882 | dev->no_d3cold || !dev->d3cold_allowed || | |
2883 | ||
2884 | /* ... and if it is wakeup capable to do so from D3cold. */ | |
2885 | (device_may_wakeup(&dev->dev) && | |
2886 | !pci_pme_capable(dev, PCI_D3cold)) || | |
2887 | ||
2888 | /* If it is a bridge it must be allowed to go to D3. */ | |
d98e0929 | 2889 | !pci_power_manageable(dev)) |
9d26d3a8 | 2890 | |
718a0609 | 2891 | *d3cold_ok = false; |
9d26d3a8 | 2892 | |
718a0609 | 2893 | return !*d3cold_ok; |
9d26d3a8 MW |
2894 | } |
2895 | ||
2896 | /* | |
2897 | * pci_bridge_d3_update - Update bridge D3 capabilities | |
2898 | * @dev: PCI device which is changed | |
9d26d3a8 MW |
2899 | * |
2900 | * Update upstream bridge PM capabilities accordingly depending on if the | |
2901 | * device PM configuration was changed or the device is being removed. The | |
2902 | * change is also propagated upstream. | |
2903 | */ | |
1ed276a7 | 2904 | void pci_bridge_d3_update(struct pci_dev *dev) |
9d26d3a8 | 2905 | { |
1ed276a7 | 2906 | bool remove = !device_is_registered(&dev->dev); |
9d26d3a8 MW |
2907 | struct pci_dev *bridge; |
2908 | bool d3cold_ok = true; | |
2909 | ||
2910 | bridge = pci_upstream_bridge(dev); | |
2911 | if (!bridge || !pci_bridge_d3_possible(bridge)) | |
2912 | return; | |
2913 | ||
9d26d3a8 | 2914 | /* |
e8559b71 LW |
2915 | * If D3 is currently allowed for the bridge, removing one of its |
2916 | * children won't change that. | |
2917 | */ | |
2918 | if (remove && bridge->bridge_d3) | |
2919 | return; | |
2920 | ||
2921 | /* | |
2922 | * If D3 is currently allowed for the bridge and a child is added or | |
2923 | * changed, disallowance of D3 can only be caused by that child, so | |
2924 | * we only need to check that single device, not any of its siblings. | |
2925 | * | |
2926 | * If D3 is currently not allowed for the bridge, checking the device | |
2927 | * first may allow us to skip checking its siblings. | |
9d26d3a8 MW |
2928 | */ |
2929 | if (!remove) | |
2930 | pci_dev_check_d3cold(dev, &d3cold_ok); | |
2931 | ||
e8559b71 LW |
2932 | /* |
2933 | * If D3 is currently not allowed for the bridge, this may be caused | |
2934 | * either by the device being changed/removed or any of its siblings, | |
2935 | * so we need to go through all children to find out if one of them | |
2936 | * continues to block D3. | |
2937 | */ | |
2938 | if (d3cold_ok && !bridge->bridge_d3) | |
9d26d3a8 MW |
2939 | pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, |
2940 | &d3cold_ok); | |
9d26d3a8 MW |
2941 | |
2942 | if (bridge->bridge_d3 != d3cold_ok) { | |
2943 | bridge->bridge_d3 = d3cold_ok; | |
2944 | /* Propagate change to upstream bridges */ | |
1ed276a7 | 2945 | pci_bridge_d3_update(bridge); |
9d26d3a8 | 2946 | } |
9d26d3a8 MW |
2947 | } |
2948 | ||
9d26d3a8 MW |
2949 | /** |
2950 | * pci_d3cold_enable - Enable D3cold for device | |
2951 | * @dev: PCI device to handle | |
2952 | * | |
2953 | * This function can be used in drivers to enable D3cold from the device | |
2954 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2955 | * accordingly. | |
2956 | */ | |
2957 | void pci_d3cold_enable(struct pci_dev *dev) | |
2958 | { | |
2959 | if (dev->no_d3cold) { | |
2960 | dev->no_d3cold = false; | |
1ed276a7 | 2961 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2962 | } |
2963 | } | |
2964 | EXPORT_SYMBOL_GPL(pci_d3cold_enable); | |
2965 | ||
2966 | /** | |
2967 | * pci_d3cold_disable - Disable D3cold for device | |
2968 | * @dev: PCI device to handle | |
2969 | * | |
2970 | * This function can be used in drivers to disable D3cold from the device | |
2971 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2972 | * accordingly. | |
2973 | */ | |
2974 | void pci_d3cold_disable(struct pci_dev *dev) | |
2975 | { | |
2976 | if (!dev->no_d3cold) { | |
2977 | dev->no_d3cold = true; | |
1ed276a7 | 2978 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2979 | } |
2980 | } | |
2981 | EXPORT_SYMBOL_GPL(pci_d3cold_disable); | |
2982 | ||
eb9d0fe4 RW |
2983 | /** |
2984 | * pci_pm_init - Initialize PM functions of given PCI device | |
2985 | * @dev: PCI device to handle. | |
2986 | */ | |
2987 | void pci_pm_init(struct pci_dev *dev) | |
2988 | { | |
2989 | int pm; | |
d6112f8d | 2990 | u16 status; |
eb9d0fe4 | 2991 | u16 pmc; |
1da177e4 | 2992 | |
bb910a70 | 2993 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2994 | pm_runtime_set_active(&dev->dev); |
2995 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2996 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2997 | dev->wakeup_prepared = false; |
bb910a70 | 2998 | |
337001b6 | 2999 | dev->pm_cap = 0; |
ffaddbe8 | 3000 | dev->pme_support = 0; |
337001b6 | 3001 | |
eb9d0fe4 RW |
3002 | /* find PCI PM capability in list */ |
3003 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
3004 | if (!pm) | |
50246dd4 | 3005 | return; |
eb9d0fe4 RW |
3006 | /* Check device's ability to generate PME# */ |
3007 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 3008 | |
eb9d0fe4 | 3009 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
7506dc79 | 3010 | pci_err(dev, "unsupported PM cap regs version (%u)\n", |
eb9d0fe4 | 3011 | pmc & PCI_PM_CAP_VER_MASK); |
50246dd4 | 3012 | return; |
eb9d0fe4 RW |
3013 | } |
3014 | ||
337001b6 | 3015 | dev->pm_cap = pm; |
1ae861e6 | 3016 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 3017 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
9d26d3a8 | 3018 | dev->bridge_d3 = pci_bridge_d3_possible(dev); |
4f9c1397 | 3019 | dev->d3cold_allowed = true; |
337001b6 RW |
3020 | |
3021 | dev->d1_support = false; | |
3022 | dev->d2_support = false; | |
3023 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 3024 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 3025 | dev->d1_support = true; |
c9ed77ee | 3026 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 3027 | dev->d2_support = true; |
c9ed77ee BH |
3028 | |
3029 | if (dev->d1_support || dev->d2_support) | |
34c6b710 | 3030 | pci_info(dev, "supports%s%s\n", |
ec84f126 JB |
3031 | dev->d1_support ? " D1" : "", |
3032 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
3033 | } |
3034 | ||
3035 | pmc &= PCI_PM_CAP_PME_MASK; | |
3036 | if (pmc) { | |
34c6b710 | 3037 | pci_info(dev, "PME# supported from%s%s%s%s%s\n", |
c9ed77ee BH |
3038 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
3039 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
3040 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
3041 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
3042 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 3043 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 3044 | dev->pme_poll = true; |
eb9d0fe4 RW |
3045 | /* |
3046 | * Make device's PM flags reflect the wake-up capability, but | |
3047 | * let the user space enable it to wake up the system as needed. | |
3048 | */ | |
3049 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 3050 | /* Disable the PME# generation functionality */ |
337001b6 | 3051 | pci_pme_active(dev, false); |
eb9d0fe4 | 3052 | } |
d6112f8d FB |
3053 | |
3054 | pci_read_config_word(dev, PCI_STATUS, &status); | |
3055 | if (status & PCI_STATUS_IMM_READY) | |
3056 | dev->imm_ready = 1; | |
1da177e4 LT |
3057 | } |
3058 | ||
938174e5 SS |
3059 | static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) |
3060 | { | |
92efb1bd | 3061 | unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; |
938174e5 SS |
3062 | |
3063 | switch (prop) { | |
3064 | case PCI_EA_P_MEM: | |
3065 | case PCI_EA_P_VF_MEM: | |
3066 | flags |= IORESOURCE_MEM; | |
3067 | break; | |
3068 | case PCI_EA_P_MEM_PREFETCH: | |
3069 | case PCI_EA_P_VF_MEM_PREFETCH: | |
3070 | flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
3071 | break; | |
3072 | case PCI_EA_P_IO: | |
3073 | flags |= IORESOURCE_IO; | |
3074 | break; | |
3075 | default: | |
3076 | return 0; | |
3077 | } | |
3078 | ||
3079 | return flags; | |
3080 | } | |
3081 | ||
3082 | static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, | |
3083 | u8 prop) | |
3084 | { | |
3085 | if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) | |
3086 | return &dev->resource[bei]; | |
11183991 DD |
3087 | #ifdef CONFIG_PCI_IOV |
3088 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && | |
3089 | (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) | |
3090 | return &dev->resource[PCI_IOV_RESOURCES + | |
3091 | bei - PCI_EA_BEI_VF_BAR0]; | |
3092 | #endif | |
938174e5 SS |
3093 | else if (bei == PCI_EA_BEI_ROM) |
3094 | return &dev->resource[PCI_ROM_RESOURCE]; | |
3095 | else | |
3096 | return NULL; | |
3097 | } | |
3098 | ||
3099 | /* Read an Enhanced Allocation (EA) entry */ | |
3100 | static int pci_ea_read(struct pci_dev *dev, int offset) | |
3101 | { | |
3102 | struct resource *res; | |
3103 | int ent_size, ent_offset = offset; | |
3104 | resource_size_t start, end; | |
3105 | unsigned long flags; | |
26635112 | 3106 | u32 dw0, bei, base, max_offset; |
938174e5 SS |
3107 | u8 prop; |
3108 | bool support_64 = (sizeof(resource_size_t) >= 8); | |
3109 | ||
3110 | pci_read_config_dword(dev, ent_offset, &dw0); | |
3111 | ent_offset += 4; | |
3112 | ||
3113 | /* Entry size field indicates DWORDs after 1st */ | |
3114 | ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; | |
3115 | ||
3116 | if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ | |
3117 | goto out; | |
3118 | ||
26635112 BH |
3119 | bei = (dw0 & PCI_EA_BEI) >> 4; |
3120 | prop = (dw0 & PCI_EA_PP) >> 8; | |
3121 | ||
938174e5 SS |
3122 | /* |
3123 | * If the Property is in the reserved range, try the Secondary | |
3124 | * Property instead. | |
3125 | */ | |
3126 | if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) | |
26635112 | 3127 | prop = (dw0 & PCI_EA_SP) >> 16; |
938174e5 SS |
3128 | if (prop > PCI_EA_P_BRIDGE_IO) |
3129 | goto out; | |
3130 | ||
26635112 | 3131 | res = pci_ea_get_resource(dev, bei, prop); |
938174e5 | 3132 | if (!res) { |
7506dc79 | 3133 | pci_err(dev, "Unsupported EA entry BEI: %u\n", bei); |
938174e5 SS |
3134 | goto out; |
3135 | } | |
3136 | ||
3137 | flags = pci_ea_flags(dev, prop); | |
3138 | if (!flags) { | |
7506dc79 | 3139 | pci_err(dev, "Unsupported EA properties: %#x\n", prop); |
938174e5 SS |
3140 | goto out; |
3141 | } | |
3142 | ||
3143 | /* Read Base */ | |
3144 | pci_read_config_dword(dev, ent_offset, &base); | |
3145 | start = (base & PCI_EA_FIELD_MASK); | |
3146 | ent_offset += 4; | |
3147 | ||
3148 | /* Read MaxOffset */ | |
3149 | pci_read_config_dword(dev, ent_offset, &max_offset); | |
3150 | ent_offset += 4; | |
3151 | ||
3152 | /* Read Base MSBs (if 64-bit entry) */ | |
3153 | if (base & PCI_EA_IS_64) { | |
3154 | u32 base_upper; | |
3155 | ||
3156 | pci_read_config_dword(dev, ent_offset, &base_upper); | |
3157 | ent_offset += 4; | |
3158 | ||
3159 | flags |= IORESOURCE_MEM_64; | |
3160 | ||
3161 | /* entry starts above 32-bit boundary, can't use */ | |
3162 | if (!support_64 && base_upper) | |
3163 | goto out; | |
3164 | ||
3165 | if (support_64) | |
3166 | start |= ((u64)base_upper << 32); | |
3167 | } | |
3168 | ||
3169 | end = start + (max_offset | 0x03); | |
3170 | ||
3171 | /* Read MaxOffset MSBs (if 64-bit entry) */ | |
3172 | if (max_offset & PCI_EA_IS_64) { | |
3173 | u32 max_offset_upper; | |
3174 | ||
3175 | pci_read_config_dword(dev, ent_offset, &max_offset_upper); | |
3176 | ent_offset += 4; | |
3177 | ||
3178 | flags |= IORESOURCE_MEM_64; | |
3179 | ||
3180 | /* entry too big, can't use */ | |
3181 | if (!support_64 && max_offset_upper) | |
3182 | goto out; | |
3183 | ||
3184 | if (support_64) | |
3185 | end += ((u64)max_offset_upper << 32); | |
3186 | } | |
3187 | ||
3188 | if (end < start) { | |
7506dc79 | 3189 | pci_err(dev, "EA Entry crosses address boundary\n"); |
938174e5 SS |
3190 | goto out; |
3191 | } | |
3192 | ||
3193 | if (ent_size != ent_offset - offset) { | |
7506dc79 | 3194 | pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n", |
938174e5 SS |
3195 | ent_size, ent_offset - offset); |
3196 | goto out; | |
3197 | } | |
3198 | ||
3199 | res->name = pci_name(dev); | |
3200 | res->start = start; | |
3201 | res->end = end; | |
3202 | res->flags = flags; | |
597becb4 BH |
3203 | |
3204 | if (bei <= PCI_EA_BEI_BAR5) | |
34c6b710 | 3205 | pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3206 | bei, res, prop); |
3207 | else if (bei == PCI_EA_BEI_ROM) | |
34c6b710 | 3208 | pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3209 | res, prop); |
3210 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) | |
34c6b710 | 3211 | pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3212 | bei - PCI_EA_BEI_VF_BAR0, res, prop); |
3213 | else | |
34c6b710 | 3214 | pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3215 | bei, res, prop); |
3216 | ||
938174e5 SS |
3217 | out: |
3218 | return offset + ent_size; | |
3219 | } | |
3220 | ||
dcbb408a | 3221 | /* Enhanced Allocation Initialization */ |
938174e5 SS |
3222 | void pci_ea_init(struct pci_dev *dev) |
3223 | { | |
3224 | int ea; | |
3225 | u8 num_ent; | |
3226 | int offset; | |
3227 | int i; | |
3228 | ||
3229 | /* find PCI EA capability in list */ | |
3230 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
3231 | if (!ea) | |
3232 | return; | |
3233 | ||
3234 | /* determine the number of entries */ | |
3235 | pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, | |
3236 | &num_ent); | |
3237 | num_ent &= PCI_EA_NUM_ENT_MASK; | |
3238 | ||
3239 | offset = ea + PCI_EA_FIRST_ENT; | |
3240 | ||
3241 | /* Skip DWORD 2 for type 1 functions */ | |
3242 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
3243 | offset += 4; | |
3244 | ||
3245 | /* parse each EA entry */ | |
3246 | for (i = 0; i < num_ent; ++i) | |
3247 | offset = pci_ea_read(dev, offset); | |
3248 | } | |
3249 | ||
34a4876e YL |
3250 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
3251 | struct pci_cap_saved_state *new_cap) | |
3252 | { | |
3253 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
3254 | } | |
3255 | ||
63f4898a | 3256 | /** |
fd0f7f73 | 3257 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
74356add | 3258 | * capability registers |
63f4898a RW |
3259 | * @dev: the PCI device |
3260 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 3261 | * @extended: Standard or Extended capability ID |
63f4898a RW |
3262 | * @size: requested size of the buffer |
3263 | */ | |
fd0f7f73 AW |
3264 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
3265 | bool extended, unsigned int size) | |
63f4898a RW |
3266 | { |
3267 | int pos; | |
3268 | struct pci_cap_saved_state *save_state; | |
3269 | ||
fd0f7f73 AW |
3270 | if (extended) |
3271 | pos = pci_find_ext_capability(dev, cap); | |
3272 | else | |
3273 | pos = pci_find_capability(dev, cap); | |
3274 | ||
0a1a9b49 | 3275 | if (!pos) |
63f4898a RW |
3276 | return 0; |
3277 | ||
3278 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
3279 | if (!save_state) | |
3280 | return -ENOMEM; | |
3281 | ||
24a4742f | 3282 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 3283 | save_state->cap.cap_extended = extended; |
24a4742f | 3284 | save_state->cap.size = size; |
63f4898a RW |
3285 | pci_add_saved_cap(dev, save_state); |
3286 | ||
3287 | return 0; | |
3288 | } | |
3289 | ||
fd0f7f73 AW |
3290 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
3291 | { | |
3292 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
3293 | } | |
3294 | ||
3295 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
3296 | { | |
3297 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
3298 | } | |
3299 | ||
63f4898a RW |
3300 | /** |
3301 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
3302 | * @dev: the PCI device | |
3303 | */ | |
3304 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
3305 | { | |
3306 | int error; | |
3307 | ||
89858517 YZ |
3308 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
3309 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a | 3310 | if (error) |
7506dc79 | 3311 | pci_err(dev, "unable to preallocate PCI Express save buffer\n"); |
63f4898a RW |
3312 | |
3313 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
3314 | if (error) | |
7506dc79 | 3315 | pci_err(dev, "unable to preallocate PCI-X save buffer\n"); |
425c1b22 | 3316 | |
dbbfadf2 BH |
3317 | error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR, |
3318 | 2 * sizeof(u16)); | |
3319 | if (error) | |
3320 | pci_err(dev, "unable to allocate suspend buffer for LTR\n"); | |
3321 | ||
425c1b22 | 3322 | pci_allocate_vc_save_buffers(dev); |
63f4898a RW |
3323 | } |
3324 | ||
f796841e YL |
3325 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
3326 | { | |
3327 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 3328 | struct hlist_node *n; |
f796841e | 3329 | |
b67bfe0d | 3330 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
3331 | kfree(tmp); |
3332 | } | |
3333 | ||
58c3a727 | 3334 | /** |
31ab2476 | 3335 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 3336 | * @dev: the PCI device |
b0cc6020 YW |
3337 | * |
3338 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
3339 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 3340 | */ |
31ab2476 | 3341 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 3342 | { |
58c3a727 | 3343 | u32 cap; |
8113587c | 3344 | struct pci_dev *bridge; |
58c3a727 | 3345 | |
6748dcc2 | 3346 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
3347 | return; |
3348 | ||
8113587c | 3349 | bridge = dev->bus->self; |
cb97ae34 | 3350 | if (!bridge) |
8113587c ZY |
3351 | return; |
3352 | ||
59875ae4 | 3353 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
3354 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
3355 | return; | |
3356 | ||
b0cc6020 YW |
3357 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
3358 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
3359 | PCI_EXP_DEVCTL2_ARI); | |
3360 | bridge->ari_enabled = 1; | |
3361 | } else { | |
3362 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
3363 | PCI_EXP_DEVCTL2_ARI); | |
3364 | bridge->ari_enabled = 0; | |
3365 | } | |
58c3a727 YZ |
3366 | } |
3367 | ||
0a67119f AW |
3368 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
3369 | { | |
3370 | int pos; | |
83db7e0b | 3371 | u16 cap, ctrl; |
0a67119f | 3372 | |
52fbf5bd | 3373 | pos = pdev->acs_cap; |
0a67119f AW |
3374 | if (!pos) |
3375 | return false; | |
3376 | ||
83db7e0b AW |
3377 | /* |
3378 | * Except for egress control, capabilities are either required | |
3379 | * or only required if controllable. Features missing from the | |
3380 | * capability field can therefore be assumed as hard-wired enabled. | |
3381 | */ | |
3382 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
3383 | acs_flags &= (cap | PCI_ACS_EC); | |
3384 | ||
0a67119f AW |
3385 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
3386 | return (ctrl & acs_flags) == acs_flags; | |
3387 | } | |
3388 | ||
ad805758 AW |
3389 | /** |
3390 | * pci_acs_enabled - test ACS against required flags for a given device | |
3391 | * @pdev: device to test | |
3392 | * @acs_flags: required PCI ACS flags | |
3393 | * | |
3394 | * Return true if the device supports the provided flags. Automatically | |
3395 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
3396 | * |
3397 | * Note that this interface checks the effective ACS capabilities of the | |
3398 | * device rather than the actual capabilities. For instance, most single | |
3399 | * function endpoints are not required to support ACS because they have no | |
3400 | * opportunity for peer-to-peer access. We therefore return 'true' | |
3401 | * regardless of whether the device exposes an ACS capability. This makes | |
3402 | * it much easier for callers of this function to ignore the actual type | |
3403 | * or topology of the device when testing ACS support. | |
ad805758 AW |
3404 | */ |
3405 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
3406 | { | |
0a67119f | 3407 | int ret; |
ad805758 AW |
3408 | |
3409 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
3410 | if (ret >= 0) | |
3411 | return ret > 0; | |
3412 | ||
0a67119f AW |
3413 | /* |
3414 | * Conventional PCI and PCI-X devices never support ACS, either | |
3415 | * effectively or actually. The shared bus topology implies that | |
3416 | * any device on the bus can receive or snoop DMA. | |
3417 | */ | |
ad805758 AW |
3418 | if (!pci_is_pcie(pdev)) |
3419 | return false; | |
3420 | ||
0a67119f AW |
3421 | switch (pci_pcie_type(pdev)) { |
3422 | /* | |
3423 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 3424 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
3425 | * handle them as we would a non-PCIe device. |
3426 | */ | |
3427 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
3428 | /* | |
3429 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
3430 | * applicable... must never implement an ACS Extended Capability...". | |
3431 | * This seems arbitrary, but we take a conservative interpretation | |
3432 | * of this statement. | |
3433 | */ | |
3434 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
3435 | case PCI_EXP_TYPE_RC_EC: | |
3436 | return false; | |
3437 | /* | |
3438 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
3439 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
3440 | * regardless of whether they are single- or multi-function devices. | |
3441 | */ | |
3442 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3443 | case PCI_EXP_TYPE_ROOT_PORT: | |
3444 | return pci_acs_flags_enabled(pdev, acs_flags); | |
3445 | /* | |
3446 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
3447 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 3448 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
3449 | * device. The footnote for section 6.12 indicates the specific |
3450 | * PCIe types included here. | |
3451 | */ | |
3452 | case PCI_EXP_TYPE_ENDPOINT: | |
3453 | case PCI_EXP_TYPE_UPSTREAM: | |
3454 | case PCI_EXP_TYPE_LEG_END: | |
3455 | case PCI_EXP_TYPE_RC_END: | |
3456 | if (!pdev->multifunction) | |
3457 | break; | |
3458 | ||
0a67119f | 3459 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
3460 | } |
3461 | ||
0a67119f | 3462 | /* |
f7625980 | 3463 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
3464 | * to single function devices with the exception of downstream ports. |
3465 | */ | |
ad805758 AW |
3466 | return true; |
3467 | } | |
3468 | ||
3469 | /** | |
3470 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
3471 | * @start: starting downstream device | |
3472 | * @end: ending upstream device or NULL to search to the root bus | |
3473 | * @acs_flags: required flags | |
3474 | * | |
3475 | * Walk up a device tree from start to end testing PCI ACS support. If | |
3476 | * any step along the way does not support the required flags, return false. | |
3477 | */ | |
3478 | bool pci_acs_path_enabled(struct pci_dev *start, | |
3479 | struct pci_dev *end, u16 acs_flags) | |
3480 | { | |
3481 | struct pci_dev *pdev, *parent = start; | |
3482 | ||
3483 | do { | |
3484 | pdev = parent; | |
3485 | ||
3486 | if (!pci_acs_enabled(pdev, acs_flags)) | |
3487 | return false; | |
3488 | ||
3489 | if (pci_is_root_bus(pdev->bus)) | |
3490 | return (end == NULL); | |
3491 | ||
3492 | parent = pdev->bus->self; | |
3493 | } while (pdev != end); | |
3494 | ||
3495 | return true; | |
3496 | } | |
3497 | ||
52fbf5bd RJ |
3498 | /** |
3499 | * pci_acs_init - Initialize ACS if hardware supports it | |
3500 | * @dev: the PCI device | |
3501 | */ | |
3502 | void pci_acs_init(struct pci_dev *dev) | |
3503 | { | |
3504 | dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); | |
3505 | ||
3506 | if (dev->acs_cap) | |
3507 | pci_enable_acs(dev); | |
3508 | } | |
3509 | ||
276b738d CK |
3510 | /** |
3511 | * pci_rebar_find_pos - find position of resize ctrl reg for BAR | |
3512 | * @pdev: PCI device | |
3513 | * @bar: BAR to find | |
3514 | * | |
3515 | * Helper to find the position of the ctrl register for a BAR. | |
3516 | * Returns -ENOTSUPP if resizable BARs are not supported at all. | |
3517 | * Returns -ENOENT if no ctrl register for the BAR could be found. | |
3518 | */ | |
3519 | static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) | |
3520 | { | |
3521 | unsigned int pos, nbars, i; | |
3522 | u32 ctrl; | |
3523 | ||
3524 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
3525 | if (!pos) | |
3526 | return -ENOTSUPP; | |
3527 | ||
3528 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3529 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
3530 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
3531 | ||
3532 | for (i = 0; i < nbars; i++, pos += 8) { | |
3533 | int bar_idx; | |
3534 | ||
3535 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3536 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
3537 | if (bar_idx == bar) | |
3538 | return pos; | |
3539 | } | |
3540 | ||
3541 | return -ENOENT; | |
3542 | } | |
3543 | ||
3544 | /** | |
3545 | * pci_rebar_get_possible_sizes - get possible sizes for BAR | |
3546 | * @pdev: PCI device | |
3547 | * @bar: BAR to query | |
3548 | * | |
3549 | * Get the possible sizes of a resizable BAR as bitmask defined in the spec | |
3550 | * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable. | |
3551 | */ | |
3552 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) | |
3553 | { | |
3554 | int pos; | |
3555 | u32 cap; | |
3556 | ||
3557 | pos = pci_rebar_find_pos(pdev, bar); | |
3558 | if (pos < 0) | |
3559 | return 0; | |
3560 | ||
3561 | pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); | |
3562 | return (cap & PCI_REBAR_CAP_SIZES) >> 4; | |
3563 | } | |
3564 | ||
3565 | /** | |
3566 | * pci_rebar_get_current_size - get the current size of a BAR | |
3567 | * @pdev: PCI device | |
3568 | * @bar: BAR to set size to | |
3569 | * | |
3570 | * Read the size of a BAR from the resizable BAR config. | |
3571 | * Returns size if found or negative error code. | |
3572 | */ | |
3573 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) | |
3574 | { | |
3575 | int pos; | |
3576 | u32 ctrl; | |
3577 | ||
3578 | pos = pci_rebar_find_pos(pdev, bar); | |
3579 | if (pos < 0) | |
3580 | return pos; | |
3581 | ||
3582 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
b1277a22 | 3583 | return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3584 | } |
3585 | ||
3586 | /** | |
3587 | * pci_rebar_set_size - set a new size for a BAR | |
3588 | * @pdev: PCI device | |
3589 | * @bar: BAR to set size to | |
3590 | * @size: new size as defined in the spec (0=1MB, 19=512GB) | |
3591 | * | |
3592 | * Set the new size of a BAR as defined in the spec. | |
3593 | * Returns zero if resizing was successful, error code otherwise. | |
3594 | */ | |
3595 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) | |
3596 | { | |
3597 | int pos; | |
3598 | u32 ctrl; | |
3599 | ||
3600 | pos = pci_rebar_find_pos(pdev, bar); | |
3601 | if (pos < 0) | |
3602 | return pos; | |
3603 | ||
3604 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3605 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; | |
b1277a22 | 3606 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3607 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
3608 | return 0; | |
3609 | } | |
3610 | ||
430a2368 JC |
3611 | /** |
3612 | * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port | |
3613 | * @dev: the PCI device | |
3614 | * @cap_mask: mask of desired AtomicOp sizes, including one or more of: | |
3615 | * PCI_EXP_DEVCAP2_ATOMIC_COMP32 | |
3616 | * PCI_EXP_DEVCAP2_ATOMIC_COMP64 | |
3617 | * PCI_EXP_DEVCAP2_ATOMIC_COMP128 | |
3618 | * | |
3619 | * Return 0 if all upstream bridges support AtomicOp routing, egress | |
3620 | * blocking is disabled on all upstream ports, and the root port supports | |
3621 | * the requested completion capabilities (32-bit, 64-bit and/or 128-bit | |
3622 | * AtomicOp completion), or negative otherwise. | |
3623 | */ | |
3624 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) | |
3625 | { | |
3626 | struct pci_bus *bus = dev->bus; | |
3627 | struct pci_dev *bridge; | |
3628 | u32 cap, ctl2; | |
3629 | ||
3630 | if (!pci_is_pcie(dev)) | |
3631 | return -EINVAL; | |
3632 | ||
3633 | /* | |
3634 | * Per PCIe r4.0, sec 6.15, endpoints and root ports may be | |
3635 | * AtomicOp requesters. For now, we only support endpoints as | |
3636 | * requesters and root ports as completers. No endpoints as | |
3637 | * completers, and no peer-to-peer. | |
3638 | */ | |
3639 | ||
3640 | switch (pci_pcie_type(dev)) { | |
3641 | case PCI_EXP_TYPE_ENDPOINT: | |
3642 | case PCI_EXP_TYPE_LEG_END: | |
3643 | case PCI_EXP_TYPE_RC_END: | |
3644 | break; | |
3645 | default: | |
3646 | return -EINVAL; | |
3647 | } | |
3648 | ||
3649 | while (bus->parent) { | |
3650 | bridge = bus->self; | |
3651 | ||
3652 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); | |
3653 | ||
3654 | switch (pci_pcie_type(bridge)) { | |
3655 | /* Ensure switch ports support AtomicOp routing */ | |
3656 | case PCI_EXP_TYPE_UPSTREAM: | |
3657 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3658 | if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) | |
3659 | return -EINVAL; | |
3660 | break; | |
3661 | ||
3662 | /* Ensure root port supports all the sizes we care about */ | |
3663 | case PCI_EXP_TYPE_ROOT_PORT: | |
3664 | if ((cap & cap_mask) != cap_mask) | |
3665 | return -EINVAL; | |
3666 | break; | |
3667 | } | |
3668 | ||
3669 | /* Ensure upstream ports don't block AtomicOps on egress */ | |
ca784104 | 3670 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) { |
430a2368 JC |
3671 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, |
3672 | &ctl2); | |
3673 | if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) | |
3674 | return -EINVAL; | |
3675 | } | |
3676 | ||
3677 | bus = bus->parent; | |
3678 | } | |
3679 | ||
3680 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, | |
3681 | PCI_EXP_DEVCTL2_ATOMIC_REQ); | |
3682 | return 0; | |
3683 | } | |
3684 | EXPORT_SYMBOL(pci_enable_atomic_ops_to_root); | |
3685 | ||
57c2cf71 BH |
3686 | /** |
3687 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
3688 | * @dev: the PCI device | |
bb5c2de2 | 3689 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
3690 | * |
3691 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
3692 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
3693 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
3694 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
3695 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 3696 | */ |
3df425f3 | 3697 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 3698 | { |
46b952a3 MW |
3699 | int slot; |
3700 | ||
3701 | if (pci_ari_enabled(dev->bus)) | |
3702 | slot = 0; | |
3703 | else | |
3704 | slot = PCI_SLOT(dev->devfn); | |
3705 | ||
3706 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
3707 | } |
3708 | ||
3c78bc61 | 3709 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
3710 | { |
3711 | u8 pin; | |
3712 | ||
514d207d | 3713 | pin = dev->pin; |
1da177e4 LT |
3714 | if (!pin) |
3715 | return -1; | |
878f2e50 | 3716 | |
8784fd4d | 3717 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 3718 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
3719 | dev = dev->bus->self; |
3720 | } | |
3721 | *bridge = dev; | |
3722 | return pin; | |
3723 | } | |
3724 | ||
68feac87 BH |
3725 | /** |
3726 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
3727 | * @dev: the PCI device | |
3728 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
3729 | * | |
3730 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
3731 | * bridges all the way up to a PCI root bus. | |
3732 | */ | |
3733 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
3734 | { | |
3735 | u8 pin = *pinp; | |
3736 | ||
1eb39487 | 3737 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
3738 | pin = pci_swizzle_interrupt_pin(dev, pin); |
3739 | dev = dev->bus->self; | |
3740 | } | |
3741 | *pinp = pin; | |
3742 | return PCI_SLOT(dev->devfn); | |
3743 | } | |
e6b29dea | 3744 | EXPORT_SYMBOL_GPL(pci_common_swizzle); |
68feac87 | 3745 | |
1da177e4 | 3746 | /** |
74356add BH |
3747 | * pci_release_region - Release a PCI bar |
3748 | * @pdev: PCI device whose resources were previously reserved by | |
3749 | * pci_request_region() | |
3750 | * @bar: BAR to release | |
1da177e4 | 3751 | * |
74356add BH |
3752 | * Releases the PCI I/O and memory resources previously reserved by a |
3753 | * successful call to pci_request_region(). Call this function only | |
3754 | * after all use of the PCI regions has ceased. | |
1da177e4 LT |
3755 | */ |
3756 | void pci_release_region(struct pci_dev *pdev, int bar) | |
3757 | { | |
9ac7849e TH |
3758 | struct pci_devres *dr; |
3759 | ||
1da177e4 LT |
3760 | if (pci_resource_len(pdev, bar) == 0) |
3761 | return; | |
3762 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
3763 | release_region(pci_resource_start(pdev, bar), | |
3764 | pci_resource_len(pdev, bar)); | |
3765 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
3766 | release_mem_region(pci_resource_start(pdev, bar), | |
3767 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
3768 | |
3769 | dr = find_pci_dr(pdev); | |
3770 | if (dr) | |
3771 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 3772 | } |
b7fe9434 | 3773 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
3774 | |
3775 | /** | |
74356add BH |
3776 | * __pci_request_region - Reserved PCI I/O and memory resource |
3777 | * @pdev: PCI device whose resources are to be reserved | |
3778 | * @bar: BAR to be reserved | |
3779 | * @res_name: Name to be associated with resource. | |
3780 | * @exclusive: whether the region access is exclusive or not | |
1da177e4 | 3781 | * |
74356add BH |
3782 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
3783 | * being reserved by owner @res_name. Do not access any | |
3784 | * address inside the PCI regions unless this call returns | |
3785 | * successfully. | |
1da177e4 | 3786 | * |
74356add BH |
3787 | * If @exclusive is set, then the region is marked so that userspace |
3788 | * is explicitly not allowed to map the resource via /dev/mem or | |
3789 | * sysfs MMIO access. | |
f5ddcac4 | 3790 | * |
74356add BH |
3791 | * Returns 0 on success, or %EBUSY on error. A warning |
3792 | * message is also printed on failure. | |
1da177e4 | 3793 | */ |
3c78bc61 RD |
3794 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
3795 | const char *res_name, int exclusive) | |
1da177e4 | 3796 | { |
9ac7849e TH |
3797 | struct pci_devres *dr; |
3798 | ||
1da177e4 LT |
3799 | if (pci_resource_len(pdev, bar) == 0) |
3800 | return 0; | |
f7625980 | 3801 | |
1da177e4 LT |
3802 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
3803 | if (!request_region(pci_resource_start(pdev, bar), | |
3804 | pci_resource_len(pdev, bar), res_name)) | |
3805 | goto err_out; | |
3c78bc61 | 3806 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
3807 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
3808 | pci_resource_len(pdev, bar), res_name, | |
3809 | exclusive)) | |
1da177e4 LT |
3810 | goto err_out; |
3811 | } | |
9ac7849e TH |
3812 | |
3813 | dr = find_pci_dr(pdev); | |
3814 | if (dr) | |
3815 | dr->region_mask |= 1 << bar; | |
3816 | ||
1da177e4 LT |
3817 | return 0; |
3818 | ||
3819 | err_out: | |
7506dc79 | 3820 | pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 3821 | &pdev->resource[bar]); |
1da177e4 LT |
3822 | return -EBUSY; |
3823 | } | |
3824 | ||
e8de1481 | 3825 | /** |
74356add BH |
3826 | * pci_request_region - Reserve PCI I/O and memory resource |
3827 | * @pdev: PCI device whose resources are to be reserved | |
3828 | * @bar: BAR to be reserved | |
3829 | * @res_name: Name to be associated with resource | |
e8de1481 | 3830 | * |
74356add BH |
3831 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
3832 | * being reserved by owner @res_name. Do not access any | |
3833 | * address inside the PCI regions unless this call returns | |
3834 | * successfully. | |
e8de1481 | 3835 | * |
74356add BH |
3836 | * Returns 0 on success, or %EBUSY on error. A warning |
3837 | * message is also printed on failure. | |
e8de1481 AV |
3838 | */ |
3839 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
3840 | { | |
3841 | return __pci_request_region(pdev, bar, res_name, 0); | |
3842 | } | |
b7fe9434 | 3843 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 | 3844 | |
c87deff7 HS |
3845 | /** |
3846 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
3847 | * @pdev: PCI device whose resources were previously reserved | |
3848 | * @bars: Bitmask of BARs to be released | |
3849 | * | |
3850 | * Release selected PCI I/O and memory resources previously reserved. | |
3851 | * Call this function only after all use of the PCI regions has ceased. | |
3852 | */ | |
3853 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
3854 | { | |
3855 | int i; | |
3856 | ||
c9c13ba4 | 3857 | for (i = 0; i < PCI_STD_NUM_BARS; i++) |
c87deff7 HS |
3858 | if (bars & (1 << i)) |
3859 | pci_release_region(pdev, i); | |
3860 | } | |
b7fe9434 | 3861 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 3862 | |
9738abed | 3863 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 3864 | const char *res_name, int excl) |
c87deff7 HS |
3865 | { |
3866 | int i; | |
3867 | ||
c9c13ba4 | 3868 | for (i = 0; i < PCI_STD_NUM_BARS; i++) |
c87deff7 | 3869 | if (bars & (1 << i)) |
e8de1481 | 3870 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
3871 | goto err_out; |
3872 | return 0; | |
3873 | ||
3874 | err_out: | |
3c78bc61 | 3875 | while (--i >= 0) |
c87deff7 HS |
3876 | if (bars & (1 << i)) |
3877 | pci_release_region(pdev, i); | |
3878 | ||
3879 | return -EBUSY; | |
3880 | } | |
1da177e4 | 3881 | |
e8de1481 AV |
3882 | |
3883 | /** | |
3884 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
3885 | * @pdev: PCI device whose resources are to be reserved | |
3886 | * @bars: Bitmask of BARs to be requested | |
3887 | * @res_name: Name to be associated with resource | |
3888 | */ | |
3889 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
3890 | const char *res_name) | |
3891 | { | |
3892 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
3893 | } | |
b7fe9434 | 3894 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 3895 | |
3c78bc61 RD |
3896 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
3897 | const char *res_name) | |
e8de1481 AV |
3898 | { |
3899 | return __pci_request_selected_regions(pdev, bars, res_name, | |
3900 | IORESOURCE_EXCLUSIVE); | |
3901 | } | |
b7fe9434 | 3902 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 3903 | |
1da177e4 | 3904 | /** |
74356add BH |
3905 | * pci_release_regions - Release reserved PCI I/O and memory resources |
3906 | * @pdev: PCI device whose resources were previously reserved by | |
3907 | * pci_request_regions() | |
1da177e4 | 3908 | * |
74356add BH |
3909 | * Releases all PCI I/O and memory resources previously reserved by a |
3910 | * successful call to pci_request_regions(). Call this function only | |
3911 | * after all use of the PCI regions has ceased. | |
1da177e4 LT |
3912 | */ |
3913 | ||
3914 | void pci_release_regions(struct pci_dev *pdev) | |
3915 | { | |
c9c13ba4 | 3916 | pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); |
1da177e4 | 3917 | } |
b7fe9434 | 3918 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
3919 | |
3920 | /** | |
74356add BH |
3921 | * pci_request_regions - Reserve PCI I/O and memory resources |
3922 | * @pdev: PCI device whose resources are to be reserved | |
3923 | * @res_name: Name to be associated with resource. | |
1da177e4 | 3924 | * |
74356add BH |
3925 | * Mark all PCI regions associated with PCI device @pdev as |
3926 | * being reserved by owner @res_name. Do not access any | |
3927 | * address inside the PCI regions unless this call returns | |
3928 | * successfully. | |
1da177e4 | 3929 | * |
74356add BH |
3930 | * Returns 0 on success, or %EBUSY on error. A warning |
3931 | * message is also printed on failure. | |
1da177e4 | 3932 | */ |
3c990e92 | 3933 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 3934 | { |
c9c13ba4 DE |
3935 | return pci_request_selected_regions(pdev, |
3936 | ((1 << PCI_STD_NUM_BARS) - 1), res_name); | |
1da177e4 | 3937 | } |
b7fe9434 | 3938 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 3939 | |
e8de1481 | 3940 | /** |
74356add BH |
3941 | * pci_request_regions_exclusive - Reserve PCI I/O and memory resources |
3942 | * @pdev: PCI device whose resources are to be reserved | |
3943 | * @res_name: Name to be associated with resource. | |
e8de1481 | 3944 | * |
74356add BH |
3945 | * Mark all PCI regions associated with PCI device @pdev as being reserved |
3946 | * by owner @res_name. Do not access any address inside the PCI regions | |
3947 | * unless this call returns successfully. | |
e8de1481 | 3948 | * |
74356add BH |
3949 | * pci_request_regions_exclusive() will mark the region so that /dev/mem |
3950 | * and the sysfs MMIO access will not be allowed. | |
e8de1481 | 3951 | * |
74356add BH |
3952 | * Returns 0 on success, or %EBUSY on error. A warning message is also |
3953 | * printed on failure. | |
e8de1481 AV |
3954 | */ |
3955 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
3956 | { | |
3957 | return pci_request_selected_regions_exclusive(pdev, | |
c9c13ba4 | 3958 | ((1 << PCI_STD_NUM_BARS) - 1), res_name); |
e8de1481 | 3959 | } |
b7fe9434 | 3960 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 3961 | |
c5076cfe TN |
3962 | /* |
3963 | * Record the PCI IO range (expressed as CPU physical address + size). | |
74356add | 3964 | * Return a negative value if an error has occurred, zero otherwise |
c5076cfe | 3965 | */ |
fcfaab30 GP |
3966 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
3967 | resource_size_t size) | |
c5076cfe | 3968 | { |
5745392e | 3969 | int ret = 0; |
c5076cfe | 3970 | #ifdef PCI_IOBASE |
5745392e | 3971 | struct logic_pio_hwaddr *range; |
c5076cfe | 3972 | |
5745392e ZY |
3973 | if (!size || addr + size < addr) |
3974 | return -EINVAL; | |
c5076cfe | 3975 | |
c5076cfe | 3976 | range = kzalloc(sizeof(*range), GFP_ATOMIC); |
5745392e ZY |
3977 | if (!range) |
3978 | return -ENOMEM; | |
c5076cfe | 3979 | |
5745392e | 3980 | range->fwnode = fwnode; |
c5076cfe | 3981 | range->size = size; |
5745392e ZY |
3982 | range->hw_start = addr; |
3983 | range->flags = LOGIC_PIO_CPU_MMIO; | |
c5076cfe | 3984 | |
5745392e ZY |
3985 | ret = logic_pio_register_range(range); |
3986 | if (ret) | |
3987 | kfree(range); | |
c5076cfe TN |
3988 | #endif |
3989 | ||
5745392e | 3990 | return ret; |
c5076cfe TN |
3991 | } |
3992 | ||
3993 | phys_addr_t pci_pio_to_address(unsigned long pio) | |
3994 | { | |
3995 | phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; | |
3996 | ||
3997 | #ifdef PCI_IOBASE | |
5745392e | 3998 | if (pio >= MMIO_UPPER_LIMIT) |
c5076cfe TN |
3999 | return address; |
4000 | ||
5745392e | 4001 | address = logic_pio_to_hwaddr(pio); |
c5076cfe TN |
4002 | #endif |
4003 | ||
4004 | return address; | |
4005 | } | |
4006 | ||
4007 | unsigned long __weak pci_address_to_pio(phys_addr_t address) | |
4008 | { | |
4009 | #ifdef PCI_IOBASE | |
5745392e | 4010 | return logic_pio_trans_cpuaddr(address); |
c5076cfe TN |
4011 | #else |
4012 | if (address > IO_SPACE_LIMIT) | |
4013 | return (unsigned long)-1; | |
4014 | ||
4015 | return (unsigned long) address; | |
4016 | #endif | |
4017 | } | |
4018 | ||
8b921acf | 4019 | /** |
74356add BH |
4020 | * pci_remap_iospace - Remap the memory mapped I/O space |
4021 | * @res: Resource describing the I/O space | |
4022 | * @phys_addr: physical address of range to be mapped | |
8b921acf | 4023 | * |
74356add BH |
4024 | * Remap the memory mapped I/O space described by the @res and the CPU |
4025 | * physical address @phys_addr into virtual address space. Only | |
4026 | * architectures that have memory mapped IO functions defined (and the | |
4027 | * PCI_IOBASE value defined) should call this function. | |
8b921acf | 4028 | */ |
7b309aef | 4029 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) |
8b921acf LD |
4030 | { |
4031 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
4032 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
4033 | ||
4034 | if (!(res->flags & IORESOURCE_IO)) | |
4035 | return -EINVAL; | |
4036 | ||
4037 | if (res->end > IO_SPACE_LIMIT) | |
4038 | return -EINVAL; | |
4039 | ||
4040 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
4041 | pgprot_device(PAGE_KERNEL)); | |
4042 | #else | |
74356add BH |
4043 | /* |
4044 | * This architecture does not have memory mapped I/O space, | |
4045 | * so this function should never be called | |
4046 | */ | |
8b921acf LD |
4047 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); |
4048 | return -ENODEV; | |
4049 | #endif | |
4050 | } | |
f90b0875 | 4051 | EXPORT_SYMBOL(pci_remap_iospace); |
8b921acf | 4052 | |
4d3f1384 | 4053 | /** |
74356add BH |
4054 | * pci_unmap_iospace - Unmap the memory mapped I/O space |
4055 | * @res: resource to be unmapped | |
4d3f1384 | 4056 | * |
74356add BH |
4057 | * Unmap the CPU virtual address @res from virtual address space. Only |
4058 | * architectures that have memory mapped IO functions defined (and the | |
4059 | * PCI_IOBASE value defined) should call this function. | |
4d3f1384 SK |
4060 | */ |
4061 | void pci_unmap_iospace(struct resource *res) | |
4062 | { | |
4063 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
4064 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
4065 | ||
4066 | unmap_kernel_range(vaddr, resource_size(res)); | |
4067 | #endif | |
4068 | } | |
f90b0875 | 4069 | EXPORT_SYMBOL(pci_unmap_iospace); |
4d3f1384 | 4070 | |
a5fb9fb0 SS |
4071 | static void devm_pci_unmap_iospace(struct device *dev, void *ptr) |
4072 | { | |
4073 | struct resource **res = ptr; | |
4074 | ||
4075 | pci_unmap_iospace(*res); | |
4076 | } | |
4077 | ||
4078 | /** | |
4079 | * devm_pci_remap_iospace - Managed pci_remap_iospace() | |
4080 | * @dev: Generic device to remap IO address for | |
4081 | * @res: Resource describing the I/O space | |
4082 | * @phys_addr: physical address of range to be mapped | |
4083 | * | |
4084 | * Managed pci_remap_iospace(). Map is automatically unmapped on driver | |
4085 | * detach. | |
4086 | */ | |
4087 | int devm_pci_remap_iospace(struct device *dev, const struct resource *res, | |
4088 | phys_addr_t phys_addr) | |
4089 | { | |
4090 | const struct resource **ptr; | |
4091 | int error; | |
4092 | ||
4093 | ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL); | |
4094 | if (!ptr) | |
4095 | return -ENOMEM; | |
4096 | ||
4097 | error = pci_remap_iospace(res, phys_addr); | |
4098 | if (error) { | |
4099 | devres_free(ptr); | |
4100 | } else { | |
4101 | *ptr = res; | |
4102 | devres_add(dev, ptr); | |
4103 | } | |
4104 | ||
4105 | return error; | |
4106 | } | |
4107 | EXPORT_SYMBOL(devm_pci_remap_iospace); | |
4108 | ||
490cb6dd LP |
4109 | /** |
4110 | * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace() | |
4111 | * @dev: Generic device to remap IO address for | |
4112 | * @offset: Resource address to map | |
4113 | * @size: Size of map | |
4114 | * | |
4115 | * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver | |
4116 | * detach. | |
4117 | */ | |
4118 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, | |
4119 | resource_size_t offset, | |
4120 | resource_size_t size) | |
4121 | { | |
4122 | void __iomem **ptr, *addr; | |
4123 | ||
4124 | ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL); | |
4125 | if (!ptr) | |
4126 | return NULL; | |
4127 | ||
4128 | addr = pci_remap_cfgspace(offset, size); | |
4129 | if (addr) { | |
4130 | *ptr = addr; | |
4131 | devres_add(dev, ptr); | |
4132 | } else | |
4133 | devres_free(ptr); | |
4134 | ||
4135 | return addr; | |
4136 | } | |
4137 | EXPORT_SYMBOL(devm_pci_remap_cfgspace); | |
4138 | ||
4139 | /** | |
4140 | * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource | |
4141 | * @dev: generic device to handle the resource for | |
4142 | * @res: configuration space resource to be handled | |
4143 | * | |
4144 | * Checks that a resource is a valid memory region, requests the memory | |
4145 | * region and ioremaps with pci_remap_cfgspace() API that ensures the | |
4146 | * proper PCI configuration space memory attributes are guaranteed. | |
4147 | * | |
4148 | * All operations are managed and will be undone on driver detach. | |
4149 | * | |
4150 | * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code | |
505fb746 | 4151 | * on failure. Usage example:: |
490cb6dd LP |
4152 | * |
4153 | * res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
4154 | * base = devm_pci_remap_cfg_resource(&pdev->dev, res); | |
4155 | * if (IS_ERR(base)) | |
4156 | * return PTR_ERR(base); | |
4157 | */ | |
4158 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
4159 | struct resource *res) | |
4160 | { | |
4161 | resource_size_t size; | |
4162 | const char *name; | |
4163 | void __iomem *dest_ptr; | |
4164 | ||
4165 | BUG_ON(!dev); | |
4166 | ||
4167 | if (!res || resource_type(res) != IORESOURCE_MEM) { | |
4168 | dev_err(dev, "invalid resource\n"); | |
4169 | return IOMEM_ERR_PTR(-EINVAL); | |
4170 | } | |
4171 | ||
4172 | size = resource_size(res); | |
4173 | name = res->name ?: dev_name(dev); | |
4174 | ||
4175 | if (!devm_request_mem_region(dev, res->start, size, name)) { | |
4176 | dev_err(dev, "can't request region for resource %pR\n", res); | |
4177 | return IOMEM_ERR_PTR(-EBUSY); | |
4178 | } | |
4179 | ||
4180 | dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); | |
4181 | if (!dest_ptr) { | |
4182 | dev_err(dev, "ioremap failed for resource %pR\n", res); | |
4183 | devm_release_mem_region(dev, res->start, size); | |
4184 | dest_ptr = IOMEM_ERR_PTR(-ENOMEM); | |
4185 | } | |
4186 | ||
4187 | return dest_ptr; | |
4188 | } | |
4189 | EXPORT_SYMBOL(devm_pci_remap_cfg_resource); | |
4190 | ||
6a479079 BH |
4191 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
4192 | { | |
4193 | u16 old_cmd, cmd; | |
4194 | ||
4195 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
4196 | if (enable) | |
4197 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
4198 | else | |
4199 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
4200 | if (cmd != old_cmd) { | |
7506dc79 | 4201 | pci_dbg(dev, "%s bus mastering\n", |
6a479079 BH |
4202 | enable ? "enabling" : "disabling"); |
4203 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4204 | } | |
4205 | dev->is_busmaster = enable; | |
4206 | } | |
e8de1481 | 4207 | |
2b6f2c35 MS |
4208 | /** |
4209 | * pcibios_setup - process "pci=" kernel boot arguments | |
4210 | * @str: string used to pass in "pci=" kernel boot arguments | |
4211 | * | |
4212 | * Process kernel boot arguments. This is the default implementation. | |
4213 | * Architecture specific implementations can override this as necessary. | |
4214 | */ | |
4215 | char * __weak __init pcibios_setup(char *str) | |
4216 | { | |
4217 | return str; | |
4218 | } | |
4219 | ||
96c55900 MS |
4220 | /** |
4221 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
4222 | * @dev: the PCI device to enable | |
4223 | * | |
4224 | * Enables PCI bus-mastering for the device. This is the default | |
4225 | * implementation. Architecture specific implementations can override | |
4226 | * this if necessary. | |
4227 | */ | |
4228 | void __weak pcibios_set_master(struct pci_dev *dev) | |
4229 | { | |
4230 | u8 lat; | |
4231 | ||
f676678f MS |
4232 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
4233 | if (pci_is_pcie(dev)) | |
4234 | return; | |
4235 | ||
96c55900 MS |
4236 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
4237 | if (lat < 16) | |
4238 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
4239 | else if (lat > pcibios_max_latency) | |
4240 | lat = pcibios_max_latency; | |
4241 | else | |
4242 | return; | |
a006482b | 4243 | |
96c55900 MS |
4244 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
4245 | } | |
4246 | ||
1da177e4 LT |
4247 | /** |
4248 | * pci_set_master - enables bus-mastering for device dev | |
4249 | * @dev: the PCI device to enable | |
4250 | * | |
4251 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
4252 | * to do the needed arch specific settings. | |
4253 | */ | |
6a479079 | 4254 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 4255 | { |
6a479079 | 4256 | __pci_set_master(dev, true); |
1da177e4 LT |
4257 | pcibios_set_master(dev); |
4258 | } | |
b7fe9434 | 4259 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 4260 | |
6a479079 BH |
4261 | /** |
4262 | * pci_clear_master - disables bus-mastering for device dev | |
4263 | * @dev: the PCI device to disable | |
4264 | */ | |
4265 | void pci_clear_master(struct pci_dev *dev) | |
4266 | { | |
4267 | __pci_set_master(dev, false); | |
4268 | } | |
b7fe9434 | 4269 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 4270 | |
1da177e4 | 4271 | /** |
edb2d97e MW |
4272 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
4273 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 4274 | * |
edb2d97e MW |
4275 | * Helper function for pci_set_mwi. |
4276 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
4277 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
4278 | * | |
4279 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4280 | */ | |
15ea76d4 | 4281 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
4282 | { |
4283 | u8 cacheline_size; | |
4284 | ||
4285 | if (!pci_cache_line_size) | |
15ea76d4 | 4286 | return -EINVAL; |
1da177e4 LT |
4287 | |
4288 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
4289 | equal to or multiple of the right value. */ | |
4290 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4291 | if (cacheline_size >= pci_cache_line_size && | |
4292 | (cacheline_size % pci_cache_line_size) == 0) | |
4293 | return 0; | |
4294 | ||
4295 | /* Write the correct value. */ | |
4296 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
4297 | /* Read it back. */ | |
4298 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4299 | if (cacheline_size == pci_cache_line_size) | |
4300 | return 0; | |
4301 | ||
34c6b710 | 4302 | pci_info(dev, "cache line size of %d is not supported\n", |
227f0647 | 4303 | pci_cache_line_size << 2); |
1da177e4 LT |
4304 | |
4305 | return -EINVAL; | |
4306 | } | |
15ea76d4 TH |
4307 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
4308 | ||
1da177e4 LT |
4309 | /** |
4310 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
4311 | * @dev: the PCI device for which MWI is enabled | |
4312 | * | |
694625c0 | 4313 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
4314 | * |
4315 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4316 | */ | |
3c78bc61 | 4317 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 4318 | { |
b7fe9434 RD |
4319 | #ifdef PCI_DISABLE_MWI |
4320 | return 0; | |
4321 | #else | |
1da177e4 LT |
4322 | int rc; |
4323 | u16 cmd; | |
4324 | ||
edb2d97e | 4325 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
4326 | if (rc) |
4327 | return rc; | |
4328 | ||
4329 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 4330 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
7506dc79 | 4331 | pci_dbg(dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
4332 | cmd |= PCI_COMMAND_INVALIDATE; |
4333 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4334 | } | |
1da177e4 | 4335 | return 0; |
b7fe9434 | 4336 | #endif |
1da177e4 | 4337 | } |
b7fe9434 | 4338 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 4339 | |
fc0f9f4d HK |
4340 | /** |
4341 | * pcim_set_mwi - a device-managed pci_set_mwi() | |
4342 | * @dev: the PCI device for which MWI is enabled | |
4343 | * | |
4344 | * Managed pci_set_mwi(). | |
4345 | * | |
4346 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4347 | */ | |
4348 | int pcim_set_mwi(struct pci_dev *dev) | |
4349 | { | |
4350 | struct pci_devres *dr; | |
4351 | ||
4352 | dr = find_pci_dr(dev); | |
4353 | if (!dr) | |
4354 | return -ENOMEM; | |
4355 | ||
4356 | dr->mwi = 1; | |
4357 | return pci_set_mwi(dev); | |
4358 | } | |
4359 | EXPORT_SYMBOL(pcim_set_mwi); | |
4360 | ||
694625c0 RD |
4361 | /** |
4362 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
4363 | * @dev: the PCI device for which MWI is enabled | |
4364 | * | |
4365 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
4366 | * Callers are not required to check the return value. | |
4367 | * | |
4368 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4369 | */ | |
4370 | int pci_try_set_mwi(struct pci_dev *dev) | |
4371 | { | |
b7fe9434 RD |
4372 | #ifdef PCI_DISABLE_MWI |
4373 | return 0; | |
4374 | #else | |
4375 | return pci_set_mwi(dev); | |
4376 | #endif | |
694625c0 | 4377 | } |
b7fe9434 | 4378 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 4379 | |
1da177e4 LT |
4380 | /** |
4381 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
4382 | * @dev: the PCI device to disable | |
4383 | * | |
4384 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
4385 | */ | |
3c78bc61 | 4386 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 4387 | { |
b7fe9434 | 4388 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
4389 | u16 cmd; |
4390 | ||
4391 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4392 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
4393 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
4394 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4395 | } | |
b7fe9434 | 4396 | #endif |
1da177e4 | 4397 | } |
b7fe9434 | 4398 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 4399 | |
a04ce0ff BR |
4400 | /** |
4401 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
4402 | * @pdev: the PCI device to operate on |
4403 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff | 4404 | * |
74356add | 4405 | * Enables/disables PCI INTx for device @pdev |
a04ce0ff | 4406 | */ |
3c78bc61 | 4407 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
4408 | { |
4409 | u16 pci_command, new; | |
4410 | ||
4411 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
4412 | ||
3c78bc61 | 4413 | if (enable) |
a04ce0ff | 4414 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 4415 | else |
a04ce0ff | 4416 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
4417 | |
4418 | if (new != pci_command) { | |
9ac7849e TH |
4419 | struct pci_devres *dr; |
4420 | ||
2fd9d74b | 4421 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
4422 | |
4423 | dr = find_pci_dr(pdev); | |
4424 | if (dr && !dr->restore_intx) { | |
4425 | dr->restore_intx = 1; | |
4426 | dr->orig_intx = !enable; | |
4427 | } | |
a04ce0ff BR |
4428 | } |
4429 | } | |
b7fe9434 | 4430 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 4431 | |
a2e27787 JK |
4432 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) |
4433 | { | |
4434 | struct pci_bus *bus = dev->bus; | |
4435 | bool mask_updated = true; | |
4436 | u32 cmd_status_dword; | |
4437 | u16 origcmd, newcmd; | |
4438 | unsigned long flags; | |
4439 | bool irq_pending; | |
4440 | ||
4441 | /* | |
4442 | * We do a single dword read to retrieve both command and status. | |
4443 | * Document assumptions that make this possible. | |
4444 | */ | |
4445 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
4446 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
4447 | ||
4448 | raw_spin_lock_irqsave(&pci_lock, flags); | |
4449 | ||
4450 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
4451 | ||
4452 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
4453 | ||
4454 | /* | |
4455 | * Check interrupt status register to see whether our device | |
4456 | * triggered the interrupt (when masking) or the next IRQ is | |
4457 | * already pending (when unmasking). | |
4458 | */ | |
4459 | if (mask != irq_pending) { | |
4460 | mask_updated = false; | |
4461 | goto done; | |
4462 | } | |
4463 | ||
4464 | origcmd = cmd_status_dword; | |
4465 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
4466 | if (mask) | |
4467 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
4468 | if (newcmd != origcmd) | |
4469 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
4470 | ||
4471 | done: | |
4472 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
4473 | ||
4474 | return mask_updated; | |
4475 | } | |
4476 | ||
4477 | /** | |
4478 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 4479 | * @dev: the PCI device to operate on |
a2e27787 | 4480 | * |
74356add BH |
4481 | * Check if the device dev has its INTx line asserted, mask it and return |
4482 | * true in that case. False is returned if no interrupt was pending. | |
a2e27787 JK |
4483 | */ |
4484 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
4485 | { | |
4486 | return pci_check_and_set_intx_mask(dev, true); | |
4487 | } | |
4488 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
4489 | ||
4490 | /** | |
ebd50b93 | 4491 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 4492 | * @dev: the PCI device to operate on |
a2e27787 | 4493 | * |
74356add BH |
4494 | * Check if the device dev has its INTx line asserted, unmask it if not and |
4495 | * return true. False is returned and the mask remains active if there was | |
4496 | * still an interrupt pending. | |
a2e27787 JK |
4497 | */ |
4498 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
4499 | { | |
4500 | return pci_check_and_set_intx_mask(dev, false); | |
4501 | } | |
4502 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
4503 | ||
3775a209 | 4504 | /** |
74356add | 4505 | * pci_wait_for_pending_transaction - wait for pending transaction |
3775a209 CL |
4506 | * @dev: the PCI device to operate on |
4507 | * | |
4508 | * Return 0 if transaction is pending 1 otherwise. | |
4509 | */ | |
4510 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 4511 | { |
157e876f AW |
4512 | if (!pci_is_pcie(dev)) |
4513 | return 1; | |
8c1c699f | 4514 | |
d0b4cc4e GS |
4515 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
4516 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
4517 | } |
4518 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
4519 | ||
a60a2b73 CH |
4520 | /** |
4521 | * pcie_has_flr - check if a device supports function level resets | |
74356add | 4522 | * @dev: device to check |
a60a2b73 CH |
4523 | * |
4524 | * Returns true if the device advertises support for PCIe function level | |
4525 | * resets. | |
4526 | */ | |
2d2917f7 | 4527 | bool pcie_has_flr(struct pci_dev *dev) |
3775a209 CL |
4528 | { |
4529 | u32 cap; | |
4530 | ||
f65fd1aa | 4531 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
a60a2b73 | 4532 | return false; |
3775a209 | 4533 | |
a60a2b73 CH |
4534 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
4535 | return cap & PCI_EXP_DEVCAP_FLR; | |
4536 | } | |
2d2917f7 | 4537 | EXPORT_SYMBOL_GPL(pcie_has_flr); |
3775a209 | 4538 | |
a60a2b73 CH |
4539 | /** |
4540 | * pcie_flr - initiate a PCIe function level reset | |
74356add | 4541 | * @dev: device to reset |
a60a2b73 CH |
4542 | * |
4543 | * Initiate a function level reset on @dev. The caller should ensure the | |
4544 | * device supports FLR before calling this function, e.g. by using the | |
4545 | * pcie_has_flr() helper. | |
4546 | */ | |
91295d79 | 4547 | int pcie_flr(struct pci_dev *dev) |
a60a2b73 | 4548 | { |
3775a209 | 4549 | if (!pci_wait_for_pending_transaction(dev)) |
7506dc79 | 4550 | pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 4551 | |
59875ae4 | 4552 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
a2758b6b | 4553 | |
d6112f8d FB |
4554 | if (dev->imm_ready) |
4555 | return 0; | |
4556 | ||
a2758b6b SK |
4557 | /* |
4558 | * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within | |
4559 | * 100ms, but may silently discard requests while the FLR is in | |
4560 | * progress. Wait 100ms before trying to access the device. | |
4561 | */ | |
4562 | msleep(100); | |
4563 | ||
4564 | return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); | |
8dd7f803 | 4565 | } |
a60a2b73 | 4566 | EXPORT_SYMBOL_GPL(pcie_flr); |
d91cdc74 | 4567 | |
8c1c699f | 4568 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 4569 | { |
8c1c699f | 4570 | int pos; |
1ca88797 SY |
4571 | u8 cap; |
4572 | ||
8c1c699f YZ |
4573 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
4574 | if (!pos) | |
1ca88797 | 4575 | return -ENOTTY; |
8c1c699f | 4576 | |
f65fd1aa SN |
4577 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
4578 | return -ENOTTY; | |
4579 | ||
8c1c699f | 4580 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); |
1ca88797 SY |
4581 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
4582 | return -ENOTTY; | |
4583 | ||
4584 | if (probe) | |
4585 | return 0; | |
4586 | ||
d066c946 AW |
4587 | /* |
4588 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
f6b6aefe | 4589 | * is used, so we use the control offset rather than status and shift |
d066c946 AW |
4590 | * the test bit to match. |
4591 | */ | |
bb383e28 | 4592 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 4593 | PCI_AF_STATUS_TP << 8)) |
7506dc79 | 4594 | pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 4595 | |
8c1c699f | 4596 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
a2758b6b | 4597 | |
d6112f8d FB |
4598 | if (dev->imm_ready) |
4599 | return 0; | |
4600 | ||
a2758b6b SK |
4601 | /* |
4602 | * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, | |
4603 | * updated 27 July 2006; a device must complete an FLR within | |
4604 | * 100ms, but may silently discard requests while the FLR is in | |
4605 | * progress. Wait 100ms before trying to access the device. | |
4606 | */ | |
4607 | msleep(100); | |
4608 | ||
4609 | return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); | |
1ca88797 SY |
4610 | } |
4611 | ||
83d74e03 RW |
4612 | /** |
4613 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
4614 | * @dev: Device to reset. | |
4615 | * @probe: If set, only check if the device can be reset this way. | |
4616 | * | |
4617 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
4618 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
4619 | * PCI_D0. If that's the case and the device is not in a low-power state | |
4620 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
4621 | * | |
4622 | * NOTE: This causes the caller to sleep for twice the device power transition | |
4623 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 4624 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
4625 | * Moreover, only devices in D0 can be reset by this function. |
4626 | */ | |
f85876ba | 4627 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 4628 | { |
f85876ba YZ |
4629 | u16 csr; |
4630 | ||
51e53738 | 4631 | if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) |
f85876ba | 4632 | return -ENOTTY; |
d91cdc74 | 4633 | |
f85876ba YZ |
4634 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
4635 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
4636 | return -ENOTTY; | |
d91cdc74 | 4637 | |
f85876ba YZ |
4638 | if (probe) |
4639 | return 0; | |
1ca88797 | 4640 | |
f85876ba YZ |
4641 | if (dev->current_state != PCI_D0) |
4642 | return -EINVAL; | |
4643 | ||
4644 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4645 | csr |= PCI_D3hot; | |
4646 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4647 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
4648 | |
4649 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4650 | csr |= PCI_D0; | |
4651 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4652 | pci_dev_d3_sleep(dev); |
f85876ba | 4653 | |
993cc6d1 | 4654 | return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); |
f85876ba | 4655 | } |
4827d638 | 4656 | |
9f5a70f1 | 4657 | /** |
4827d638 | 4658 | * pcie_wait_for_link_delay - Wait until link is active or inactive |
9f5a70f1 OP |
4659 | * @pdev: Bridge device |
4660 | * @active: waiting for active or inactive? | |
d08c30d7 | 4661 | * @delay: Delay to wait after link has become active (in ms) |
9f5a70f1 OP |
4662 | * |
4663 | * Use this to wait till link becomes active or inactive. | |
4664 | */ | |
4827d638 MW |
4665 | static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, |
4666 | int delay) | |
9f5a70f1 OP |
4667 | { |
4668 | int timeout = 1000; | |
4669 | bool ret; | |
4670 | u16 lnk_status; | |
4671 | ||
f0157160 KB |
4672 | /* |
4673 | * Some controllers might not implement link active reporting. In this | |
f044baaf | 4674 | * case, we wait for 1000 ms + any delay requested by the caller. |
f0157160 KB |
4675 | */ |
4676 | if (!pdev->link_active_reporting) { | |
f044baaf | 4677 | msleep(timeout + delay); |
f0157160 KB |
4678 | return true; |
4679 | } | |
4680 | ||
4681 | /* | |
4682 | * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms, | |
4683 | * after which we should expect an link active if the reset was | |
4684 | * successful. If so, software must wait a minimum 100ms before sending | |
4685 | * configuration requests to devices downstream this port. | |
4686 | * | |
4687 | * If the link fails to activate, either the device was physically | |
4688 | * removed or the link is permanently failed. | |
4689 | */ | |
4690 | if (active) | |
4691 | msleep(20); | |
9f5a70f1 OP |
4692 | for (;;) { |
4693 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); | |
4694 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); | |
4695 | if (ret == active) | |
f0157160 | 4696 | break; |
9f5a70f1 OP |
4697 | if (timeout <= 0) |
4698 | break; | |
4699 | msleep(10); | |
4700 | timeout -= 10; | |
4701 | } | |
d08c30d7 | 4702 | if (active && ret) |
4827d638 | 4703 | msleep(delay); |
f0157160 KB |
4704 | else if (ret != active) |
4705 | pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n", | |
4706 | active ? "set" : "cleared"); | |
4707 | return ret == active; | |
9f5a70f1 | 4708 | } |
f85876ba | 4709 | |
4827d638 MW |
4710 | /** |
4711 | * pcie_wait_for_link - Wait until link is active or inactive | |
4712 | * @pdev: Bridge device | |
4713 | * @active: waiting for active or inactive? | |
4714 | * | |
4715 | * Use this to wait till link becomes active or inactive. | |
4716 | */ | |
4717 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active) | |
4718 | { | |
4719 | return pcie_wait_for_link_delay(pdev, active, 100); | |
4720 | } | |
4721 | ||
ad9001f2 MW |
4722 | /* |
4723 | * Find maximum D3cold delay required by all the devices on the bus. The | |
4724 | * spec says 100 ms, but firmware can lower it and we allow drivers to | |
4725 | * increase it as well. | |
4726 | * | |
4727 | * Called with @pci_bus_sem locked for reading. | |
4728 | */ | |
4729 | static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) | |
4730 | { | |
4731 | const struct pci_dev *pdev; | |
4732 | int min_delay = 100; | |
4733 | int max_delay = 0; | |
4734 | ||
4735 | list_for_each_entry(pdev, &bus->devices, bus_list) { | |
4736 | if (pdev->d3cold_delay < min_delay) | |
4737 | min_delay = pdev->d3cold_delay; | |
4738 | if (pdev->d3cold_delay > max_delay) | |
4739 | max_delay = pdev->d3cold_delay; | |
4740 | } | |
4741 | ||
4742 | return max(min_delay, max_delay); | |
4743 | } | |
4744 | ||
4745 | /** | |
4746 | * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible | |
4747 | * @dev: PCI bridge | |
4748 | * | |
4749 | * Handle necessary delays before access to the devices on the secondary | |
4750 | * side of the bridge are permitted after D3cold to D0 transition. | |
4751 | * | |
4752 | * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For | |
4753 | * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section | |
4754 | * 4.3.2. | |
4755 | */ | |
4756 | void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev) | |
4757 | { | |
4758 | struct pci_dev *child; | |
4759 | int delay; | |
4760 | ||
4761 | if (pci_dev_is_disconnected(dev)) | |
4762 | return; | |
4763 | ||
4764 | if (!pci_is_bridge(dev) || !dev->bridge_d3) | |
4765 | return; | |
4766 | ||
4767 | down_read(&pci_bus_sem); | |
4768 | ||
4769 | /* | |
4770 | * We only deal with devices that are present currently on the bus. | |
4771 | * For any hot-added devices the access delay is handled in pciehp | |
4772 | * board_added(). In case of ACPI hotplug the firmware is expected | |
4773 | * to configure the devices before OS is notified. | |
4774 | */ | |
4775 | if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { | |
4776 | up_read(&pci_bus_sem); | |
4777 | return; | |
4778 | } | |
4779 | ||
4780 | /* Take d3cold_delay requirements into account */ | |
4781 | delay = pci_bus_max_d3cold_delay(dev->subordinate); | |
4782 | if (!delay) { | |
4783 | up_read(&pci_bus_sem); | |
4784 | return; | |
4785 | } | |
4786 | ||
4787 | child = list_first_entry(&dev->subordinate->devices, struct pci_dev, | |
4788 | bus_list); | |
4789 | up_read(&pci_bus_sem); | |
4790 | ||
4791 | /* | |
4792 | * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before | |
4793 | * accessing the device after reset (that is 1000 ms + 100 ms). In | |
4794 | * practice this should not be needed because we don't do power | |
4795 | * management for them (see pci_bridge_d3_possible()). | |
4796 | */ | |
4797 | if (!pci_is_pcie(dev)) { | |
4798 | pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay); | |
4799 | msleep(1000 + delay); | |
4800 | return; | |
4801 | } | |
4802 | ||
4803 | /* | |
4804 | * For PCIe downstream and root ports that do not support speeds | |
4805 | * greater than 5 GT/s need to wait minimum 100 ms. For higher | |
4806 | * speeds (gen3) we need to wait first for the data link layer to | |
4807 | * become active. | |
4808 | * | |
4809 | * However, 100 ms is the minimum and the PCIe spec says the | |
4810 | * software must allow at least 1s before it can determine that the | |
4811 | * device that did not respond is a broken device. There is | |
4812 | * evidence that 100 ms is not always enough, for example certain | |
4813 | * Titan Ridge xHCI controller does not always respond to | |
4814 | * configuration requests if we only wait for 100 ms (see | |
4815 | * https://bugzilla.kernel.org/show_bug.cgi?id=203885). | |
4816 | * | |
4817 | * Therefore we wait for 100 ms and check for the device presence. | |
4818 | * If it is still not present give it an additional 100 ms. | |
4819 | */ | |
4820 | if (!pcie_downstream_port(dev)) | |
4821 | return; | |
4822 | ||
d08c30d7 BH |
4823 | if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) { |
4824 | pci_dbg(dev, "waiting %d ms for downstream link\n", delay); | |
4825 | msleep(delay); | |
4826 | } else { | |
4827 | pci_dbg(dev, "waiting %d ms for downstream link, after activation\n", | |
4828 | delay); | |
4829 | if (!pcie_wait_for_link_delay(dev, true, delay)) { | |
ad9001f2 MW |
4830 | /* Did not train, no need to wait any further */ |
4831 | return; | |
4832 | } | |
4833 | } | |
4834 | ||
4835 | if (!pci_device_is_present(child)) { | |
4836 | pci_dbg(child, "waiting additional %d ms to become accessible\n", delay); | |
4837 | msleep(delay); | |
4838 | } | |
4839 | } | |
4840 | ||
9e33002f | 4841 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
4842 | { |
4843 | u16 ctrl; | |
64e8674f AW |
4844 | |
4845 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
4846 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
4847 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
df62ab5e | 4848 | |
de0c548c AW |
4849 | /* |
4850 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 4851 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
4852 | */ |
4853 | msleep(2); | |
64e8674f AW |
4854 | |
4855 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
4856 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
4857 | |
4858 | /* | |
4859 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
4860 | * Assuming a minimum 33MHz clock this results in a 1s | |
4861 | * delay before we can consider subordinate devices to | |
4862 | * be re-initialized. PCIe has some ways to shorten this, | |
4863 | * but we don't make use of them yet. | |
4864 | */ | |
4865 | ssleep(1); | |
64e8674f | 4866 | } |
d92a208d | 4867 | |
9e33002f GS |
4868 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
4869 | { | |
4870 | pci_reset_secondary_bus(dev); | |
4871 | } | |
4872 | ||
d92a208d | 4873 | /** |
381634ca | 4874 | * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge. |
d92a208d GS |
4875 | * @dev: Bridge device |
4876 | * | |
4877 | * Use the bridge control register to assert reset on the secondary bus. | |
4878 | * Devices on the secondary bus are left in power-on state. | |
4879 | */ | |
381634ca | 4880 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev) |
d92a208d GS |
4881 | { |
4882 | pcibios_reset_secondary_bus(dev); | |
01fd61c0 | 4883 | |
6b2f1351 | 4884 | return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS); |
d92a208d | 4885 | } |
bfc45606 | 4886 | EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); |
64e8674f AW |
4887 | |
4888 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
4889 | { | |
c12ff1df YZ |
4890 | struct pci_dev *pdev; |
4891 | ||
f331a859 AW |
4892 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
4893 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
4894 | return -ENOTTY; |
4895 | ||
4896 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4897 | if (pdev != dev) | |
4898 | return -ENOTTY; | |
4899 | ||
4900 | if (probe) | |
4901 | return 0; | |
4902 | ||
381634ca | 4903 | return pci_bridge_secondary_bus_reset(dev->bus->self); |
c12ff1df YZ |
4904 | } |
4905 | ||
608c3881 AW |
4906 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
4907 | { | |
4908 | int rc = -ENOTTY; | |
4909 | ||
81c4b5bf | 4910 | if (!hotplug || !try_module_get(hotplug->owner)) |
608c3881 AW |
4911 | return rc; |
4912 | ||
4913 | if (hotplug->ops->reset_slot) | |
4914 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
4915 | ||
81c4b5bf | 4916 | module_put(hotplug->owner); |
608c3881 AW |
4917 | |
4918 | return rc; | |
4919 | } | |
4920 | ||
4921 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
4922 | { | |
4923 | struct pci_dev *pdev; | |
4924 | ||
f331a859 AW |
4925 | if (dev->subordinate || !dev->slot || |
4926 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
608c3881 AW |
4927 | return -ENOTTY; |
4928 | ||
4929 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4930 | if (pdev != dev && pdev->slot == dev->slot) | |
4931 | return -ENOTTY; | |
4932 | ||
4933 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
4934 | } | |
4935 | ||
77cb985a AW |
4936 | static void pci_dev_lock(struct pci_dev *dev) |
4937 | { | |
4938 | pci_cfg_access_lock(dev); | |
4939 | /* block PM suspend, driver probe, etc. */ | |
4940 | device_lock(&dev->dev); | |
4941 | } | |
4942 | ||
61cf16d8 AW |
4943 | /* Return 1 on successful lock, 0 on contention */ |
4944 | static int pci_dev_trylock(struct pci_dev *dev) | |
4945 | { | |
4946 | if (pci_cfg_access_trylock(dev)) { | |
4947 | if (device_trylock(&dev->dev)) | |
4948 | return 1; | |
4949 | pci_cfg_access_unlock(dev); | |
4950 | } | |
4951 | ||
4952 | return 0; | |
4953 | } | |
4954 | ||
77cb985a AW |
4955 | static void pci_dev_unlock(struct pci_dev *dev) |
4956 | { | |
4957 | device_unlock(&dev->dev); | |
4958 | pci_cfg_access_unlock(dev); | |
4959 | } | |
4960 | ||
775755ed | 4961 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
3ebe7f9f KB |
4962 | { |
4963 | const struct pci_error_handlers *err_handler = | |
4964 | dev->driver ? dev->driver->err_handler : NULL; | |
3ebe7f9f | 4965 | |
b014e96d | 4966 | /* |
775755ed | 4967 | * dev->driver->err_handler->reset_prepare() is protected against |
b014e96d CH |
4968 | * races with ->remove() by the device lock, which must be held by |
4969 | * the caller. | |
4970 | */ | |
775755ed CH |
4971 | if (err_handler && err_handler->reset_prepare) |
4972 | err_handler->reset_prepare(dev); | |
3ebe7f9f | 4973 | |
a6cbaade AW |
4974 | /* |
4975 | * Wake-up device prior to save. PM registers default to D0 after | |
4976 | * reset and a simple register restore doesn't reliably return | |
4977 | * to a non-D0 state anyway. | |
4978 | */ | |
4979 | pci_set_power_state(dev, PCI_D0); | |
4980 | ||
77cb985a AW |
4981 | pci_save_state(dev); |
4982 | /* | |
4983 | * Disable the device by clearing the Command register, except for | |
4984 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
4985 | * BARs, but also prevents the device from being Bus Master, preventing | |
4986 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
4987 | * compliant devices, INTx-disable prevents legacy interrupts. | |
4988 | */ | |
4989 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
4990 | } | |
4991 | ||
4992 | static void pci_dev_restore(struct pci_dev *dev) | |
4993 | { | |
775755ed CH |
4994 | const struct pci_error_handlers *err_handler = |
4995 | dev->driver ? dev->driver->err_handler : NULL; | |
977f857c | 4996 | |
77cb985a | 4997 | pci_restore_state(dev); |
77cb985a | 4998 | |
775755ed CH |
4999 | /* |
5000 | * dev->driver->err_handler->reset_done() is protected against | |
5001 | * races with ->remove() by the device lock, which must be held by | |
5002 | * the caller. | |
5003 | */ | |
5004 | if (err_handler && err_handler->reset_done) | |
5005 | err_handler->reset_done(dev); | |
d91cdc74 | 5006 | } |
3ebe7f9f | 5007 | |
6fbf9e7a KRW |
5008 | /** |
5009 | * __pci_reset_function_locked - reset a PCI device function while holding | |
5010 | * the @dev mutex lock. | |
5011 | * @dev: PCI device to reset | |
5012 | * | |
5013 | * Some devices allow an individual function to be reset without affecting | |
5014 | * other functions in the same device. The PCI device must be responsive | |
5015 | * to PCI config space in order to use this function. | |
5016 | * | |
5017 | * The device function is presumed to be unused and the caller is holding | |
5018 | * the device mutex lock when this function is called. | |
74356add | 5019 | * |
6fbf9e7a KRW |
5020 | * Resetting the device will make the contents of PCI configuration space |
5021 | * random, so any caller of this must be prepared to reinitialise the | |
5022 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
5023 | * etc. | |
5024 | * | |
5025 | * Returns 0 if the device function was successfully reset or negative if the | |
5026 | * device doesn't support resetting a single function. | |
5027 | */ | |
5028 | int __pci_reset_function_locked(struct pci_dev *dev) | |
5029 | { | |
52354b9d CH |
5030 | int rc; |
5031 | ||
5032 | might_sleep(); | |
5033 | ||
832c418a BH |
5034 | /* |
5035 | * A reset method returns -ENOTTY if it doesn't support this device | |
5036 | * and we should try the next method. | |
5037 | * | |
5038 | * If it returns 0 (success), we're finished. If it returns any | |
5039 | * other error, we're also finished: this indicates that further | |
5040 | * reset mechanisms might be broken on the device. | |
5041 | */ | |
52354b9d CH |
5042 | rc = pci_dev_specific_reset(dev, 0); |
5043 | if (rc != -ENOTTY) | |
5044 | return rc; | |
5045 | if (pcie_has_flr(dev)) { | |
91295d79 SK |
5046 | rc = pcie_flr(dev); |
5047 | if (rc != -ENOTTY) | |
5048 | return rc; | |
52354b9d CH |
5049 | } |
5050 | rc = pci_af_flr(dev, 0); | |
5051 | if (rc != -ENOTTY) | |
5052 | return rc; | |
5053 | rc = pci_pm_reset(dev, 0); | |
5054 | if (rc != -ENOTTY) | |
5055 | return rc; | |
5056 | rc = pci_dev_reset_slot_function(dev, 0); | |
5057 | if (rc != -ENOTTY) | |
5058 | return rc; | |
5059 | return pci_parent_bus_reset(dev, 0); | |
6fbf9e7a KRW |
5060 | } |
5061 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
5062 | ||
711d5779 MT |
5063 | /** |
5064 | * pci_probe_reset_function - check whether the device can be safely reset | |
5065 | * @dev: PCI device to reset | |
5066 | * | |
5067 | * Some devices allow an individual function to be reset without affecting | |
5068 | * other functions in the same device. The PCI device must be responsive | |
5069 | * to PCI config space in order to use this function. | |
5070 | * | |
5071 | * Returns 0 if the device function can be reset or negative if the | |
5072 | * device doesn't support resetting a single function. | |
5073 | */ | |
5074 | int pci_probe_reset_function(struct pci_dev *dev) | |
5075 | { | |
52354b9d CH |
5076 | int rc; |
5077 | ||
5078 | might_sleep(); | |
5079 | ||
5080 | rc = pci_dev_specific_reset(dev, 1); | |
5081 | if (rc != -ENOTTY) | |
5082 | return rc; | |
5083 | if (pcie_has_flr(dev)) | |
5084 | return 0; | |
5085 | rc = pci_af_flr(dev, 1); | |
5086 | if (rc != -ENOTTY) | |
5087 | return rc; | |
5088 | rc = pci_pm_reset(dev, 1); | |
5089 | if (rc != -ENOTTY) | |
5090 | return rc; | |
5091 | rc = pci_dev_reset_slot_function(dev, 1); | |
5092 | if (rc != -ENOTTY) | |
5093 | return rc; | |
5094 | ||
5095 | return pci_parent_bus_reset(dev, 1); | |
711d5779 MT |
5096 | } |
5097 | ||
8dd7f803 | 5098 | /** |
8c1c699f YZ |
5099 | * pci_reset_function - quiesce and reset a PCI device function |
5100 | * @dev: PCI device to reset | |
8dd7f803 SY |
5101 | * |
5102 | * Some devices allow an individual function to be reset without affecting | |
5103 | * other functions in the same device. The PCI device must be responsive | |
5104 | * to PCI config space in order to use this function. | |
5105 | * | |
5106 | * This function does not just reset the PCI portion of a device, but | |
5107 | * clears all the state associated with the device. This function differs | |
79e699b6 JS |
5108 | * from __pci_reset_function_locked() in that it saves and restores device state |
5109 | * over the reset and takes the PCI device lock. | |
8dd7f803 | 5110 | * |
8c1c699f | 5111 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
5112 | * device doesn't support resetting a single function. |
5113 | */ | |
5114 | int pci_reset_function(struct pci_dev *dev) | |
5115 | { | |
8c1c699f | 5116 | int rc; |
8dd7f803 | 5117 | |
204f4afa BH |
5118 | if (!dev->reset_fn) |
5119 | return -ENOTTY; | |
8dd7f803 | 5120 | |
b014e96d | 5121 | pci_dev_lock(dev); |
77cb985a | 5122 | pci_dev_save_and_disable(dev); |
8dd7f803 | 5123 | |
52354b9d | 5124 | rc = __pci_reset_function_locked(dev); |
8dd7f803 | 5125 | |
77cb985a | 5126 | pci_dev_restore(dev); |
b014e96d | 5127 | pci_dev_unlock(dev); |
8dd7f803 | 5128 | |
8c1c699f | 5129 | return rc; |
8dd7f803 SY |
5130 | } |
5131 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
5132 | ||
a477b9cd MZ |
5133 | /** |
5134 | * pci_reset_function_locked - quiesce and reset a PCI device function | |
5135 | * @dev: PCI device to reset | |
5136 | * | |
5137 | * Some devices allow an individual function to be reset without affecting | |
5138 | * other functions in the same device. The PCI device must be responsive | |
5139 | * to PCI config space in order to use this function. | |
5140 | * | |
5141 | * This function does not just reset the PCI portion of a device, but | |
5142 | * clears all the state associated with the device. This function differs | |
79e699b6 | 5143 | * from __pci_reset_function_locked() in that it saves and restores device state |
a477b9cd MZ |
5144 | * over the reset. It also differs from pci_reset_function() in that it |
5145 | * requires the PCI device lock to be held. | |
5146 | * | |
5147 | * Returns 0 if the device function was successfully reset or negative if the | |
5148 | * device doesn't support resetting a single function. | |
5149 | */ | |
5150 | int pci_reset_function_locked(struct pci_dev *dev) | |
5151 | { | |
5152 | int rc; | |
5153 | ||
204f4afa BH |
5154 | if (!dev->reset_fn) |
5155 | return -ENOTTY; | |
a477b9cd MZ |
5156 | |
5157 | pci_dev_save_and_disable(dev); | |
5158 | ||
5159 | rc = __pci_reset_function_locked(dev); | |
5160 | ||
5161 | pci_dev_restore(dev); | |
5162 | ||
5163 | return rc; | |
5164 | } | |
5165 | EXPORT_SYMBOL_GPL(pci_reset_function_locked); | |
5166 | ||
61cf16d8 AW |
5167 | /** |
5168 | * pci_try_reset_function - quiesce and reset a PCI device function | |
5169 | * @dev: PCI device to reset | |
5170 | * | |
5171 | * Same as above, except return -EAGAIN if unable to lock device. | |
5172 | */ | |
5173 | int pci_try_reset_function(struct pci_dev *dev) | |
5174 | { | |
5175 | int rc; | |
5176 | ||
204f4afa BH |
5177 | if (!dev->reset_fn) |
5178 | return -ENOTTY; | |
61cf16d8 | 5179 | |
b014e96d CH |
5180 | if (!pci_dev_trylock(dev)) |
5181 | return -EAGAIN; | |
61cf16d8 | 5182 | |
b014e96d | 5183 | pci_dev_save_and_disable(dev); |
52354b9d | 5184 | rc = __pci_reset_function_locked(dev); |
cb5e0d06 | 5185 | pci_dev_restore(dev); |
b014e96d | 5186 | pci_dev_unlock(dev); |
61cf16d8 | 5187 | |
61cf16d8 AW |
5188 | return rc; |
5189 | } | |
5190 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
5191 | ||
f331a859 AW |
5192 | /* Do any devices on or below this bus prevent a bus reset? */ |
5193 | static bool pci_bus_resetable(struct pci_bus *bus) | |
5194 | { | |
5195 | struct pci_dev *dev; | |
5196 | ||
35702778 DD |
5197 | |
5198 | if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
5199 | return false; | |
5200 | ||
f331a859 AW |
5201 | list_for_each_entry(dev, &bus->devices, bus_list) { |
5202 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
5203 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
5204 | return false; | |
5205 | } | |
5206 | ||
5207 | return true; | |
5208 | } | |
5209 | ||
090a3c53 AW |
5210 | /* Lock devices from the top of the tree down */ |
5211 | static void pci_bus_lock(struct pci_bus *bus) | |
5212 | { | |
5213 | struct pci_dev *dev; | |
5214 | ||
5215 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5216 | pci_dev_lock(dev); | |
5217 | if (dev->subordinate) | |
5218 | pci_bus_lock(dev->subordinate); | |
5219 | } | |
5220 | } | |
5221 | ||
5222 | /* Unlock devices from the bottom of the tree up */ | |
5223 | static void pci_bus_unlock(struct pci_bus *bus) | |
5224 | { | |
5225 | struct pci_dev *dev; | |
5226 | ||
5227 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5228 | if (dev->subordinate) | |
5229 | pci_bus_unlock(dev->subordinate); | |
5230 | pci_dev_unlock(dev); | |
5231 | } | |
5232 | } | |
5233 | ||
61cf16d8 AW |
5234 | /* Return 1 on successful lock, 0 on contention */ |
5235 | static int pci_bus_trylock(struct pci_bus *bus) | |
5236 | { | |
5237 | struct pci_dev *dev; | |
5238 | ||
5239 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5240 | if (!pci_dev_trylock(dev)) | |
5241 | goto unlock; | |
5242 | if (dev->subordinate) { | |
5243 | if (!pci_bus_trylock(dev->subordinate)) { | |
5244 | pci_dev_unlock(dev); | |
5245 | goto unlock; | |
5246 | } | |
5247 | } | |
5248 | } | |
5249 | return 1; | |
5250 | ||
5251 | unlock: | |
5252 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
5253 | if (dev->subordinate) | |
5254 | pci_bus_unlock(dev->subordinate); | |
5255 | pci_dev_unlock(dev); | |
5256 | } | |
5257 | return 0; | |
5258 | } | |
5259 | ||
f331a859 AW |
5260 | /* Do any devices on or below this slot prevent a bus reset? */ |
5261 | static bool pci_slot_resetable(struct pci_slot *slot) | |
5262 | { | |
5263 | struct pci_dev *dev; | |
5264 | ||
33ba90aa JG |
5265 | if (slot->bus->self && |
5266 | (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
5267 | return false; | |
5268 | ||
f331a859 AW |
5269 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { |
5270 | if (!dev->slot || dev->slot != slot) | |
5271 | continue; | |
5272 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
5273 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
5274 | return false; | |
5275 | } | |
5276 | ||
5277 | return true; | |
5278 | } | |
5279 | ||
090a3c53 AW |
5280 | /* Lock devices from the top of the tree down */ |
5281 | static void pci_slot_lock(struct pci_slot *slot) | |
5282 | { | |
5283 | struct pci_dev *dev; | |
5284 | ||
5285 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5286 | if (!dev->slot || dev->slot != slot) | |
5287 | continue; | |
5288 | pci_dev_lock(dev); | |
5289 | if (dev->subordinate) | |
5290 | pci_bus_lock(dev->subordinate); | |
5291 | } | |
5292 | } | |
5293 | ||
5294 | /* Unlock devices from the bottom of the tree up */ | |
5295 | static void pci_slot_unlock(struct pci_slot *slot) | |
5296 | { | |
5297 | struct pci_dev *dev; | |
5298 | ||
5299 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5300 | if (!dev->slot || dev->slot != slot) | |
5301 | continue; | |
5302 | if (dev->subordinate) | |
5303 | pci_bus_unlock(dev->subordinate); | |
5304 | pci_dev_unlock(dev); | |
5305 | } | |
5306 | } | |
5307 | ||
61cf16d8 AW |
5308 | /* Return 1 on successful lock, 0 on contention */ |
5309 | static int pci_slot_trylock(struct pci_slot *slot) | |
5310 | { | |
5311 | struct pci_dev *dev; | |
5312 | ||
5313 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5314 | if (!dev->slot || dev->slot != slot) | |
5315 | continue; | |
5316 | if (!pci_dev_trylock(dev)) | |
5317 | goto unlock; | |
5318 | if (dev->subordinate) { | |
5319 | if (!pci_bus_trylock(dev->subordinate)) { | |
5320 | pci_dev_unlock(dev); | |
5321 | goto unlock; | |
5322 | } | |
5323 | } | |
5324 | } | |
5325 | return 1; | |
5326 | ||
5327 | unlock: | |
5328 | list_for_each_entry_continue_reverse(dev, | |
5329 | &slot->bus->devices, bus_list) { | |
5330 | if (!dev->slot || dev->slot != slot) | |
5331 | continue; | |
5332 | if (dev->subordinate) | |
5333 | pci_bus_unlock(dev->subordinate); | |
5334 | pci_dev_unlock(dev); | |
5335 | } | |
5336 | return 0; | |
5337 | } | |
5338 | ||
ddefc033 AW |
5339 | /* |
5340 | * Save and disable devices from the top of the tree down while holding | |
5341 | * the @dev mutex lock for the entire tree. | |
5342 | */ | |
5343 | static void pci_bus_save_and_disable_locked(struct pci_bus *bus) | |
090a3c53 AW |
5344 | { |
5345 | struct pci_dev *dev; | |
5346 | ||
5347 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5348 | pci_dev_save_and_disable(dev); | |
5349 | if (dev->subordinate) | |
ddefc033 | 5350 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5351 | } |
5352 | } | |
5353 | ||
5354 | /* | |
ddefc033 AW |
5355 | * Restore devices from top of the tree down while holding @dev mutex lock |
5356 | * for the entire tree. Parent bridges need to be restored before we can | |
5357 | * get to subordinate devices. | |
090a3c53 | 5358 | */ |
ddefc033 | 5359 | static void pci_bus_restore_locked(struct pci_bus *bus) |
090a3c53 AW |
5360 | { |
5361 | struct pci_dev *dev; | |
5362 | ||
5363 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5364 | pci_dev_restore(dev); | |
5365 | if (dev->subordinate) | |
ddefc033 | 5366 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5367 | } |
5368 | } | |
5369 | ||
ddefc033 AW |
5370 | /* |
5371 | * Save and disable devices from the top of the tree down while holding | |
5372 | * the @dev mutex lock for the entire tree. | |
5373 | */ | |
5374 | static void pci_slot_save_and_disable_locked(struct pci_slot *slot) | |
090a3c53 AW |
5375 | { |
5376 | struct pci_dev *dev; | |
5377 | ||
5378 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5379 | if (!dev->slot || dev->slot != slot) | |
5380 | continue; | |
5381 | pci_dev_save_and_disable(dev); | |
5382 | if (dev->subordinate) | |
ddefc033 | 5383 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5384 | } |
5385 | } | |
5386 | ||
5387 | /* | |
ddefc033 AW |
5388 | * Restore devices from top of the tree down while holding @dev mutex lock |
5389 | * for the entire tree. Parent bridges need to be restored before we can | |
5390 | * get to subordinate devices. | |
090a3c53 | 5391 | */ |
ddefc033 | 5392 | static void pci_slot_restore_locked(struct pci_slot *slot) |
090a3c53 AW |
5393 | { |
5394 | struct pci_dev *dev; | |
5395 | ||
5396 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5397 | if (!dev->slot || dev->slot != slot) | |
5398 | continue; | |
5399 | pci_dev_restore(dev); | |
5400 | if (dev->subordinate) | |
ddefc033 | 5401 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5402 | } |
5403 | } | |
5404 | ||
5405 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
5406 | { | |
5407 | int rc; | |
5408 | ||
f331a859 | 5409 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
5410 | return -ENOTTY; |
5411 | ||
5412 | if (!probe) | |
5413 | pci_slot_lock(slot); | |
5414 | ||
5415 | might_sleep(); | |
5416 | ||
5417 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
5418 | ||
5419 | if (!probe) | |
5420 | pci_slot_unlock(slot); | |
5421 | ||
5422 | return rc; | |
5423 | } | |
5424 | ||
9a3d2b9b AW |
5425 | /** |
5426 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
5427 | * @slot: PCI slot to probe | |
5428 | * | |
5429 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
5430 | */ | |
5431 | int pci_probe_reset_slot(struct pci_slot *slot) | |
5432 | { | |
5433 | return pci_slot_reset(slot, 1); | |
5434 | } | |
5435 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
5436 | ||
090a3c53 | 5437 | /** |
c6a44ba9 | 5438 | * __pci_reset_slot - Try to reset a PCI slot |
090a3c53 AW |
5439 | * @slot: PCI slot to reset |
5440 | * | |
5441 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
5442 | * independent of other slots. For instance, some slots may support slot power | |
5443 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
5444 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
5445 | * Generally a slot reset should be attempted before a bus reset. All of the | |
5446 | * function of the slot and any subordinate buses behind the slot are reset | |
5447 | * through this function. PCI config space of all devices in the slot and | |
5448 | * behind the slot is saved before and restored after reset. | |
5449 | * | |
61cf16d8 AW |
5450 | * Same as above except return -EAGAIN if the slot cannot be locked |
5451 | */ | |
c6a44ba9 | 5452 | static int __pci_reset_slot(struct pci_slot *slot) |
61cf16d8 AW |
5453 | { |
5454 | int rc; | |
5455 | ||
5456 | rc = pci_slot_reset(slot, 1); | |
5457 | if (rc) | |
5458 | return rc; | |
5459 | ||
61cf16d8 | 5460 | if (pci_slot_trylock(slot)) { |
ddefc033 | 5461 | pci_slot_save_and_disable_locked(slot); |
61cf16d8 AW |
5462 | might_sleep(); |
5463 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
ddefc033 | 5464 | pci_slot_restore_locked(slot); |
61cf16d8 AW |
5465 | pci_slot_unlock(slot); |
5466 | } else | |
5467 | rc = -EAGAIN; | |
5468 | ||
61cf16d8 AW |
5469 | return rc; |
5470 | } | |
61cf16d8 | 5471 | |
090a3c53 AW |
5472 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
5473 | { | |
18426238 SK |
5474 | int ret; |
5475 | ||
f331a859 | 5476 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
5477 | return -ENOTTY; |
5478 | ||
5479 | if (probe) | |
5480 | return 0; | |
5481 | ||
5482 | pci_bus_lock(bus); | |
5483 | ||
5484 | might_sleep(); | |
5485 | ||
381634ca | 5486 | ret = pci_bridge_secondary_bus_reset(bus->self); |
090a3c53 AW |
5487 | |
5488 | pci_bus_unlock(bus); | |
5489 | ||
18426238 | 5490 | return ret; |
090a3c53 AW |
5491 | } |
5492 | ||
c4eed62a KB |
5493 | /** |
5494 | * pci_bus_error_reset - reset the bridge's subordinate bus | |
5495 | * @bridge: The parent device that connects to the bus to reset | |
5496 | * | |
5497 | * This function will first try to reset the slots on this bus if the method is | |
5498 | * available. If slot reset fails or is not available, this will fall back to a | |
5499 | * secondary bus reset. | |
5500 | */ | |
5501 | int pci_bus_error_reset(struct pci_dev *bridge) | |
5502 | { | |
5503 | struct pci_bus *bus = bridge->subordinate; | |
5504 | struct pci_slot *slot; | |
5505 | ||
5506 | if (!bus) | |
5507 | return -ENOTTY; | |
5508 | ||
5509 | mutex_lock(&pci_slot_mutex); | |
5510 | if (list_empty(&bus->slots)) | |
5511 | goto bus_reset; | |
5512 | ||
5513 | list_for_each_entry(slot, &bus->slots, list) | |
5514 | if (pci_probe_reset_slot(slot)) | |
5515 | goto bus_reset; | |
5516 | ||
5517 | list_for_each_entry(slot, &bus->slots, list) | |
5518 | if (pci_slot_reset(slot, 0)) | |
5519 | goto bus_reset; | |
5520 | ||
5521 | mutex_unlock(&pci_slot_mutex); | |
5522 | return 0; | |
5523 | bus_reset: | |
5524 | mutex_unlock(&pci_slot_mutex); | |
5525 | return pci_bus_reset(bridge->subordinate, 0); | |
5526 | } | |
5527 | ||
9a3d2b9b AW |
5528 | /** |
5529 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
5530 | * @bus: PCI bus to probe | |
5531 | * | |
5532 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
5533 | */ | |
5534 | int pci_probe_reset_bus(struct pci_bus *bus) | |
5535 | { | |
5536 | return pci_bus_reset(bus, 1); | |
5537 | } | |
5538 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
5539 | ||
090a3c53 | 5540 | /** |
c6a44ba9 | 5541 | * __pci_reset_bus - Try to reset a PCI bus |
090a3c53 AW |
5542 | * @bus: top level PCI bus to reset |
5543 | * | |
61cf16d8 | 5544 | * Same as above except return -EAGAIN if the bus cannot be locked |
090a3c53 | 5545 | */ |
c6a44ba9 | 5546 | static int __pci_reset_bus(struct pci_bus *bus) |
090a3c53 AW |
5547 | { |
5548 | int rc; | |
5549 | ||
5550 | rc = pci_bus_reset(bus, 1); | |
5551 | if (rc) | |
5552 | return rc; | |
5553 | ||
61cf16d8 | 5554 | if (pci_bus_trylock(bus)) { |
ddefc033 | 5555 | pci_bus_save_and_disable_locked(bus); |
61cf16d8 | 5556 | might_sleep(); |
381634ca | 5557 | rc = pci_bridge_secondary_bus_reset(bus->self); |
ddefc033 | 5558 | pci_bus_restore_locked(bus); |
61cf16d8 AW |
5559 | pci_bus_unlock(bus); |
5560 | } else | |
5561 | rc = -EAGAIN; | |
090a3c53 | 5562 | |
090a3c53 AW |
5563 | return rc; |
5564 | } | |
090a3c53 | 5565 | |
61cf16d8 | 5566 | /** |
c6a44ba9 | 5567 | * pci_reset_bus - Try to reset a PCI bus |
811c5cb3 | 5568 | * @pdev: top level PCI device to reset via slot/bus |
61cf16d8 AW |
5569 | * |
5570 | * Same as above except return -EAGAIN if the bus cannot be locked | |
5571 | */ | |
c6a44ba9 | 5572 | int pci_reset_bus(struct pci_dev *pdev) |
61cf16d8 | 5573 | { |
d8a52810 | 5574 | return (!pci_probe_reset_slot(pdev->slot)) ? |
c6a44ba9 | 5575 | __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); |
61cf16d8 | 5576 | } |
c6a44ba9 | 5577 | EXPORT_SYMBOL_GPL(pci_reset_bus); |
61cf16d8 | 5578 | |
d556ad4b PO |
5579 | /** |
5580 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
5581 | * @dev: PCI device to query | |
5582 | * | |
74356add BH |
5583 | * Returns mmrbc: maximum designed memory read count in bytes or |
5584 | * appropriate error value. | |
d556ad4b PO |
5585 | */ |
5586 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
5587 | { | |
7c9e2b1c | 5588 | int cap; |
d556ad4b PO |
5589 | u32 stat; |
5590 | ||
5591 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5592 | if (!cap) | |
5593 | return -EINVAL; | |
5594 | ||
7c9e2b1c | 5595 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
5596 | return -EINVAL; |
5597 | ||
25daeb55 | 5598 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
5599 | } |
5600 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
5601 | ||
5602 | /** | |
5603 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
5604 | * @dev: PCI device to query | |
5605 | * | |
74356add BH |
5606 | * Returns mmrbc: maximum memory read count in bytes or appropriate error |
5607 | * value. | |
d556ad4b PO |
5608 | */ |
5609 | int pcix_get_mmrbc(struct pci_dev *dev) | |
5610 | { | |
7c9e2b1c | 5611 | int cap; |
bdc2bda7 | 5612 | u16 cmd; |
d556ad4b PO |
5613 | |
5614 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5615 | if (!cap) | |
5616 | return -EINVAL; | |
5617 | ||
7c9e2b1c DN |
5618 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5619 | return -EINVAL; | |
d556ad4b | 5620 | |
7c9e2b1c | 5621 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
5622 | } |
5623 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
5624 | ||
5625 | /** | |
5626 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
5627 | * @dev: PCI device to query | |
5628 | * @mmrbc: maximum memory read count in bytes | |
5629 | * valid values are 512, 1024, 2048, 4096 | |
5630 | * | |
74356add | 5631 | * If possible sets maximum memory read byte count, some bridges have errata |
d556ad4b PO |
5632 | * that prevent this. |
5633 | */ | |
5634 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
5635 | { | |
7c9e2b1c | 5636 | int cap; |
bdc2bda7 DN |
5637 | u32 stat, v, o; |
5638 | u16 cmd; | |
d556ad4b | 5639 | |
229f5afd | 5640 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 5641 | return -EINVAL; |
d556ad4b PO |
5642 | |
5643 | v = ffs(mmrbc) - 10; | |
5644 | ||
5645 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5646 | if (!cap) | |
7c9e2b1c | 5647 | return -EINVAL; |
d556ad4b | 5648 | |
7c9e2b1c DN |
5649 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
5650 | return -EINVAL; | |
d556ad4b PO |
5651 | |
5652 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
5653 | return -E2BIG; | |
5654 | ||
7c9e2b1c DN |
5655 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5656 | return -EINVAL; | |
d556ad4b PO |
5657 | |
5658 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
5659 | if (o != v) { | |
809a3bf9 | 5660 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
5661 | return -EIO; |
5662 | ||
5663 | cmd &= ~PCI_X_CMD_MAX_READ; | |
5664 | cmd |= v << 2; | |
7c9e2b1c DN |
5665 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
5666 | return -EIO; | |
d556ad4b | 5667 | } |
7c9e2b1c | 5668 | return 0; |
d556ad4b PO |
5669 | } |
5670 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
5671 | ||
5672 | /** | |
5673 | * pcie_get_readrq - get PCI Express read request size | |
5674 | * @dev: PCI device to query | |
5675 | * | |
74356add | 5676 | * Returns maximum memory read request in bytes or appropriate error value. |
d556ad4b PO |
5677 | */ |
5678 | int pcie_get_readrq(struct pci_dev *dev) | |
5679 | { | |
d556ad4b PO |
5680 | u16 ctl; |
5681 | ||
59875ae4 | 5682 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 5683 | |
59875ae4 | 5684 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
5685 | } |
5686 | EXPORT_SYMBOL(pcie_get_readrq); | |
5687 | ||
5688 | /** | |
5689 | * pcie_set_readrq - set PCI Express maximum memory read request | |
5690 | * @dev: PCI device to query | |
42e61f4a | 5691 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
5692 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5693 | * | |
c9b378c7 | 5694 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
5695 | */ |
5696 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
5697 | { | |
59875ae4 | 5698 | u16 v; |
d20df83b | 5699 | int ret; |
d556ad4b | 5700 | |
229f5afd | 5701 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 5702 | return -EINVAL; |
d556ad4b | 5703 | |
a1c473aa | 5704 | /* |
74356add BH |
5705 | * If using the "performance" PCIe config, we clamp the read rq |
5706 | * size to the max packet size to keep the host bridge from | |
5707 | * generating requests larger than we can cope with. | |
a1c473aa BH |
5708 | */ |
5709 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
5710 | int mps = pcie_get_mps(dev); | |
5711 | ||
a1c473aa BH |
5712 | if (mps < rq) |
5713 | rq = mps; | |
5714 | } | |
5715 | ||
5716 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 5717 | |
d20df83b | 5718 | ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
59875ae4 | 5719 | PCI_EXP_DEVCTL_READRQ, v); |
d20df83b BOS |
5720 | |
5721 | return pcibios_err_to_errno(ret); | |
d556ad4b PO |
5722 | } |
5723 | EXPORT_SYMBOL(pcie_set_readrq); | |
5724 | ||
b03e7495 JM |
5725 | /** |
5726 | * pcie_get_mps - get PCI Express maximum payload size | |
5727 | * @dev: PCI device to query | |
5728 | * | |
5729 | * Returns maximum payload size in bytes | |
b03e7495 JM |
5730 | */ |
5731 | int pcie_get_mps(struct pci_dev *dev) | |
5732 | { | |
b03e7495 JM |
5733 | u16 ctl; |
5734 | ||
59875ae4 | 5735 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 5736 | |
59875ae4 | 5737 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 5738 | } |
f1c66c46 | 5739 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
5740 | |
5741 | /** | |
5742 | * pcie_set_mps - set PCI Express maximum payload size | |
5743 | * @dev: PCI device to query | |
47c08f31 | 5744 | * @mps: maximum payload size in bytes |
b03e7495 JM |
5745 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5746 | * | |
5747 | * If possible sets maximum payload size | |
5748 | */ | |
5749 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
5750 | { | |
59875ae4 | 5751 | u16 v; |
d20df83b | 5752 | int ret; |
b03e7495 JM |
5753 | |
5754 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 5755 | return -EINVAL; |
b03e7495 JM |
5756 | |
5757 | v = ffs(mps) - 8; | |
f7625980 | 5758 | if (v > dev->pcie_mpss) |
59875ae4 | 5759 | return -EINVAL; |
b03e7495 JM |
5760 | v <<= 5; |
5761 | ||
d20df83b | 5762 | ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
59875ae4 | 5763 | PCI_EXP_DEVCTL_PAYLOAD, v); |
d20df83b BOS |
5764 | |
5765 | return pcibios_err_to_errno(ret); | |
b03e7495 | 5766 | } |
f1c66c46 | 5767 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 5768 | |
6db79a88 TG |
5769 | /** |
5770 | * pcie_bandwidth_available - determine minimum link settings of a PCIe | |
5771 | * device and its bandwidth limitation | |
5772 | * @dev: PCI device to query | |
5773 | * @limiting_dev: storage for device causing the bandwidth limitation | |
5774 | * @speed: storage for speed of limiting device | |
5775 | * @width: storage for width of limiting device | |
5776 | * | |
5777 | * Walk up the PCI device chain and find the point where the minimum | |
5778 | * bandwidth is available. Return the bandwidth available there and (if | |
5779 | * limiting_dev, speed, and width pointers are supplied) information about | |
5780 | * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of | |
5781 | * raw bandwidth. | |
5782 | */ | |
5783 | u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, | |
5784 | enum pci_bus_speed *speed, | |
5785 | enum pcie_link_width *width) | |
5786 | { | |
5787 | u16 lnksta; | |
5788 | enum pci_bus_speed next_speed; | |
5789 | enum pcie_link_width next_width; | |
5790 | u32 bw, next_bw; | |
5791 | ||
5792 | if (speed) | |
5793 | *speed = PCI_SPEED_UNKNOWN; | |
5794 | if (width) | |
5795 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
5796 | ||
5797 | bw = 0; | |
5798 | ||
5799 | while (dev) { | |
5800 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
5801 | ||
5802 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
5803 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
5804 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
5805 | ||
5806 | next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); | |
5807 | ||
5808 | /* Check if current device limits the total bandwidth */ | |
5809 | if (!bw || next_bw <= bw) { | |
5810 | bw = next_bw; | |
5811 | ||
5812 | if (limiting_dev) | |
5813 | *limiting_dev = dev; | |
5814 | if (speed) | |
5815 | *speed = next_speed; | |
5816 | if (width) | |
5817 | *width = next_width; | |
5818 | } | |
5819 | ||
5820 | dev = pci_upstream_bridge(dev); | |
5821 | } | |
5822 | ||
5823 | return bw; | |
5824 | } | |
5825 | EXPORT_SYMBOL(pcie_bandwidth_available); | |
5826 | ||
6cf57be0 TG |
5827 | /** |
5828 | * pcie_get_speed_cap - query for the PCI device's link speed capability | |
5829 | * @dev: PCI device to query | |
5830 | * | |
5831 | * Query the PCI device speed capability. Return the maximum link speed | |
5832 | * supported by the device. | |
5833 | */ | |
5834 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) | |
5835 | { | |
5836 | u32 lnkcap2, lnkcap; | |
5837 | ||
5838 | /* | |
f1f90e25 MP |
5839 | * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The |
5840 | * implementation note there recommends using the Supported Link | |
5841 | * Speeds Vector in Link Capabilities 2 when supported. | |
5842 | * | |
5843 | * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software | |
5844 | * should use the Supported Link Speeds field in Link Capabilities, | |
5845 | * where only 2.5 GT/s and 5.0 GT/s speeds were defined. | |
6cf57be0 TG |
5846 | */ |
5847 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); | |
757bfaa2 YY |
5848 | |
5849 | /* PCIe r3.0-compliant */ | |
5850 | if (lnkcap2) | |
5851 | return PCIE_LNKCAP2_SLS2SPEED(lnkcap2); | |
6cf57be0 TG |
5852 | |
5853 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
f1f90e25 MP |
5854 | if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) |
5855 | return PCIE_SPEED_5_0GT; | |
5856 | else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) | |
5857 | return PCIE_SPEED_2_5GT; | |
6cf57be0 TG |
5858 | |
5859 | return PCI_SPEED_UNKNOWN; | |
5860 | } | |
576c7218 | 5861 | EXPORT_SYMBOL(pcie_get_speed_cap); |
6cf57be0 | 5862 | |
c70b65fb TG |
5863 | /** |
5864 | * pcie_get_width_cap - query for the PCI device's link width capability | |
5865 | * @dev: PCI device to query | |
5866 | * | |
5867 | * Query the PCI device width capability. Return the maximum link width | |
5868 | * supported by the device. | |
5869 | */ | |
5870 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) | |
5871 | { | |
5872 | u32 lnkcap; | |
5873 | ||
5874 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
5875 | if (lnkcap) | |
5876 | return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; | |
5877 | ||
5878 | return PCIE_LNK_WIDTH_UNKNOWN; | |
5879 | } | |
576c7218 | 5880 | EXPORT_SYMBOL(pcie_get_width_cap); |
c70b65fb | 5881 | |
b852f63a TG |
5882 | /** |
5883 | * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability | |
5884 | * @dev: PCI device | |
5885 | * @speed: storage for link speed | |
5886 | * @width: storage for link width | |
5887 | * | |
5888 | * Calculate a PCI device's link bandwidth by querying for its link speed | |
5889 | * and width, multiplying them, and applying encoding overhead. The result | |
5890 | * is in Mb/s, i.e., megabits/second of raw bandwidth. | |
5891 | */ | |
5892 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, | |
5893 | enum pcie_link_width *width) | |
5894 | { | |
5895 | *speed = pcie_get_speed_cap(dev); | |
5896 | *width = pcie_get_width_cap(dev); | |
5897 | ||
5898 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
5899 | return 0; | |
5900 | ||
5901 | return *width * PCIE_SPEED2MBS_ENC(*speed); | |
5902 | } | |
5903 | ||
9e506a7b | 5904 | /** |
2d1ce5ec | 5905 | * __pcie_print_link_status - Report the PCI device's link speed and width |
9e506a7b | 5906 | * @dev: PCI device to query |
2d1ce5ec | 5907 | * @verbose: Print info even when enough bandwidth is available |
9e506a7b | 5908 | * |
2d1ce5ec AG |
5909 | * If the available bandwidth at the device is less than the device is |
5910 | * capable of, report the device's maximum possible bandwidth and the | |
5911 | * upstream link that limits its performance. If @verbose, always print | |
5912 | * the available bandwidth, even if the device isn't constrained. | |
9e506a7b | 5913 | */ |
2d1ce5ec | 5914 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose) |
9e506a7b TG |
5915 | { |
5916 | enum pcie_link_width width, width_cap; | |
5917 | enum pci_bus_speed speed, speed_cap; | |
5918 | struct pci_dev *limiting_dev = NULL; | |
5919 | u32 bw_avail, bw_cap; | |
5920 | ||
5921 | bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap); | |
5922 | bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width); | |
5923 | ||
2d1ce5ec | 5924 | if (bw_avail >= bw_cap && verbose) |
0cf22d6b | 5925 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n", |
9e506a7b | 5926 | bw_cap / 1000, bw_cap % 1000, |
6348a34d | 5927 | pci_speed_string(speed_cap), width_cap); |
2d1ce5ec | 5928 | else if (bw_avail < bw_cap) |
0cf22d6b | 5929 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n", |
9e506a7b | 5930 | bw_avail / 1000, bw_avail % 1000, |
6348a34d | 5931 | pci_speed_string(speed), width, |
9e506a7b TG |
5932 | limiting_dev ? pci_name(limiting_dev) : "<unknown>", |
5933 | bw_cap / 1000, bw_cap % 1000, | |
6348a34d | 5934 | pci_speed_string(speed_cap), width_cap); |
9e506a7b | 5935 | } |
2d1ce5ec AG |
5936 | |
5937 | /** | |
5938 | * pcie_print_link_status - Report the PCI device's link speed and width | |
5939 | * @dev: PCI device to query | |
5940 | * | |
5941 | * Report the available bandwidth at the device. | |
5942 | */ | |
5943 | void pcie_print_link_status(struct pci_dev *dev) | |
5944 | { | |
5945 | __pcie_print_link_status(dev, true); | |
5946 | } | |
9e506a7b TG |
5947 | EXPORT_SYMBOL(pcie_print_link_status); |
5948 | ||
c87deff7 HS |
5949 | /** |
5950 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 5951 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
5952 | * @flags: resource type mask to be selected |
5953 | * | |
5954 | * This helper routine makes bar mask from the type of resource. | |
5955 | */ | |
5956 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
5957 | { | |
5958 | int i, bars = 0; | |
5959 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
5960 | if (pci_resource_flags(dev, i) & flags) | |
5961 | bars |= (1 << i); | |
5962 | return bars; | |
5963 | } | |
b7fe9434 | 5964 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 5965 | |
95a8b6ef MT |
5966 | /* Some architectures require additional programming to enable VGA */ |
5967 | static arch_set_vga_state_t arch_set_vga_state; | |
5968 | ||
5969 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
5970 | { | |
5971 | arch_set_vga_state = func; /* NULL disables */ | |
5972 | } | |
5973 | ||
5974 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 5975 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
5976 | { |
5977 | if (arch_set_vga_state) | |
5978 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 5979 | flags); |
95a8b6ef MT |
5980 | return 0; |
5981 | } | |
5982 | ||
deb2d2ec BH |
5983 | /** |
5984 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
5985 | * @dev: the PCI device |
5986 | * @decode: true = enable decoding, false = disable decoding | |
5987 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 5988 | * @flags: traverse ancestors and change bridges |
3448a19d | 5989 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
5990 | */ |
5991 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 5992 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
5993 | { |
5994 | struct pci_bus *bus; | |
5995 | struct pci_dev *bridge; | |
5996 | u16 cmd; | |
95a8b6ef | 5997 | int rc; |
deb2d2ec | 5998 | |
67ebd814 | 5999 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 6000 | |
95a8b6ef | 6001 | /* ARCH specific VGA enables */ |
3448a19d | 6002 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
6003 | if (rc) |
6004 | return rc; | |
6005 | ||
3448a19d DA |
6006 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
6007 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
6008 | if (decode == true) | |
6009 | cmd |= command_bits; | |
6010 | else | |
6011 | cmd &= ~command_bits; | |
6012 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
6013 | } | |
deb2d2ec | 6014 | |
3448a19d | 6015 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
6016 | return 0; |
6017 | ||
6018 | bus = dev->bus; | |
6019 | while (bus) { | |
6020 | bridge = bus->self; | |
6021 | if (bridge) { | |
6022 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
6023 | &cmd); | |
6024 | if (decode == true) | |
6025 | cmd |= PCI_BRIDGE_CTL_VGA; | |
6026 | else | |
6027 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
6028 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
6029 | cmd); | |
6030 | } | |
6031 | bus = bus->parent; | |
6032 | } | |
6033 | return 0; | |
6034 | } | |
6035 | ||
52525b7a KHF |
6036 | #ifdef CONFIG_ACPI |
6037 | bool pci_pr3_present(struct pci_dev *pdev) | |
6038 | { | |
6039 | struct acpi_device *adev; | |
6040 | ||
6041 | if (acpi_disabled) | |
6042 | return false; | |
6043 | ||
6044 | adev = ACPI_COMPANION(&pdev->dev); | |
6045 | if (!adev) | |
6046 | return false; | |
6047 | ||
6048 | return adev->power.flags.power_resources && | |
6049 | acpi_has_method(adev->handle, "_PR3"); | |
6050 | } | |
6051 | EXPORT_SYMBOL_GPL(pci_pr3_present); | |
6052 | #endif | |
6053 | ||
f0af9593 BH |
6054 | /** |
6055 | * pci_add_dma_alias - Add a DMA devfn alias for a device | |
6056 | * @dev: the PCI device for which alias is added | |
09298542 JS |
6057 | * @devfn_from: alias slot and function |
6058 | * @nr_devfns: number of subsequent devfns to alias | |
f0af9593 | 6059 | * |
f778a0d2 LG |
6060 | * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask |
6061 | * which is used to program permissible bus-devfn source addresses for DMA | |
6062 | * requests in an IOMMU. These aliases factor into IOMMU group creation | |
6063 | * and are useful for devices generating DMA requests beyond or different | |
6064 | * from their logical bus-devfn. Examples include device quirks where the | |
6065 | * device simply uses the wrong devfn, as well as non-transparent bridges | |
6066 | * where the alias may be a proxy for devices in another domain. | |
6067 | * | |
6068 | * IOMMU group creation is performed during device discovery or addition, | |
6069 | * prior to any potential DMA mapping and therefore prior to driver probing | |
6070 | * (especially for userspace assigned devices where IOMMU group definition | |
6071 | * cannot be left as a userspace activity). DMA aliases should therefore | |
6072 | * be configured via quirks, such as the PCI fixup header quirk. | |
f0af9593 | 6073 | */ |
09298542 | 6074 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns) |
f0af9593 | 6075 | { |
09298542 JS |
6076 | int devfn_to; |
6077 | ||
6078 | nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from); | |
6079 | devfn_to = devfn_from + nr_devfns - 1; | |
6080 | ||
338c3149 | 6081 | if (!dev->dma_alias_mask) |
f8bf2aeb | 6082 | dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); |
338c3149 | 6083 | if (!dev->dma_alias_mask) { |
7506dc79 | 6084 | pci_warn(dev, "Unable to allocate DMA alias mask\n"); |
338c3149 JL |
6085 | return; |
6086 | } | |
6087 | ||
09298542 JS |
6088 | bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); |
6089 | ||
6090 | if (nr_devfns == 1) | |
6091 | pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n", | |
6092 | PCI_SLOT(devfn_from), PCI_FUNC(devfn_from)); | |
6093 | else if (nr_devfns > 1) | |
6094 | pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n", | |
6095 | PCI_SLOT(devfn_from), PCI_FUNC(devfn_from), | |
6096 | PCI_SLOT(devfn_to), PCI_FUNC(devfn_to)); | |
f0af9593 BH |
6097 | } |
6098 | ||
338c3149 JL |
6099 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) |
6100 | { | |
6101 | return (dev1->dma_alias_mask && | |
6102 | test_bit(dev2->devfn, dev1->dma_alias_mask)) || | |
6103 | (dev2->dma_alias_mask && | |
2856ba60 JD |
6104 | test_bit(dev1->devfn, dev2->dma_alias_mask)) || |
6105 | pci_real_dma_dev(dev1) == dev2 || | |
6106 | pci_real_dma_dev(dev2) == dev1; | |
338c3149 JL |
6107 | } |
6108 | ||
8496e85c RW |
6109 | bool pci_device_is_present(struct pci_dev *pdev) |
6110 | { | |
6111 | u32 v; | |
6112 | ||
fe2bd75b KB |
6113 | if (pci_dev_is_disconnected(pdev)) |
6114 | return false; | |
8496e85c RW |
6115 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); |
6116 | } | |
6117 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
6118 | ||
08249651 RW |
6119 | void pci_ignore_hotplug(struct pci_dev *dev) |
6120 | { | |
6121 | struct pci_dev *bridge = dev->bus->self; | |
6122 | ||
6123 | dev->ignore_hotplug = 1; | |
6124 | /* Propagate the "ignore hotplug" setting to the parent bridge. */ | |
6125 | if (bridge) | |
6126 | bridge->ignore_hotplug = 1; | |
6127 | } | |
6128 | EXPORT_SYMBOL_GPL(pci_ignore_hotplug); | |
6129 | ||
2856ba60 JD |
6130 | /** |
6131 | * pci_real_dma_dev - Get PCI DMA device for PCI device | |
6132 | * @dev: the PCI device that may have a PCI DMA alias | |
6133 | * | |
6134 | * Permits the platform to provide architecture-specific functionality to | |
6135 | * devices needing to alias DMA to another PCI device on another PCI bus. If | |
6136 | * the PCI device is on the same bus, it is recommended to use | |
6137 | * pci_add_dma_alias(). This is the default implementation. Architecture | |
6138 | * implementations can override this. | |
6139 | */ | |
6140 | struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev) | |
6141 | { | |
6142 | return dev; | |
6143 | } | |
6144 | ||
0a701aa6 YX |
6145 | resource_size_t __weak pcibios_default_alignment(void) |
6146 | { | |
6147 | return 0; | |
6148 | } | |
6149 | ||
b8074aa2 DE |
6150 | /* |
6151 | * Arches that don't want to expose struct resource to userland as-is in | |
6152 | * sysfs and /proc can implement their own pci_resource_to_user(). | |
6153 | */ | |
6154 | void __weak pci_resource_to_user(const struct pci_dev *dev, int bar, | |
6155 | const struct resource *rsrc, | |
6156 | resource_size_t *start, resource_size_t *end) | |
6157 | { | |
6158 | *start = rsrc->start; | |
6159 | *end = rsrc->end; | |
6160 | } | |
6161 | ||
70aaf61a | 6162 | static char *resource_alignment_param; |
e9d1e492 | 6163 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
6164 | |
6165 | /** | |
6166 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
6167 | * @dev: the PCI device to get | |
e3adec72 | 6168 | * @resize: whether or not to change resources' size when reassigning alignment |
32a9a682 YS |
6169 | * |
6170 | * RETURNS: Resource alignment if it is specified. | |
6171 | * Zero if it is not specified. | |
6172 | */ | |
e3adec72 YX |
6173 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, |
6174 | bool *resize) | |
32a9a682 | 6175 | { |
07d8d7e5 | 6176 | int align_order, count; |
0a701aa6 | 6177 | resource_size_t align = pcibios_default_alignment(); |
07d8d7e5 LG |
6178 | const char *p; |
6179 | int ret; | |
32a9a682 YS |
6180 | |
6181 | spin_lock(&resource_alignment_lock); | |
6182 | p = resource_alignment_param; | |
70aaf61a | 6183 | if (!p || !*p) |
f0b99f70 YX |
6184 | goto out; |
6185 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
0a701aa6 | 6186 | align = 0; |
f0b99f70 YX |
6187 | pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n"); |
6188 | goto out; | |
6189 | } | |
6190 | ||
32a9a682 YS |
6191 | while (*p) { |
6192 | count = 0; | |
6193 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
6194 | p[count] == '@') { | |
6195 | p += count + 1; | |
6196 | } else { | |
6197 | align_order = -1; | |
6198 | } | |
07d8d7e5 LG |
6199 | |
6200 | ret = pci_dev_str_match(dev, p, &p); | |
6201 | if (ret == 1) { | |
6202 | *resize = true; | |
6203 | if (align_order == -1) | |
6204 | align = PAGE_SIZE; | |
6205 | else | |
6206 | align = 1 << align_order; | |
6207 | break; | |
6208 | } else if (ret < 0) { | |
6209 | pr_err("PCI: Can't parse resource_alignment parameter: %s\n", | |
6210 | p); | |
6211 | break; | |
32a9a682 | 6212 | } |
07d8d7e5 | 6213 | |
32a9a682 YS |
6214 | if (*p != ';' && *p != ',') { |
6215 | /* End of param or invalid format */ | |
6216 | break; | |
6217 | } | |
6218 | p++; | |
6219 | } | |
f0b99f70 | 6220 | out: |
32a9a682 YS |
6221 | spin_unlock(&resource_alignment_lock); |
6222 | return align; | |
6223 | } | |
6224 | ||
81a5e70e | 6225 | static void pci_request_resource_alignment(struct pci_dev *dev, int bar, |
e3adec72 | 6226 | resource_size_t align, bool resize) |
81a5e70e BH |
6227 | { |
6228 | struct resource *r = &dev->resource[bar]; | |
6229 | resource_size_t size; | |
6230 | ||
6231 | if (!(r->flags & IORESOURCE_MEM)) | |
6232 | return; | |
6233 | ||
6234 | if (r->flags & IORESOURCE_PCI_FIXED) { | |
7506dc79 | 6235 | pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n", |
81a5e70e BH |
6236 | bar, r, (unsigned long long)align); |
6237 | return; | |
6238 | } | |
6239 | ||
6240 | size = resource_size(r); | |
0dde1c08 BH |
6241 | if (size >= align) |
6242 | return; | |
81a5e70e | 6243 | |
0dde1c08 | 6244 | /* |
e3adec72 YX |
6245 | * Increase the alignment of the resource. There are two ways we |
6246 | * can do this: | |
0dde1c08 | 6247 | * |
e3adec72 YX |
6248 | * 1) Increase the size of the resource. BARs are aligned on their |
6249 | * size, so when we reallocate space for this resource, we'll | |
6250 | * allocate it with the larger alignment. This also prevents | |
6251 | * assignment of any other BARs inside the alignment region, so | |
6252 | * if we're requesting page alignment, this means no other BARs | |
6253 | * will share the page. | |
6254 | * | |
6255 | * The disadvantage is that this makes the resource larger than | |
6256 | * the hardware BAR, which may break drivers that compute things | |
6257 | * based on the resource size, e.g., to find registers at a | |
6258 | * fixed offset before the end of the BAR. | |
6259 | * | |
6260 | * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and | |
6261 | * set r->start to the desired alignment. By itself this | |
6262 | * doesn't prevent other BARs being put inside the alignment | |
6263 | * region, but if we realign *every* resource of every device in | |
6264 | * the system, none of them will share an alignment region. | |
6265 | * | |
6266 | * When the user has requested alignment for only some devices via | |
6267 | * the "pci=resource_alignment" argument, "resize" is true and we | |
6268 | * use the first method. Otherwise we assume we're aligning all | |
6269 | * devices and we use the second. | |
0dde1c08 | 6270 | */ |
e3adec72 | 6271 | |
7506dc79 | 6272 | pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n", |
0dde1c08 | 6273 | bar, r, (unsigned long long)align); |
81a5e70e | 6274 | |
e3adec72 YX |
6275 | if (resize) { |
6276 | r->start = 0; | |
6277 | r->end = align - 1; | |
6278 | } else { | |
6279 | r->flags &= ~IORESOURCE_SIZEALIGN; | |
6280 | r->flags |= IORESOURCE_STARTALIGN; | |
6281 | r->start = align; | |
6282 | r->end = r->start + size - 1; | |
6283 | } | |
0dde1c08 | 6284 | r->flags |= IORESOURCE_UNSET; |
81a5e70e BH |
6285 | } |
6286 | ||
2069ecfb YL |
6287 | /* |
6288 | * This function disables memory decoding and releases memory resources | |
6289 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
6290 | * It also rounds up size to specified alignment. | |
6291 | * Later on, the kernel will assign page-aligned memory resource back | |
6292 | * to the device. | |
6293 | */ | |
6294 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
6295 | { | |
6296 | int i; | |
6297 | struct resource *r; | |
81a5e70e | 6298 | resource_size_t align; |
2069ecfb | 6299 | u16 command; |
e3adec72 | 6300 | bool resize = false; |
2069ecfb | 6301 | |
62d9a78f YX |
6302 | /* |
6303 | * VF BARs are read-only zero according to SR-IOV spec r1.1, sec | |
6304 | * 3.4.1.11. Their resources are allocated from the space | |
6305 | * described by the VF BARx register in the PF's SR-IOV capability. | |
6306 | * We can't influence their alignment here. | |
6307 | */ | |
6308 | if (dev->is_virtfn) | |
6309 | return; | |
6310 | ||
10c463a7 | 6311 | /* check if specified PCI is target device to reassign */ |
e3adec72 | 6312 | align = pci_specified_resource_alignment(dev, &resize); |
10c463a7 | 6313 | if (!align) |
2069ecfb YL |
6314 | return; |
6315 | ||
6316 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
6317 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
7506dc79 | 6318 | pci_warn(dev, "Can't reassign resources to host bridge\n"); |
2069ecfb YL |
6319 | return; |
6320 | } | |
6321 | ||
2069ecfb YL |
6322 | pci_read_config_word(dev, PCI_COMMAND, &command); |
6323 | command &= ~PCI_COMMAND_MEMORY; | |
6324 | pci_write_config_word(dev, PCI_COMMAND, command); | |
6325 | ||
81a5e70e | 6326 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) |
e3adec72 | 6327 | pci_request_resource_alignment(dev, i, align, resize); |
f0b99f70 | 6328 | |
81a5e70e BH |
6329 | /* |
6330 | * Need to disable bridge's resource window, | |
2069ecfb YL |
6331 | * to enable the kernel to reassign new resource |
6332 | * window later on. | |
6333 | */ | |
b2fb5cc5 | 6334 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { |
2069ecfb YL |
6335 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { |
6336 | r = &dev->resource[i]; | |
6337 | if (!(r->flags & IORESOURCE_MEM)) | |
6338 | continue; | |
bd064f0a | 6339 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
6340 | r->end = resource_size(r) - 1; |
6341 | r->start = 0; | |
6342 | } | |
6343 | pci_disable_bridge_window(dev); | |
6344 | } | |
6345 | } | |
6346 | ||
273b177c | 6347 | static ssize_t resource_alignment_show(struct bus_type *bus, char *buf) |
32a9a682 | 6348 | { |
70aaf61a | 6349 | size_t count = 0; |
32a9a682 | 6350 | |
32a9a682 | 6351 | spin_lock(&resource_alignment_lock); |
70aaf61a | 6352 | if (resource_alignment_param) |
273b177c | 6353 | count = snprintf(buf, PAGE_SIZE, "%s", resource_alignment_param); |
32a9a682 | 6354 | spin_unlock(&resource_alignment_lock); |
32a9a682 | 6355 | |
e499081d LG |
6356 | /* |
6357 | * When set by the command line, resource_alignment_param will not | |
6358 | * have a trailing line feed, which is ugly. So conditionally add | |
6359 | * it here. | |
6360 | */ | |
6361 | if (count >= 2 && buf[count - 2] != '\n' && count < PAGE_SIZE - 1) { | |
6362 | buf[count - 1] = '\n'; | |
6363 | buf[count++] = 0; | |
6364 | } | |
6365 | ||
32a9a682 | 6366 | return count; |
32a9a682 YS |
6367 | } |
6368 | ||
d61dfafc | 6369 | static ssize_t resource_alignment_store(struct bus_type *bus, |
32a9a682 YS |
6370 | const char *buf, size_t count) |
6371 | { | |
273b177c LG |
6372 | char *param = kstrndup(buf, count, GFP_KERNEL); |
6373 | ||
6374 | if (!param) | |
6375 | return -ENOMEM; | |
6376 | ||
6377 | spin_lock(&resource_alignment_lock); | |
6378 | kfree(resource_alignment_param); | |
6379 | resource_alignment_param = param; | |
6380 | spin_unlock(&resource_alignment_lock); | |
6381 | return count; | |
32a9a682 YS |
6382 | } |
6383 | ||
d61dfafc | 6384 | static BUS_ATTR_RW(resource_alignment); |
32a9a682 YS |
6385 | |
6386 | static int __init pci_resource_alignment_sysfs_init(void) | |
6387 | { | |
6388 | return bus_create_file(&pci_bus_type, | |
6389 | &bus_attr_resource_alignment); | |
6390 | } | |
32a9a682 YS |
6391 | late_initcall(pci_resource_alignment_sysfs_init); |
6392 | ||
15856ad5 | 6393 | static void pci_no_domains(void) |
32a2eea7 JG |
6394 | { |
6395 | #ifdef CONFIG_PCI_DOMAINS | |
6396 | pci_domains_supported = 0; | |
6397 | #endif | |
6398 | } | |
6399 | ||
ae07b786 | 6400 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
41e5c0f8 LD |
6401 | static atomic_t __domain_nr = ATOMIC_INIT(-1); |
6402 | ||
ae07b786 | 6403 | static int pci_get_new_domain_nr(void) |
41e5c0f8 LD |
6404 | { |
6405 | return atomic_inc_return(&__domain_nr); | |
6406 | } | |
7c674700 | 6407 | |
1a4f93f7 | 6408 | static int of_pci_bus_find_domain_nr(struct device *parent) |
7c674700 LP |
6409 | { |
6410 | static int use_dt_domains = -1; | |
54c6e2dd | 6411 | int domain = -1; |
7c674700 | 6412 | |
54c6e2dd KHC |
6413 | if (parent) |
6414 | domain = of_get_pci_domain_nr(parent->of_node); | |
74356add | 6415 | |
7c674700 LP |
6416 | /* |
6417 | * Check DT domain and use_dt_domains values. | |
6418 | * | |
6419 | * If DT domain property is valid (domain >= 0) and | |
6420 | * use_dt_domains != 0, the DT assignment is valid since this means | |
6421 | * we have not previously allocated a domain number by using | |
6422 | * pci_get_new_domain_nr(); we should also update use_dt_domains to | |
6423 | * 1, to indicate that we have just assigned a domain number from | |
6424 | * DT. | |
6425 | * | |
6426 | * If DT domain property value is not valid (ie domain < 0), and we | |
6427 | * have not previously assigned a domain number from DT | |
6428 | * (use_dt_domains != 1) we should assign a domain number by | |
6429 | * using the: | |
6430 | * | |
6431 | * pci_get_new_domain_nr() | |
6432 | * | |
6433 | * API and update the use_dt_domains value to keep track of method we | |
6434 | * are using to assign domain numbers (use_dt_domains = 0). | |
6435 | * | |
6436 | * All other combinations imply we have a platform that is trying | |
6437 | * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), | |
6438 | * which is a recipe for domain mishandling and it is prevented by | |
6439 | * invalidating the domain value (domain = -1) and printing a | |
6440 | * corresponding error. | |
6441 | */ | |
6442 | if (domain >= 0 && use_dt_domains) { | |
6443 | use_dt_domains = 1; | |
6444 | } else if (domain < 0 && use_dt_domains != 1) { | |
6445 | use_dt_domains = 0; | |
6446 | domain = pci_get_new_domain_nr(); | |
6447 | } else { | |
9df1c6ec SL |
6448 | if (parent) |
6449 | pr_err("Node %pOF has ", parent->of_node); | |
6450 | pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); | |
7c674700 LP |
6451 | domain = -1; |
6452 | } | |
6453 | ||
9c7cb891 | 6454 | return domain; |
7c674700 | 6455 | } |
1a4f93f7 TN |
6456 | |
6457 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) | |
6458 | { | |
2ab51dde TN |
6459 | return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : |
6460 | acpi_pci_bus_find_domain_nr(bus); | |
7c674700 LP |
6461 | } |
6462 | #endif | |
41e5c0f8 | 6463 | |
0ef5f8f6 | 6464 | /** |
642c92da | 6465 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
6466 | * |
6467 | * Returns 1 if we can access PCI extended config space (offsets | |
6468 | * greater than 0xff). This is the default implementation. Architecture | |
6469 | * implementations can override this. | |
6470 | */ | |
642c92da | 6471 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
6472 | { |
6473 | return 1; | |
6474 | } | |
6475 | ||
2d1c8618 BH |
6476 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
6477 | { | |
6478 | } | |
6479 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
6480 | ||
ad04d31e | 6481 | static int __init pci_setup(char *str) |
1da177e4 LT |
6482 | { |
6483 | while (str) { | |
6484 | char *k = strchr(str, ','); | |
6485 | if (k) | |
6486 | *k++ = 0; | |
6487 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
6488 | if (!strcmp(str, "nomsi")) { |
6489 | pci_no_msi(); | |
cef74409 GK |
6490 | } else if (!strncmp(str, "noats", 5)) { |
6491 | pr_info("PCIe: ATS is disabled\n"); | |
6492 | pcie_ats_disabled = true; | |
7f785763 RD |
6493 | } else if (!strcmp(str, "noaer")) { |
6494 | pci_no_aer(); | |
11eb0e0e SK |
6495 | } else if (!strcmp(str, "earlydump")) { |
6496 | pci_early_dump = true; | |
b55438fd YL |
6497 | } else if (!strncmp(str, "realloc=", 8)) { |
6498 | pci_realloc_get_opt(str + 8); | |
f483d392 | 6499 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 6500 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
6501 | } else if (!strcmp(str, "nodomains")) { |
6502 | pci_no_domains(); | |
6748dcc2 RW |
6503 | } else if (!strncmp(str, "noari", 5)) { |
6504 | pcie_ari_disabled = true; | |
4516a618 AN |
6505 | } else if (!strncmp(str, "cbiosize=", 9)) { |
6506 | pci_cardbus_io_size = memparse(str + 9, &str); | |
6507 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
6508 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 | 6509 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
70aaf61a | 6510 | resource_alignment_param = str + 19; |
43c16408 AP |
6511 | } else if (!strncmp(str, "ecrc=", 5)) { |
6512 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
6513 | } else if (!strncmp(str, "hpiosize=", 9)) { |
6514 | pci_hotplug_io_size = memparse(str + 9, &str); | |
d7b8a217 NJ |
6515 | } else if (!strncmp(str, "hpmmiosize=", 11)) { |
6516 | pci_hotplug_mmio_size = memparse(str + 11, &str); | |
6517 | } else if (!strncmp(str, "hpmmioprefsize=", 15)) { | |
6518 | pci_hotplug_mmio_pref_size = memparse(str + 15, &str); | |
28760489 | 6519 | } else if (!strncmp(str, "hpmemsize=", 10)) { |
d7b8a217 NJ |
6520 | pci_hotplug_mmio_size = memparse(str + 10, &str); |
6521 | pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size; | |
e16b4660 KB |
6522 | } else if (!strncmp(str, "hpbussize=", 10)) { |
6523 | pci_hotplug_bus_size = | |
6524 | simple_strtoul(str + 10, &str, 0); | |
6525 | if (pci_hotplug_bus_size > 0xff) | |
6526 | pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
5f39e670 JM |
6527 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
6528 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
6529 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
6530 | pcie_bus_config = PCIE_BUS_SAFE; | |
6531 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
6532 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
6533 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
6534 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
6535 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
6536 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
aaca43fd | 6537 | } else if (!strncmp(str, "disable_acs_redir=", 18)) { |
d5bc73f3 | 6538 | disable_acs_redir_param = str + 18; |
309e57df | 6539 | } else { |
25da8dba | 6540 | pr_err("PCI: Unknown option `%s'\n", str); |
309e57df | 6541 | } |
1da177e4 LT |
6542 | } |
6543 | str = k; | |
6544 | } | |
0637a70a | 6545 | return 0; |
1da177e4 | 6546 | } |
0637a70a | 6547 | early_param("pci", pci_setup); |
d5bc73f3 LG |
6548 | |
6549 | /* | |
70aaf61a LG |
6550 | * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized |
6551 | * in pci_setup(), above, to point to data in the __initdata section which | |
6552 | * will be freed after the init sequence is complete. We can't allocate memory | |
6553 | * in pci_setup() because some architectures do not have any memory allocation | |
6554 | * service available during an early_param() call. So we allocate memory and | |
6555 | * copy the variable here before the init section is freed. | |
6556 | * | |
d5bc73f3 LG |
6557 | */ |
6558 | static int __init pci_realloc_setup_params(void) | |
6559 | { | |
70aaf61a LG |
6560 | resource_alignment_param = kstrdup(resource_alignment_param, |
6561 | GFP_KERNEL); | |
d5bc73f3 LG |
6562 | disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL); |
6563 | ||
6564 | return 0; | |
6565 | } | |
6566 | pure_initcall(pci_realloc_setup_params); |