Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
1da177e4 | 4 | * |
df62ab5e BH |
5 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
6 | * David Mosberger-Tang | |
1da177e4 | 7 | * |
df62ab5e | 8 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> |
1da177e4 LT |
9 | */ |
10 | ||
2ab51dde | 11 | #include <linux/acpi.h> |
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/delay.h> | |
9d26d3a8 | 14 | #include <linux/dmi.h> |
1da177e4 | 15 | #include <linux/init.h> |
7c674700 LP |
16 | #include <linux/of.h> |
17 | #include <linux/of_pci.h> | |
1da177e4 | 18 | #include <linux/pci.h> |
075c1771 | 19 | #include <linux/pm.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1da177e4 LT |
21 | #include <linux/module.h> |
22 | #include <linux/spinlock.h> | |
4e57b681 | 23 | #include <linux/string.h> |
229f5afd | 24 | #include <linux/log2.h> |
5745392e | 25 | #include <linux/logic_pio.h> |
c300bd2f | 26 | #include <linux/pm_wakeup.h> |
8dd7f803 | 27 | #include <linux/interrupt.h> |
32a9a682 | 28 | #include <linux/device.h> |
b67ea761 | 29 | #include <linux/pm_runtime.h> |
608c3881 | 30 | #include <linux/pci_hotplug.h> |
4d3f1384 | 31 | #include <linux/vmalloc.h> |
4ebeb1ec | 32 | #include <linux/pci-ats.h> |
32a9a682 | 33 | #include <asm/setup.h> |
2a2aca31 | 34 | #include <asm/dma.h> |
b07461a8 | 35 | #include <linux/aer.h> |
bc56b9e0 | 36 | #include "pci.h" |
1da177e4 | 37 | |
c4eed62a KB |
38 | DEFINE_MUTEX(pci_slot_mutex); |
39 | ||
00240c38 AS |
40 | const char *pci_power_names[] = { |
41 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
42 | }; | |
43 | EXPORT_SYMBOL_GPL(pci_power_names); | |
44 | ||
93177a74 RW |
45 | int isa_dma_bridge_buggy; |
46 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
47 | ||
48 | int pci_pci_problems; | |
49 | EXPORT_SYMBOL(pci_pci_problems); | |
50 | ||
1ae861e6 RW |
51 | unsigned int pci_pm_d3_delay; |
52 | ||
df17e62e MG |
53 | static void pci_pme_list_scan(struct work_struct *work); |
54 | ||
55 | static LIST_HEAD(pci_pme_list); | |
56 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
57 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
58 | ||
59 | struct pci_pme_device { | |
60 | struct list_head list; | |
61 | struct pci_dev *dev; | |
62 | }; | |
63 | ||
64 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
65 | ||
1ae861e6 RW |
66 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
67 | { | |
68 | unsigned int delay = dev->d3_delay; | |
69 | ||
70 | if (delay < pci_pm_d3_delay) | |
71 | delay = pci_pm_d3_delay; | |
72 | ||
50b2b540 AH |
73 | if (delay) |
74 | msleep(delay); | |
1ae861e6 | 75 | } |
1da177e4 | 76 | |
32a2eea7 JG |
77 | #ifdef CONFIG_PCI_DOMAINS |
78 | int pci_domains_supported = 1; | |
79 | #endif | |
80 | ||
4516a618 AN |
81 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
82 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
83 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
84 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
85 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
86 | ||
28760489 EB |
87 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
88 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
89 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
90 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
91 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
92 | ||
e16b4660 KB |
93 | #define DEFAULT_HOTPLUG_BUS_SIZE 1 |
94 | unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
95 | ||
27d868b5 | 96 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; |
b03e7495 | 97 | |
ac1aa47b JB |
98 | /* |
99 | * The default CLS is used if arch didn't set CLS explicitly and not | |
100 | * all pci devices agree on the same value. Arch can override either | |
101 | * the dfl or actual value as it sees fit. Don't forget this is | |
102 | * measured in 32-bit words, not bytes. | |
103 | */ | |
15856ad5 | 104 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
105 | u8 pci_cache_line_size; |
106 | ||
96c55900 MS |
107 | /* |
108 | * If we set up a device for bus mastering, we need to check the latency | |
109 | * timer as certain BIOSes forget to set it properly. | |
110 | */ | |
111 | unsigned int pcibios_max_latency = 255; | |
112 | ||
6748dcc2 RW |
113 | /* If set, the PCIe ARI capability will not be used. */ |
114 | static bool pcie_ari_disabled; | |
115 | ||
cef74409 GK |
116 | /* If set, the PCIe ATS capability will not be used. */ |
117 | static bool pcie_ats_disabled; | |
118 | ||
11eb0e0e SK |
119 | /* If set, the PCI config space of each device is printed during boot. */ |
120 | bool pci_early_dump; | |
121 | ||
cef74409 GK |
122 | bool pci_ats_disabled(void) |
123 | { | |
124 | return pcie_ats_disabled; | |
125 | } | |
126 | ||
9d26d3a8 MW |
127 | /* Disable bridge_d3 for all PCIe ports */ |
128 | static bool pci_bridge_d3_disable; | |
129 | /* Force bridge_d3 for all PCIe ports */ | |
130 | static bool pci_bridge_d3_force; | |
131 | ||
132 | static int __init pcie_port_pm_setup(char *str) | |
133 | { | |
134 | if (!strcmp(str, "off")) | |
135 | pci_bridge_d3_disable = true; | |
136 | else if (!strcmp(str, "force")) | |
137 | pci_bridge_d3_force = true; | |
138 | return 1; | |
139 | } | |
140 | __setup("pcie_port_pm=", pcie_port_pm_setup); | |
141 | ||
a2758b6b SK |
142 | /* Time to wait after a reset for device to become responsive */ |
143 | #define PCIE_RESET_READY_POLL_MS 60000 | |
144 | ||
1da177e4 LT |
145 | /** |
146 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
147 | * @bus: pointer to PCI bus structure to search | |
148 | * | |
149 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
150 | * including the given PCI bus and its list of child PCI buses. | |
151 | */ | |
07656d83 | 152 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 153 | { |
94e6a9b9 | 154 | struct pci_bus *tmp; |
1da177e4 LT |
155 | unsigned char max, n; |
156 | ||
b918c62e | 157 | max = bus->busn_res.end; |
94e6a9b9 YW |
158 | list_for_each_entry(tmp, &bus->children, node) { |
159 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 160 | if (n > max) |
1da177e4 LT |
161 | max = n; |
162 | } | |
163 | return max; | |
164 | } | |
b82db5ce | 165 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 166 | |
1684f5dd AM |
167 | #ifdef CONFIG_HAS_IOMEM |
168 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
169 | { | |
1f7bf3bf BH |
170 | struct resource *res = &pdev->resource[bar]; |
171 | ||
1684f5dd AM |
172 | /* |
173 | * Make sure the BAR is actually a memory resource, not an IO resource | |
174 | */ | |
646c0282 | 175 | if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { |
7506dc79 | 176 | pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res); |
1684f5dd AM |
177 | return NULL; |
178 | } | |
1f7bf3bf | 179 | return ioremap_nocache(res->start, resource_size(res)); |
1684f5dd AM |
180 | } |
181 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
c43996f4 LR |
182 | |
183 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) | |
184 | { | |
185 | /* | |
186 | * Make sure the BAR is actually a memory resource, not an IO resource | |
187 | */ | |
188 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
189 | WARN_ON(1); | |
190 | return NULL; | |
191 | } | |
192 | return ioremap_wc(pci_resource_start(pdev, bar), | |
193 | pci_resource_len(pdev, bar)); | |
194 | } | |
195 | EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); | |
1684f5dd AM |
196 | #endif |
197 | ||
45db3370 LG |
198 | /** |
199 | * pci_dev_str_match_path - test if a path string matches a device | |
74356add BH |
200 | * @dev: the PCI device to test |
201 | * @path: string to match the device against | |
45db3370 LG |
202 | * @endptr: pointer to the string after the match |
203 | * | |
204 | * Test if a string (typically from a kernel parameter) formatted as a | |
205 | * path of device/function addresses matches a PCI device. The string must | |
206 | * be of the form: | |
207 | * | |
208 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* | |
209 | * | |
210 | * A path for a device can be obtained using 'lspci -t'. Using a path | |
211 | * is more robust against bus renumbering than using only a single bus, | |
212 | * device and function address. | |
213 | * | |
214 | * Returns 1 if the string matches the device, 0 if it does not and | |
215 | * a negative error code if it fails to parse the string. | |
216 | */ | |
217 | static int pci_dev_str_match_path(struct pci_dev *dev, const char *path, | |
218 | const char **endptr) | |
219 | { | |
220 | int ret; | |
221 | int seg, bus, slot, func; | |
222 | char *wpath, *p; | |
223 | char end; | |
224 | ||
225 | *endptr = strchrnul(path, ';'); | |
226 | ||
227 | wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL); | |
228 | if (!wpath) | |
229 | return -ENOMEM; | |
230 | ||
231 | while (1) { | |
232 | p = strrchr(wpath, '/'); | |
233 | if (!p) | |
234 | break; | |
235 | ret = sscanf(p, "/%x.%x%c", &slot, &func, &end); | |
236 | if (ret != 2) { | |
237 | ret = -EINVAL; | |
238 | goto free_and_exit; | |
239 | } | |
240 | ||
241 | if (dev->devfn != PCI_DEVFN(slot, func)) { | |
242 | ret = 0; | |
243 | goto free_and_exit; | |
244 | } | |
245 | ||
246 | /* | |
247 | * Note: we don't need to get a reference to the upstream | |
248 | * bridge because we hold a reference to the top level | |
249 | * device which should hold a reference to the bridge, | |
250 | * and so on. | |
251 | */ | |
252 | dev = pci_upstream_bridge(dev); | |
253 | if (!dev) { | |
254 | ret = 0; | |
255 | goto free_and_exit; | |
256 | } | |
257 | ||
258 | *p = 0; | |
259 | } | |
260 | ||
261 | ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot, | |
262 | &func, &end); | |
263 | if (ret != 4) { | |
264 | seg = 0; | |
265 | ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end); | |
266 | if (ret != 3) { | |
267 | ret = -EINVAL; | |
268 | goto free_and_exit; | |
269 | } | |
270 | } | |
271 | ||
272 | ret = (seg == pci_domain_nr(dev->bus) && | |
273 | bus == dev->bus->number && | |
274 | dev->devfn == PCI_DEVFN(slot, func)); | |
275 | ||
276 | free_and_exit: | |
277 | kfree(wpath); | |
278 | return ret; | |
279 | } | |
280 | ||
07d8d7e5 LG |
281 | /** |
282 | * pci_dev_str_match - test if a string matches a device | |
74356add BH |
283 | * @dev: the PCI device to test |
284 | * @p: string to match the device against | |
07d8d7e5 LG |
285 | * @endptr: pointer to the string after the match |
286 | * | |
287 | * Test if a string (typically from a kernel parameter) matches a specified | |
288 | * PCI device. The string may be of one of the following formats: | |
289 | * | |
45db3370 | 290 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* |
07d8d7e5 LG |
291 | * pci:<vendor>:<device>[:<subvendor>:<subdevice>] |
292 | * | |
293 | * The first format specifies a PCI bus/device/function address which | |
294 | * may change if new hardware is inserted, if motherboard firmware changes, | |
295 | * or due to changes caused in kernel parameters. If the domain is | |
45db3370 LG |
296 | * left unspecified, it is taken to be 0. In order to be robust against |
297 | * bus renumbering issues, a path of PCI device/function numbers may be used | |
298 | * to address the specific device. The path for a device can be determined | |
299 | * through the use of 'lspci -t'. | |
07d8d7e5 LG |
300 | * |
301 | * The second format matches devices using IDs in the configuration | |
302 | * space which may match multiple devices in the system. A value of 0 | |
303 | * for any field will match all devices. (Note: this differs from | |
304 | * in-kernel code that uses PCI_ANY_ID which is ~0; this is for | |
305 | * legacy reasons and convenience so users don't have to specify | |
306 | * FFFFFFFFs on the command line.) | |
307 | * | |
308 | * Returns 1 if the string matches the device, 0 if it does not and | |
309 | * a negative error code if the string cannot be parsed. | |
310 | */ | |
311 | static int pci_dev_str_match(struct pci_dev *dev, const char *p, | |
312 | const char **endptr) | |
313 | { | |
314 | int ret; | |
45db3370 | 315 | int count; |
07d8d7e5 LG |
316 | unsigned short vendor, device, subsystem_vendor, subsystem_device; |
317 | ||
318 | if (strncmp(p, "pci:", 4) == 0) { | |
319 | /* PCI vendor/device (subvendor/subdevice) IDs are specified */ | |
320 | p += 4; | |
321 | ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device, | |
322 | &subsystem_vendor, &subsystem_device, &count); | |
323 | if (ret != 4) { | |
324 | ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count); | |
325 | if (ret != 2) | |
326 | return -EINVAL; | |
327 | ||
328 | subsystem_vendor = 0; | |
329 | subsystem_device = 0; | |
330 | } | |
331 | ||
332 | p += count; | |
333 | ||
334 | if ((!vendor || vendor == dev->vendor) && | |
335 | (!device || device == dev->device) && | |
336 | (!subsystem_vendor || | |
337 | subsystem_vendor == dev->subsystem_vendor) && | |
338 | (!subsystem_device || | |
339 | subsystem_device == dev->subsystem_device)) | |
340 | goto found; | |
07d8d7e5 | 341 | } else { |
45db3370 LG |
342 | /* |
343 | * PCI Bus, Device, Function IDs are specified | |
74356add | 344 | * (optionally, may include a path of devfns following it) |
45db3370 LG |
345 | */ |
346 | ret = pci_dev_str_match_path(dev, p, &p); | |
347 | if (ret < 0) | |
348 | return ret; | |
349 | else if (ret) | |
07d8d7e5 LG |
350 | goto found; |
351 | } | |
352 | ||
353 | *endptr = p; | |
354 | return 0; | |
355 | ||
356 | found: | |
357 | *endptr = p; | |
358 | return 1; | |
359 | } | |
687d5fe3 ME |
360 | |
361 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
362 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
363 | { |
364 | u8 id; | |
55db3208 SS |
365 | u16 ent; |
366 | ||
367 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
24a4e377 | 368 | |
687d5fe3 | 369 | while ((*ttl)--) { |
24a4e377 RD |
370 | if (pos < 0x40) |
371 | break; | |
372 | pos &= ~3; | |
55db3208 SS |
373 | pci_bus_read_config_word(bus, devfn, pos, &ent); |
374 | ||
375 | id = ent & 0xff; | |
24a4e377 RD |
376 | if (id == 0xff) |
377 | break; | |
378 | if (id == cap) | |
379 | return pos; | |
55db3208 | 380 | pos = (ent >> 8); |
24a4e377 RD |
381 | } |
382 | return 0; | |
383 | } | |
384 | ||
687d5fe3 ME |
385 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
386 | u8 pos, int cap) | |
387 | { | |
388 | int ttl = PCI_FIND_CAP_TTL; | |
389 | ||
390 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
391 | } | |
392 | ||
24a4e377 RD |
393 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
394 | { | |
395 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
396 | pos + PCI_CAP_LIST_NEXT, cap); | |
397 | } | |
398 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
399 | ||
d3bac118 ME |
400 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
401 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
402 | { |
403 | u16 status; | |
1da177e4 LT |
404 | |
405 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
406 | if (!(status & PCI_STATUS_CAP_LIST)) | |
407 | return 0; | |
408 | ||
409 | switch (hdr_type) { | |
410 | case PCI_HEADER_TYPE_NORMAL: | |
411 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 412 | return PCI_CAPABILITY_LIST; |
1da177e4 | 413 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 414 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 | 415 | } |
d3bac118 ME |
416 | |
417 | return 0; | |
1da177e4 LT |
418 | } |
419 | ||
420 | /** | |
f7625980 | 421 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
422 | * @dev: PCI device to query |
423 | * @cap: capability code | |
424 | * | |
425 | * Tell if a device supports a given PCI capability. | |
426 | * Returns the address of the requested capability structure within the | |
427 | * device's PCI configuration space or 0 in case the device does not | |
74356add | 428 | * support it. Possible values for @cap include: |
1da177e4 | 429 | * |
f7625980 BH |
430 | * %PCI_CAP_ID_PM Power Management |
431 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
432 | * %PCI_CAP_ID_VPD Vital Product Data | |
433 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 434 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 435 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
436 | * %PCI_CAP_ID_PCIX PCI-X |
437 | * %PCI_CAP_ID_EXP PCI Express | |
438 | */ | |
439 | int pci_find_capability(struct pci_dev *dev, int cap) | |
440 | { | |
d3bac118 ME |
441 | int pos; |
442 | ||
443 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
444 | if (pos) | |
445 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
446 | ||
447 | return pos; | |
1da177e4 | 448 | } |
b7fe9434 | 449 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
450 | |
451 | /** | |
f7625980 | 452 | * pci_bus_find_capability - query for devices' capabilities |
74356add | 453 | * @bus: the PCI bus to query |
1da177e4 | 454 | * @devfn: PCI device to query |
74356add | 455 | * @cap: capability code |
1da177e4 | 456 | * |
74356add | 457 | * Like pci_find_capability() but works for PCI devices that do not have a |
f7625980 | 458 | * pci_dev structure set up yet. |
1da177e4 LT |
459 | * |
460 | * Returns the address of the requested capability structure within the | |
461 | * device's PCI configuration space or 0 in case the device does not | |
462 | * support it. | |
463 | */ | |
464 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
465 | { | |
d3bac118 | 466 | int pos; |
1da177e4 LT |
467 | u8 hdr_type; |
468 | ||
469 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
470 | ||
d3bac118 ME |
471 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
472 | if (pos) | |
473 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
474 | ||
475 | return pos; | |
1da177e4 | 476 | } |
b7fe9434 | 477 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
478 | |
479 | /** | |
44a9a36f | 480 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 481 | * @dev: PCI device to query |
44a9a36f | 482 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
483 | * @cap: capability code |
484 | * | |
44a9a36f | 485 | * Returns the address of the next matching extended capability structure |
1da177e4 | 486 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
487 | * not support it. Some capabilities can occur several times, e.g., the |
488 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 489 | */ |
44a9a36f | 490 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
491 | { |
492 | u32 header; | |
557848c3 ZY |
493 | int ttl; |
494 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 495 | |
557848c3 ZY |
496 | /* minimum 8 bytes per capability */ |
497 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
498 | ||
499 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
500 | return 0; |
501 | ||
44a9a36f BH |
502 | if (start) |
503 | pos = start; | |
504 | ||
1da177e4 LT |
505 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
506 | return 0; | |
507 | ||
508 | /* | |
509 | * If we have no capabilities, this is indicated by cap ID, | |
510 | * cap version and next pointer all being 0. | |
511 | */ | |
512 | if (header == 0) | |
513 | return 0; | |
514 | ||
515 | while (ttl-- > 0) { | |
44a9a36f | 516 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
517 | return pos; |
518 | ||
519 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 520 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
521 | break; |
522 | ||
523 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
524 | break; | |
525 | } | |
526 | ||
527 | return 0; | |
528 | } | |
44a9a36f BH |
529 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
530 | ||
531 | /** | |
532 | * pci_find_ext_capability - Find an extended capability | |
533 | * @dev: PCI device to query | |
534 | * @cap: capability code | |
535 | * | |
536 | * Returns the address of the requested extended capability structure | |
537 | * within the device's PCI configuration space or 0 if the device does | |
74356add | 538 | * not support it. Possible values for @cap include: |
44a9a36f BH |
539 | * |
540 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
541 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
542 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
543 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
544 | */ | |
545 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
546 | { | |
547 | return pci_find_next_ext_capability(dev, 0, cap); | |
548 | } | |
3a720d72 | 549 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 550 | |
687d5fe3 ME |
551 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
552 | { | |
553 | int rc, ttl = PCI_FIND_CAP_TTL; | |
554 | u8 cap, mask; | |
555 | ||
556 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
557 | mask = HT_3BIT_CAP_MASK; | |
558 | else | |
559 | mask = HT_5BIT_CAP_MASK; | |
560 | ||
561 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
562 | PCI_CAP_ID_HT, &ttl); | |
563 | while (pos) { | |
564 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
565 | if (rc != PCIBIOS_SUCCESSFUL) | |
566 | return 0; | |
567 | ||
568 | if ((cap & mask) == ht_cap) | |
569 | return pos; | |
570 | ||
47a4d5be BG |
571 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
572 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
573 | PCI_CAP_ID_HT, &ttl); |
574 | } | |
575 | ||
576 | return 0; | |
577 | } | |
578 | /** | |
579 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
580 | * @dev: PCI device to query | |
581 | * @pos: Position from which to continue searching | |
582 | * @ht_cap: Hypertransport capability code | |
583 | * | |
584 | * To be used in conjunction with pci_find_ht_capability() to search for | |
585 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
586 | * from pci_find_ht_capability(). | |
587 | * | |
588 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
589 | * steps to avoid an infinite loop. | |
590 | */ | |
591 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
592 | { | |
593 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
594 | } | |
595 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
596 | ||
597 | /** | |
598 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
599 | * @dev: PCI device to query | |
600 | * @ht_cap: Hypertransport capability code | |
601 | * | |
602 | * Tell if a device supports a given Hypertransport capability. | |
603 | * Returns an address within the device's PCI configuration space | |
604 | * or 0 in case the device does not support the request capability. | |
605 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
606 | * which has a Hypertransport capability matching @ht_cap. | |
607 | */ | |
608 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
609 | { | |
610 | int pos; | |
611 | ||
612 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
613 | if (pos) | |
614 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
615 | ||
616 | return pos; | |
617 | } | |
618 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
619 | ||
1da177e4 | 620 | /** |
74356add BH |
621 | * pci_find_parent_resource - return resource region of parent bus of given |
622 | * region | |
1da177e4 LT |
623 | * @dev: PCI device structure contains resources to be searched |
624 | * @res: child resource record for which parent is sought | |
625 | * | |
74356add BH |
626 | * For given resource region of given device, return the resource region of |
627 | * parent bus the given region is contained in. | |
1da177e4 | 628 | */ |
3c78bc61 RD |
629 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
630 | struct resource *res) | |
1da177e4 LT |
631 | { |
632 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 633 | struct resource *r; |
1da177e4 | 634 | int i; |
1da177e4 | 635 | |
89a74ecc | 636 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
637 | if (!r) |
638 | continue; | |
31342330 | 639 | if (resource_contains(r, res)) { |
f44116ae BH |
640 | |
641 | /* | |
642 | * If the window is prefetchable but the BAR is | |
643 | * not, the allocator made a mistake. | |
644 | */ | |
645 | if (r->flags & IORESOURCE_PREFETCH && | |
646 | !(res->flags & IORESOURCE_PREFETCH)) | |
647 | return NULL; | |
648 | ||
649 | /* | |
650 | * If we're below a transparent bridge, there may | |
651 | * be both a positively-decoded aperture and a | |
652 | * subtractively-decoded region that contain the BAR. | |
653 | * We want the positively-decoded one, so this depends | |
654 | * on pci_bus_for_each_resource() giving us those | |
655 | * first. | |
656 | */ | |
657 | return r; | |
658 | } | |
1da177e4 | 659 | } |
f44116ae | 660 | return NULL; |
1da177e4 | 661 | } |
b7fe9434 | 662 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 663 | |
afd29f90 MW |
664 | /** |
665 | * pci_find_resource - Return matching PCI device resource | |
666 | * @dev: PCI device to query | |
667 | * @res: Resource to look for | |
668 | * | |
669 | * Goes over standard PCI resources (BARs) and checks if the given resource | |
670 | * is partially or fully contained in any of them. In that case the | |
671 | * matching resource is returned, %NULL otherwise. | |
672 | */ | |
673 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res) | |
674 | { | |
675 | int i; | |
676 | ||
677 | for (i = 0; i < PCI_ROM_RESOURCE; i++) { | |
678 | struct resource *r = &dev->resource[i]; | |
679 | ||
680 | if (r->start && resource_contains(r, res)) | |
681 | return r; | |
682 | } | |
683 | ||
684 | return NULL; | |
685 | } | |
686 | EXPORT_SYMBOL(pci_find_resource); | |
687 | ||
c56d4450 HS |
688 | /** |
689 | * pci_find_pcie_root_port - return PCIe Root Port | |
690 | * @dev: PCI device to query | |
691 | * | |
692 | * Traverse up the parent chain and return the PCIe Root Port PCI Device | |
693 | * for a given PCI Device. | |
694 | */ | |
695 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev) | |
696 | { | |
b6f6d56c | 697 | struct pci_dev *bridge, *highest_pcie_bridge = dev; |
c56d4450 HS |
698 | |
699 | bridge = pci_upstream_bridge(dev); | |
700 | while (bridge && pci_is_pcie(bridge)) { | |
701 | highest_pcie_bridge = bridge; | |
702 | bridge = pci_upstream_bridge(bridge); | |
703 | } | |
704 | ||
b6f6d56c TR |
705 | if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT) |
706 | return NULL; | |
c56d4450 | 707 | |
b6f6d56c | 708 | return highest_pcie_bridge; |
c56d4450 HS |
709 | } |
710 | EXPORT_SYMBOL(pci_find_pcie_root_port); | |
711 | ||
157e876f AW |
712 | /** |
713 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
714 | * @dev: the PCI device to operate on | |
715 | * @pos: config space offset of status word | |
716 | * @mask: mask of bit(s) to care about in status word | |
717 | * | |
718 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
719 | */ | |
720 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
721 | { | |
722 | int i; | |
723 | ||
724 | /* Wait for Transaction Pending bit clean */ | |
725 | for (i = 0; i < 4; i++) { | |
726 | u16 status; | |
727 | if (i) | |
728 | msleep((1 << (i - 1)) * 100); | |
729 | ||
730 | pci_read_config_word(dev, pos, &status); | |
731 | if (!(status & mask)) | |
732 | return 1; | |
733 | } | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
064b53db | 738 | /** |
70675e0b | 739 | * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) |
064b53db JL |
740 | * @dev: PCI device to have its BARs restored |
741 | * | |
742 | * Restore the BAR values for a given device, so as to make it | |
743 | * accessible by its driver. | |
744 | */ | |
3c78bc61 | 745 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 746 | { |
bc5f5a82 | 747 | int i; |
064b53db | 748 | |
bc5f5a82 | 749 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 750 | pci_update_resource(dev, i); |
064b53db JL |
751 | } |
752 | ||
299f2ffe | 753 | static const struct pci_platform_pm_ops *pci_platform_pm; |
961d9120 | 754 | |
299f2ffe | 755 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) |
961d9120 | 756 | { |
cc7cc02b | 757 | if (!ops->is_manageable || !ops->set_state || !ops->get_state || |
0847684c | 758 | !ops->choose_state || !ops->set_wakeup || !ops->need_resume) |
961d9120 RW |
759 | return -EINVAL; |
760 | pci_platform_pm = ops; | |
761 | return 0; | |
762 | } | |
763 | ||
764 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
765 | { | |
766 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
767 | } | |
768 | ||
769 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 770 | pci_power_t t) |
961d9120 RW |
771 | { |
772 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
773 | } | |
774 | ||
cc7cc02b LW |
775 | static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev) |
776 | { | |
777 | return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; | |
778 | } | |
779 | ||
961d9120 RW |
780 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
781 | { | |
782 | return pci_platform_pm ? | |
783 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
784 | } | |
8f7020d3 | 785 | |
0847684c | 786 | static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
787 | { |
788 | return pci_platform_pm ? | |
0847684c | 789 | pci_platform_pm->set_wakeup(dev, enable) : -ENODEV; |
b67ea761 RW |
790 | } |
791 | ||
bac2a909 RW |
792 | static inline bool platform_pci_need_resume(struct pci_dev *dev) |
793 | { | |
794 | return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; | |
795 | } | |
796 | ||
26ad34d5 MW |
797 | static inline bool platform_pci_bridge_d3(struct pci_dev *dev) |
798 | { | |
799 | return pci_platform_pm ? pci_platform_pm->bridge_d3(dev) : false; | |
800 | } | |
801 | ||
1da177e4 | 802 | /** |
44e4e66e | 803 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
74356add | 804 | * given PCI device |
44e4e66e | 805 | * @dev: PCI device to handle. |
44e4e66e | 806 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 807 | * |
44e4e66e RW |
808 | * RETURN VALUE: |
809 | * -EINVAL if the requested state is invalid. | |
810 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
811 | * wrong version, or device doesn't support the requested state. | |
812 | * 0 if device already is in the requested state. | |
813 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 814 | */ |
f00a20ef | 815 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 816 | { |
337001b6 | 817 | u16 pmcsr; |
44e4e66e | 818 | bool need_restore = false; |
1da177e4 | 819 | |
4a865905 RW |
820 | /* Check if we're already there */ |
821 | if (dev->current_state == state) | |
822 | return 0; | |
823 | ||
337001b6 | 824 | if (!dev->pm_cap) |
cca03dec AL |
825 | return -EIO; |
826 | ||
44e4e66e RW |
827 | if (state < PCI_D0 || state > PCI_D3hot) |
828 | return -EINVAL; | |
829 | ||
74356add BH |
830 | /* |
831 | * Validate current state: | |
f7625980 | 832 | * Can enter D0 from any state, but if we can only go deeper |
1da177e4 LT |
833 | * to sleep if we're already in a low power state |
834 | */ | |
4a865905 | 835 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 836 | && dev->current_state > state) { |
7506dc79 | 837 | pci_err(dev, "invalid power transition (from state %d to %d)\n", |
227f0647 | 838 | dev->current_state, state); |
1da177e4 | 839 | return -EINVAL; |
44e4e66e | 840 | } |
1da177e4 | 841 | |
74356add | 842 | /* Check if this device supports the desired state */ |
337001b6 RW |
843 | if ((state == PCI_D1 && !dev->d1_support) |
844 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 845 | return -EIO; |
1da177e4 | 846 | |
337001b6 | 847 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 848 | |
74356add BH |
849 | /* |
850 | * If we're (effectively) in D3, force entire word to 0. | |
1da177e4 LT |
851 | * This doesn't affect PME_Status, disables PME_En, and |
852 | * sets PowerState to 0. | |
853 | */ | |
32a36585 | 854 | switch (dev->current_state) { |
d3535fbb JL |
855 | case PCI_D0: |
856 | case PCI_D1: | |
857 | case PCI_D2: | |
858 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
859 | pmcsr |= state; | |
860 | break; | |
f62795f1 RW |
861 | case PCI_D3hot: |
862 | case PCI_D3cold: | |
32a36585 JL |
863 | case PCI_UNKNOWN: /* Boot-up */ |
864 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 865 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 866 | need_restore = true; |
1d09d577 | 867 | /* Fall-through - force to D0 */ |
32a36585 | 868 | default: |
d3535fbb | 869 | pmcsr = 0; |
32a36585 | 870 | break; |
1da177e4 LT |
871 | } |
872 | ||
74356add | 873 | /* Enter specified state */ |
337001b6 | 874 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 | 875 | |
74356add BH |
876 | /* |
877 | * Mandatory power management transition delays; see PCI PM 1.1 | |
878 | * 5.6.1 table 18 | |
879 | */ | |
1da177e4 | 880 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
1ae861e6 | 881 | pci_dev_d3_sleep(dev); |
1da177e4 | 882 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 883 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 884 | |
e13cdbd7 RW |
885 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
886 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
887 | if (dev->current_state != state && printk_ratelimit()) | |
7506dc79 | 888 | pci_info(dev, "Refused to change power state, currently in D%d\n", |
227f0647 | 889 | dev->current_state); |
064b53db | 890 | |
448bd857 HY |
891 | /* |
892 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
893 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
894 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
895 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
896 | * For example, at least some versions of the 3c905B and the | |
897 | * 3c556B exhibit this behaviour. | |
898 | * | |
899 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
900 | * devices in a D3hot state at boot. Consequently, we need to | |
901 | * restore at least the BARs so that the device will be | |
902 | * accessible to its driver. | |
903 | */ | |
904 | if (need_restore) | |
905 | pci_restore_bars(dev); | |
906 | ||
f00a20ef | 907 | if (dev->bus->self) |
7d715a6c SL |
908 | pcie_aspm_pm_state_change(dev->bus->self); |
909 | ||
1da177e4 LT |
910 | return 0; |
911 | } | |
912 | ||
44e4e66e | 913 | /** |
a6a64026 | 914 | * pci_update_current_state - Read power state of given device and cache it |
44e4e66e | 915 | * @dev: PCI device to handle. |
f06fc0b6 | 916 | * @state: State to cache in case the device doesn't have the PM capability |
a6a64026 LW |
917 | * |
918 | * The power state is read from the PMCSR register, which however is | |
919 | * inaccessible in D3cold. The platform firmware is therefore queried first | |
920 | * to detect accessibility of the register. In case the platform firmware | |
921 | * reports an incorrect state or the device isn't power manageable by the | |
922 | * platform at all, we try to detect D3cold by testing accessibility of the | |
923 | * vendor ID in config space. | |
44e4e66e | 924 | */ |
73410429 | 925 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 926 | { |
a6a64026 LW |
927 | if (platform_pci_get_power_state(dev) == PCI_D3cold || |
928 | !pci_device_is_present(dev)) { | |
929 | dev->current_state = PCI_D3cold; | |
930 | } else if (dev->pm_cap) { | |
44e4e66e RW |
931 | u16 pmcsr; |
932 | ||
337001b6 | 933 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 934 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
935 | } else { |
936 | dev->current_state = state; | |
44e4e66e RW |
937 | } |
938 | } | |
939 | ||
db288c9c RW |
940 | /** |
941 | * pci_power_up - Put the given device into D0 forcibly | |
942 | * @dev: PCI device to power up | |
943 | */ | |
944 | void pci_power_up(struct pci_dev *dev) | |
945 | { | |
946 | if (platform_pci_power_manageable(dev)) | |
947 | platform_pci_set_power_state(dev, PCI_D0); | |
948 | ||
949 | pci_raw_set_power_state(dev, PCI_D0); | |
950 | pci_update_current_state(dev, PCI_D0); | |
951 | } | |
952 | ||
0e5dd46b RW |
953 | /** |
954 | * pci_platform_power_transition - Use platform to change device power state | |
955 | * @dev: PCI device to handle. | |
956 | * @state: State to put the device into. | |
957 | */ | |
958 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
959 | { | |
960 | int error; | |
961 | ||
962 | if (platform_pci_power_manageable(dev)) { | |
963 | error = platform_pci_set_power_state(dev, state); | |
964 | if (!error) | |
965 | pci_update_current_state(dev, state); | |
769ba721 | 966 | } else |
0e5dd46b | 967 | error = -ENODEV; |
769ba721 RW |
968 | |
969 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
970 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
971 | |
972 | return error; | |
973 | } | |
974 | ||
0b950f0f SH |
975 | /** |
976 | * pci_wakeup - Wake up a PCI device | |
977 | * @pci_dev: Device to handle. | |
978 | * @ign: ignored parameter | |
979 | */ | |
980 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
981 | { | |
982 | pci_wakeup_event(pci_dev); | |
983 | pm_request_resume(&pci_dev->dev); | |
984 | return 0; | |
985 | } | |
986 | ||
987 | /** | |
988 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
989 | * @bus: Top bus of the subtree to walk. | |
990 | */ | |
2a4d2c42 | 991 | void pci_wakeup_bus(struct pci_bus *bus) |
0b950f0f SH |
992 | { |
993 | if (bus) | |
994 | pci_walk_bus(bus, pci_wakeup, NULL); | |
995 | } | |
996 | ||
0e5dd46b RW |
997 | /** |
998 | * __pci_start_power_transition - Start power transition of a PCI device | |
999 | * @dev: PCI device to handle. | |
1000 | * @state: State to put the device into. | |
1001 | */ | |
1002 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
1003 | { | |
448bd857 | 1004 | if (state == PCI_D0) { |
0e5dd46b | 1005 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
1006 | /* |
1007 | * Mandatory power management transition delays, see | |
1008 | * PCI Express Base Specification Revision 2.0 Section | |
1009 | * 6.6.1: Conventional Reset. Do not delay for | |
1010 | * devices powered on/off by corresponding bridge, | |
1011 | * because have already delayed for the bridge. | |
1012 | */ | |
1013 | if (dev->runtime_d3cold) { | |
d6112f8d | 1014 | if (dev->d3cold_delay && !dev->imm_ready) |
50b2b540 | 1015 | msleep(dev->d3cold_delay); |
448bd857 HY |
1016 | /* |
1017 | * When powering on a bridge from D3cold, the | |
1018 | * whole hierarchy may be powered on into | |
1019 | * D0uninitialized state, resume them to give | |
1020 | * them a chance to suspend again | |
1021 | */ | |
1022 | pci_wakeup_bus(dev->subordinate); | |
1023 | } | |
1024 | } | |
1025 | } | |
1026 | ||
1027 | /** | |
1028 | * __pci_dev_set_current_state - Set current state of a PCI device | |
1029 | * @dev: Device to handle | |
1030 | * @data: pointer to state to be set | |
1031 | */ | |
1032 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
1033 | { | |
1034 | pci_power_t state = *(pci_power_t *)data; | |
1035 | ||
1036 | dev->current_state = state; | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | /** | |
2a4d2c42 | 1041 | * pci_bus_set_current_state - Walk given bus and set current state of devices |
448bd857 HY |
1042 | * @bus: Top bus of the subtree to walk. |
1043 | * @state: state to be set | |
1044 | */ | |
2a4d2c42 | 1045 | void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) |
448bd857 HY |
1046 | { |
1047 | if (bus) | |
1048 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
1049 | } |
1050 | ||
1051 | /** | |
1052 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
1053 | * @dev: PCI device to handle. | |
1054 | * @state: State to put the device into. | |
1055 | * | |
1056 | * This function should not be called directly by device drivers. | |
1057 | */ | |
1058 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
1059 | { | |
448bd857 HY |
1060 | int ret; |
1061 | ||
db288c9c | 1062 | if (state <= PCI_D0) |
448bd857 HY |
1063 | return -EINVAL; |
1064 | ret = pci_platform_power_transition(dev, state); | |
1065 | /* Power off the bridge may power off the whole hierarchy */ | |
1066 | if (!ret && state == PCI_D3cold) | |
2a4d2c42 | 1067 | pci_bus_set_current_state(dev->subordinate, PCI_D3cold); |
448bd857 | 1068 | return ret; |
0e5dd46b RW |
1069 | } |
1070 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
1071 | ||
44e4e66e RW |
1072 | /** |
1073 | * pci_set_power_state - Set the power state of a PCI device | |
1074 | * @dev: PCI device to handle. | |
1075 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
1076 | * | |
877d0310 | 1077 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
1078 | * the device's PCI PM registers. |
1079 | * | |
1080 | * RETURN VALUE: | |
1081 | * -EINVAL if the requested state is invalid. | |
1082 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
1083 | * wrong version, or device doesn't support the requested state. | |
ab4b8a47 | 1084 | * 0 if the transition is to D1 or D2 but D1 and D2 are not supported. |
44e4e66e | 1085 | * 0 if device already is in the requested state. |
ab4b8a47 | 1086 | * 0 if the transition is to D3 but D3 is not supported. |
44e4e66e RW |
1087 | * 0 if device's power state has been successfully changed. |
1088 | */ | |
1089 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
1090 | { | |
337001b6 | 1091 | int error; |
44e4e66e | 1092 | |
74356add | 1093 | /* Bound the state we're entering */ |
448bd857 HY |
1094 | if (state > PCI_D3cold) |
1095 | state = PCI_D3cold; | |
44e4e66e RW |
1096 | else if (state < PCI_D0) |
1097 | state = PCI_D0; | |
1098 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
74356add | 1099 | |
44e4e66e | 1100 | /* |
74356add BH |
1101 | * If the device or the parent bridge do not support PCI |
1102 | * PM, ignore the request if we're doing anything other | |
1103 | * than putting it into D0 (which would only happen on | |
1104 | * boot). | |
44e4e66e RW |
1105 | */ |
1106 | return 0; | |
1107 | ||
db288c9c RW |
1108 | /* Check if we're already there */ |
1109 | if (dev->current_state == state) | |
1110 | return 0; | |
1111 | ||
0e5dd46b RW |
1112 | __pci_start_power_transition(dev, state); |
1113 | ||
74356add BH |
1114 | /* |
1115 | * This device is quirked not to be put into D3, so don't put it in | |
1116 | * D3 | |
1117 | */ | |
448bd857 | 1118 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 1119 | return 0; |
44e4e66e | 1120 | |
448bd857 HY |
1121 | /* |
1122 | * To put device in D3cold, we put device into D3hot in native | |
1123 | * way, then put device into D3cold with platform ops | |
1124 | */ | |
1125 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
1126 | PCI_D3hot : state); | |
44e4e66e | 1127 | |
0e5dd46b RW |
1128 | if (!__pci_complete_power_transition(dev, state)) |
1129 | error = 0; | |
44e4e66e RW |
1130 | |
1131 | return error; | |
1132 | } | |
b7fe9434 | 1133 | EXPORT_SYMBOL(pci_set_power_state); |
44e4e66e | 1134 | |
1da177e4 LT |
1135 | /** |
1136 | * pci_choose_state - Choose the power state of a PCI device | |
1137 | * @dev: PCI device to be suspended | |
1138 | * @state: target sleep state for the whole system. This is the value | |
74356add | 1139 | * that is passed to suspend() function. |
1da177e4 LT |
1140 | * |
1141 | * Returns PCI power state suitable for given device and given system | |
1142 | * message. | |
1143 | */ | |
1da177e4 LT |
1144 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) |
1145 | { | |
ab826ca4 | 1146 | pci_power_t ret; |
0f64474b | 1147 | |
728cdb75 | 1148 | if (!dev->pm_cap) |
1da177e4 LT |
1149 | return PCI_D0; |
1150 | ||
961d9120 RW |
1151 | ret = platform_pci_choose_state(dev); |
1152 | if (ret != PCI_POWER_ERROR) | |
1153 | return ret; | |
ca078bae PM |
1154 | |
1155 | switch (state.event) { | |
1156 | case PM_EVENT_ON: | |
1157 | return PCI_D0; | |
1158 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
1159 | case PM_EVENT_PRETHAW: |
1160 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 1161 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 1162 | case PM_EVENT_HIBERNATE: |
ca078bae | 1163 | return PCI_D3hot; |
1da177e4 | 1164 | default: |
7506dc79 | 1165 | pci_info(dev, "unrecognized suspend event %d\n", |
80ccba11 | 1166 | state.event); |
1da177e4 LT |
1167 | BUG(); |
1168 | } | |
1169 | return PCI_D0; | |
1170 | } | |
1da177e4 LT |
1171 | EXPORT_SYMBOL(pci_choose_state); |
1172 | ||
89858517 YZ |
1173 | #define PCI_EXP_SAVE_REGS 7 |
1174 | ||
fd0f7f73 AW |
1175 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
1176 | u16 cap, bool extended) | |
34a4876e YL |
1177 | { |
1178 | struct pci_cap_saved_state *tmp; | |
34a4876e | 1179 | |
b67bfe0d | 1180 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 1181 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
1182 | return tmp; |
1183 | } | |
1184 | return NULL; | |
1185 | } | |
1186 | ||
fd0f7f73 AW |
1187 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
1188 | { | |
1189 | return _pci_find_saved_cap(dev, cap, false); | |
1190 | } | |
1191 | ||
1192 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
1193 | { | |
1194 | return _pci_find_saved_cap(dev, cap, true); | |
1195 | } | |
1196 | ||
b56a5a23 MT |
1197 | static int pci_save_pcie_state(struct pci_dev *dev) |
1198 | { | |
59875ae4 | 1199 | int i = 0; |
b56a5a23 MT |
1200 | struct pci_cap_saved_state *save_state; |
1201 | u16 *cap; | |
1202 | ||
59875ae4 | 1203 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
1204 | return 0; |
1205 | ||
9f35575d | 1206 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 1207 | if (!save_state) { |
7506dc79 | 1208 | pci_err(dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
1209 | return -ENOMEM; |
1210 | } | |
63f4898a | 1211 | |
59875ae4 JL |
1212 | cap = (u16 *)&save_state->cap.data[0]; |
1213 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
1214 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
1215 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
1216 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
1217 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
1218 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
1219 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 1220 | |
b56a5a23 MT |
1221 | return 0; |
1222 | } | |
1223 | ||
1224 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
1225 | { | |
59875ae4 | 1226 | int i = 0; |
b56a5a23 MT |
1227 | struct pci_cap_saved_state *save_state; |
1228 | u16 *cap; | |
1229 | ||
1230 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 1231 | if (!save_state) |
9cb604ed MS |
1232 | return; |
1233 | ||
59875ae4 JL |
1234 | cap = (u16 *)&save_state->cap.data[0]; |
1235 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
1236 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
1237 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
1238 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
1239 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
1240 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
1241 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
1242 | } |
1243 | ||
cc692a5f SH |
1244 | static int pci_save_pcix_state(struct pci_dev *dev) |
1245 | { | |
63f4898a | 1246 | int pos; |
cc692a5f | 1247 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
1248 | |
1249 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1250 | if (!pos) |
cc692a5f SH |
1251 | return 0; |
1252 | ||
f34303de | 1253 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 1254 | if (!save_state) { |
7506dc79 | 1255 | pci_err(dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
1256 | return -ENOMEM; |
1257 | } | |
cc692a5f | 1258 | |
24a4742f AW |
1259 | pci_read_config_word(dev, pos + PCI_X_CMD, |
1260 | (u16 *)save_state->cap.data); | |
63f4898a | 1261 | |
cc692a5f SH |
1262 | return 0; |
1263 | } | |
1264 | ||
1265 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
1266 | { | |
1267 | int i = 0, pos; | |
1268 | struct pci_cap_saved_state *save_state; | |
1269 | u16 *cap; | |
1270 | ||
1271 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
1272 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1273 | if (!save_state || !pos) |
cc692a5f | 1274 | return; |
24a4742f | 1275 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
1276 | |
1277 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
1278 | } |
1279 | ||
dbbfadf2 BH |
1280 | static void pci_save_ltr_state(struct pci_dev *dev) |
1281 | { | |
1282 | int ltr; | |
1283 | struct pci_cap_saved_state *save_state; | |
1284 | u16 *cap; | |
1285 | ||
1286 | if (!pci_is_pcie(dev)) | |
1287 | return; | |
1288 | ||
1289 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1290 | if (!ltr) | |
1291 | return; | |
1292 | ||
1293 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1294 | if (!save_state) { | |
1295 | pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n"); | |
1296 | return; | |
1297 | } | |
1298 | ||
1299 | cap = (u16 *)&save_state->cap.data[0]; | |
1300 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++); | |
1301 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++); | |
1302 | } | |
1303 | ||
1304 | static void pci_restore_ltr_state(struct pci_dev *dev) | |
1305 | { | |
1306 | struct pci_cap_saved_state *save_state; | |
1307 | int ltr; | |
1308 | u16 *cap; | |
1309 | ||
1310 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1311 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1312 | if (!save_state || !ltr) | |
1313 | return; | |
1314 | ||
1315 | cap = (u16 *)&save_state->cap.data[0]; | |
1316 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++); | |
1317 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++); | |
1318 | } | |
cc692a5f | 1319 | |
1da177e4 | 1320 | /** |
74356add BH |
1321 | * pci_save_state - save the PCI configuration space of a device before |
1322 | * suspending | |
1323 | * @dev: PCI device that we're dealing with | |
1da177e4 | 1324 | */ |
3c78bc61 | 1325 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1326 | { |
1327 | int i; | |
1328 | /* XXX: 100% dword access ok here? */ | |
1329 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 1330 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 1331 | dev->state_saved = true; |
79e50e72 QL |
1332 | |
1333 | i = pci_save_pcie_state(dev); | |
1334 | if (i != 0) | |
b56a5a23 | 1335 | return i; |
79e50e72 QL |
1336 | |
1337 | i = pci_save_pcix_state(dev); | |
1338 | if (i != 0) | |
cc692a5f | 1339 | return i; |
79e50e72 | 1340 | |
dbbfadf2 | 1341 | pci_save_ltr_state(dev); |
4f802170 | 1342 | pci_save_dpc_state(dev); |
754834b9 | 1343 | return pci_save_vc_state(dev); |
1da177e4 | 1344 | } |
b7fe9434 | 1345 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1346 | |
ebfc5b80 | 1347 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
08387454 | 1348 | u32 saved_val, int retry, bool force) |
ebfc5b80 RW |
1349 | { |
1350 | u32 val; | |
1351 | ||
1352 | pci_read_config_dword(pdev, offset, &val); | |
08387454 | 1353 | if (!force && val == saved_val) |
ebfc5b80 RW |
1354 | return; |
1355 | ||
1356 | for (;;) { | |
7506dc79 | 1357 | pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
227f0647 | 1358 | offset, val, saved_val); |
ebfc5b80 RW |
1359 | pci_write_config_dword(pdev, offset, saved_val); |
1360 | if (retry-- <= 0) | |
1361 | return; | |
1362 | ||
1363 | pci_read_config_dword(pdev, offset, &val); | |
1364 | if (val == saved_val) | |
1365 | return; | |
1366 | ||
1367 | mdelay(1); | |
1368 | } | |
1369 | } | |
1370 | ||
a6cb9ee7 | 1371 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
08387454 DD |
1372 | int start, int end, int retry, |
1373 | bool force) | |
ebfc5b80 RW |
1374 | { |
1375 | int index; | |
1376 | ||
1377 | for (index = end; index >= start; index--) | |
1378 | pci_restore_config_dword(pdev, 4 * index, | |
1379 | pdev->saved_config_space[index], | |
08387454 | 1380 | retry, force); |
ebfc5b80 RW |
1381 | } |
1382 | ||
a6cb9ee7 RW |
1383 | static void pci_restore_config_space(struct pci_dev *pdev) |
1384 | { | |
1385 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
08387454 | 1386 | pci_restore_config_space_range(pdev, 10, 15, 0, false); |
a6cb9ee7 | 1387 | /* Restore BARs before the command register. */ |
08387454 DD |
1388 | pci_restore_config_space_range(pdev, 4, 9, 10, false); |
1389 | pci_restore_config_space_range(pdev, 0, 3, 0, false); | |
1390 | } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1391 | pci_restore_config_space_range(pdev, 12, 15, 0, false); | |
1392 | ||
1393 | /* | |
1394 | * Force rewriting of prefetch registers to avoid S3 resume | |
1395 | * issues on Intel PCI bridges that occur when these | |
1396 | * registers are not explicitly written. | |
1397 | */ | |
1398 | pci_restore_config_space_range(pdev, 9, 11, 0, true); | |
1399 | pci_restore_config_space_range(pdev, 0, 8, 0, false); | |
a6cb9ee7 | 1400 | } else { |
08387454 | 1401 | pci_restore_config_space_range(pdev, 0, 15, 0, false); |
a6cb9ee7 RW |
1402 | } |
1403 | } | |
1404 | ||
d3252ace CK |
1405 | static void pci_restore_rebar_state(struct pci_dev *pdev) |
1406 | { | |
1407 | unsigned int pos, nbars, i; | |
1408 | u32 ctrl; | |
1409 | ||
1410 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
1411 | if (!pos) | |
1412 | return; | |
1413 | ||
1414 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1415 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
1416 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
1417 | ||
1418 | for (i = 0; i < nbars; i++, pos += 8) { | |
1419 | struct resource *res; | |
1420 | int bar_idx, size; | |
1421 | ||
1422 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1423 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
1424 | res = pdev->resource + bar_idx; | |
1425 | size = order_base_2((resource_size(res) >> 20) | 1) - 1; | |
1426 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; | |
b1277a22 | 1427 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
d3252ace CK |
1428 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
1429 | } | |
1430 | } | |
1431 | ||
f7625980 | 1432 | /** |
1da177e4 | 1433 | * pci_restore_state - Restore the saved state of a PCI device |
74356add | 1434 | * @dev: PCI device that we're dealing with |
1da177e4 | 1435 | */ |
1d3c16a8 | 1436 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1437 | { |
c82f63e4 | 1438 | if (!dev->state_saved) |
1d3c16a8 | 1439 | return; |
4b77b0a2 | 1440 | |
dbbfadf2 BH |
1441 | /* |
1442 | * Restore max latencies (in the LTR capability) before enabling | |
1443 | * LTR itself (in the PCIe capability). | |
1444 | */ | |
1445 | pci_restore_ltr_state(dev); | |
1446 | ||
b56a5a23 | 1447 | pci_restore_pcie_state(dev); |
4ebeb1ec CT |
1448 | pci_restore_pasid_state(dev); |
1449 | pci_restore_pri_state(dev); | |
1900ca13 | 1450 | pci_restore_ats_state(dev); |
425c1b22 | 1451 | pci_restore_vc_state(dev); |
d3252ace | 1452 | pci_restore_rebar_state(dev); |
4f802170 | 1453 | pci_restore_dpc_state(dev); |
b56a5a23 | 1454 | |
b07461a8 TI |
1455 | pci_cleanup_aer_error_status_regs(dev); |
1456 | ||
a6cb9ee7 | 1457 | pci_restore_config_space(dev); |
ebfc5b80 | 1458 | |
cc692a5f | 1459 | pci_restore_pcix_state(dev); |
41017f0c | 1460 | pci_restore_msi_state(dev); |
ccbc175a AD |
1461 | |
1462 | /* Restore ACS and IOV configuration state */ | |
1463 | pci_enable_acs(dev); | |
8c5cdb6a | 1464 | pci_restore_iov_state(dev); |
8fed4b65 | 1465 | |
4b77b0a2 | 1466 | dev->state_saved = false; |
1da177e4 | 1467 | } |
b7fe9434 | 1468 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1469 | |
ffbdd3f7 AW |
1470 | struct pci_saved_state { |
1471 | u32 config_space[16]; | |
1472 | struct pci_cap_saved_data cap[0]; | |
1473 | }; | |
1474 | ||
1475 | /** | |
1476 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1477 | * the device saved state. | |
1478 | * @dev: PCI device that we're dealing with | |
1479 | * | |
f7625980 | 1480 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1481 | */ |
1482 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1483 | { | |
1484 | struct pci_saved_state *state; | |
1485 | struct pci_cap_saved_state *tmp; | |
1486 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1487 | size_t size; |
1488 | ||
1489 | if (!dev->state_saved) | |
1490 | return NULL; | |
1491 | ||
1492 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1493 | ||
b67bfe0d | 1494 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1495 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1496 | ||
1497 | state = kzalloc(size, GFP_KERNEL); | |
1498 | if (!state) | |
1499 | return NULL; | |
1500 | ||
1501 | memcpy(state->config_space, dev->saved_config_space, | |
1502 | sizeof(state->config_space)); | |
1503 | ||
1504 | cap = state->cap; | |
b67bfe0d | 1505 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1506 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1507 | memcpy(cap, &tmp->cap, len); | |
1508 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1509 | } | |
1510 | /* Empty cap_save terminates list */ | |
1511 | ||
1512 | return state; | |
1513 | } | |
1514 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1515 | ||
1516 | /** | |
1517 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1518 | * @dev: PCI device that we're dealing with | |
1519 | * @state: Saved state returned from pci_store_saved_state() | |
1520 | */ | |
98d9b271 KRW |
1521 | int pci_load_saved_state(struct pci_dev *dev, |
1522 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1523 | { |
1524 | struct pci_cap_saved_data *cap; | |
1525 | ||
1526 | dev->state_saved = false; | |
1527 | ||
1528 | if (!state) | |
1529 | return 0; | |
1530 | ||
1531 | memcpy(dev->saved_config_space, state->config_space, | |
1532 | sizeof(state->config_space)); | |
1533 | ||
1534 | cap = state->cap; | |
1535 | while (cap->size) { | |
1536 | struct pci_cap_saved_state *tmp; | |
1537 | ||
fd0f7f73 | 1538 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1539 | if (!tmp || tmp->cap.size != cap->size) |
1540 | return -EINVAL; | |
1541 | ||
1542 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1543 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1544 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1545 | } | |
1546 | ||
1547 | dev->state_saved = true; | |
1548 | return 0; | |
1549 | } | |
98d9b271 | 1550 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1551 | |
1552 | /** | |
1553 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1554 | * and free the memory allocated for it. | |
1555 | * @dev: PCI device that we're dealing with | |
1556 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1557 | */ | |
1558 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1559 | struct pci_saved_state **state) | |
1560 | { | |
1561 | int ret = pci_load_saved_state(dev, *state); | |
1562 | kfree(*state); | |
1563 | *state = NULL; | |
1564 | return ret; | |
1565 | } | |
1566 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1567 | ||
8a9d5609 BH |
1568 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1569 | { | |
1570 | return pci_enable_resources(dev, bars); | |
1571 | } | |
1572 | ||
38cc1302 HS |
1573 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1574 | { | |
1575 | int err; | |
1f6ae47e | 1576 | struct pci_dev *bridge; |
1e2571a7 BH |
1577 | u16 cmd; |
1578 | u8 pin; | |
38cc1302 HS |
1579 | |
1580 | err = pci_set_power_state(dev, PCI_D0); | |
1581 | if (err < 0 && err != -EIO) | |
1582 | return err; | |
1f6ae47e VS |
1583 | |
1584 | bridge = pci_upstream_bridge(dev); | |
1585 | if (bridge) | |
1586 | pcie_aspm_powersave_config_link(bridge); | |
1587 | ||
38cc1302 HS |
1588 | err = pcibios_enable_device(dev, bars); |
1589 | if (err < 0) | |
1590 | return err; | |
1591 | pci_fixup_device(pci_fixup_enable, dev); | |
1592 | ||
866d5417 BH |
1593 | if (dev->msi_enabled || dev->msix_enabled) |
1594 | return 0; | |
1595 | ||
1e2571a7 BH |
1596 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1597 | if (pin) { | |
1598 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1599 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1600 | pci_write_config_word(dev, PCI_COMMAND, | |
1601 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1602 | } | |
1603 | ||
38cc1302 HS |
1604 | return 0; |
1605 | } | |
1606 | ||
1607 | /** | |
0b62e13b | 1608 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1609 | * @dev: PCI device to be resumed |
1610 | * | |
74356add BH |
1611 | * NOTE: This function is a backend of pci_default_resume() and is not supposed |
1612 | * to be called by normal code, write proper resume handler and use it instead. | |
38cc1302 | 1613 | */ |
0b62e13b | 1614 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1615 | { |
296ccb08 | 1616 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1617 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1618 | return 0; | |
1619 | } | |
b7fe9434 | 1620 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1621 | |
928bea96 YL |
1622 | static void pci_enable_bridge(struct pci_dev *dev) |
1623 | { | |
79272138 | 1624 | struct pci_dev *bridge; |
928bea96 YL |
1625 | int retval; |
1626 | ||
79272138 BH |
1627 | bridge = pci_upstream_bridge(dev); |
1628 | if (bridge) | |
1629 | pci_enable_bridge(bridge); | |
928bea96 | 1630 | |
cf3e1feb | 1631 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1632 | if (!dev->is_busmaster) |
cf3e1feb | 1633 | pci_set_master(dev); |
0f50a49e | 1634 | return; |
cf3e1feb YL |
1635 | } |
1636 | ||
928bea96 YL |
1637 | retval = pci_enable_device(dev); |
1638 | if (retval) | |
7506dc79 | 1639 | pci_err(dev, "Error enabling bridge (%d), continuing\n", |
928bea96 YL |
1640 | retval); |
1641 | pci_set_master(dev); | |
1642 | } | |
1643 | ||
b4b4fbba | 1644 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1645 | { |
79272138 | 1646 | struct pci_dev *bridge; |
1da177e4 | 1647 | int err; |
b718989d | 1648 | int i, bars = 0; |
1da177e4 | 1649 | |
97c145f7 JB |
1650 | /* |
1651 | * Power state could be unknown at this point, either due to a fresh | |
1652 | * boot or a device removal call. So get the current power state | |
1653 | * so that things like MSI message writing will behave as expected | |
1654 | * (e.g. if the device really is in D0 at enable time). | |
1655 | */ | |
1656 | if (dev->pm_cap) { | |
1657 | u16 pmcsr; | |
1658 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1659 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1660 | } | |
1661 | ||
cc7ba39b | 1662 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1663 | return 0; /* already enabled */ |
1664 | ||
79272138 | 1665 | bridge = pci_upstream_bridge(dev); |
0f50a49e | 1666 | if (bridge) |
79272138 | 1667 | pci_enable_bridge(bridge); |
928bea96 | 1668 | |
497f16f2 YL |
1669 | /* only skip sriov related */ |
1670 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1671 | if (dev->resource[i].flags & flags) | |
1672 | bars |= (1 << i); | |
1673 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1674 | if (dev->resource[i].flags & flags) |
1675 | bars |= (1 << i); | |
1676 | ||
38cc1302 | 1677 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1678 | if (err < 0) |
38cc1302 | 1679 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1680 | return err; |
1da177e4 LT |
1681 | } |
1682 | ||
b718989d BH |
1683 | /** |
1684 | * pci_enable_device_io - Initialize a device for use with IO space | |
1685 | * @dev: PCI device to be initialized | |
1686 | * | |
74356add BH |
1687 | * Initialize device before it's used by a driver. Ask low-level code |
1688 | * to enable I/O resources. Wake up the device if it was suspended. | |
1689 | * Beware, this function can fail. | |
b718989d BH |
1690 | */ |
1691 | int pci_enable_device_io(struct pci_dev *dev) | |
1692 | { | |
b4b4fbba | 1693 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1694 | } |
b7fe9434 | 1695 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1696 | |
1697 | /** | |
1698 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1699 | * @dev: PCI device to be initialized | |
1700 | * | |
74356add BH |
1701 | * Initialize device before it's used by a driver. Ask low-level code |
1702 | * to enable Memory resources. Wake up the device if it was suspended. | |
1703 | * Beware, this function can fail. | |
b718989d BH |
1704 | */ |
1705 | int pci_enable_device_mem(struct pci_dev *dev) | |
1706 | { | |
b4b4fbba | 1707 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1708 | } |
b7fe9434 | 1709 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1710 | |
bae94d02 IPG |
1711 | /** |
1712 | * pci_enable_device - Initialize device before it's used by a driver. | |
1713 | * @dev: PCI device to be initialized | |
1714 | * | |
74356add BH |
1715 | * Initialize device before it's used by a driver. Ask low-level code |
1716 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1717 | * Beware, this function can fail. | |
bae94d02 | 1718 | * |
74356add BH |
1719 | * Note we don't actually enable the device many times if we call |
1720 | * this function repeatedly (we just increment the count). | |
bae94d02 IPG |
1721 | */ |
1722 | int pci_enable_device(struct pci_dev *dev) | |
1723 | { | |
b4b4fbba | 1724 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1725 | } |
b7fe9434 | 1726 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1727 | |
9ac7849e | 1728 | /* |
74356add BH |
1729 | * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X |
1730 | * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so | |
9ac7849e TH |
1731 | * there's no need to track it separately. pci_devres is initialized |
1732 | * when a device is enabled using managed PCI device enable interface. | |
1733 | */ | |
1734 | struct pci_devres { | |
7f375f32 TH |
1735 | unsigned int enabled:1; |
1736 | unsigned int pinned:1; | |
9ac7849e TH |
1737 | unsigned int orig_intx:1; |
1738 | unsigned int restore_intx:1; | |
fc0f9f4d | 1739 | unsigned int mwi:1; |
9ac7849e TH |
1740 | u32 region_mask; |
1741 | }; | |
1742 | ||
1743 | static void pcim_release(struct device *gendev, void *res) | |
1744 | { | |
f3d2f165 | 1745 | struct pci_dev *dev = to_pci_dev(gendev); |
9ac7849e TH |
1746 | struct pci_devres *this = res; |
1747 | int i; | |
1748 | ||
1749 | if (dev->msi_enabled) | |
1750 | pci_disable_msi(dev); | |
1751 | if (dev->msix_enabled) | |
1752 | pci_disable_msix(dev); | |
1753 | ||
1754 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1755 | if (this->region_mask & (1 << i)) | |
1756 | pci_release_region(dev, i); | |
1757 | ||
fc0f9f4d HK |
1758 | if (this->mwi) |
1759 | pci_clear_mwi(dev); | |
1760 | ||
9ac7849e TH |
1761 | if (this->restore_intx) |
1762 | pci_intx(dev, this->orig_intx); | |
1763 | ||
7f375f32 | 1764 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1765 | pci_disable_device(dev); |
1766 | } | |
1767 | ||
07656d83 | 1768 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1769 | { |
1770 | struct pci_devres *dr, *new_dr; | |
1771 | ||
1772 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1773 | if (dr) | |
1774 | return dr; | |
1775 | ||
1776 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1777 | if (!new_dr) | |
1778 | return NULL; | |
1779 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1780 | } | |
1781 | ||
07656d83 | 1782 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1783 | { |
1784 | if (pci_is_managed(pdev)) | |
1785 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1786 | return NULL; | |
1787 | } | |
1788 | ||
1789 | /** | |
1790 | * pcim_enable_device - Managed pci_enable_device() | |
1791 | * @pdev: PCI device to be initialized | |
1792 | * | |
1793 | * Managed pci_enable_device(). | |
1794 | */ | |
1795 | int pcim_enable_device(struct pci_dev *pdev) | |
1796 | { | |
1797 | struct pci_devres *dr; | |
1798 | int rc; | |
1799 | ||
1800 | dr = get_pci_dr(pdev); | |
1801 | if (unlikely(!dr)) | |
1802 | return -ENOMEM; | |
b95d58ea TH |
1803 | if (dr->enabled) |
1804 | return 0; | |
9ac7849e TH |
1805 | |
1806 | rc = pci_enable_device(pdev); | |
1807 | if (!rc) { | |
1808 | pdev->is_managed = 1; | |
7f375f32 | 1809 | dr->enabled = 1; |
9ac7849e TH |
1810 | } |
1811 | return rc; | |
1812 | } | |
b7fe9434 | 1813 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
1814 | |
1815 | /** | |
1816 | * pcim_pin_device - Pin managed PCI device | |
1817 | * @pdev: PCI device to pin | |
1818 | * | |
1819 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1820 | * driver detach. @pdev must have been enabled with | |
1821 | * pcim_enable_device(). | |
1822 | */ | |
1823 | void pcim_pin_device(struct pci_dev *pdev) | |
1824 | { | |
1825 | struct pci_devres *dr; | |
1826 | ||
1827 | dr = find_pci_dr(pdev); | |
7f375f32 | 1828 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1829 | if (dr) |
7f375f32 | 1830 | dr->pinned = 1; |
9ac7849e | 1831 | } |
b7fe9434 | 1832 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 1833 | |
eca0d467 MG |
1834 | /* |
1835 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1836 | * @dev: the PCI device being added | |
1837 | * | |
1838 | * Permits the platform to provide architecture specific functionality when | |
1839 | * devices are added. This is the default implementation. Architecture | |
1840 | * implementations can override this. | |
1841 | */ | |
3c78bc61 | 1842 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
1843 | { |
1844 | return 0; | |
1845 | } | |
1846 | ||
6ae32c53 | 1847 | /** |
74356add BH |
1848 | * pcibios_release_device - provide arch specific hooks when releasing |
1849 | * device dev | |
6ae32c53 SO |
1850 | * @dev: the PCI device being released |
1851 | * | |
1852 | * Permits the platform to provide architecture specific functionality when | |
1853 | * devices are released. This is the default implementation. Architecture | |
1854 | * implementations can override this. | |
1855 | */ | |
1856 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1857 | ||
1da177e4 LT |
1858 | /** |
1859 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1860 | * @dev: the PCI device to disable | |
1861 | * | |
1862 | * Disables architecture specific PCI resources for the device. This | |
1863 | * is the default implementation. Architecture implementations can | |
1864 | * override this. | |
1865 | */ | |
ff3ce480 | 1866 | void __weak pcibios_disable_device(struct pci_dev *dev) {} |
1da177e4 | 1867 | |
a43ae58c HG |
1868 | /** |
1869 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
1870 | * @irq: ISA IRQ to penalize | |
1871 | * @active: IRQ active or not | |
1872 | * | |
1873 | * Permits the platform to provide architecture-specific functionality when | |
1874 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
1875 | * implementations can override this. | |
1876 | */ | |
1877 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
1878 | ||
fa58d305 RW |
1879 | static void do_pci_disable_device(struct pci_dev *dev) |
1880 | { | |
1881 | u16 pci_command; | |
1882 | ||
1883 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1884 | if (pci_command & PCI_COMMAND_MASTER) { | |
1885 | pci_command &= ~PCI_COMMAND_MASTER; | |
1886 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1887 | } | |
1888 | ||
1889 | pcibios_disable_device(dev); | |
1890 | } | |
1891 | ||
1892 | /** | |
1893 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1894 | * @dev: PCI device to disable | |
1895 | * | |
1896 | * NOTE: This function is a backend of PCI power management routines and is | |
1897 | * not supposed to be called drivers. | |
1898 | */ | |
1899 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1900 | { | |
296ccb08 | 1901 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1902 | do_pci_disable_device(dev); |
1903 | } | |
1904 | ||
1da177e4 LT |
1905 | /** |
1906 | * pci_disable_device - Disable PCI device after use | |
1907 | * @dev: PCI device to be disabled | |
1908 | * | |
1909 | * Signal to the system that the PCI device is not in use by the system | |
1910 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1911 | * |
1912 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1913 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 1914 | */ |
3c78bc61 | 1915 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 1916 | { |
9ac7849e | 1917 | struct pci_devres *dr; |
99dc804d | 1918 | |
9ac7849e TH |
1919 | dr = find_pci_dr(dev); |
1920 | if (dr) | |
7f375f32 | 1921 | dr->enabled = 0; |
9ac7849e | 1922 | |
fd6dceab KK |
1923 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1924 | "disabling already-disabled device"); | |
1925 | ||
cc7ba39b | 1926 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1927 | return; |
1928 | ||
fa58d305 | 1929 | do_pci_disable_device(dev); |
1da177e4 | 1930 | |
fa58d305 | 1931 | dev->is_busmaster = 0; |
1da177e4 | 1932 | } |
b7fe9434 | 1933 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 1934 | |
f7bdd12d BK |
1935 | /** |
1936 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1937 | * @dev: the PCIe device reset |
f7bdd12d BK |
1938 | * @state: Reset state to enter into |
1939 | * | |
74356add | 1940 | * Set the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1941 | * implementation. Architecture implementations can override this. |
1942 | */ | |
d6d88c83 BH |
1943 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1944 | enum pcie_reset_state state) | |
f7bdd12d BK |
1945 | { |
1946 | return -EINVAL; | |
1947 | } | |
1948 | ||
1949 | /** | |
1950 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1951 | * @dev: the PCIe device reset |
f7bdd12d BK |
1952 | * @state: Reset state to enter into |
1953 | * | |
f7bdd12d BK |
1954 | * Sets the PCI reset state for the device. |
1955 | */ | |
1956 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1957 | { | |
1958 | return pcibios_set_pcie_reset_state(dev, state); | |
1959 | } | |
b7fe9434 | 1960 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 1961 | |
dcb0453d BH |
1962 | /** |
1963 | * pcie_clear_root_pme_status - Clear root port PME interrupt status. | |
1964 | * @dev: PCIe root port or event collector. | |
1965 | */ | |
1966 | void pcie_clear_root_pme_status(struct pci_dev *dev) | |
1967 | { | |
1968 | pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME); | |
1969 | } | |
1970 | ||
58ff4633 RW |
1971 | /** |
1972 | * pci_check_pme_status - Check if given device has generated PME. | |
1973 | * @dev: Device to check. | |
1974 | * | |
1975 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1976 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1977 | * 'false' otherwise. | |
1978 | */ | |
1979 | bool pci_check_pme_status(struct pci_dev *dev) | |
1980 | { | |
1981 | int pmcsr_pos; | |
1982 | u16 pmcsr; | |
1983 | bool ret = false; | |
1984 | ||
1985 | if (!dev->pm_cap) | |
1986 | return false; | |
1987 | ||
1988 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1989 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1990 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1991 | return false; | |
1992 | ||
1993 | /* Clear PME status. */ | |
1994 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1995 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1996 | /* Disable PME to avoid interrupt flood. */ | |
1997 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1998 | ret = true; | |
1999 | } | |
2000 | ||
2001 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
2002 | ||
2003 | return ret; | |
2004 | } | |
2005 | ||
b67ea761 RW |
2006 | /** |
2007 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
2008 | * @dev: Device to handle. | |
379021d5 | 2009 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
2010 | * |
2011 | * Check if @dev has generated PME and queue a resume request for it in that | |
2012 | * case. | |
2013 | */ | |
379021d5 | 2014 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 2015 | { |
379021d5 RW |
2016 | if (pme_poll_reset && dev->pme_poll) |
2017 | dev->pme_poll = false; | |
2018 | ||
c125e96f | 2019 | if (pci_check_pme_status(dev)) { |
c125e96f | 2020 | pci_wakeup_event(dev); |
0f953bf6 | 2021 | pm_request_resume(&dev->dev); |
c125e96f | 2022 | } |
b67ea761 RW |
2023 | return 0; |
2024 | } | |
2025 | ||
2026 | /** | |
2027 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
2028 | * @bus: Top bus of the subtree to walk. | |
2029 | */ | |
2030 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
2031 | { | |
2032 | if (bus) | |
379021d5 | 2033 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
2034 | } |
2035 | ||
448bd857 | 2036 | |
eb9d0fe4 RW |
2037 | /** |
2038 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
2039 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
2040 | * @state: PCI state from which device will issue PME#. |
2041 | */ | |
e5899e1b | 2042 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 2043 | { |
337001b6 | 2044 | if (!dev->pm_cap) |
eb9d0fe4 RW |
2045 | return false; |
2046 | ||
337001b6 | 2047 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 2048 | } |
b7fe9434 | 2049 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 2050 | |
df17e62e MG |
2051 | static void pci_pme_list_scan(struct work_struct *work) |
2052 | { | |
379021d5 | 2053 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
2054 | |
2055 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
2056 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
2057 | if (pme_dev->dev->pme_poll) { | |
2058 | struct pci_dev *bridge; | |
2059 | ||
2060 | bridge = pme_dev->dev->bus->self; | |
2061 | /* | |
2062 | * If bridge is in low power state, the | |
2063 | * configuration space of subordinate devices | |
2064 | * may be not accessible | |
2065 | */ | |
2066 | if (bridge && bridge->current_state != PCI_D0) | |
2067 | continue; | |
2068 | pci_pme_wakeup(pme_dev->dev, NULL); | |
2069 | } else { | |
2070 | list_del(&pme_dev->list); | |
2071 | kfree(pme_dev); | |
379021d5 | 2072 | } |
df17e62e | 2073 | } |
ce300008 | 2074 | if (!list_empty(&pci_pme_list)) |
ea00353f LW |
2075 | queue_delayed_work(system_freezable_wq, &pci_pme_work, |
2076 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2077 | mutex_unlock(&pci_pme_list_mutex); |
2078 | } | |
2079 | ||
2cef548a | 2080 | static void __pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
2081 | { |
2082 | u16 pmcsr; | |
2083 | ||
ffaddbe8 | 2084 | if (!dev->pme_support) |
eb9d0fe4 RW |
2085 | return; |
2086 | ||
337001b6 | 2087 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
2088 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
2089 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
2090 | if (!enable) | |
2091 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2092 | ||
337001b6 | 2093 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
2cef548a RW |
2094 | } |
2095 | ||
0ce3fcaf RW |
2096 | /** |
2097 | * pci_pme_restore - Restore PME configuration after config space restore. | |
2098 | * @dev: PCI device to update. | |
2099 | */ | |
2100 | void pci_pme_restore(struct pci_dev *dev) | |
dc15e71e RW |
2101 | { |
2102 | u16 pmcsr; | |
2103 | ||
2104 | if (!dev->pme_support) | |
2105 | return; | |
2106 | ||
2107 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
2108 | if (dev->wakeup_prepared) { | |
2109 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
0ce3fcaf | 2110 | pmcsr &= ~PCI_PM_CTRL_PME_STATUS; |
dc15e71e RW |
2111 | } else { |
2112 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2113 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
2114 | } | |
2115 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); | |
2116 | } | |
2117 | ||
2cef548a RW |
2118 | /** |
2119 | * pci_pme_active - enable or disable PCI device's PME# function | |
2120 | * @dev: PCI device to handle. | |
2121 | * @enable: 'true' to enable PME# generation; 'false' to disable it. | |
2122 | * | |
2123 | * The caller must verify that the device is capable of generating PME# before | |
2124 | * calling this function with @enable equal to 'true'. | |
2125 | */ | |
2126 | void pci_pme_active(struct pci_dev *dev, bool enable) | |
2127 | { | |
2128 | __pci_pme_active(dev, enable); | |
eb9d0fe4 | 2129 | |
6e965e0d HY |
2130 | /* |
2131 | * PCI (as opposed to PCIe) PME requires that the device have | |
2132 | * its PME# line hooked up correctly. Not all hardware vendors | |
2133 | * do this, so the PME never gets delivered and the device | |
2134 | * remains asleep. The easiest way around this is to | |
2135 | * periodically walk the list of suspended devices and check | |
2136 | * whether any have their PME flag set. The assumption is that | |
2137 | * we'll wake up often enough anyway that this won't be a huge | |
2138 | * hit, and the power savings from the devices will still be a | |
2139 | * win. | |
2140 | * | |
2141 | * Although PCIe uses in-band PME message instead of PME# line | |
2142 | * to report PME, PME does not work for some PCIe devices in | |
2143 | * reality. For example, there are devices that set their PME | |
2144 | * status bits, but don't really bother to send a PME message; | |
2145 | * there are PCI Express Root Ports that don't bother to | |
2146 | * trigger interrupts when they receive PME messages from the | |
2147 | * devices below. So PME poll is used for PCIe devices too. | |
2148 | */ | |
df17e62e | 2149 | |
379021d5 | 2150 | if (dev->pme_poll) { |
df17e62e MG |
2151 | struct pci_pme_device *pme_dev; |
2152 | if (enable) { | |
2153 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
2154 | GFP_KERNEL); | |
0394cb19 | 2155 | if (!pme_dev) { |
7506dc79 | 2156 | pci_warn(dev, "can't enable PME#\n"); |
0394cb19 BH |
2157 | return; |
2158 | } | |
df17e62e MG |
2159 | pme_dev->dev = dev; |
2160 | mutex_lock(&pci_pme_list_mutex); | |
2161 | list_add(&pme_dev->list, &pci_pme_list); | |
2162 | if (list_is_singular(&pci_pme_list)) | |
ea00353f LW |
2163 | queue_delayed_work(system_freezable_wq, |
2164 | &pci_pme_work, | |
2165 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2166 | mutex_unlock(&pci_pme_list_mutex); |
2167 | } else { | |
2168 | mutex_lock(&pci_pme_list_mutex); | |
2169 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
2170 | if (pme_dev->dev == dev) { | |
2171 | list_del(&pme_dev->list); | |
2172 | kfree(pme_dev); | |
2173 | break; | |
2174 | } | |
2175 | } | |
2176 | mutex_unlock(&pci_pme_list_mutex); | |
2177 | } | |
2178 | } | |
2179 | ||
7506dc79 | 2180 | pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 2181 | } |
b7fe9434 | 2182 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 2183 | |
1da177e4 | 2184 | /** |
cfcadfaa | 2185 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
2186 | * @dev: PCI device affected |
2187 | * @state: PCI state from which device will issue wakeup events | |
2188 | * @enable: True to enable event generation; false to disable | |
2189 | * | |
2190 | * This enables the device as a wakeup event source, or disables it. | |
2191 | * When such events involves platform-specific hooks, those hooks are | |
2192 | * called automatically by this routine. | |
2193 | * | |
2194 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 2195 | * always require such platform hooks. |
075c1771 | 2196 | * |
eb9d0fe4 RW |
2197 | * RETURN VALUE: |
2198 | * 0 is returned on success | |
2199 | * -EINVAL is returned if device is not supposed to wake up the system | |
2200 | * Error code depending on the platform is returned if both the platform and | |
2201 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 2202 | */ |
cfcadfaa | 2203 | static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) |
1da177e4 | 2204 | { |
5bcc2fb4 | 2205 | int ret = 0; |
075c1771 | 2206 | |
baecc470 | 2207 | /* |
ac86e8ee MW |
2208 | * Bridges that are not power-manageable directly only signal |
2209 | * wakeup on behalf of subordinate devices which is set up | |
2210 | * elsewhere, so skip them. However, bridges that are | |
2211 | * power-manageable may signal wakeup for themselves (for example, | |
2212 | * on a hotplug event) and they need to be covered here. | |
baecc470 | 2213 | */ |
ac86e8ee | 2214 | if (!pci_power_manageable(dev)) |
baecc470 RW |
2215 | return 0; |
2216 | ||
0ce3fcaf RW |
2217 | /* Don't do the same thing twice in a row for one device. */ |
2218 | if (!!enable == !!dev->wakeup_prepared) | |
e80bb09d RW |
2219 | return 0; |
2220 | ||
eb9d0fe4 RW |
2221 | /* |
2222 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
2223 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
2224 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 2225 | */ |
1da177e4 | 2226 | |
5bcc2fb4 RW |
2227 | if (enable) { |
2228 | int error; | |
1da177e4 | 2229 | |
5bcc2fb4 RW |
2230 | if (pci_pme_capable(dev, state)) |
2231 | pci_pme_active(dev, true); | |
2232 | else | |
2233 | ret = 1; | |
0847684c | 2234 | error = platform_pci_set_wakeup(dev, true); |
5bcc2fb4 RW |
2235 | if (ret) |
2236 | ret = error; | |
e80bb09d RW |
2237 | if (!ret) |
2238 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 2239 | } else { |
0847684c | 2240 | platform_pci_set_wakeup(dev, false); |
5bcc2fb4 | 2241 | pci_pme_active(dev, false); |
e80bb09d | 2242 | dev->wakeup_prepared = false; |
5bcc2fb4 | 2243 | } |
1da177e4 | 2244 | |
5bcc2fb4 | 2245 | return ret; |
eb9d0fe4 | 2246 | } |
cfcadfaa RW |
2247 | |
2248 | /** | |
2249 | * pci_enable_wake - change wakeup settings for a PCI device | |
2250 | * @pci_dev: Target device | |
2251 | * @state: PCI state from which device will issue wakeup events | |
2252 | * @enable: Whether or not to enable event generation | |
2253 | * | |
2254 | * If @enable is set, check device_may_wakeup() for the device before calling | |
2255 | * __pci_enable_wake() for it. | |
2256 | */ | |
2257 | int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable) | |
2258 | { | |
2259 | if (enable && !device_may_wakeup(&pci_dev->dev)) | |
2260 | return -EINVAL; | |
2261 | ||
2262 | return __pci_enable_wake(pci_dev, state, enable); | |
2263 | } | |
0847684c | 2264 | EXPORT_SYMBOL(pci_enable_wake); |
1da177e4 | 2265 | |
0235c4fc RW |
2266 | /** |
2267 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
2268 | * @dev: PCI device to prepare | |
2269 | * @enable: True to enable wake-up event generation; false to disable | |
2270 | * | |
2271 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
2272 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
2273 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
2274 | * ordering constraints. | |
2275 | * | |
cfcadfaa RW |
2276 | * This function only returns error code if the device is not allowed to wake |
2277 | * up the system from sleep or it is not capable of generating PME# from both | |
2278 | * D3_hot and D3_cold and the platform is unable to enable wake-up power for it. | |
0235c4fc RW |
2279 | */ |
2280 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
2281 | { | |
2282 | return pci_pme_capable(dev, PCI_D3cold) ? | |
2283 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
2284 | pci_enable_wake(dev, PCI_D3hot, enable); | |
2285 | } | |
b7fe9434 | 2286 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 2287 | |
404cc2d8 | 2288 | /** |
37139074 JB |
2289 | * pci_target_state - find an appropriate low power state for a given PCI dev |
2290 | * @dev: PCI device | |
666ff6f8 | 2291 | * @wakeup: Whether or not wakeup functionality will be enabled for the device. |
37139074 JB |
2292 | * |
2293 | * Use underlying platform code to find a supported low power state for @dev. | |
2294 | * If the platform can't manage @dev, return the deepest state from which it | |
2295 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 2296 | */ |
666ff6f8 | 2297 | static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup) |
404cc2d8 RW |
2298 | { |
2299 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
2300 | |
2301 | if (platform_pci_power_manageable(dev)) { | |
2302 | /* | |
60ee031a | 2303 | * Call the platform to find the target state for the device. |
404cc2d8 RW |
2304 | */ |
2305 | pci_power_t state = platform_pci_choose_state(dev); | |
2306 | ||
2307 | switch (state) { | |
2308 | case PCI_POWER_ERROR: | |
2309 | case PCI_UNKNOWN: | |
2310 | break; | |
2311 | case PCI_D1: | |
2312 | case PCI_D2: | |
2313 | if (pci_no_d1d2(dev)) | |
2314 | break; | |
1d09d577 | 2315 | /* else, fall through */ |
404cc2d8 RW |
2316 | default: |
2317 | target_state = state; | |
404cc2d8 | 2318 | } |
4132a577 LW |
2319 | |
2320 | return target_state; | |
2321 | } | |
2322 | ||
2323 | if (!dev->pm_cap) | |
d2abdf62 | 2324 | target_state = PCI_D0; |
4132a577 LW |
2325 | |
2326 | /* | |
2327 | * If the device is in D3cold even though it's not power-manageable by | |
2328 | * the platform, it may have been powered down by non-standard means. | |
2329 | * Best to let it slumber. | |
2330 | */ | |
2331 | if (dev->current_state == PCI_D3cold) | |
2332 | target_state = PCI_D3cold; | |
2333 | ||
666ff6f8 | 2334 | if (wakeup) { |
404cc2d8 RW |
2335 | /* |
2336 | * Find the deepest state from which the device can generate | |
60ee031a | 2337 | * PME#. |
404cc2d8 | 2338 | */ |
337001b6 RW |
2339 | if (dev->pme_support) { |
2340 | while (target_state | |
2341 | && !(dev->pme_support & (1 << target_state))) | |
2342 | target_state--; | |
404cc2d8 RW |
2343 | } |
2344 | } | |
2345 | ||
e5899e1b RW |
2346 | return target_state; |
2347 | } | |
2348 | ||
2349 | /** | |
74356add BH |
2350 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition |
2351 | * into a sleep state | |
e5899e1b RW |
2352 | * @dev: Device to handle. |
2353 | * | |
2354 | * Choose the power state appropriate for the device depending on whether | |
2355 | * it can wake up the system and/or is power manageable by the platform | |
2356 | * (PCI_D3hot is the default) and put the device into that state. | |
2357 | */ | |
2358 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
2359 | { | |
666ff6f8 RW |
2360 | bool wakeup = device_may_wakeup(&dev->dev); |
2361 | pci_power_t target_state = pci_target_state(dev, wakeup); | |
e5899e1b RW |
2362 | int error; |
2363 | ||
2364 | if (target_state == PCI_POWER_ERROR) | |
2365 | return -EIO; | |
2366 | ||
666ff6f8 | 2367 | pci_enable_wake(dev, target_state, wakeup); |
c157dfa3 | 2368 | |
404cc2d8 RW |
2369 | error = pci_set_power_state(dev, target_state); |
2370 | ||
2371 | if (error) | |
2372 | pci_enable_wake(dev, target_state, false); | |
2373 | ||
2374 | return error; | |
2375 | } | |
b7fe9434 | 2376 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
2377 | |
2378 | /** | |
74356add BH |
2379 | * pci_back_from_sleep - turn PCI device on during system-wide transition |
2380 | * into working state | |
404cc2d8 RW |
2381 | * @dev: Device to handle. |
2382 | * | |
88393161 | 2383 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
2384 | */ |
2385 | int pci_back_from_sleep(struct pci_dev *dev) | |
2386 | { | |
2387 | pci_enable_wake(dev, PCI_D0, false); | |
2388 | return pci_set_power_state(dev, PCI_D0); | |
2389 | } | |
b7fe9434 | 2390 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 2391 | |
6cbf8214 RW |
2392 | /** |
2393 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
2394 | * @dev: PCI device being suspended. | |
2395 | * | |
2396 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
2397 | * power state. | |
2398 | */ | |
2399 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
2400 | { | |
666ff6f8 | 2401 | pci_power_t target_state; |
6cbf8214 RW |
2402 | int error; |
2403 | ||
666ff6f8 | 2404 | target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); |
6cbf8214 RW |
2405 | if (target_state == PCI_POWER_ERROR) |
2406 | return -EIO; | |
2407 | ||
448bd857 HY |
2408 | dev->runtime_d3cold = target_state == PCI_D3cold; |
2409 | ||
cfcadfaa | 2410 | __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev)); |
6cbf8214 RW |
2411 | |
2412 | error = pci_set_power_state(dev, target_state); | |
2413 | ||
448bd857 | 2414 | if (error) { |
0847684c | 2415 | pci_enable_wake(dev, target_state, false); |
448bd857 HY |
2416 | dev->runtime_d3cold = false; |
2417 | } | |
6cbf8214 RW |
2418 | |
2419 | return error; | |
2420 | } | |
2421 | ||
b67ea761 RW |
2422 | /** |
2423 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
2424 | * @dev: Device to check. | |
2425 | * | |
f7625980 | 2426 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
2427 | * (through the platform or using the native PCIe PME) or if the device supports |
2428 | * PME and one of its upstream bridges can generate wake-up events. | |
2429 | */ | |
2430 | bool pci_dev_run_wake(struct pci_dev *dev) | |
2431 | { | |
2432 | struct pci_bus *bus = dev->bus; | |
2433 | ||
b67ea761 RW |
2434 | if (!dev->pme_support) |
2435 | return false; | |
2436 | ||
666ff6f8 | 2437 | /* PME-capable in principle, but not from the target power state */ |
8feaec33 | 2438 | if (!pci_pme_capable(dev, pci_target_state(dev, true))) |
6496ebd7 AS |
2439 | return false; |
2440 | ||
8feaec33 KHF |
2441 | if (device_can_wakeup(&dev->dev)) |
2442 | return true; | |
2443 | ||
b67ea761 RW |
2444 | while (bus->parent) { |
2445 | struct pci_dev *bridge = bus->self; | |
2446 | ||
de3ef1eb | 2447 | if (device_can_wakeup(&bridge->dev)) |
b67ea761 RW |
2448 | return true; |
2449 | ||
2450 | bus = bus->parent; | |
2451 | } | |
2452 | ||
2453 | /* We have reached the root bus. */ | |
2454 | if (bus->bridge) | |
de3ef1eb | 2455 | return device_can_wakeup(bus->bridge); |
b67ea761 RW |
2456 | |
2457 | return false; | |
2458 | } | |
2459 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2460 | ||
bac2a909 RW |
2461 | /** |
2462 | * pci_dev_keep_suspended - Check if the device can stay in the suspended state. | |
2463 | * @pci_dev: Device to check. | |
2464 | * | |
2465 | * Return 'true' if the device is runtime-suspended, it doesn't have to be | |
2466 | * reconfigured due to wakeup settings difference between system and runtime | |
2467 | * suspend and the current power state of it is suitable for the upcoming | |
2468 | * (system) transition. | |
2cef548a RW |
2469 | * |
2470 | * If the device is not configured for system wakeup, disable PME for it before | |
2471 | * returning 'true' to prevent it from waking up the system unnecessarily. | |
bac2a909 RW |
2472 | */ |
2473 | bool pci_dev_keep_suspended(struct pci_dev *pci_dev) | |
2474 | { | |
2475 | struct device *dev = &pci_dev->dev; | |
666ff6f8 | 2476 | bool wakeup = device_may_wakeup(dev); |
bac2a909 RW |
2477 | |
2478 | if (!pm_runtime_suspended(dev) | |
666ff6f8 | 2479 | || pci_target_state(pci_dev, wakeup) != pci_dev->current_state |
c2eac4d3 | 2480 | || platform_pci_need_resume(pci_dev)) |
bac2a909 RW |
2481 | return false; |
2482 | ||
2cef548a RW |
2483 | /* |
2484 | * At this point the device is good to go unless it's been configured | |
2485 | * to generate PME at the runtime suspend time, but it is not supposed | |
2486 | * to wake up the system. In that case, simply disable PME for it | |
2487 | * (it will have to be re-enabled on exit from system resume). | |
2488 | * | |
2489 | * If the device's power state is D3cold and the platform check above | |
2490 | * hasn't triggered, the device's configuration is suitable and we don't | |
2491 | * need to manipulate it at all. | |
2492 | */ | |
2493 | spin_lock_irq(&dev->power.lock); | |
2494 | ||
2495 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold && | |
666ff6f8 | 2496 | !wakeup) |
2cef548a RW |
2497 | __pci_pme_active(pci_dev, false); |
2498 | ||
2499 | spin_unlock_irq(&dev->power.lock); | |
2500 | return true; | |
2501 | } | |
2502 | ||
2503 | /** | |
2504 | * pci_dev_complete_resume - Finalize resume from system sleep for a device. | |
2505 | * @pci_dev: Device to handle. | |
2506 | * | |
2507 | * If the device is runtime suspended and wakeup-capable, enable PME for it as | |
2508 | * it might have been disabled during the prepare phase of system suspend if | |
2509 | * the device was not configured for system wakeup. | |
2510 | */ | |
2511 | void pci_dev_complete_resume(struct pci_dev *pci_dev) | |
2512 | { | |
2513 | struct device *dev = &pci_dev->dev; | |
2514 | ||
2515 | if (!pci_dev_run_wake(pci_dev)) | |
2516 | return; | |
2517 | ||
2518 | spin_lock_irq(&dev->power.lock); | |
2519 | ||
2520 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) | |
2521 | __pci_pme_active(pci_dev, true); | |
2522 | ||
2523 | spin_unlock_irq(&dev->power.lock); | |
bac2a909 RW |
2524 | } |
2525 | ||
b3c32c4f HY |
2526 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2527 | { | |
2528 | struct device *dev = &pdev->dev; | |
2529 | struct device *parent = dev->parent; | |
2530 | ||
2531 | if (parent) | |
2532 | pm_runtime_get_sync(parent); | |
2533 | pm_runtime_get_noresume(dev); | |
2534 | /* | |
2535 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2536 | * so wait until suspending completes | |
2537 | */ | |
2538 | pm_runtime_barrier(dev); | |
2539 | /* | |
2540 | * Only need to resume devices in D3cold, because config | |
2541 | * registers are still accessible for devices suspended but | |
2542 | * not in D3cold. | |
2543 | */ | |
2544 | if (pdev->current_state == PCI_D3cold) | |
2545 | pm_runtime_resume(dev); | |
2546 | } | |
2547 | ||
2548 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2549 | { | |
2550 | struct device *dev = &pdev->dev; | |
2551 | struct device *parent = dev->parent; | |
2552 | ||
2553 | pm_runtime_put(dev); | |
2554 | if (parent) | |
2555 | pm_runtime_put_sync(parent); | |
2556 | } | |
2557 | ||
85b0cae8 MW |
2558 | static const struct dmi_system_id bridge_d3_blacklist[] = { |
2559 | #ifdef CONFIG_X86 | |
2560 | { | |
2561 | /* | |
2562 | * Gigabyte X299 root port is not marked as hotplug capable | |
2563 | * which allows Linux to power manage it. However, this | |
2564 | * confuses the BIOS SMI handler so don't power manage root | |
2565 | * ports on that system. | |
2566 | */ | |
2567 | .ident = "X299 DESIGNARE EX-CF", | |
2568 | .matches = { | |
2569 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
2570 | DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"), | |
2571 | }, | |
2572 | }, | |
2573 | #endif | |
2574 | { } | |
2575 | }; | |
2576 | ||
9d26d3a8 MW |
2577 | /** |
2578 | * pci_bridge_d3_possible - Is it possible to put the bridge into D3 | |
2579 | * @bridge: Bridge to check | |
2580 | * | |
2581 | * This function checks if it is possible to move the bridge to D3. | |
47a8e237 | 2582 | * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt. |
9d26d3a8 | 2583 | */ |
c6a63307 | 2584 | bool pci_bridge_d3_possible(struct pci_dev *bridge) |
9d26d3a8 | 2585 | { |
9d26d3a8 MW |
2586 | if (!pci_is_pcie(bridge)) |
2587 | return false; | |
2588 | ||
2589 | switch (pci_pcie_type(bridge)) { | |
2590 | case PCI_EXP_TYPE_ROOT_PORT: | |
2591 | case PCI_EXP_TYPE_UPSTREAM: | |
2592 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2593 | if (pci_bridge_d3_disable) | |
2594 | return false; | |
97a90aee LW |
2595 | |
2596 | /* | |
eb3b5bf1 | 2597 | * Hotplug ports handled by firmware in System Management Mode |
97a90aee | 2598 | * may not be put into D3 by the OS (Thunderbolt on non-Macs). |
97a90aee | 2599 | */ |
eb3b5bf1 | 2600 | if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) |
97a90aee LW |
2601 | return false; |
2602 | ||
9d26d3a8 MW |
2603 | if (pci_bridge_d3_force) |
2604 | return true; | |
2605 | ||
47a8e237 LW |
2606 | /* Even the oldest 2010 Thunderbolt controller supports D3. */ |
2607 | if (bridge->is_thunderbolt) | |
2608 | return true; | |
2609 | ||
26ad34d5 MW |
2610 | /* Platform might know better if the bridge supports D3 */ |
2611 | if (platform_pci_bridge_d3(bridge)) | |
2612 | return true; | |
2613 | ||
eb3b5bf1 LW |
2614 | /* |
2615 | * Hotplug ports handled natively by the OS were not validated | |
2616 | * by vendors for runtime D3 at least until 2018 because there | |
2617 | * was no OS support. | |
2618 | */ | |
2619 | if (bridge->is_hotplug_bridge) | |
2620 | return false; | |
2621 | ||
85b0cae8 MW |
2622 | if (dmi_check_system(bridge_d3_blacklist)) |
2623 | return false; | |
2624 | ||
9d26d3a8 MW |
2625 | /* |
2626 | * It should be safe to put PCIe ports from 2015 or newer | |
2627 | * to D3. | |
2628 | */ | |
ac95090a | 2629 | if (dmi_get_bios_year() >= 2015) |
9d26d3a8 | 2630 | return true; |
9d26d3a8 MW |
2631 | break; |
2632 | } | |
2633 | ||
2634 | return false; | |
2635 | } | |
2636 | ||
2637 | static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) | |
2638 | { | |
2639 | bool *d3cold_ok = data; | |
9d26d3a8 | 2640 | |
718a0609 LW |
2641 | if (/* The device needs to be allowed to go D3cold ... */ |
2642 | dev->no_d3cold || !dev->d3cold_allowed || | |
2643 | ||
2644 | /* ... and if it is wakeup capable to do so from D3cold. */ | |
2645 | (device_may_wakeup(&dev->dev) && | |
2646 | !pci_pme_capable(dev, PCI_D3cold)) || | |
2647 | ||
2648 | /* If it is a bridge it must be allowed to go to D3. */ | |
d98e0929 | 2649 | !pci_power_manageable(dev)) |
9d26d3a8 | 2650 | |
718a0609 | 2651 | *d3cold_ok = false; |
9d26d3a8 | 2652 | |
718a0609 | 2653 | return !*d3cold_ok; |
9d26d3a8 MW |
2654 | } |
2655 | ||
2656 | /* | |
2657 | * pci_bridge_d3_update - Update bridge D3 capabilities | |
2658 | * @dev: PCI device which is changed | |
9d26d3a8 MW |
2659 | * |
2660 | * Update upstream bridge PM capabilities accordingly depending on if the | |
2661 | * device PM configuration was changed or the device is being removed. The | |
2662 | * change is also propagated upstream. | |
2663 | */ | |
1ed276a7 | 2664 | void pci_bridge_d3_update(struct pci_dev *dev) |
9d26d3a8 | 2665 | { |
1ed276a7 | 2666 | bool remove = !device_is_registered(&dev->dev); |
9d26d3a8 MW |
2667 | struct pci_dev *bridge; |
2668 | bool d3cold_ok = true; | |
2669 | ||
2670 | bridge = pci_upstream_bridge(dev); | |
2671 | if (!bridge || !pci_bridge_d3_possible(bridge)) | |
2672 | return; | |
2673 | ||
9d26d3a8 | 2674 | /* |
e8559b71 LW |
2675 | * If D3 is currently allowed for the bridge, removing one of its |
2676 | * children won't change that. | |
2677 | */ | |
2678 | if (remove && bridge->bridge_d3) | |
2679 | return; | |
2680 | ||
2681 | /* | |
2682 | * If D3 is currently allowed for the bridge and a child is added or | |
2683 | * changed, disallowance of D3 can only be caused by that child, so | |
2684 | * we only need to check that single device, not any of its siblings. | |
2685 | * | |
2686 | * If D3 is currently not allowed for the bridge, checking the device | |
2687 | * first may allow us to skip checking its siblings. | |
9d26d3a8 MW |
2688 | */ |
2689 | if (!remove) | |
2690 | pci_dev_check_d3cold(dev, &d3cold_ok); | |
2691 | ||
e8559b71 LW |
2692 | /* |
2693 | * If D3 is currently not allowed for the bridge, this may be caused | |
2694 | * either by the device being changed/removed or any of its siblings, | |
2695 | * so we need to go through all children to find out if one of them | |
2696 | * continues to block D3. | |
2697 | */ | |
2698 | if (d3cold_ok && !bridge->bridge_d3) | |
9d26d3a8 MW |
2699 | pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, |
2700 | &d3cold_ok); | |
9d26d3a8 MW |
2701 | |
2702 | if (bridge->bridge_d3 != d3cold_ok) { | |
2703 | bridge->bridge_d3 = d3cold_ok; | |
2704 | /* Propagate change to upstream bridges */ | |
1ed276a7 | 2705 | pci_bridge_d3_update(bridge); |
9d26d3a8 | 2706 | } |
9d26d3a8 MW |
2707 | } |
2708 | ||
9d26d3a8 MW |
2709 | /** |
2710 | * pci_d3cold_enable - Enable D3cold for device | |
2711 | * @dev: PCI device to handle | |
2712 | * | |
2713 | * This function can be used in drivers to enable D3cold from the device | |
2714 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2715 | * accordingly. | |
2716 | */ | |
2717 | void pci_d3cold_enable(struct pci_dev *dev) | |
2718 | { | |
2719 | if (dev->no_d3cold) { | |
2720 | dev->no_d3cold = false; | |
1ed276a7 | 2721 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2722 | } |
2723 | } | |
2724 | EXPORT_SYMBOL_GPL(pci_d3cold_enable); | |
2725 | ||
2726 | /** | |
2727 | * pci_d3cold_disable - Disable D3cold for device | |
2728 | * @dev: PCI device to handle | |
2729 | * | |
2730 | * This function can be used in drivers to disable D3cold from the device | |
2731 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2732 | * accordingly. | |
2733 | */ | |
2734 | void pci_d3cold_disable(struct pci_dev *dev) | |
2735 | { | |
2736 | if (!dev->no_d3cold) { | |
2737 | dev->no_d3cold = true; | |
1ed276a7 | 2738 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2739 | } |
2740 | } | |
2741 | EXPORT_SYMBOL_GPL(pci_d3cold_disable); | |
2742 | ||
eb9d0fe4 RW |
2743 | /** |
2744 | * pci_pm_init - Initialize PM functions of given PCI device | |
2745 | * @dev: PCI device to handle. | |
2746 | */ | |
2747 | void pci_pm_init(struct pci_dev *dev) | |
2748 | { | |
2749 | int pm; | |
d6112f8d | 2750 | u16 status; |
eb9d0fe4 | 2751 | u16 pmc; |
1da177e4 | 2752 | |
bb910a70 | 2753 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2754 | pm_runtime_set_active(&dev->dev); |
2755 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2756 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2757 | dev->wakeup_prepared = false; |
bb910a70 | 2758 | |
337001b6 | 2759 | dev->pm_cap = 0; |
ffaddbe8 | 2760 | dev->pme_support = 0; |
337001b6 | 2761 | |
eb9d0fe4 RW |
2762 | /* find PCI PM capability in list */ |
2763 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
2764 | if (!pm) | |
50246dd4 | 2765 | return; |
eb9d0fe4 RW |
2766 | /* Check device's ability to generate PME# */ |
2767 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 2768 | |
eb9d0fe4 | 2769 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
7506dc79 | 2770 | pci_err(dev, "unsupported PM cap regs version (%u)\n", |
eb9d0fe4 | 2771 | pmc & PCI_PM_CAP_VER_MASK); |
50246dd4 | 2772 | return; |
eb9d0fe4 RW |
2773 | } |
2774 | ||
337001b6 | 2775 | dev->pm_cap = pm; |
1ae861e6 | 2776 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 2777 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
9d26d3a8 | 2778 | dev->bridge_d3 = pci_bridge_d3_possible(dev); |
4f9c1397 | 2779 | dev->d3cold_allowed = true; |
337001b6 RW |
2780 | |
2781 | dev->d1_support = false; | |
2782 | dev->d2_support = false; | |
2783 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 2784 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 2785 | dev->d1_support = true; |
c9ed77ee | 2786 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 2787 | dev->d2_support = true; |
c9ed77ee BH |
2788 | |
2789 | if (dev->d1_support || dev->d2_support) | |
34c6b710 | 2790 | pci_info(dev, "supports%s%s\n", |
ec84f126 JB |
2791 | dev->d1_support ? " D1" : "", |
2792 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
2793 | } |
2794 | ||
2795 | pmc &= PCI_PM_CAP_PME_MASK; | |
2796 | if (pmc) { | |
34c6b710 | 2797 | pci_info(dev, "PME# supported from%s%s%s%s%s\n", |
c9ed77ee BH |
2798 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
2799 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
2800 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2801 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2802 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2803 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2804 | dev->pme_poll = true; |
eb9d0fe4 RW |
2805 | /* |
2806 | * Make device's PM flags reflect the wake-up capability, but | |
2807 | * let the user space enable it to wake up the system as needed. | |
2808 | */ | |
2809 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2810 | /* Disable the PME# generation functionality */ |
337001b6 | 2811 | pci_pme_active(dev, false); |
eb9d0fe4 | 2812 | } |
d6112f8d FB |
2813 | |
2814 | pci_read_config_word(dev, PCI_STATUS, &status); | |
2815 | if (status & PCI_STATUS_IMM_READY) | |
2816 | dev->imm_ready = 1; | |
1da177e4 LT |
2817 | } |
2818 | ||
938174e5 SS |
2819 | static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) |
2820 | { | |
92efb1bd | 2821 | unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; |
938174e5 SS |
2822 | |
2823 | switch (prop) { | |
2824 | case PCI_EA_P_MEM: | |
2825 | case PCI_EA_P_VF_MEM: | |
2826 | flags |= IORESOURCE_MEM; | |
2827 | break; | |
2828 | case PCI_EA_P_MEM_PREFETCH: | |
2829 | case PCI_EA_P_VF_MEM_PREFETCH: | |
2830 | flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
2831 | break; | |
2832 | case PCI_EA_P_IO: | |
2833 | flags |= IORESOURCE_IO; | |
2834 | break; | |
2835 | default: | |
2836 | return 0; | |
2837 | } | |
2838 | ||
2839 | return flags; | |
2840 | } | |
2841 | ||
2842 | static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, | |
2843 | u8 prop) | |
2844 | { | |
2845 | if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) | |
2846 | return &dev->resource[bei]; | |
11183991 DD |
2847 | #ifdef CONFIG_PCI_IOV |
2848 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && | |
2849 | (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) | |
2850 | return &dev->resource[PCI_IOV_RESOURCES + | |
2851 | bei - PCI_EA_BEI_VF_BAR0]; | |
2852 | #endif | |
938174e5 SS |
2853 | else if (bei == PCI_EA_BEI_ROM) |
2854 | return &dev->resource[PCI_ROM_RESOURCE]; | |
2855 | else | |
2856 | return NULL; | |
2857 | } | |
2858 | ||
2859 | /* Read an Enhanced Allocation (EA) entry */ | |
2860 | static int pci_ea_read(struct pci_dev *dev, int offset) | |
2861 | { | |
2862 | struct resource *res; | |
2863 | int ent_size, ent_offset = offset; | |
2864 | resource_size_t start, end; | |
2865 | unsigned long flags; | |
26635112 | 2866 | u32 dw0, bei, base, max_offset; |
938174e5 SS |
2867 | u8 prop; |
2868 | bool support_64 = (sizeof(resource_size_t) >= 8); | |
2869 | ||
2870 | pci_read_config_dword(dev, ent_offset, &dw0); | |
2871 | ent_offset += 4; | |
2872 | ||
2873 | /* Entry size field indicates DWORDs after 1st */ | |
2874 | ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; | |
2875 | ||
2876 | if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ | |
2877 | goto out; | |
2878 | ||
26635112 BH |
2879 | bei = (dw0 & PCI_EA_BEI) >> 4; |
2880 | prop = (dw0 & PCI_EA_PP) >> 8; | |
2881 | ||
938174e5 SS |
2882 | /* |
2883 | * If the Property is in the reserved range, try the Secondary | |
2884 | * Property instead. | |
2885 | */ | |
2886 | if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) | |
26635112 | 2887 | prop = (dw0 & PCI_EA_SP) >> 16; |
938174e5 SS |
2888 | if (prop > PCI_EA_P_BRIDGE_IO) |
2889 | goto out; | |
2890 | ||
26635112 | 2891 | res = pci_ea_get_resource(dev, bei, prop); |
938174e5 | 2892 | if (!res) { |
7506dc79 | 2893 | pci_err(dev, "Unsupported EA entry BEI: %u\n", bei); |
938174e5 SS |
2894 | goto out; |
2895 | } | |
2896 | ||
2897 | flags = pci_ea_flags(dev, prop); | |
2898 | if (!flags) { | |
7506dc79 | 2899 | pci_err(dev, "Unsupported EA properties: %#x\n", prop); |
938174e5 SS |
2900 | goto out; |
2901 | } | |
2902 | ||
2903 | /* Read Base */ | |
2904 | pci_read_config_dword(dev, ent_offset, &base); | |
2905 | start = (base & PCI_EA_FIELD_MASK); | |
2906 | ent_offset += 4; | |
2907 | ||
2908 | /* Read MaxOffset */ | |
2909 | pci_read_config_dword(dev, ent_offset, &max_offset); | |
2910 | ent_offset += 4; | |
2911 | ||
2912 | /* Read Base MSBs (if 64-bit entry) */ | |
2913 | if (base & PCI_EA_IS_64) { | |
2914 | u32 base_upper; | |
2915 | ||
2916 | pci_read_config_dword(dev, ent_offset, &base_upper); | |
2917 | ent_offset += 4; | |
2918 | ||
2919 | flags |= IORESOURCE_MEM_64; | |
2920 | ||
2921 | /* entry starts above 32-bit boundary, can't use */ | |
2922 | if (!support_64 && base_upper) | |
2923 | goto out; | |
2924 | ||
2925 | if (support_64) | |
2926 | start |= ((u64)base_upper << 32); | |
2927 | } | |
2928 | ||
2929 | end = start + (max_offset | 0x03); | |
2930 | ||
2931 | /* Read MaxOffset MSBs (if 64-bit entry) */ | |
2932 | if (max_offset & PCI_EA_IS_64) { | |
2933 | u32 max_offset_upper; | |
2934 | ||
2935 | pci_read_config_dword(dev, ent_offset, &max_offset_upper); | |
2936 | ent_offset += 4; | |
2937 | ||
2938 | flags |= IORESOURCE_MEM_64; | |
2939 | ||
2940 | /* entry too big, can't use */ | |
2941 | if (!support_64 && max_offset_upper) | |
2942 | goto out; | |
2943 | ||
2944 | if (support_64) | |
2945 | end += ((u64)max_offset_upper << 32); | |
2946 | } | |
2947 | ||
2948 | if (end < start) { | |
7506dc79 | 2949 | pci_err(dev, "EA Entry crosses address boundary\n"); |
938174e5 SS |
2950 | goto out; |
2951 | } | |
2952 | ||
2953 | if (ent_size != ent_offset - offset) { | |
7506dc79 | 2954 | pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n", |
938174e5 SS |
2955 | ent_size, ent_offset - offset); |
2956 | goto out; | |
2957 | } | |
2958 | ||
2959 | res->name = pci_name(dev); | |
2960 | res->start = start; | |
2961 | res->end = end; | |
2962 | res->flags = flags; | |
597becb4 BH |
2963 | |
2964 | if (bei <= PCI_EA_BEI_BAR5) | |
34c6b710 | 2965 | pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
2966 | bei, res, prop); |
2967 | else if (bei == PCI_EA_BEI_ROM) | |
34c6b710 | 2968 | pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
2969 | res, prop); |
2970 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) | |
34c6b710 | 2971 | pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
2972 | bei - PCI_EA_BEI_VF_BAR0, res, prop); |
2973 | else | |
34c6b710 | 2974 | pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
2975 | bei, res, prop); |
2976 | ||
938174e5 SS |
2977 | out: |
2978 | return offset + ent_size; | |
2979 | } | |
2980 | ||
dcbb408a | 2981 | /* Enhanced Allocation Initialization */ |
938174e5 SS |
2982 | void pci_ea_init(struct pci_dev *dev) |
2983 | { | |
2984 | int ea; | |
2985 | u8 num_ent; | |
2986 | int offset; | |
2987 | int i; | |
2988 | ||
2989 | /* find PCI EA capability in list */ | |
2990 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
2991 | if (!ea) | |
2992 | return; | |
2993 | ||
2994 | /* determine the number of entries */ | |
2995 | pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, | |
2996 | &num_ent); | |
2997 | num_ent &= PCI_EA_NUM_ENT_MASK; | |
2998 | ||
2999 | offset = ea + PCI_EA_FIRST_ENT; | |
3000 | ||
3001 | /* Skip DWORD 2 for type 1 functions */ | |
3002 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
3003 | offset += 4; | |
3004 | ||
3005 | /* parse each EA entry */ | |
3006 | for (i = 0; i < num_ent; ++i) | |
3007 | offset = pci_ea_read(dev, offset); | |
3008 | } | |
3009 | ||
34a4876e YL |
3010 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
3011 | struct pci_cap_saved_state *new_cap) | |
3012 | { | |
3013 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
3014 | } | |
3015 | ||
63f4898a | 3016 | /** |
fd0f7f73 | 3017 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
74356add | 3018 | * capability registers |
63f4898a RW |
3019 | * @dev: the PCI device |
3020 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 3021 | * @extended: Standard or Extended capability ID |
63f4898a RW |
3022 | * @size: requested size of the buffer |
3023 | */ | |
fd0f7f73 AW |
3024 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
3025 | bool extended, unsigned int size) | |
63f4898a RW |
3026 | { |
3027 | int pos; | |
3028 | struct pci_cap_saved_state *save_state; | |
3029 | ||
fd0f7f73 AW |
3030 | if (extended) |
3031 | pos = pci_find_ext_capability(dev, cap); | |
3032 | else | |
3033 | pos = pci_find_capability(dev, cap); | |
3034 | ||
0a1a9b49 | 3035 | if (!pos) |
63f4898a RW |
3036 | return 0; |
3037 | ||
3038 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
3039 | if (!save_state) | |
3040 | return -ENOMEM; | |
3041 | ||
24a4742f | 3042 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 3043 | save_state->cap.cap_extended = extended; |
24a4742f | 3044 | save_state->cap.size = size; |
63f4898a RW |
3045 | pci_add_saved_cap(dev, save_state); |
3046 | ||
3047 | return 0; | |
3048 | } | |
3049 | ||
fd0f7f73 AW |
3050 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
3051 | { | |
3052 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
3053 | } | |
3054 | ||
3055 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
3056 | { | |
3057 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
3058 | } | |
3059 | ||
63f4898a RW |
3060 | /** |
3061 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
3062 | * @dev: the PCI device | |
3063 | */ | |
3064 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
3065 | { | |
3066 | int error; | |
3067 | ||
89858517 YZ |
3068 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
3069 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a | 3070 | if (error) |
7506dc79 | 3071 | pci_err(dev, "unable to preallocate PCI Express save buffer\n"); |
63f4898a RW |
3072 | |
3073 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
3074 | if (error) | |
7506dc79 | 3075 | pci_err(dev, "unable to preallocate PCI-X save buffer\n"); |
425c1b22 | 3076 | |
dbbfadf2 BH |
3077 | error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR, |
3078 | 2 * sizeof(u16)); | |
3079 | if (error) | |
3080 | pci_err(dev, "unable to allocate suspend buffer for LTR\n"); | |
3081 | ||
425c1b22 | 3082 | pci_allocate_vc_save_buffers(dev); |
63f4898a RW |
3083 | } |
3084 | ||
f796841e YL |
3085 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
3086 | { | |
3087 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 3088 | struct hlist_node *n; |
f796841e | 3089 | |
b67bfe0d | 3090 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
3091 | kfree(tmp); |
3092 | } | |
3093 | ||
58c3a727 | 3094 | /** |
31ab2476 | 3095 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 3096 | * @dev: the PCI device |
b0cc6020 YW |
3097 | * |
3098 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
3099 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 3100 | */ |
31ab2476 | 3101 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 3102 | { |
58c3a727 | 3103 | u32 cap; |
8113587c | 3104 | struct pci_dev *bridge; |
58c3a727 | 3105 | |
6748dcc2 | 3106 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
3107 | return; |
3108 | ||
8113587c | 3109 | bridge = dev->bus->self; |
cb97ae34 | 3110 | if (!bridge) |
8113587c ZY |
3111 | return; |
3112 | ||
59875ae4 | 3113 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
3114 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
3115 | return; | |
3116 | ||
b0cc6020 YW |
3117 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
3118 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
3119 | PCI_EXP_DEVCTL2_ARI); | |
3120 | bridge->ari_enabled = 1; | |
3121 | } else { | |
3122 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
3123 | PCI_EXP_DEVCTL2_ARI); | |
3124 | bridge->ari_enabled = 0; | |
3125 | } | |
58c3a727 YZ |
3126 | } |
3127 | ||
5d990b62 CW |
3128 | static int pci_acs_enable; |
3129 | ||
3130 | /** | |
3131 | * pci_request_acs - ask for ACS to be enabled if supported | |
3132 | */ | |
3133 | void pci_request_acs(void) | |
3134 | { | |
3135 | pci_acs_enable = 1; | |
3136 | } | |
3137 | ||
aaca43fd LG |
3138 | static const char *disable_acs_redir_param; |
3139 | ||
3140 | /** | |
3141 | * pci_disable_acs_redir - disable ACS redirect capabilities | |
3142 | * @dev: the PCI device | |
3143 | * | |
3144 | * For only devices specified in the disable_acs_redir parameter. | |
3145 | */ | |
3146 | static void pci_disable_acs_redir(struct pci_dev *dev) | |
3147 | { | |
3148 | int ret = 0; | |
3149 | const char *p; | |
3150 | int pos; | |
3151 | u16 ctrl; | |
3152 | ||
3153 | if (!disable_acs_redir_param) | |
3154 | return; | |
3155 | ||
3156 | p = disable_acs_redir_param; | |
3157 | while (*p) { | |
3158 | ret = pci_dev_str_match(dev, p, &p); | |
3159 | if (ret < 0) { | |
3160 | pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n", | |
3161 | disable_acs_redir_param); | |
3162 | ||
3163 | break; | |
3164 | } else if (ret == 1) { | |
3165 | /* Found a match */ | |
3166 | break; | |
3167 | } | |
3168 | ||
3169 | if (*p != ';' && *p != ',') { | |
3170 | /* End of param or invalid format */ | |
3171 | break; | |
3172 | } | |
3173 | p++; | |
3174 | } | |
3175 | ||
3176 | if (ret != 1) | |
3177 | return; | |
3178 | ||
73c47dde LG |
3179 | if (!pci_dev_specific_disable_acs_redir(dev)) |
3180 | return; | |
3181 | ||
aaca43fd LG |
3182 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
3183 | if (!pos) { | |
3184 | pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n"); | |
3185 | return; | |
3186 | } | |
3187 | ||
3188 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
3189 | ||
3190 | /* P2P Request & Completion Redirect */ | |
3191 | ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); | |
3192 | ||
3193 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
3194 | ||
3195 | pci_info(dev, "disabled ACS redirect\n"); | |
3196 | } | |
3197 | ||
ae21ee65 | 3198 | /** |
74356add | 3199 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities |
ae21ee65 AK |
3200 | * @dev: the PCI device |
3201 | */ | |
c1d61c9b | 3202 | static void pci_std_enable_acs(struct pci_dev *dev) |
ae21ee65 AK |
3203 | { |
3204 | int pos; | |
3205 | u16 cap; | |
3206 | u16 ctrl; | |
3207 | ||
ae21ee65 AK |
3208 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
3209 | if (!pos) | |
c1d61c9b | 3210 | return; |
ae21ee65 AK |
3211 | |
3212 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
3213 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
3214 | ||
3215 | /* Source Validation */ | |
3216 | ctrl |= (cap & PCI_ACS_SV); | |
3217 | ||
3218 | /* P2P Request Redirect */ | |
3219 | ctrl |= (cap & PCI_ACS_RR); | |
3220 | ||
3221 | /* P2P Completion Redirect */ | |
3222 | ctrl |= (cap & PCI_ACS_CR); | |
3223 | ||
3224 | /* Upstream Forwarding */ | |
3225 | ctrl |= (cap & PCI_ACS_UF); | |
3226 | ||
3227 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2c744244 AW |
3228 | } |
3229 | ||
3230 | /** | |
3231 | * pci_enable_acs - enable ACS if hardware support it | |
3232 | * @dev: the PCI device | |
3233 | */ | |
3234 | void pci_enable_acs(struct pci_dev *dev) | |
3235 | { | |
3236 | if (!pci_acs_enable) | |
aaca43fd | 3237 | goto disable_acs_redir; |
2c744244 | 3238 | |
c1d61c9b | 3239 | if (!pci_dev_specific_enable_acs(dev)) |
aaca43fd | 3240 | goto disable_acs_redir; |
2c744244 | 3241 | |
c1d61c9b | 3242 | pci_std_enable_acs(dev); |
aaca43fd LG |
3243 | |
3244 | disable_acs_redir: | |
3245 | /* | |
3246 | * Note: pci_disable_acs_redir() must be called even if ACS was not | |
3247 | * enabled by the kernel because it may have been enabled by | |
3248 | * platform firmware. So if we are told to disable it, we should | |
3249 | * always disable it after setting the kernel's default | |
3250 | * preferences. | |
3251 | */ | |
3252 | pci_disable_acs_redir(dev); | |
ae21ee65 AK |
3253 | } |
3254 | ||
0a67119f AW |
3255 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
3256 | { | |
3257 | int pos; | |
83db7e0b | 3258 | u16 cap, ctrl; |
0a67119f AW |
3259 | |
3260 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
3261 | if (!pos) | |
3262 | return false; | |
3263 | ||
83db7e0b AW |
3264 | /* |
3265 | * Except for egress control, capabilities are either required | |
3266 | * or only required if controllable. Features missing from the | |
3267 | * capability field can therefore be assumed as hard-wired enabled. | |
3268 | */ | |
3269 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
3270 | acs_flags &= (cap | PCI_ACS_EC); | |
3271 | ||
0a67119f AW |
3272 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
3273 | return (ctrl & acs_flags) == acs_flags; | |
3274 | } | |
3275 | ||
ad805758 AW |
3276 | /** |
3277 | * pci_acs_enabled - test ACS against required flags for a given device | |
3278 | * @pdev: device to test | |
3279 | * @acs_flags: required PCI ACS flags | |
3280 | * | |
3281 | * Return true if the device supports the provided flags. Automatically | |
3282 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
3283 | * |
3284 | * Note that this interface checks the effective ACS capabilities of the | |
3285 | * device rather than the actual capabilities. For instance, most single | |
3286 | * function endpoints are not required to support ACS because they have no | |
3287 | * opportunity for peer-to-peer access. We therefore return 'true' | |
3288 | * regardless of whether the device exposes an ACS capability. This makes | |
3289 | * it much easier for callers of this function to ignore the actual type | |
3290 | * or topology of the device when testing ACS support. | |
ad805758 AW |
3291 | */ |
3292 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
3293 | { | |
0a67119f | 3294 | int ret; |
ad805758 AW |
3295 | |
3296 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
3297 | if (ret >= 0) | |
3298 | return ret > 0; | |
3299 | ||
0a67119f AW |
3300 | /* |
3301 | * Conventional PCI and PCI-X devices never support ACS, either | |
3302 | * effectively or actually. The shared bus topology implies that | |
3303 | * any device on the bus can receive or snoop DMA. | |
3304 | */ | |
ad805758 AW |
3305 | if (!pci_is_pcie(pdev)) |
3306 | return false; | |
3307 | ||
0a67119f AW |
3308 | switch (pci_pcie_type(pdev)) { |
3309 | /* | |
3310 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 3311 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
3312 | * handle them as we would a non-PCIe device. |
3313 | */ | |
3314 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
3315 | /* | |
3316 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
3317 | * applicable... must never implement an ACS Extended Capability...". | |
3318 | * This seems arbitrary, but we take a conservative interpretation | |
3319 | * of this statement. | |
3320 | */ | |
3321 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
3322 | case PCI_EXP_TYPE_RC_EC: | |
3323 | return false; | |
3324 | /* | |
3325 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
3326 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
3327 | * regardless of whether they are single- or multi-function devices. | |
3328 | */ | |
3329 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3330 | case PCI_EXP_TYPE_ROOT_PORT: | |
3331 | return pci_acs_flags_enabled(pdev, acs_flags); | |
3332 | /* | |
3333 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
3334 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 3335 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
3336 | * device. The footnote for section 6.12 indicates the specific |
3337 | * PCIe types included here. | |
3338 | */ | |
3339 | case PCI_EXP_TYPE_ENDPOINT: | |
3340 | case PCI_EXP_TYPE_UPSTREAM: | |
3341 | case PCI_EXP_TYPE_LEG_END: | |
3342 | case PCI_EXP_TYPE_RC_END: | |
3343 | if (!pdev->multifunction) | |
3344 | break; | |
3345 | ||
0a67119f | 3346 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
3347 | } |
3348 | ||
0a67119f | 3349 | /* |
f7625980 | 3350 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
3351 | * to single function devices with the exception of downstream ports. |
3352 | */ | |
ad805758 AW |
3353 | return true; |
3354 | } | |
3355 | ||
3356 | /** | |
3357 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
3358 | * @start: starting downstream device | |
3359 | * @end: ending upstream device or NULL to search to the root bus | |
3360 | * @acs_flags: required flags | |
3361 | * | |
3362 | * Walk up a device tree from start to end testing PCI ACS support. If | |
3363 | * any step along the way does not support the required flags, return false. | |
3364 | */ | |
3365 | bool pci_acs_path_enabled(struct pci_dev *start, | |
3366 | struct pci_dev *end, u16 acs_flags) | |
3367 | { | |
3368 | struct pci_dev *pdev, *parent = start; | |
3369 | ||
3370 | do { | |
3371 | pdev = parent; | |
3372 | ||
3373 | if (!pci_acs_enabled(pdev, acs_flags)) | |
3374 | return false; | |
3375 | ||
3376 | if (pci_is_root_bus(pdev->bus)) | |
3377 | return (end == NULL); | |
3378 | ||
3379 | parent = pdev->bus->self; | |
3380 | } while (pdev != end); | |
3381 | ||
3382 | return true; | |
3383 | } | |
3384 | ||
276b738d CK |
3385 | /** |
3386 | * pci_rebar_find_pos - find position of resize ctrl reg for BAR | |
3387 | * @pdev: PCI device | |
3388 | * @bar: BAR to find | |
3389 | * | |
3390 | * Helper to find the position of the ctrl register for a BAR. | |
3391 | * Returns -ENOTSUPP if resizable BARs are not supported at all. | |
3392 | * Returns -ENOENT if no ctrl register for the BAR could be found. | |
3393 | */ | |
3394 | static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) | |
3395 | { | |
3396 | unsigned int pos, nbars, i; | |
3397 | u32 ctrl; | |
3398 | ||
3399 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
3400 | if (!pos) | |
3401 | return -ENOTSUPP; | |
3402 | ||
3403 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3404 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
3405 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
3406 | ||
3407 | for (i = 0; i < nbars; i++, pos += 8) { | |
3408 | int bar_idx; | |
3409 | ||
3410 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3411 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
3412 | if (bar_idx == bar) | |
3413 | return pos; | |
3414 | } | |
3415 | ||
3416 | return -ENOENT; | |
3417 | } | |
3418 | ||
3419 | /** | |
3420 | * pci_rebar_get_possible_sizes - get possible sizes for BAR | |
3421 | * @pdev: PCI device | |
3422 | * @bar: BAR to query | |
3423 | * | |
3424 | * Get the possible sizes of a resizable BAR as bitmask defined in the spec | |
3425 | * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable. | |
3426 | */ | |
3427 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) | |
3428 | { | |
3429 | int pos; | |
3430 | u32 cap; | |
3431 | ||
3432 | pos = pci_rebar_find_pos(pdev, bar); | |
3433 | if (pos < 0) | |
3434 | return 0; | |
3435 | ||
3436 | pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); | |
3437 | return (cap & PCI_REBAR_CAP_SIZES) >> 4; | |
3438 | } | |
3439 | ||
3440 | /** | |
3441 | * pci_rebar_get_current_size - get the current size of a BAR | |
3442 | * @pdev: PCI device | |
3443 | * @bar: BAR to set size to | |
3444 | * | |
3445 | * Read the size of a BAR from the resizable BAR config. | |
3446 | * Returns size if found or negative error code. | |
3447 | */ | |
3448 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) | |
3449 | { | |
3450 | int pos; | |
3451 | u32 ctrl; | |
3452 | ||
3453 | pos = pci_rebar_find_pos(pdev, bar); | |
3454 | if (pos < 0) | |
3455 | return pos; | |
3456 | ||
3457 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
b1277a22 | 3458 | return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3459 | } |
3460 | ||
3461 | /** | |
3462 | * pci_rebar_set_size - set a new size for a BAR | |
3463 | * @pdev: PCI device | |
3464 | * @bar: BAR to set size to | |
3465 | * @size: new size as defined in the spec (0=1MB, 19=512GB) | |
3466 | * | |
3467 | * Set the new size of a BAR as defined in the spec. | |
3468 | * Returns zero if resizing was successful, error code otherwise. | |
3469 | */ | |
3470 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) | |
3471 | { | |
3472 | int pos; | |
3473 | u32 ctrl; | |
3474 | ||
3475 | pos = pci_rebar_find_pos(pdev, bar); | |
3476 | if (pos < 0) | |
3477 | return pos; | |
3478 | ||
3479 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3480 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; | |
b1277a22 | 3481 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3482 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
3483 | return 0; | |
3484 | } | |
3485 | ||
430a2368 JC |
3486 | /** |
3487 | * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port | |
3488 | * @dev: the PCI device | |
3489 | * @cap_mask: mask of desired AtomicOp sizes, including one or more of: | |
3490 | * PCI_EXP_DEVCAP2_ATOMIC_COMP32 | |
3491 | * PCI_EXP_DEVCAP2_ATOMIC_COMP64 | |
3492 | * PCI_EXP_DEVCAP2_ATOMIC_COMP128 | |
3493 | * | |
3494 | * Return 0 if all upstream bridges support AtomicOp routing, egress | |
3495 | * blocking is disabled on all upstream ports, and the root port supports | |
3496 | * the requested completion capabilities (32-bit, 64-bit and/or 128-bit | |
3497 | * AtomicOp completion), or negative otherwise. | |
3498 | */ | |
3499 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) | |
3500 | { | |
3501 | struct pci_bus *bus = dev->bus; | |
3502 | struct pci_dev *bridge; | |
3503 | u32 cap, ctl2; | |
3504 | ||
3505 | if (!pci_is_pcie(dev)) | |
3506 | return -EINVAL; | |
3507 | ||
3508 | /* | |
3509 | * Per PCIe r4.0, sec 6.15, endpoints and root ports may be | |
3510 | * AtomicOp requesters. For now, we only support endpoints as | |
3511 | * requesters and root ports as completers. No endpoints as | |
3512 | * completers, and no peer-to-peer. | |
3513 | */ | |
3514 | ||
3515 | switch (pci_pcie_type(dev)) { | |
3516 | case PCI_EXP_TYPE_ENDPOINT: | |
3517 | case PCI_EXP_TYPE_LEG_END: | |
3518 | case PCI_EXP_TYPE_RC_END: | |
3519 | break; | |
3520 | default: | |
3521 | return -EINVAL; | |
3522 | } | |
3523 | ||
3524 | while (bus->parent) { | |
3525 | bridge = bus->self; | |
3526 | ||
3527 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); | |
3528 | ||
3529 | switch (pci_pcie_type(bridge)) { | |
3530 | /* Ensure switch ports support AtomicOp routing */ | |
3531 | case PCI_EXP_TYPE_UPSTREAM: | |
3532 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3533 | if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) | |
3534 | return -EINVAL; | |
3535 | break; | |
3536 | ||
3537 | /* Ensure root port supports all the sizes we care about */ | |
3538 | case PCI_EXP_TYPE_ROOT_PORT: | |
3539 | if ((cap & cap_mask) != cap_mask) | |
3540 | return -EINVAL; | |
3541 | break; | |
3542 | } | |
3543 | ||
3544 | /* Ensure upstream ports don't block AtomicOps on egress */ | |
3545 | if (!bridge->has_secondary_link) { | |
3546 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, | |
3547 | &ctl2); | |
3548 | if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) | |
3549 | return -EINVAL; | |
3550 | } | |
3551 | ||
3552 | bus = bus->parent; | |
3553 | } | |
3554 | ||
3555 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, | |
3556 | PCI_EXP_DEVCTL2_ATOMIC_REQ); | |
3557 | return 0; | |
3558 | } | |
3559 | EXPORT_SYMBOL(pci_enable_atomic_ops_to_root); | |
3560 | ||
57c2cf71 BH |
3561 | /** |
3562 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
3563 | * @dev: the PCI device | |
bb5c2de2 | 3564 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
3565 | * |
3566 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
3567 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
3568 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
3569 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
3570 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 3571 | */ |
3df425f3 | 3572 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 3573 | { |
46b952a3 MW |
3574 | int slot; |
3575 | ||
3576 | if (pci_ari_enabled(dev->bus)) | |
3577 | slot = 0; | |
3578 | else | |
3579 | slot = PCI_SLOT(dev->devfn); | |
3580 | ||
3581 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
3582 | } |
3583 | ||
3c78bc61 | 3584 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
3585 | { |
3586 | u8 pin; | |
3587 | ||
514d207d | 3588 | pin = dev->pin; |
1da177e4 LT |
3589 | if (!pin) |
3590 | return -1; | |
878f2e50 | 3591 | |
8784fd4d | 3592 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 3593 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
3594 | dev = dev->bus->self; |
3595 | } | |
3596 | *bridge = dev; | |
3597 | return pin; | |
3598 | } | |
3599 | ||
68feac87 BH |
3600 | /** |
3601 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
3602 | * @dev: the PCI device | |
3603 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
3604 | * | |
3605 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
3606 | * bridges all the way up to a PCI root bus. | |
3607 | */ | |
3608 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
3609 | { | |
3610 | u8 pin = *pinp; | |
3611 | ||
1eb39487 | 3612 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
3613 | pin = pci_swizzle_interrupt_pin(dev, pin); |
3614 | dev = dev->bus->self; | |
3615 | } | |
3616 | *pinp = pin; | |
3617 | return PCI_SLOT(dev->devfn); | |
3618 | } | |
e6b29dea | 3619 | EXPORT_SYMBOL_GPL(pci_common_swizzle); |
68feac87 | 3620 | |
1da177e4 | 3621 | /** |
74356add BH |
3622 | * pci_release_region - Release a PCI bar |
3623 | * @pdev: PCI device whose resources were previously reserved by | |
3624 | * pci_request_region() | |
3625 | * @bar: BAR to release | |
1da177e4 | 3626 | * |
74356add BH |
3627 | * Releases the PCI I/O and memory resources previously reserved by a |
3628 | * successful call to pci_request_region(). Call this function only | |
3629 | * after all use of the PCI regions has ceased. | |
1da177e4 LT |
3630 | */ |
3631 | void pci_release_region(struct pci_dev *pdev, int bar) | |
3632 | { | |
9ac7849e TH |
3633 | struct pci_devres *dr; |
3634 | ||
1da177e4 LT |
3635 | if (pci_resource_len(pdev, bar) == 0) |
3636 | return; | |
3637 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
3638 | release_region(pci_resource_start(pdev, bar), | |
3639 | pci_resource_len(pdev, bar)); | |
3640 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
3641 | release_mem_region(pci_resource_start(pdev, bar), | |
3642 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
3643 | |
3644 | dr = find_pci_dr(pdev); | |
3645 | if (dr) | |
3646 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 3647 | } |
b7fe9434 | 3648 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
3649 | |
3650 | /** | |
74356add BH |
3651 | * __pci_request_region - Reserved PCI I/O and memory resource |
3652 | * @pdev: PCI device whose resources are to be reserved | |
3653 | * @bar: BAR to be reserved | |
3654 | * @res_name: Name to be associated with resource. | |
3655 | * @exclusive: whether the region access is exclusive or not | |
1da177e4 | 3656 | * |
74356add BH |
3657 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
3658 | * being reserved by owner @res_name. Do not access any | |
3659 | * address inside the PCI regions unless this call returns | |
3660 | * successfully. | |
1da177e4 | 3661 | * |
74356add BH |
3662 | * If @exclusive is set, then the region is marked so that userspace |
3663 | * is explicitly not allowed to map the resource via /dev/mem or | |
3664 | * sysfs MMIO access. | |
f5ddcac4 | 3665 | * |
74356add BH |
3666 | * Returns 0 on success, or %EBUSY on error. A warning |
3667 | * message is also printed on failure. | |
1da177e4 | 3668 | */ |
3c78bc61 RD |
3669 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
3670 | const char *res_name, int exclusive) | |
1da177e4 | 3671 | { |
9ac7849e TH |
3672 | struct pci_devres *dr; |
3673 | ||
1da177e4 LT |
3674 | if (pci_resource_len(pdev, bar) == 0) |
3675 | return 0; | |
f7625980 | 3676 | |
1da177e4 LT |
3677 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
3678 | if (!request_region(pci_resource_start(pdev, bar), | |
3679 | pci_resource_len(pdev, bar), res_name)) | |
3680 | goto err_out; | |
3c78bc61 | 3681 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
3682 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
3683 | pci_resource_len(pdev, bar), res_name, | |
3684 | exclusive)) | |
1da177e4 LT |
3685 | goto err_out; |
3686 | } | |
9ac7849e TH |
3687 | |
3688 | dr = find_pci_dr(pdev); | |
3689 | if (dr) | |
3690 | dr->region_mask |= 1 << bar; | |
3691 | ||
1da177e4 LT |
3692 | return 0; |
3693 | ||
3694 | err_out: | |
7506dc79 | 3695 | pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 3696 | &pdev->resource[bar]); |
1da177e4 LT |
3697 | return -EBUSY; |
3698 | } | |
3699 | ||
e8de1481 | 3700 | /** |
74356add BH |
3701 | * pci_request_region - Reserve PCI I/O and memory resource |
3702 | * @pdev: PCI device whose resources are to be reserved | |
3703 | * @bar: BAR to be reserved | |
3704 | * @res_name: Name to be associated with resource | |
e8de1481 | 3705 | * |
74356add BH |
3706 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
3707 | * being reserved by owner @res_name. Do not access any | |
3708 | * address inside the PCI regions unless this call returns | |
3709 | * successfully. | |
e8de1481 | 3710 | * |
74356add BH |
3711 | * Returns 0 on success, or %EBUSY on error. A warning |
3712 | * message is also printed on failure. | |
e8de1481 AV |
3713 | */ |
3714 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
3715 | { | |
3716 | return __pci_request_region(pdev, bar, res_name, 0); | |
3717 | } | |
b7fe9434 | 3718 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 | 3719 | |
c87deff7 HS |
3720 | /** |
3721 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
3722 | * @pdev: PCI device whose resources were previously reserved | |
3723 | * @bars: Bitmask of BARs to be released | |
3724 | * | |
3725 | * Release selected PCI I/O and memory resources previously reserved. | |
3726 | * Call this function only after all use of the PCI regions has ceased. | |
3727 | */ | |
3728 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
3729 | { | |
3730 | int i; | |
3731 | ||
3732 | for (i = 0; i < 6; i++) | |
3733 | if (bars & (1 << i)) | |
3734 | pci_release_region(pdev, i); | |
3735 | } | |
b7fe9434 | 3736 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 3737 | |
9738abed | 3738 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 3739 | const char *res_name, int excl) |
c87deff7 HS |
3740 | { |
3741 | int i; | |
3742 | ||
3743 | for (i = 0; i < 6; i++) | |
3744 | if (bars & (1 << i)) | |
e8de1481 | 3745 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
3746 | goto err_out; |
3747 | return 0; | |
3748 | ||
3749 | err_out: | |
3c78bc61 | 3750 | while (--i >= 0) |
c87deff7 HS |
3751 | if (bars & (1 << i)) |
3752 | pci_release_region(pdev, i); | |
3753 | ||
3754 | return -EBUSY; | |
3755 | } | |
1da177e4 | 3756 | |
e8de1481 AV |
3757 | |
3758 | /** | |
3759 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
3760 | * @pdev: PCI device whose resources are to be reserved | |
3761 | * @bars: Bitmask of BARs to be requested | |
3762 | * @res_name: Name to be associated with resource | |
3763 | */ | |
3764 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
3765 | const char *res_name) | |
3766 | { | |
3767 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
3768 | } | |
b7fe9434 | 3769 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 3770 | |
3c78bc61 RD |
3771 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
3772 | const char *res_name) | |
e8de1481 AV |
3773 | { |
3774 | return __pci_request_selected_regions(pdev, bars, res_name, | |
3775 | IORESOURCE_EXCLUSIVE); | |
3776 | } | |
b7fe9434 | 3777 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 3778 | |
1da177e4 | 3779 | /** |
74356add BH |
3780 | * pci_release_regions - Release reserved PCI I/O and memory resources |
3781 | * @pdev: PCI device whose resources were previously reserved by | |
3782 | * pci_request_regions() | |
1da177e4 | 3783 | * |
74356add BH |
3784 | * Releases all PCI I/O and memory resources previously reserved by a |
3785 | * successful call to pci_request_regions(). Call this function only | |
3786 | * after all use of the PCI regions has ceased. | |
1da177e4 LT |
3787 | */ |
3788 | ||
3789 | void pci_release_regions(struct pci_dev *pdev) | |
3790 | { | |
c87deff7 | 3791 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 | 3792 | } |
b7fe9434 | 3793 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
3794 | |
3795 | /** | |
74356add BH |
3796 | * pci_request_regions - Reserve PCI I/O and memory resources |
3797 | * @pdev: PCI device whose resources are to be reserved | |
3798 | * @res_name: Name to be associated with resource. | |
1da177e4 | 3799 | * |
74356add BH |
3800 | * Mark all PCI regions associated with PCI device @pdev as |
3801 | * being reserved by owner @res_name. Do not access any | |
3802 | * address inside the PCI regions unless this call returns | |
3803 | * successfully. | |
1da177e4 | 3804 | * |
74356add BH |
3805 | * Returns 0 on success, or %EBUSY on error. A warning |
3806 | * message is also printed on failure. | |
1da177e4 | 3807 | */ |
3c990e92 | 3808 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 3809 | { |
c87deff7 | 3810 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 | 3811 | } |
b7fe9434 | 3812 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 3813 | |
e8de1481 | 3814 | /** |
74356add BH |
3815 | * pci_request_regions_exclusive - Reserve PCI I/O and memory resources |
3816 | * @pdev: PCI device whose resources are to be reserved | |
3817 | * @res_name: Name to be associated with resource. | |
e8de1481 | 3818 | * |
74356add BH |
3819 | * Mark all PCI regions associated with PCI device @pdev as being reserved |
3820 | * by owner @res_name. Do not access any address inside the PCI regions | |
3821 | * unless this call returns successfully. | |
e8de1481 | 3822 | * |
74356add BH |
3823 | * pci_request_regions_exclusive() will mark the region so that /dev/mem |
3824 | * and the sysfs MMIO access will not be allowed. | |
e8de1481 | 3825 | * |
74356add BH |
3826 | * Returns 0 on success, or %EBUSY on error. A warning message is also |
3827 | * printed on failure. | |
e8de1481 AV |
3828 | */ |
3829 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
3830 | { | |
3831 | return pci_request_selected_regions_exclusive(pdev, | |
3832 | ((1 << 6) - 1), res_name); | |
3833 | } | |
b7fe9434 | 3834 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 3835 | |
c5076cfe TN |
3836 | /* |
3837 | * Record the PCI IO range (expressed as CPU physical address + size). | |
74356add | 3838 | * Return a negative value if an error has occurred, zero otherwise |
c5076cfe | 3839 | */ |
fcfaab30 GP |
3840 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
3841 | resource_size_t size) | |
c5076cfe | 3842 | { |
5745392e | 3843 | int ret = 0; |
c5076cfe | 3844 | #ifdef PCI_IOBASE |
5745392e | 3845 | struct logic_pio_hwaddr *range; |
c5076cfe | 3846 | |
5745392e ZY |
3847 | if (!size || addr + size < addr) |
3848 | return -EINVAL; | |
c5076cfe | 3849 | |
c5076cfe | 3850 | range = kzalloc(sizeof(*range), GFP_ATOMIC); |
5745392e ZY |
3851 | if (!range) |
3852 | return -ENOMEM; | |
c5076cfe | 3853 | |
5745392e | 3854 | range->fwnode = fwnode; |
c5076cfe | 3855 | range->size = size; |
5745392e ZY |
3856 | range->hw_start = addr; |
3857 | range->flags = LOGIC_PIO_CPU_MMIO; | |
c5076cfe | 3858 | |
5745392e ZY |
3859 | ret = logic_pio_register_range(range); |
3860 | if (ret) | |
3861 | kfree(range); | |
c5076cfe TN |
3862 | #endif |
3863 | ||
5745392e | 3864 | return ret; |
c5076cfe TN |
3865 | } |
3866 | ||
3867 | phys_addr_t pci_pio_to_address(unsigned long pio) | |
3868 | { | |
3869 | phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; | |
3870 | ||
3871 | #ifdef PCI_IOBASE | |
5745392e | 3872 | if (pio >= MMIO_UPPER_LIMIT) |
c5076cfe TN |
3873 | return address; |
3874 | ||
5745392e | 3875 | address = logic_pio_to_hwaddr(pio); |
c5076cfe TN |
3876 | #endif |
3877 | ||
3878 | return address; | |
3879 | } | |
3880 | ||
3881 | unsigned long __weak pci_address_to_pio(phys_addr_t address) | |
3882 | { | |
3883 | #ifdef PCI_IOBASE | |
5745392e | 3884 | return logic_pio_trans_cpuaddr(address); |
c5076cfe TN |
3885 | #else |
3886 | if (address > IO_SPACE_LIMIT) | |
3887 | return (unsigned long)-1; | |
3888 | ||
3889 | return (unsigned long) address; | |
3890 | #endif | |
3891 | } | |
3892 | ||
8b921acf | 3893 | /** |
74356add BH |
3894 | * pci_remap_iospace - Remap the memory mapped I/O space |
3895 | * @res: Resource describing the I/O space | |
3896 | * @phys_addr: physical address of range to be mapped | |
8b921acf | 3897 | * |
74356add BH |
3898 | * Remap the memory mapped I/O space described by the @res and the CPU |
3899 | * physical address @phys_addr into virtual address space. Only | |
3900 | * architectures that have memory mapped IO functions defined (and the | |
3901 | * PCI_IOBASE value defined) should call this function. | |
8b921acf | 3902 | */ |
7b309aef | 3903 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) |
8b921acf LD |
3904 | { |
3905 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3906 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3907 | ||
3908 | if (!(res->flags & IORESOURCE_IO)) | |
3909 | return -EINVAL; | |
3910 | ||
3911 | if (res->end > IO_SPACE_LIMIT) | |
3912 | return -EINVAL; | |
3913 | ||
3914 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
3915 | pgprot_device(PAGE_KERNEL)); | |
3916 | #else | |
74356add BH |
3917 | /* |
3918 | * This architecture does not have memory mapped I/O space, | |
3919 | * so this function should never be called | |
3920 | */ | |
8b921acf LD |
3921 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); |
3922 | return -ENODEV; | |
3923 | #endif | |
3924 | } | |
f90b0875 | 3925 | EXPORT_SYMBOL(pci_remap_iospace); |
8b921acf | 3926 | |
4d3f1384 | 3927 | /** |
74356add BH |
3928 | * pci_unmap_iospace - Unmap the memory mapped I/O space |
3929 | * @res: resource to be unmapped | |
4d3f1384 | 3930 | * |
74356add BH |
3931 | * Unmap the CPU virtual address @res from virtual address space. Only |
3932 | * architectures that have memory mapped IO functions defined (and the | |
3933 | * PCI_IOBASE value defined) should call this function. | |
4d3f1384 SK |
3934 | */ |
3935 | void pci_unmap_iospace(struct resource *res) | |
3936 | { | |
3937 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3938 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3939 | ||
3940 | unmap_kernel_range(vaddr, resource_size(res)); | |
3941 | #endif | |
3942 | } | |
f90b0875 | 3943 | EXPORT_SYMBOL(pci_unmap_iospace); |
4d3f1384 | 3944 | |
a5fb9fb0 SS |
3945 | static void devm_pci_unmap_iospace(struct device *dev, void *ptr) |
3946 | { | |
3947 | struct resource **res = ptr; | |
3948 | ||
3949 | pci_unmap_iospace(*res); | |
3950 | } | |
3951 | ||
3952 | /** | |
3953 | * devm_pci_remap_iospace - Managed pci_remap_iospace() | |
3954 | * @dev: Generic device to remap IO address for | |
3955 | * @res: Resource describing the I/O space | |
3956 | * @phys_addr: physical address of range to be mapped | |
3957 | * | |
3958 | * Managed pci_remap_iospace(). Map is automatically unmapped on driver | |
3959 | * detach. | |
3960 | */ | |
3961 | int devm_pci_remap_iospace(struct device *dev, const struct resource *res, | |
3962 | phys_addr_t phys_addr) | |
3963 | { | |
3964 | const struct resource **ptr; | |
3965 | int error; | |
3966 | ||
3967 | ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL); | |
3968 | if (!ptr) | |
3969 | return -ENOMEM; | |
3970 | ||
3971 | error = pci_remap_iospace(res, phys_addr); | |
3972 | if (error) { | |
3973 | devres_free(ptr); | |
3974 | } else { | |
3975 | *ptr = res; | |
3976 | devres_add(dev, ptr); | |
3977 | } | |
3978 | ||
3979 | return error; | |
3980 | } | |
3981 | EXPORT_SYMBOL(devm_pci_remap_iospace); | |
3982 | ||
490cb6dd LP |
3983 | /** |
3984 | * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace() | |
3985 | * @dev: Generic device to remap IO address for | |
3986 | * @offset: Resource address to map | |
3987 | * @size: Size of map | |
3988 | * | |
3989 | * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver | |
3990 | * detach. | |
3991 | */ | |
3992 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, | |
3993 | resource_size_t offset, | |
3994 | resource_size_t size) | |
3995 | { | |
3996 | void __iomem **ptr, *addr; | |
3997 | ||
3998 | ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL); | |
3999 | if (!ptr) | |
4000 | return NULL; | |
4001 | ||
4002 | addr = pci_remap_cfgspace(offset, size); | |
4003 | if (addr) { | |
4004 | *ptr = addr; | |
4005 | devres_add(dev, ptr); | |
4006 | } else | |
4007 | devres_free(ptr); | |
4008 | ||
4009 | return addr; | |
4010 | } | |
4011 | EXPORT_SYMBOL(devm_pci_remap_cfgspace); | |
4012 | ||
4013 | /** | |
4014 | * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource | |
4015 | * @dev: generic device to handle the resource for | |
4016 | * @res: configuration space resource to be handled | |
4017 | * | |
4018 | * Checks that a resource is a valid memory region, requests the memory | |
4019 | * region and ioremaps with pci_remap_cfgspace() API that ensures the | |
4020 | * proper PCI configuration space memory attributes are guaranteed. | |
4021 | * | |
4022 | * All operations are managed and will be undone on driver detach. | |
4023 | * | |
4024 | * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code | |
505fb746 | 4025 | * on failure. Usage example:: |
490cb6dd LP |
4026 | * |
4027 | * res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
4028 | * base = devm_pci_remap_cfg_resource(&pdev->dev, res); | |
4029 | * if (IS_ERR(base)) | |
4030 | * return PTR_ERR(base); | |
4031 | */ | |
4032 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
4033 | struct resource *res) | |
4034 | { | |
4035 | resource_size_t size; | |
4036 | const char *name; | |
4037 | void __iomem *dest_ptr; | |
4038 | ||
4039 | BUG_ON(!dev); | |
4040 | ||
4041 | if (!res || resource_type(res) != IORESOURCE_MEM) { | |
4042 | dev_err(dev, "invalid resource\n"); | |
4043 | return IOMEM_ERR_PTR(-EINVAL); | |
4044 | } | |
4045 | ||
4046 | size = resource_size(res); | |
4047 | name = res->name ?: dev_name(dev); | |
4048 | ||
4049 | if (!devm_request_mem_region(dev, res->start, size, name)) { | |
4050 | dev_err(dev, "can't request region for resource %pR\n", res); | |
4051 | return IOMEM_ERR_PTR(-EBUSY); | |
4052 | } | |
4053 | ||
4054 | dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); | |
4055 | if (!dest_ptr) { | |
4056 | dev_err(dev, "ioremap failed for resource %pR\n", res); | |
4057 | devm_release_mem_region(dev, res->start, size); | |
4058 | dest_ptr = IOMEM_ERR_PTR(-ENOMEM); | |
4059 | } | |
4060 | ||
4061 | return dest_ptr; | |
4062 | } | |
4063 | EXPORT_SYMBOL(devm_pci_remap_cfg_resource); | |
4064 | ||
6a479079 BH |
4065 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
4066 | { | |
4067 | u16 old_cmd, cmd; | |
4068 | ||
4069 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
4070 | if (enable) | |
4071 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
4072 | else | |
4073 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
4074 | if (cmd != old_cmd) { | |
7506dc79 | 4075 | pci_dbg(dev, "%s bus mastering\n", |
6a479079 BH |
4076 | enable ? "enabling" : "disabling"); |
4077 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4078 | } | |
4079 | dev->is_busmaster = enable; | |
4080 | } | |
e8de1481 | 4081 | |
2b6f2c35 MS |
4082 | /** |
4083 | * pcibios_setup - process "pci=" kernel boot arguments | |
4084 | * @str: string used to pass in "pci=" kernel boot arguments | |
4085 | * | |
4086 | * Process kernel boot arguments. This is the default implementation. | |
4087 | * Architecture specific implementations can override this as necessary. | |
4088 | */ | |
4089 | char * __weak __init pcibios_setup(char *str) | |
4090 | { | |
4091 | return str; | |
4092 | } | |
4093 | ||
96c55900 MS |
4094 | /** |
4095 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
4096 | * @dev: the PCI device to enable | |
4097 | * | |
4098 | * Enables PCI bus-mastering for the device. This is the default | |
4099 | * implementation. Architecture specific implementations can override | |
4100 | * this if necessary. | |
4101 | */ | |
4102 | void __weak pcibios_set_master(struct pci_dev *dev) | |
4103 | { | |
4104 | u8 lat; | |
4105 | ||
f676678f MS |
4106 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
4107 | if (pci_is_pcie(dev)) | |
4108 | return; | |
4109 | ||
96c55900 MS |
4110 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
4111 | if (lat < 16) | |
4112 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
4113 | else if (lat > pcibios_max_latency) | |
4114 | lat = pcibios_max_latency; | |
4115 | else | |
4116 | return; | |
a006482b | 4117 | |
96c55900 MS |
4118 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
4119 | } | |
4120 | ||
1da177e4 LT |
4121 | /** |
4122 | * pci_set_master - enables bus-mastering for device dev | |
4123 | * @dev: the PCI device to enable | |
4124 | * | |
4125 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
4126 | * to do the needed arch specific settings. | |
4127 | */ | |
6a479079 | 4128 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 4129 | { |
6a479079 | 4130 | __pci_set_master(dev, true); |
1da177e4 LT |
4131 | pcibios_set_master(dev); |
4132 | } | |
b7fe9434 | 4133 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 4134 | |
6a479079 BH |
4135 | /** |
4136 | * pci_clear_master - disables bus-mastering for device dev | |
4137 | * @dev: the PCI device to disable | |
4138 | */ | |
4139 | void pci_clear_master(struct pci_dev *dev) | |
4140 | { | |
4141 | __pci_set_master(dev, false); | |
4142 | } | |
b7fe9434 | 4143 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 4144 | |
1da177e4 | 4145 | /** |
edb2d97e MW |
4146 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
4147 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 4148 | * |
edb2d97e MW |
4149 | * Helper function for pci_set_mwi. |
4150 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
4151 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
4152 | * | |
4153 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4154 | */ | |
15ea76d4 | 4155 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
4156 | { |
4157 | u8 cacheline_size; | |
4158 | ||
4159 | if (!pci_cache_line_size) | |
15ea76d4 | 4160 | return -EINVAL; |
1da177e4 LT |
4161 | |
4162 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
4163 | equal to or multiple of the right value. */ | |
4164 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4165 | if (cacheline_size >= pci_cache_line_size && | |
4166 | (cacheline_size % pci_cache_line_size) == 0) | |
4167 | return 0; | |
4168 | ||
4169 | /* Write the correct value. */ | |
4170 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
4171 | /* Read it back. */ | |
4172 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4173 | if (cacheline_size == pci_cache_line_size) | |
4174 | return 0; | |
4175 | ||
34c6b710 | 4176 | pci_info(dev, "cache line size of %d is not supported\n", |
227f0647 | 4177 | pci_cache_line_size << 2); |
1da177e4 LT |
4178 | |
4179 | return -EINVAL; | |
4180 | } | |
15ea76d4 TH |
4181 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
4182 | ||
1da177e4 LT |
4183 | /** |
4184 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
4185 | * @dev: the PCI device for which MWI is enabled | |
4186 | * | |
694625c0 | 4187 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
4188 | * |
4189 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4190 | */ | |
3c78bc61 | 4191 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 4192 | { |
b7fe9434 RD |
4193 | #ifdef PCI_DISABLE_MWI |
4194 | return 0; | |
4195 | #else | |
1da177e4 LT |
4196 | int rc; |
4197 | u16 cmd; | |
4198 | ||
edb2d97e | 4199 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
4200 | if (rc) |
4201 | return rc; | |
4202 | ||
4203 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 4204 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
7506dc79 | 4205 | pci_dbg(dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
4206 | cmd |= PCI_COMMAND_INVALIDATE; |
4207 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4208 | } | |
1da177e4 | 4209 | return 0; |
b7fe9434 | 4210 | #endif |
1da177e4 | 4211 | } |
b7fe9434 | 4212 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 4213 | |
fc0f9f4d HK |
4214 | /** |
4215 | * pcim_set_mwi - a device-managed pci_set_mwi() | |
4216 | * @dev: the PCI device for which MWI is enabled | |
4217 | * | |
4218 | * Managed pci_set_mwi(). | |
4219 | * | |
4220 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4221 | */ | |
4222 | int pcim_set_mwi(struct pci_dev *dev) | |
4223 | { | |
4224 | struct pci_devres *dr; | |
4225 | ||
4226 | dr = find_pci_dr(dev); | |
4227 | if (!dr) | |
4228 | return -ENOMEM; | |
4229 | ||
4230 | dr->mwi = 1; | |
4231 | return pci_set_mwi(dev); | |
4232 | } | |
4233 | EXPORT_SYMBOL(pcim_set_mwi); | |
4234 | ||
694625c0 RD |
4235 | /** |
4236 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
4237 | * @dev: the PCI device for which MWI is enabled | |
4238 | * | |
4239 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
4240 | * Callers are not required to check the return value. | |
4241 | * | |
4242 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4243 | */ | |
4244 | int pci_try_set_mwi(struct pci_dev *dev) | |
4245 | { | |
b7fe9434 RD |
4246 | #ifdef PCI_DISABLE_MWI |
4247 | return 0; | |
4248 | #else | |
4249 | return pci_set_mwi(dev); | |
4250 | #endif | |
694625c0 | 4251 | } |
b7fe9434 | 4252 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 4253 | |
1da177e4 LT |
4254 | /** |
4255 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
4256 | * @dev: the PCI device to disable | |
4257 | * | |
4258 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
4259 | */ | |
3c78bc61 | 4260 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 4261 | { |
b7fe9434 | 4262 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
4263 | u16 cmd; |
4264 | ||
4265 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4266 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
4267 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
4268 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4269 | } | |
b7fe9434 | 4270 | #endif |
1da177e4 | 4271 | } |
b7fe9434 | 4272 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 4273 | |
a04ce0ff BR |
4274 | /** |
4275 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
4276 | * @pdev: the PCI device to operate on |
4277 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff | 4278 | * |
74356add | 4279 | * Enables/disables PCI INTx for device @pdev |
a04ce0ff | 4280 | */ |
3c78bc61 | 4281 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
4282 | { |
4283 | u16 pci_command, new; | |
4284 | ||
4285 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
4286 | ||
3c78bc61 | 4287 | if (enable) |
a04ce0ff | 4288 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 4289 | else |
a04ce0ff | 4290 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
4291 | |
4292 | if (new != pci_command) { | |
9ac7849e TH |
4293 | struct pci_devres *dr; |
4294 | ||
2fd9d74b | 4295 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
4296 | |
4297 | dr = find_pci_dr(pdev); | |
4298 | if (dr && !dr->restore_intx) { | |
4299 | dr->restore_intx = 1; | |
4300 | dr->orig_intx = !enable; | |
4301 | } | |
a04ce0ff BR |
4302 | } |
4303 | } | |
b7fe9434 | 4304 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 4305 | |
a2e27787 JK |
4306 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) |
4307 | { | |
4308 | struct pci_bus *bus = dev->bus; | |
4309 | bool mask_updated = true; | |
4310 | u32 cmd_status_dword; | |
4311 | u16 origcmd, newcmd; | |
4312 | unsigned long flags; | |
4313 | bool irq_pending; | |
4314 | ||
4315 | /* | |
4316 | * We do a single dword read to retrieve both command and status. | |
4317 | * Document assumptions that make this possible. | |
4318 | */ | |
4319 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
4320 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
4321 | ||
4322 | raw_spin_lock_irqsave(&pci_lock, flags); | |
4323 | ||
4324 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
4325 | ||
4326 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
4327 | ||
4328 | /* | |
4329 | * Check interrupt status register to see whether our device | |
4330 | * triggered the interrupt (when masking) or the next IRQ is | |
4331 | * already pending (when unmasking). | |
4332 | */ | |
4333 | if (mask != irq_pending) { | |
4334 | mask_updated = false; | |
4335 | goto done; | |
4336 | } | |
4337 | ||
4338 | origcmd = cmd_status_dword; | |
4339 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
4340 | if (mask) | |
4341 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
4342 | if (newcmd != origcmd) | |
4343 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
4344 | ||
4345 | done: | |
4346 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
4347 | ||
4348 | return mask_updated; | |
4349 | } | |
4350 | ||
4351 | /** | |
4352 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 4353 | * @dev: the PCI device to operate on |
a2e27787 | 4354 | * |
74356add BH |
4355 | * Check if the device dev has its INTx line asserted, mask it and return |
4356 | * true in that case. False is returned if no interrupt was pending. | |
a2e27787 JK |
4357 | */ |
4358 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
4359 | { | |
4360 | return pci_check_and_set_intx_mask(dev, true); | |
4361 | } | |
4362 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
4363 | ||
4364 | /** | |
ebd50b93 | 4365 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 4366 | * @dev: the PCI device to operate on |
a2e27787 | 4367 | * |
74356add BH |
4368 | * Check if the device dev has its INTx line asserted, unmask it if not and |
4369 | * return true. False is returned and the mask remains active if there was | |
4370 | * still an interrupt pending. | |
a2e27787 JK |
4371 | */ |
4372 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
4373 | { | |
4374 | return pci_check_and_set_intx_mask(dev, false); | |
4375 | } | |
4376 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
4377 | ||
3775a209 | 4378 | /** |
74356add | 4379 | * pci_wait_for_pending_transaction - wait for pending transaction |
3775a209 CL |
4380 | * @dev: the PCI device to operate on |
4381 | * | |
4382 | * Return 0 if transaction is pending 1 otherwise. | |
4383 | */ | |
4384 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 4385 | { |
157e876f AW |
4386 | if (!pci_is_pcie(dev)) |
4387 | return 1; | |
8c1c699f | 4388 | |
d0b4cc4e GS |
4389 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
4390 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
4391 | } |
4392 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
4393 | ||
a2758b6b | 4394 | static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) |
5adecf81 | 4395 | { |
a2758b6b | 4396 | int delay = 1; |
5adecf81 AW |
4397 | u32 id; |
4398 | ||
821cdad5 | 4399 | /* |
a2758b6b | 4400 | * After reset, the device should not silently discard config |
821cdad5 SK |
4401 | * requests, but it may still indicate that it needs more time by |
4402 | * responding to them with CRS completions. The Root Port will | |
4403 | * generally synthesize ~0 data to complete the read (except when | |
4404 | * CRS SV is enabled and the read was for the Vendor ID; in that | |
4405 | * case it synthesizes 0x0001 data). | |
4406 | * | |
4407 | * Wait for the device to return a non-CRS completion. Read the | |
4408 | * Command register instead of Vendor ID so we don't have to | |
4409 | * contend with the CRS SV value. | |
4410 | */ | |
4411 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
4412 | while (id == ~0) { | |
4413 | if (delay > timeout) { | |
a2758b6b SK |
4414 | pci_warn(dev, "not ready %dms after %s; giving up\n", |
4415 | delay - 1, reset_type); | |
91295d79 | 4416 | return -ENOTTY; |
821cdad5 SK |
4417 | } |
4418 | ||
4419 | if (delay > 1000) | |
a2758b6b SK |
4420 | pci_info(dev, "not ready %dms after %s; waiting\n", |
4421 | delay - 1, reset_type); | |
821cdad5 SK |
4422 | |
4423 | msleep(delay); | |
4424 | delay *= 2; | |
5adecf81 | 4425 | pci_read_config_dword(dev, PCI_COMMAND, &id); |
821cdad5 | 4426 | } |
5adecf81 | 4427 | |
821cdad5 | 4428 | if (delay > 1000) |
a2758b6b SK |
4429 | pci_info(dev, "ready %dms after %s\n", delay - 1, |
4430 | reset_type); | |
91295d79 SK |
4431 | |
4432 | return 0; | |
5adecf81 AW |
4433 | } |
4434 | ||
a60a2b73 CH |
4435 | /** |
4436 | * pcie_has_flr - check if a device supports function level resets | |
74356add | 4437 | * @dev: device to check |
a60a2b73 CH |
4438 | * |
4439 | * Returns true if the device advertises support for PCIe function level | |
4440 | * resets. | |
4441 | */ | |
2d2917f7 | 4442 | bool pcie_has_flr(struct pci_dev *dev) |
3775a209 CL |
4443 | { |
4444 | u32 cap; | |
4445 | ||
f65fd1aa | 4446 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
a60a2b73 | 4447 | return false; |
3775a209 | 4448 | |
a60a2b73 CH |
4449 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
4450 | return cap & PCI_EXP_DEVCAP_FLR; | |
4451 | } | |
2d2917f7 | 4452 | EXPORT_SYMBOL_GPL(pcie_has_flr); |
3775a209 | 4453 | |
a60a2b73 CH |
4454 | /** |
4455 | * pcie_flr - initiate a PCIe function level reset | |
74356add | 4456 | * @dev: device to reset |
a60a2b73 CH |
4457 | * |
4458 | * Initiate a function level reset on @dev. The caller should ensure the | |
4459 | * device supports FLR before calling this function, e.g. by using the | |
4460 | * pcie_has_flr() helper. | |
4461 | */ | |
91295d79 | 4462 | int pcie_flr(struct pci_dev *dev) |
a60a2b73 | 4463 | { |
3775a209 | 4464 | if (!pci_wait_for_pending_transaction(dev)) |
7506dc79 | 4465 | pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 4466 | |
59875ae4 | 4467 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
a2758b6b | 4468 | |
d6112f8d FB |
4469 | if (dev->imm_ready) |
4470 | return 0; | |
4471 | ||
a2758b6b SK |
4472 | /* |
4473 | * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within | |
4474 | * 100ms, but may silently discard requests while the FLR is in | |
4475 | * progress. Wait 100ms before trying to access the device. | |
4476 | */ | |
4477 | msleep(100); | |
4478 | ||
4479 | return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); | |
8dd7f803 | 4480 | } |
a60a2b73 | 4481 | EXPORT_SYMBOL_GPL(pcie_flr); |
d91cdc74 | 4482 | |
8c1c699f | 4483 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 4484 | { |
8c1c699f | 4485 | int pos; |
1ca88797 SY |
4486 | u8 cap; |
4487 | ||
8c1c699f YZ |
4488 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
4489 | if (!pos) | |
1ca88797 | 4490 | return -ENOTTY; |
8c1c699f | 4491 | |
f65fd1aa SN |
4492 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
4493 | return -ENOTTY; | |
4494 | ||
8c1c699f | 4495 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); |
1ca88797 SY |
4496 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
4497 | return -ENOTTY; | |
4498 | ||
4499 | if (probe) | |
4500 | return 0; | |
4501 | ||
d066c946 AW |
4502 | /* |
4503 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
4504 | * is used, so we use the conrol offset rather than status and shift | |
4505 | * the test bit to match. | |
4506 | */ | |
bb383e28 | 4507 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 4508 | PCI_AF_STATUS_TP << 8)) |
7506dc79 | 4509 | pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 4510 | |
8c1c699f | 4511 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
a2758b6b | 4512 | |
d6112f8d FB |
4513 | if (dev->imm_ready) |
4514 | return 0; | |
4515 | ||
a2758b6b SK |
4516 | /* |
4517 | * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, | |
4518 | * updated 27 July 2006; a device must complete an FLR within | |
4519 | * 100ms, but may silently discard requests while the FLR is in | |
4520 | * progress. Wait 100ms before trying to access the device. | |
4521 | */ | |
4522 | msleep(100); | |
4523 | ||
4524 | return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); | |
1ca88797 SY |
4525 | } |
4526 | ||
83d74e03 RW |
4527 | /** |
4528 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
4529 | * @dev: Device to reset. | |
4530 | * @probe: If set, only check if the device can be reset this way. | |
4531 | * | |
4532 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
4533 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
4534 | * PCI_D0. If that's the case and the device is not in a low-power state | |
4535 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
4536 | * | |
4537 | * NOTE: This causes the caller to sleep for twice the device power transition | |
4538 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 4539 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
4540 | * Moreover, only devices in D0 can be reset by this function. |
4541 | */ | |
f85876ba | 4542 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 4543 | { |
f85876ba YZ |
4544 | u16 csr; |
4545 | ||
51e53738 | 4546 | if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) |
f85876ba | 4547 | return -ENOTTY; |
d91cdc74 | 4548 | |
f85876ba YZ |
4549 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
4550 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
4551 | return -ENOTTY; | |
d91cdc74 | 4552 | |
f85876ba YZ |
4553 | if (probe) |
4554 | return 0; | |
1ca88797 | 4555 | |
f85876ba YZ |
4556 | if (dev->current_state != PCI_D0) |
4557 | return -EINVAL; | |
4558 | ||
4559 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4560 | csr |= PCI_D3hot; | |
4561 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4562 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
4563 | |
4564 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4565 | csr |= PCI_D0; | |
4566 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4567 | pci_dev_d3_sleep(dev); |
f85876ba | 4568 | |
abbcf0e2 | 4569 | return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS); |
f85876ba | 4570 | } |
9f5a70f1 OP |
4571 | /** |
4572 | * pcie_wait_for_link - Wait until link is active or inactive | |
4573 | * @pdev: Bridge device | |
4574 | * @active: waiting for active or inactive? | |
4575 | * | |
4576 | * Use this to wait till link becomes active or inactive. | |
4577 | */ | |
4578 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active) | |
4579 | { | |
4580 | int timeout = 1000; | |
4581 | bool ret; | |
4582 | u16 lnk_status; | |
4583 | ||
f0157160 KB |
4584 | /* |
4585 | * Some controllers might not implement link active reporting. In this | |
4586 | * case, we wait for 1000 + 100 ms. | |
4587 | */ | |
4588 | if (!pdev->link_active_reporting) { | |
4589 | msleep(1100); | |
4590 | return true; | |
4591 | } | |
4592 | ||
4593 | /* | |
4594 | * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms, | |
4595 | * after which we should expect an link active if the reset was | |
4596 | * successful. If so, software must wait a minimum 100ms before sending | |
4597 | * configuration requests to devices downstream this port. | |
4598 | * | |
4599 | * If the link fails to activate, either the device was physically | |
4600 | * removed or the link is permanently failed. | |
4601 | */ | |
4602 | if (active) | |
4603 | msleep(20); | |
9f5a70f1 OP |
4604 | for (;;) { |
4605 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); | |
4606 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); | |
4607 | if (ret == active) | |
f0157160 | 4608 | break; |
9f5a70f1 OP |
4609 | if (timeout <= 0) |
4610 | break; | |
4611 | msleep(10); | |
4612 | timeout -= 10; | |
4613 | } | |
f0157160 KB |
4614 | if (active && ret) |
4615 | msleep(100); | |
4616 | else if (ret != active) | |
4617 | pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n", | |
4618 | active ? "set" : "cleared"); | |
4619 | return ret == active; | |
9f5a70f1 | 4620 | } |
f85876ba | 4621 | |
9e33002f | 4622 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
4623 | { |
4624 | u16 ctrl; | |
64e8674f AW |
4625 | |
4626 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
4627 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
4628 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
df62ab5e | 4629 | |
de0c548c AW |
4630 | /* |
4631 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 4632 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
4633 | */ |
4634 | msleep(2); | |
64e8674f AW |
4635 | |
4636 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
4637 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
4638 | |
4639 | /* | |
4640 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
4641 | * Assuming a minimum 33MHz clock this results in a 1s | |
4642 | * delay before we can consider subordinate devices to | |
4643 | * be re-initialized. PCIe has some ways to shorten this, | |
4644 | * but we don't make use of them yet. | |
4645 | */ | |
4646 | ssleep(1); | |
64e8674f | 4647 | } |
d92a208d | 4648 | |
9e33002f GS |
4649 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
4650 | { | |
4651 | pci_reset_secondary_bus(dev); | |
4652 | } | |
4653 | ||
d92a208d | 4654 | /** |
381634ca | 4655 | * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge. |
d92a208d GS |
4656 | * @dev: Bridge device |
4657 | * | |
4658 | * Use the bridge control register to assert reset on the secondary bus. | |
4659 | * Devices on the secondary bus are left in power-on state. | |
4660 | */ | |
381634ca | 4661 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev) |
d92a208d GS |
4662 | { |
4663 | pcibios_reset_secondary_bus(dev); | |
01fd61c0 | 4664 | |
6b2f1351 | 4665 | return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS); |
d92a208d | 4666 | } |
bfc45606 | 4667 | EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); |
64e8674f AW |
4668 | |
4669 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
4670 | { | |
c12ff1df YZ |
4671 | struct pci_dev *pdev; |
4672 | ||
f331a859 AW |
4673 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
4674 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
4675 | return -ENOTTY; |
4676 | ||
4677 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4678 | if (pdev != dev) | |
4679 | return -ENOTTY; | |
4680 | ||
4681 | if (probe) | |
4682 | return 0; | |
4683 | ||
381634ca | 4684 | return pci_bridge_secondary_bus_reset(dev->bus->self); |
c12ff1df YZ |
4685 | } |
4686 | ||
608c3881 AW |
4687 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
4688 | { | |
4689 | int rc = -ENOTTY; | |
4690 | ||
81c4b5bf | 4691 | if (!hotplug || !try_module_get(hotplug->owner)) |
608c3881 AW |
4692 | return rc; |
4693 | ||
4694 | if (hotplug->ops->reset_slot) | |
4695 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
4696 | ||
81c4b5bf | 4697 | module_put(hotplug->owner); |
608c3881 AW |
4698 | |
4699 | return rc; | |
4700 | } | |
4701 | ||
4702 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
4703 | { | |
4704 | struct pci_dev *pdev; | |
4705 | ||
f331a859 AW |
4706 | if (dev->subordinate || !dev->slot || |
4707 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
608c3881 AW |
4708 | return -ENOTTY; |
4709 | ||
4710 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4711 | if (pdev != dev && pdev->slot == dev->slot) | |
4712 | return -ENOTTY; | |
4713 | ||
4714 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
4715 | } | |
4716 | ||
77cb985a AW |
4717 | static void pci_dev_lock(struct pci_dev *dev) |
4718 | { | |
4719 | pci_cfg_access_lock(dev); | |
4720 | /* block PM suspend, driver probe, etc. */ | |
4721 | device_lock(&dev->dev); | |
4722 | } | |
4723 | ||
61cf16d8 AW |
4724 | /* Return 1 on successful lock, 0 on contention */ |
4725 | static int pci_dev_trylock(struct pci_dev *dev) | |
4726 | { | |
4727 | if (pci_cfg_access_trylock(dev)) { | |
4728 | if (device_trylock(&dev->dev)) | |
4729 | return 1; | |
4730 | pci_cfg_access_unlock(dev); | |
4731 | } | |
4732 | ||
4733 | return 0; | |
4734 | } | |
4735 | ||
77cb985a AW |
4736 | static void pci_dev_unlock(struct pci_dev *dev) |
4737 | { | |
4738 | device_unlock(&dev->dev); | |
4739 | pci_cfg_access_unlock(dev); | |
4740 | } | |
4741 | ||
775755ed | 4742 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
3ebe7f9f KB |
4743 | { |
4744 | const struct pci_error_handlers *err_handler = | |
4745 | dev->driver ? dev->driver->err_handler : NULL; | |
3ebe7f9f | 4746 | |
b014e96d | 4747 | /* |
775755ed | 4748 | * dev->driver->err_handler->reset_prepare() is protected against |
b014e96d CH |
4749 | * races with ->remove() by the device lock, which must be held by |
4750 | * the caller. | |
4751 | */ | |
775755ed CH |
4752 | if (err_handler && err_handler->reset_prepare) |
4753 | err_handler->reset_prepare(dev); | |
3ebe7f9f | 4754 | |
a6cbaade AW |
4755 | /* |
4756 | * Wake-up device prior to save. PM registers default to D0 after | |
4757 | * reset and a simple register restore doesn't reliably return | |
4758 | * to a non-D0 state anyway. | |
4759 | */ | |
4760 | pci_set_power_state(dev, PCI_D0); | |
4761 | ||
77cb985a AW |
4762 | pci_save_state(dev); |
4763 | /* | |
4764 | * Disable the device by clearing the Command register, except for | |
4765 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
4766 | * BARs, but also prevents the device from being Bus Master, preventing | |
4767 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
4768 | * compliant devices, INTx-disable prevents legacy interrupts. | |
4769 | */ | |
4770 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
4771 | } | |
4772 | ||
4773 | static void pci_dev_restore(struct pci_dev *dev) | |
4774 | { | |
775755ed CH |
4775 | const struct pci_error_handlers *err_handler = |
4776 | dev->driver ? dev->driver->err_handler : NULL; | |
977f857c | 4777 | |
77cb985a | 4778 | pci_restore_state(dev); |
77cb985a | 4779 | |
775755ed CH |
4780 | /* |
4781 | * dev->driver->err_handler->reset_done() is protected against | |
4782 | * races with ->remove() by the device lock, which must be held by | |
4783 | * the caller. | |
4784 | */ | |
4785 | if (err_handler && err_handler->reset_done) | |
4786 | err_handler->reset_done(dev); | |
d91cdc74 | 4787 | } |
3ebe7f9f | 4788 | |
6fbf9e7a KRW |
4789 | /** |
4790 | * __pci_reset_function_locked - reset a PCI device function while holding | |
4791 | * the @dev mutex lock. | |
4792 | * @dev: PCI device to reset | |
4793 | * | |
4794 | * Some devices allow an individual function to be reset without affecting | |
4795 | * other functions in the same device. The PCI device must be responsive | |
4796 | * to PCI config space in order to use this function. | |
4797 | * | |
4798 | * The device function is presumed to be unused and the caller is holding | |
4799 | * the device mutex lock when this function is called. | |
74356add | 4800 | * |
6fbf9e7a KRW |
4801 | * Resetting the device will make the contents of PCI configuration space |
4802 | * random, so any caller of this must be prepared to reinitialise the | |
4803 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
4804 | * etc. | |
4805 | * | |
4806 | * Returns 0 if the device function was successfully reset or negative if the | |
4807 | * device doesn't support resetting a single function. | |
4808 | */ | |
4809 | int __pci_reset_function_locked(struct pci_dev *dev) | |
4810 | { | |
52354b9d CH |
4811 | int rc; |
4812 | ||
4813 | might_sleep(); | |
4814 | ||
832c418a BH |
4815 | /* |
4816 | * A reset method returns -ENOTTY if it doesn't support this device | |
4817 | * and we should try the next method. | |
4818 | * | |
4819 | * If it returns 0 (success), we're finished. If it returns any | |
4820 | * other error, we're also finished: this indicates that further | |
4821 | * reset mechanisms might be broken on the device. | |
4822 | */ | |
52354b9d CH |
4823 | rc = pci_dev_specific_reset(dev, 0); |
4824 | if (rc != -ENOTTY) | |
4825 | return rc; | |
4826 | if (pcie_has_flr(dev)) { | |
91295d79 SK |
4827 | rc = pcie_flr(dev); |
4828 | if (rc != -ENOTTY) | |
4829 | return rc; | |
52354b9d CH |
4830 | } |
4831 | rc = pci_af_flr(dev, 0); | |
4832 | if (rc != -ENOTTY) | |
4833 | return rc; | |
4834 | rc = pci_pm_reset(dev, 0); | |
4835 | if (rc != -ENOTTY) | |
4836 | return rc; | |
4837 | rc = pci_dev_reset_slot_function(dev, 0); | |
4838 | if (rc != -ENOTTY) | |
4839 | return rc; | |
4840 | return pci_parent_bus_reset(dev, 0); | |
6fbf9e7a KRW |
4841 | } |
4842 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
4843 | ||
711d5779 MT |
4844 | /** |
4845 | * pci_probe_reset_function - check whether the device can be safely reset | |
4846 | * @dev: PCI device to reset | |
4847 | * | |
4848 | * Some devices allow an individual function to be reset without affecting | |
4849 | * other functions in the same device. The PCI device must be responsive | |
4850 | * to PCI config space in order to use this function. | |
4851 | * | |
4852 | * Returns 0 if the device function can be reset or negative if the | |
4853 | * device doesn't support resetting a single function. | |
4854 | */ | |
4855 | int pci_probe_reset_function(struct pci_dev *dev) | |
4856 | { | |
52354b9d CH |
4857 | int rc; |
4858 | ||
4859 | might_sleep(); | |
4860 | ||
4861 | rc = pci_dev_specific_reset(dev, 1); | |
4862 | if (rc != -ENOTTY) | |
4863 | return rc; | |
4864 | if (pcie_has_flr(dev)) | |
4865 | return 0; | |
4866 | rc = pci_af_flr(dev, 1); | |
4867 | if (rc != -ENOTTY) | |
4868 | return rc; | |
4869 | rc = pci_pm_reset(dev, 1); | |
4870 | if (rc != -ENOTTY) | |
4871 | return rc; | |
4872 | rc = pci_dev_reset_slot_function(dev, 1); | |
4873 | if (rc != -ENOTTY) | |
4874 | return rc; | |
4875 | ||
4876 | return pci_parent_bus_reset(dev, 1); | |
711d5779 MT |
4877 | } |
4878 | ||
8dd7f803 | 4879 | /** |
8c1c699f YZ |
4880 | * pci_reset_function - quiesce and reset a PCI device function |
4881 | * @dev: PCI device to reset | |
8dd7f803 SY |
4882 | * |
4883 | * Some devices allow an individual function to be reset without affecting | |
4884 | * other functions in the same device. The PCI device must be responsive | |
4885 | * to PCI config space in order to use this function. | |
4886 | * | |
4887 | * This function does not just reset the PCI portion of a device, but | |
4888 | * clears all the state associated with the device. This function differs | |
79e699b6 JS |
4889 | * from __pci_reset_function_locked() in that it saves and restores device state |
4890 | * over the reset and takes the PCI device lock. | |
8dd7f803 | 4891 | * |
8c1c699f | 4892 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
4893 | * device doesn't support resetting a single function. |
4894 | */ | |
4895 | int pci_reset_function(struct pci_dev *dev) | |
4896 | { | |
8c1c699f | 4897 | int rc; |
8dd7f803 | 4898 | |
204f4afa BH |
4899 | if (!dev->reset_fn) |
4900 | return -ENOTTY; | |
8dd7f803 | 4901 | |
b014e96d | 4902 | pci_dev_lock(dev); |
77cb985a | 4903 | pci_dev_save_and_disable(dev); |
8dd7f803 | 4904 | |
52354b9d | 4905 | rc = __pci_reset_function_locked(dev); |
8dd7f803 | 4906 | |
77cb985a | 4907 | pci_dev_restore(dev); |
b014e96d | 4908 | pci_dev_unlock(dev); |
8dd7f803 | 4909 | |
8c1c699f | 4910 | return rc; |
8dd7f803 SY |
4911 | } |
4912 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
4913 | ||
a477b9cd MZ |
4914 | /** |
4915 | * pci_reset_function_locked - quiesce and reset a PCI device function | |
4916 | * @dev: PCI device to reset | |
4917 | * | |
4918 | * Some devices allow an individual function to be reset without affecting | |
4919 | * other functions in the same device. The PCI device must be responsive | |
4920 | * to PCI config space in order to use this function. | |
4921 | * | |
4922 | * This function does not just reset the PCI portion of a device, but | |
4923 | * clears all the state associated with the device. This function differs | |
79e699b6 | 4924 | * from __pci_reset_function_locked() in that it saves and restores device state |
a477b9cd MZ |
4925 | * over the reset. It also differs from pci_reset_function() in that it |
4926 | * requires the PCI device lock to be held. | |
4927 | * | |
4928 | * Returns 0 if the device function was successfully reset or negative if the | |
4929 | * device doesn't support resetting a single function. | |
4930 | */ | |
4931 | int pci_reset_function_locked(struct pci_dev *dev) | |
4932 | { | |
4933 | int rc; | |
4934 | ||
204f4afa BH |
4935 | if (!dev->reset_fn) |
4936 | return -ENOTTY; | |
a477b9cd MZ |
4937 | |
4938 | pci_dev_save_and_disable(dev); | |
4939 | ||
4940 | rc = __pci_reset_function_locked(dev); | |
4941 | ||
4942 | pci_dev_restore(dev); | |
4943 | ||
4944 | return rc; | |
4945 | } | |
4946 | EXPORT_SYMBOL_GPL(pci_reset_function_locked); | |
4947 | ||
61cf16d8 AW |
4948 | /** |
4949 | * pci_try_reset_function - quiesce and reset a PCI device function | |
4950 | * @dev: PCI device to reset | |
4951 | * | |
4952 | * Same as above, except return -EAGAIN if unable to lock device. | |
4953 | */ | |
4954 | int pci_try_reset_function(struct pci_dev *dev) | |
4955 | { | |
4956 | int rc; | |
4957 | ||
204f4afa BH |
4958 | if (!dev->reset_fn) |
4959 | return -ENOTTY; | |
61cf16d8 | 4960 | |
b014e96d CH |
4961 | if (!pci_dev_trylock(dev)) |
4962 | return -EAGAIN; | |
61cf16d8 | 4963 | |
b014e96d | 4964 | pci_dev_save_and_disable(dev); |
52354b9d | 4965 | rc = __pci_reset_function_locked(dev); |
cb5e0d06 | 4966 | pci_dev_restore(dev); |
b014e96d | 4967 | pci_dev_unlock(dev); |
61cf16d8 | 4968 | |
61cf16d8 AW |
4969 | return rc; |
4970 | } | |
4971 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
4972 | ||
f331a859 AW |
4973 | /* Do any devices on or below this bus prevent a bus reset? */ |
4974 | static bool pci_bus_resetable(struct pci_bus *bus) | |
4975 | { | |
4976 | struct pci_dev *dev; | |
4977 | ||
35702778 DD |
4978 | |
4979 | if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
4980 | return false; | |
4981 | ||
f331a859 AW |
4982 | list_for_each_entry(dev, &bus->devices, bus_list) { |
4983 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
4984 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
4985 | return false; | |
4986 | } | |
4987 | ||
4988 | return true; | |
4989 | } | |
4990 | ||
090a3c53 AW |
4991 | /* Lock devices from the top of the tree down */ |
4992 | static void pci_bus_lock(struct pci_bus *bus) | |
4993 | { | |
4994 | struct pci_dev *dev; | |
4995 | ||
4996 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4997 | pci_dev_lock(dev); | |
4998 | if (dev->subordinate) | |
4999 | pci_bus_lock(dev->subordinate); | |
5000 | } | |
5001 | } | |
5002 | ||
5003 | /* Unlock devices from the bottom of the tree up */ | |
5004 | static void pci_bus_unlock(struct pci_bus *bus) | |
5005 | { | |
5006 | struct pci_dev *dev; | |
5007 | ||
5008 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5009 | if (dev->subordinate) | |
5010 | pci_bus_unlock(dev->subordinate); | |
5011 | pci_dev_unlock(dev); | |
5012 | } | |
5013 | } | |
5014 | ||
61cf16d8 AW |
5015 | /* Return 1 on successful lock, 0 on contention */ |
5016 | static int pci_bus_trylock(struct pci_bus *bus) | |
5017 | { | |
5018 | struct pci_dev *dev; | |
5019 | ||
5020 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5021 | if (!pci_dev_trylock(dev)) | |
5022 | goto unlock; | |
5023 | if (dev->subordinate) { | |
5024 | if (!pci_bus_trylock(dev->subordinate)) { | |
5025 | pci_dev_unlock(dev); | |
5026 | goto unlock; | |
5027 | } | |
5028 | } | |
5029 | } | |
5030 | return 1; | |
5031 | ||
5032 | unlock: | |
5033 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
5034 | if (dev->subordinate) | |
5035 | pci_bus_unlock(dev->subordinate); | |
5036 | pci_dev_unlock(dev); | |
5037 | } | |
5038 | return 0; | |
5039 | } | |
5040 | ||
f331a859 AW |
5041 | /* Do any devices on or below this slot prevent a bus reset? */ |
5042 | static bool pci_slot_resetable(struct pci_slot *slot) | |
5043 | { | |
5044 | struct pci_dev *dev; | |
5045 | ||
33ba90aa JG |
5046 | if (slot->bus->self && |
5047 | (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
5048 | return false; | |
5049 | ||
f331a859 AW |
5050 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { |
5051 | if (!dev->slot || dev->slot != slot) | |
5052 | continue; | |
5053 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
5054 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
5055 | return false; | |
5056 | } | |
5057 | ||
5058 | return true; | |
5059 | } | |
5060 | ||
090a3c53 AW |
5061 | /* Lock devices from the top of the tree down */ |
5062 | static void pci_slot_lock(struct pci_slot *slot) | |
5063 | { | |
5064 | struct pci_dev *dev; | |
5065 | ||
5066 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5067 | if (!dev->slot || dev->slot != slot) | |
5068 | continue; | |
5069 | pci_dev_lock(dev); | |
5070 | if (dev->subordinate) | |
5071 | pci_bus_lock(dev->subordinate); | |
5072 | } | |
5073 | } | |
5074 | ||
5075 | /* Unlock devices from the bottom of the tree up */ | |
5076 | static void pci_slot_unlock(struct pci_slot *slot) | |
5077 | { | |
5078 | struct pci_dev *dev; | |
5079 | ||
5080 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5081 | if (!dev->slot || dev->slot != slot) | |
5082 | continue; | |
5083 | if (dev->subordinate) | |
5084 | pci_bus_unlock(dev->subordinate); | |
5085 | pci_dev_unlock(dev); | |
5086 | } | |
5087 | } | |
5088 | ||
61cf16d8 AW |
5089 | /* Return 1 on successful lock, 0 on contention */ |
5090 | static int pci_slot_trylock(struct pci_slot *slot) | |
5091 | { | |
5092 | struct pci_dev *dev; | |
5093 | ||
5094 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5095 | if (!dev->slot || dev->slot != slot) | |
5096 | continue; | |
5097 | if (!pci_dev_trylock(dev)) | |
5098 | goto unlock; | |
5099 | if (dev->subordinate) { | |
5100 | if (!pci_bus_trylock(dev->subordinate)) { | |
5101 | pci_dev_unlock(dev); | |
5102 | goto unlock; | |
5103 | } | |
5104 | } | |
5105 | } | |
5106 | return 1; | |
5107 | ||
5108 | unlock: | |
5109 | list_for_each_entry_continue_reverse(dev, | |
5110 | &slot->bus->devices, bus_list) { | |
5111 | if (!dev->slot || dev->slot != slot) | |
5112 | continue; | |
5113 | if (dev->subordinate) | |
5114 | pci_bus_unlock(dev->subordinate); | |
5115 | pci_dev_unlock(dev); | |
5116 | } | |
5117 | return 0; | |
5118 | } | |
5119 | ||
ddefc033 AW |
5120 | /* |
5121 | * Save and disable devices from the top of the tree down while holding | |
5122 | * the @dev mutex lock for the entire tree. | |
5123 | */ | |
5124 | static void pci_bus_save_and_disable_locked(struct pci_bus *bus) | |
090a3c53 AW |
5125 | { |
5126 | struct pci_dev *dev; | |
5127 | ||
5128 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5129 | pci_dev_save_and_disable(dev); | |
5130 | if (dev->subordinate) | |
ddefc033 | 5131 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5132 | } |
5133 | } | |
5134 | ||
5135 | /* | |
ddefc033 AW |
5136 | * Restore devices from top of the tree down while holding @dev mutex lock |
5137 | * for the entire tree. Parent bridges need to be restored before we can | |
5138 | * get to subordinate devices. | |
090a3c53 | 5139 | */ |
ddefc033 | 5140 | static void pci_bus_restore_locked(struct pci_bus *bus) |
090a3c53 AW |
5141 | { |
5142 | struct pci_dev *dev; | |
5143 | ||
5144 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5145 | pci_dev_restore(dev); | |
5146 | if (dev->subordinate) | |
ddefc033 | 5147 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5148 | } |
5149 | } | |
5150 | ||
ddefc033 AW |
5151 | /* |
5152 | * Save and disable devices from the top of the tree down while holding | |
5153 | * the @dev mutex lock for the entire tree. | |
5154 | */ | |
5155 | static void pci_slot_save_and_disable_locked(struct pci_slot *slot) | |
090a3c53 AW |
5156 | { |
5157 | struct pci_dev *dev; | |
5158 | ||
5159 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5160 | if (!dev->slot || dev->slot != slot) | |
5161 | continue; | |
5162 | pci_dev_save_and_disable(dev); | |
5163 | if (dev->subordinate) | |
ddefc033 | 5164 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5165 | } |
5166 | } | |
5167 | ||
5168 | /* | |
ddefc033 AW |
5169 | * Restore devices from top of the tree down while holding @dev mutex lock |
5170 | * for the entire tree. Parent bridges need to be restored before we can | |
5171 | * get to subordinate devices. | |
090a3c53 | 5172 | */ |
ddefc033 | 5173 | static void pci_slot_restore_locked(struct pci_slot *slot) |
090a3c53 AW |
5174 | { |
5175 | struct pci_dev *dev; | |
5176 | ||
5177 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5178 | if (!dev->slot || dev->slot != slot) | |
5179 | continue; | |
5180 | pci_dev_restore(dev); | |
5181 | if (dev->subordinate) | |
ddefc033 | 5182 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5183 | } |
5184 | } | |
5185 | ||
5186 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
5187 | { | |
5188 | int rc; | |
5189 | ||
f331a859 | 5190 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
5191 | return -ENOTTY; |
5192 | ||
5193 | if (!probe) | |
5194 | pci_slot_lock(slot); | |
5195 | ||
5196 | might_sleep(); | |
5197 | ||
5198 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
5199 | ||
5200 | if (!probe) | |
5201 | pci_slot_unlock(slot); | |
5202 | ||
5203 | return rc; | |
5204 | } | |
5205 | ||
9a3d2b9b AW |
5206 | /** |
5207 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
5208 | * @slot: PCI slot to probe | |
5209 | * | |
5210 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
5211 | */ | |
5212 | int pci_probe_reset_slot(struct pci_slot *slot) | |
5213 | { | |
5214 | return pci_slot_reset(slot, 1); | |
5215 | } | |
5216 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
5217 | ||
090a3c53 | 5218 | /** |
c6a44ba9 | 5219 | * __pci_reset_slot - Try to reset a PCI slot |
090a3c53 AW |
5220 | * @slot: PCI slot to reset |
5221 | * | |
5222 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
5223 | * independent of other slots. For instance, some slots may support slot power | |
5224 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
5225 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
5226 | * Generally a slot reset should be attempted before a bus reset. All of the | |
5227 | * function of the slot and any subordinate buses behind the slot are reset | |
5228 | * through this function. PCI config space of all devices in the slot and | |
5229 | * behind the slot is saved before and restored after reset. | |
5230 | * | |
61cf16d8 AW |
5231 | * Same as above except return -EAGAIN if the slot cannot be locked |
5232 | */ | |
c6a44ba9 | 5233 | static int __pci_reset_slot(struct pci_slot *slot) |
61cf16d8 AW |
5234 | { |
5235 | int rc; | |
5236 | ||
5237 | rc = pci_slot_reset(slot, 1); | |
5238 | if (rc) | |
5239 | return rc; | |
5240 | ||
61cf16d8 | 5241 | if (pci_slot_trylock(slot)) { |
ddefc033 | 5242 | pci_slot_save_and_disable_locked(slot); |
61cf16d8 AW |
5243 | might_sleep(); |
5244 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
ddefc033 | 5245 | pci_slot_restore_locked(slot); |
61cf16d8 AW |
5246 | pci_slot_unlock(slot); |
5247 | } else | |
5248 | rc = -EAGAIN; | |
5249 | ||
61cf16d8 AW |
5250 | return rc; |
5251 | } | |
61cf16d8 | 5252 | |
090a3c53 AW |
5253 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
5254 | { | |
18426238 SK |
5255 | int ret; |
5256 | ||
f331a859 | 5257 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
5258 | return -ENOTTY; |
5259 | ||
5260 | if (probe) | |
5261 | return 0; | |
5262 | ||
5263 | pci_bus_lock(bus); | |
5264 | ||
5265 | might_sleep(); | |
5266 | ||
381634ca | 5267 | ret = pci_bridge_secondary_bus_reset(bus->self); |
090a3c53 AW |
5268 | |
5269 | pci_bus_unlock(bus); | |
5270 | ||
18426238 | 5271 | return ret; |
090a3c53 AW |
5272 | } |
5273 | ||
c4eed62a KB |
5274 | /** |
5275 | * pci_bus_error_reset - reset the bridge's subordinate bus | |
5276 | * @bridge: The parent device that connects to the bus to reset | |
5277 | * | |
5278 | * This function will first try to reset the slots on this bus if the method is | |
5279 | * available. If slot reset fails or is not available, this will fall back to a | |
5280 | * secondary bus reset. | |
5281 | */ | |
5282 | int pci_bus_error_reset(struct pci_dev *bridge) | |
5283 | { | |
5284 | struct pci_bus *bus = bridge->subordinate; | |
5285 | struct pci_slot *slot; | |
5286 | ||
5287 | if (!bus) | |
5288 | return -ENOTTY; | |
5289 | ||
5290 | mutex_lock(&pci_slot_mutex); | |
5291 | if (list_empty(&bus->slots)) | |
5292 | goto bus_reset; | |
5293 | ||
5294 | list_for_each_entry(slot, &bus->slots, list) | |
5295 | if (pci_probe_reset_slot(slot)) | |
5296 | goto bus_reset; | |
5297 | ||
5298 | list_for_each_entry(slot, &bus->slots, list) | |
5299 | if (pci_slot_reset(slot, 0)) | |
5300 | goto bus_reset; | |
5301 | ||
5302 | mutex_unlock(&pci_slot_mutex); | |
5303 | return 0; | |
5304 | bus_reset: | |
5305 | mutex_unlock(&pci_slot_mutex); | |
5306 | return pci_bus_reset(bridge->subordinate, 0); | |
5307 | } | |
5308 | ||
9a3d2b9b AW |
5309 | /** |
5310 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
5311 | * @bus: PCI bus to probe | |
5312 | * | |
5313 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
5314 | */ | |
5315 | int pci_probe_reset_bus(struct pci_bus *bus) | |
5316 | { | |
5317 | return pci_bus_reset(bus, 1); | |
5318 | } | |
5319 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
5320 | ||
090a3c53 | 5321 | /** |
c6a44ba9 | 5322 | * __pci_reset_bus - Try to reset a PCI bus |
090a3c53 AW |
5323 | * @bus: top level PCI bus to reset |
5324 | * | |
61cf16d8 | 5325 | * Same as above except return -EAGAIN if the bus cannot be locked |
090a3c53 | 5326 | */ |
c6a44ba9 | 5327 | static int __pci_reset_bus(struct pci_bus *bus) |
090a3c53 AW |
5328 | { |
5329 | int rc; | |
5330 | ||
5331 | rc = pci_bus_reset(bus, 1); | |
5332 | if (rc) | |
5333 | return rc; | |
5334 | ||
61cf16d8 | 5335 | if (pci_bus_trylock(bus)) { |
ddefc033 | 5336 | pci_bus_save_and_disable_locked(bus); |
61cf16d8 | 5337 | might_sleep(); |
381634ca | 5338 | rc = pci_bridge_secondary_bus_reset(bus->self); |
ddefc033 | 5339 | pci_bus_restore_locked(bus); |
61cf16d8 AW |
5340 | pci_bus_unlock(bus); |
5341 | } else | |
5342 | rc = -EAGAIN; | |
090a3c53 | 5343 | |
090a3c53 AW |
5344 | return rc; |
5345 | } | |
090a3c53 | 5346 | |
61cf16d8 | 5347 | /** |
c6a44ba9 | 5348 | * pci_reset_bus - Try to reset a PCI bus |
811c5cb3 | 5349 | * @pdev: top level PCI device to reset via slot/bus |
61cf16d8 AW |
5350 | * |
5351 | * Same as above except return -EAGAIN if the bus cannot be locked | |
5352 | */ | |
c6a44ba9 | 5353 | int pci_reset_bus(struct pci_dev *pdev) |
61cf16d8 | 5354 | { |
d8a52810 | 5355 | return (!pci_probe_reset_slot(pdev->slot)) ? |
c6a44ba9 | 5356 | __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); |
61cf16d8 | 5357 | } |
c6a44ba9 | 5358 | EXPORT_SYMBOL_GPL(pci_reset_bus); |
61cf16d8 | 5359 | |
d556ad4b PO |
5360 | /** |
5361 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
5362 | * @dev: PCI device to query | |
5363 | * | |
74356add BH |
5364 | * Returns mmrbc: maximum designed memory read count in bytes or |
5365 | * appropriate error value. | |
d556ad4b PO |
5366 | */ |
5367 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
5368 | { | |
7c9e2b1c | 5369 | int cap; |
d556ad4b PO |
5370 | u32 stat; |
5371 | ||
5372 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5373 | if (!cap) | |
5374 | return -EINVAL; | |
5375 | ||
7c9e2b1c | 5376 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
5377 | return -EINVAL; |
5378 | ||
25daeb55 | 5379 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
5380 | } |
5381 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
5382 | ||
5383 | /** | |
5384 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
5385 | * @dev: PCI device to query | |
5386 | * | |
74356add BH |
5387 | * Returns mmrbc: maximum memory read count in bytes or appropriate error |
5388 | * value. | |
d556ad4b PO |
5389 | */ |
5390 | int pcix_get_mmrbc(struct pci_dev *dev) | |
5391 | { | |
7c9e2b1c | 5392 | int cap; |
bdc2bda7 | 5393 | u16 cmd; |
d556ad4b PO |
5394 | |
5395 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5396 | if (!cap) | |
5397 | return -EINVAL; | |
5398 | ||
7c9e2b1c DN |
5399 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5400 | return -EINVAL; | |
d556ad4b | 5401 | |
7c9e2b1c | 5402 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
5403 | } |
5404 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
5405 | ||
5406 | /** | |
5407 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
5408 | * @dev: PCI device to query | |
5409 | * @mmrbc: maximum memory read count in bytes | |
5410 | * valid values are 512, 1024, 2048, 4096 | |
5411 | * | |
74356add | 5412 | * If possible sets maximum memory read byte count, some bridges have errata |
d556ad4b PO |
5413 | * that prevent this. |
5414 | */ | |
5415 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
5416 | { | |
7c9e2b1c | 5417 | int cap; |
bdc2bda7 DN |
5418 | u32 stat, v, o; |
5419 | u16 cmd; | |
d556ad4b | 5420 | |
229f5afd | 5421 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 5422 | return -EINVAL; |
d556ad4b PO |
5423 | |
5424 | v = ffs(mmrbc) - 10; | |
5425 | ||
5426 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5427 | if (!cap) | |
7c9e2b1c | 5428 | return -EINVAL; |
d556ad4b | 5429 | |
7c9e2b1c DN |
5430 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
5431 | return -EINVAL; | |
d556ad4b PO |
5432 | |
5433 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
5434 | return -E2BIG; | |
5435 | ||
7c9e2b1c DN |
5436 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5437 | return -EINVAL; | |
d556ad4b PO |
5438 | |
5439 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
5440 | if (o != v) { | |
809a3bf9 | 5441 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
5442 | return -EIO; |
5443 | ||
5444 | cmd &= ~PCI_X_CMD_MAX_READ; | |
5445 | cmd |= v << 2; | |
7c9e2b1c DN |
5446 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
5447 | return -EIO; | |
d556ad4b | 5448 | } |
7c9e2b1c | 5449 | return 0; |
d556ad4b PO |
5450 | } |
5451 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
5452 | ||
5453 | /** | |
5454 | * pcie_get_readrq - get PCI Express read request size | |
5455 | * @dev: PCI device to query | |
5456 | * | |
74356add | 5457 | * Returns maximum memory read request in bytes or appropriate error value. |
d556ad4b PO |
5458 | */ |
5459 | int pcie_get_readrq(struct pci_dev *dev) | |
5460 | { | |
d556ad4b PO |
5461 | u16 ctl; |
5462 | ||
59875ae4 | 5463 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 5464 | |
59875ae4 | 5465 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
5466 | } |
5467 | EXPORT_SYMBOL(pcie_get_readrq); | |
5468 | ||
5469 | /** | |
5470 | * pcie_set_readrq - set PCI Express maximum memory read request | |
5471 | * @dev: PCI device to query | |
42e61f4a | 5472 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
5473 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5474 | * | |
c9b378c7 | 5475 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
5476 | */ |
5477 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
5478 | { | |
59875ae4 | 5479 | u16 v; |
d556ad4b | 5480 | |
229f5afd | 5481 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 5482 | return -EINVAL; |
d556ad4b | 5483 | |
a1c473aa | 5484 | /* |
74356add BH |
5485 | * If using the "performance" PCIe config, we clamp the read rq |
5486 | * size to the max packet size to keep the host bridge from | |
5487 | * generating requests larger than we can cope with. | |
a1c473aa BH |
5488 | */ |
5489 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
5490 | int mps = pcie_get_mps(dev); | |
5491 | ||
a1c473aa BH |
5492 | if (mps < rq) |
5493 | rq = mps; | |
5494 | } | |
5495 | ||
5496 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 5497 | |
59875ae4 JL |
5498 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
5499 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
5500 | } |
5501 | EXPORT_SYMBOL(pcie_set_readrq); | |
5502 | ||
b03e7495 JM |
5503 | /** |
5504 | * pcie_get_mps - get PCI Express maximum payload size | |
5505 | * @dev: PCI device to query | |
5506 | * | |
5507 | * Returns maximum payload size in bytes | |
b03e7495 JM |
5508 | */ |
5509 | int pcie_get_mps(struct pci_dev *dev) | |
5510 | { | |
b03e7495 JM |
5511 | u16 ctl; |
5512 | ||
59875ae4 | 5513 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 5514 | |
59875ae4 | 5515 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 5516 | } |
f1c66c46 | 5517 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
5518 | |
5519 | /** | |
5520 | * pcie_set_mps - set PCI Express maximum payload size | |
5521 | * @dev: PCI device to query | |
47c08f31 | 5522 | * @mps: maximum payload size in bytes |
b03e7495 JM |
5523 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5524 | * | |
5525 | * If possible sets maximum payload size | |
5526 | */ | |
5527 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
5528 | { | |
59875ae4 | 5529 | u16 v; |
b03e7495 JM |
5530 | |
5531 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 5532 | return -EINVAL; |
b03e7495 JM |
5533 | |
5534 | v = ffs(mps) - 8; | |
f7625980 | 5535 | if (v > dev->pcie_mpss) |
59875ae4 | 5536 | return -EINVAL; |
b03e7495 JM |
5537 | v <<= 5; |
5538 | ||
59875ae4 JL |
5539 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
5540 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 | 5541 | } |
f1c66c46 | 5542 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 5543 | |
6db79a88 TG |
5544 | /** |
5545 | * pcie_bandwidth_available - determine minimum link settings of a PCIe | |
5546 | * device and its bandwidth limitation | |
5547 | * @dev: PCI device to query | |
5548 | * @limiting_dev: storage for device causing the bandwidth limitation | |
5549 | * @speed: storage for speed of limiting device | |
5550 | * @width: storage for width of limiting device | |
5551 | * | |
5552 | * Walk up the PCI device chain and find the point where the minimum | |
5553 | * bandwidth is available. Return the bandwidth available there and (if | |
5554 | * limiting_dev, speed, and width pointers are supplied) information about | |
5555 | * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of | |
5556 | * raw bandwidth. | |
5557 | */ | |
5558 | u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, | |
5559 | enum pci_bus_speed *speed, | |
5560 | enum pcie_link_width *width) | |
5561 | { | |
5562 | u16 lnksta; | |
5563 | enum pci_bus_speed next_speed; | |
5564 | enum pcie_link_width next_width; | |
5565 | u32 bw, next_bw; | |
5566 | ||
5567 | if (speed) | |
5568 | *speed = PCI_SPEED_UNKNOWN; | |
5569 | if (width) | |
5570 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
5571 | ||
5572 | bw = 0; | |
5573 | ||
5574 | while (dev) { | |
5575 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
5576 | ||
5577 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
5578 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
5579 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
5580 | ||
5581 | next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); | |
5582 | ||
5583 | /* Check if current device limits the total bandwidth */ | |
5584 | if (!bw || next_bw <= bw) { | |
5585 | bw = next_bw; | |
5586 | ||
5587 | if (limiting_dev) | |
5588 | *limiting_dev = dev; | |
5589 | if (speed) | |
5590 | *speed = next_speed; | |
5591 | if (width) | |
5592 | *width = next_width; | |
5593 | } | |
5594 | ||
5595 | dev = pci_upstream_bridge(dev); | |
5596 | } | |
5597 | ||
5598 | return bw; | |
5599 | } | |
5600 | EXPORT_SYMBOL(pcie_bandwidth_available); | |
5601 | ||
6cf57be0 TG |
5602 | /** |
5603 | * pcie_get_speed_cap - query for the PCI device's link speed capability | |
5604 | * @dev: PCI device to query | |
5605 | * | |
5606 | * Query the PCI device speed capability. Return the maximum link speed | |
5607 | * supported by the device. | |
5608 | */ | |
5609 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) | |
5610 | { | |
5611 | u32 lnkcap2, lnkcap; | |
5612 | ||
5613 | /* | |
f1f90e25 MP |
5614 | * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The |
5615 | * implementation note there recommends using the Supported Link | |
5616 | * Speeds Vector in Link Capabilities 2 when supported. | |
5617 | * | |
5618 | * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software | |
5619 | * should use the Supported Link Speeds field in Link Capabilities, | |
5620 | * where only 2.5 GT/s and 5.0 GT/s speeds were defined. | |
6cf57be0 TG |
5621 | */ |
5622 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); | |
5623 | if (lnkcap2) { /* PCIe r3.0-compliant */ | |
5624 | if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) | |
5625 | return PCIE_SPEED_16_0GT; | |
5626 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
5627 | return PCIE_SPEED_8_0GT; | |
5628 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
5629 | return PCIE_SPEED_5_0GT; | |
5630 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
5631 | return PCIE_SPEED_2_5GT; | |
5632 | return PCI_SPEED_UNKNOWN; | |
5633 | } | |
5634 | ||
5635 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
f1f90e25 MP |
5636 | if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) |
5637 | return PCIE_SPEED_5_0GT; | |
5638 | else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) | |
5639 | return PCIE_SPEED_2_5GT; | |
6cf57be0 TG |
5640 | |
5641 | return PCI_SPEED_UNKNOWN; | |
5642 | } | |
576c7218 | 5643 | EXPORT_SYMBOL(pcie_get_speed_cap); |
6cf57be0 | 5644 | |
c70b65fb TG |
5645 | /** |
5646 | * pcie_get_width_cap - query for the PCI device's link width capability | |
5647 | * @dev: PCI device to query | |
5648 | * | |
5649 | * Query the PCI device width capability. Return the maximum link width | |
5650 | * supported by the device. | |
5651 | */ | |
5652 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) | |
5653 | { | |
5654 | u32 lnkcap; | |
5655 | ||
5656 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
5657 | if (lnkcap) | |
5658 | return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; | |
5659 | ||
5660 | return PCIE_LNK_WIDTH_UNKNOWN; | |
5661 | } | |
576c7218 | 5662 | EXPORT_SYMBOL(pcie_get_width_cap); |
c70b65fb | 5663 | |
b852f63a TG |
5664 | /** |
5665 | * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability | |
5666 | * @dev: PCI device | |
5667 | * @speed: storage for link speed | |
5668 | * @width: storage for link width | |
5669 | * | |
5670 | * Calculate a PCI device's link bandwidth by querying for its link speed | |
5671 | * and width, multiplying them, and applying encoding overhead. The result | |
5672 | * is in Mb/s, i.e., megabits/second of raw bandwidth. | |
5673 | */ | |
5674 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, | |
5675 | enum pcie_link_width *width) | |
5676 | { | |
5677 | *speed = pcie_get_speed_cap(dev); | |
5678 | *width = pcie_get_width_cap(dev); | |
5679 | ||
5680 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
5681 | return 0; | |
5682 | ||
5683 | return *width * PCIE_SPEED2MBS_ENC(*speed); | |
5684 | } | |
5685 | ||
9e506a7b | 5686 | /** |
2d1ce5ec | 5687 | * __pcie_print_link_status - Report the PCI device's link speed and width |
9e506a7b | 5688 | * @dev: PCI device to query |
2d1ce5ec | 5689 | * @verbose: Print info even when enough bandwidth is available |
9e506a7b | 5690 | * |
2d1ce5ec AG |
5691 | * If the available bandwidth at the device is less than the device is |
5692 | * capable of, report the device's maximum possible bandwidth and the | |
5693 | * upstream link that limits its performance. If @verbose, always print | |
5694 | * the available bandwidth, even if the device isn't constrained. | |
9e506a7b | 5695 | */ |
2d1ce5ec | 5696 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose) |
9e506a7b TG |
5697 | { |
5698 | enum pcie_link_width width, width_cap; | |
5699 | enum pci_bus_speed speed, speed_cap; | |
5700 | struct pci_dev *limiting_dev = NULL; | |
5701 | u32 bw_avail, bw_cap; | |
5702 | ||
5703 | bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap); | |
5704 | bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width); | |
5705 | ||
2d1ce5ec | 5706 | if (bw_avail >= bw_cap && verbose) |
0cf22d6b | 5707 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n", |
9e506a7b TG |
5708 | bw_cap / 1000, bw_cap % 1000, |
5709 | PCIE_SPEED2STR(speed_cap), width_cap); | |
2d1ce5ec | 5710 | else if (bw_avail < bw_cap) |
0cf22d6b | 5711 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n", |
9e506a7b TG |
5712 | bw_avail / 1000, bw_avail % 1000, |
5713 | PCIE_SPEED2STR(speed), width, | |
5714 | limiting_dev ? pci_name(limiting_dev) : "<unknown>", | |
5715 | bw_cap / 1000, bw_cap % 1000, | |
5716 | PCIE_SPEED2STR(speed_cap), width_cap); | |
5717 | } | |
2d1ce5ec AG |
5718 | |
5719 | /** | |
5720 | * pcie_print_link_status - Report the PCI device's link speed and width | |
5721 | * @dev: PCI device to query | |
5722 | * | |
5723 | * Report the available bandwidth at the device. | |
5724 | */ | |
5725 | void pcie_print_link_status(struct pci_dev *dev) | |
5726 | { | |
5727 | __pcie_print_link_status(dev, true); | |
5728 | } | |
9e506a7b TG |
5729 | EXPORT_SYMBOL(pcie_print_link_status); |
5730 | ||
c87deff7 HS |
5731 | /** |
5732 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 5733 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
5734 | * @flags: resource type mask to be selected |
5735 | * | |
5736 | * This helper routine makes bar mask from the type of resource. | |
5737 | */ | |
5738 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
5739 | { | |
5740 | int i, bars = 0; | |
5741 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
5742 | if (pci_resource_flags(dev, i) & flags) | |
5743 | bars |= (1 << i); | |
5744 | return bars; | |
5745 | } | |
b7fe9434 | 5746 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 5747 | |
95a8b6ef MT |
5748 | /* Some architectures require additional programming to enable VGA */ |
5749 | static arch_set_vga_state_t arch_set_vga_state; | |
5750 | ||
5751 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
5752 | { | |
5753 | arch_set_vga_state = func; /* NULL disables */ | |
5754 | } | |
5755 | ||
5756 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 5757 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
5758 | { |
5759 | if (arch_set_vga_state) | |
5760 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 5761 | flags); |
95a8b6ef MT |
5762 | return 0; |
5763 | } | |
5764 | ||
deb2d2ec BH |
5765 | /** |
5766 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
5767 | * @dev: the PCI device |
5768 | * @decode: true = enable decoding, false = disable decoding | |
5769 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 5770 | * @flags: traverse ancestors and change bridges |
3448a19d | 5771 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
5772 | */ |
5773 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 5774 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
5775 | { |
5776 | struct pci_bus *bus; | |
5777 | struct pci_dev *bridge; | |
5778 | u16 cmd; | |
95a8b6ef | 5779 | int rc; |
deb2d2ec | 5780 | |
67ebd814 | 5781 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 5782 | |
95a8b6ef | 5783 | /* ARCH specific VGA enables */ |
3448a19d | 5784 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
5785 | if (rc) |
5786 | return rc; | |
5787 | ||
3448a19d DA |
5788 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
5789 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
5790 | if (decode == true) | |
5791 | cmd |= command_bits; | |
5792 | else | |
5793 | cmd &= ~command_bits; | |
5794 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
5795 | } | |
deb2d2ec | 5796 | |
3448a19d | 5797 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
5798 | return 0; |
5799 | ||
5800 | bus = dev->bus; | |
5801 | while (bus) { | |
5802 | bridge = bus->self; | |
5803 | if (bridge) { | |
5804 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
5805 | &cmd); | |
5806 | if (decode == true) | |
5807 | cmd |= PCI_BRIDGE_CTL_VGA; | |
5808 | else | |
5809 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
5810 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
5811 | cmd); | |
5812 | } | |
5813 | bus = bus->parent; | |
5814 | } | |
5815 | return 0; | |
5816 | } | |
5817 | ||
f0af9593 BH |
5818 | /** |
5819 | * pci_add_dma_alias - Add a DMA devfn alias for a device | |
5820 | * @dev: the PCI device for which alias is added | |
5821 | * @devfn: alias slot and function | |
5822 | * | |
f778a0d2 LG |
5823 | * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask |
5824 | * which is used to program permissible bus-devfn source addresses for DMA | |
5825 | * requests in an IOMMU. These aliases factor into IOMMU group creation | |
5826 | * and are useful for devices generating DMA requests beyond or different | |
5827 | * from their logical bus-devfn. Examples include device quirks where the | |
5828 | * device simply uses the wrong devfn, as well as non-transparent bridges | |
5829 | * where the alias may be a proxy for devices in another domain. | |
5830 | * | |
5831 | * IOMMU group creation is performed during device discovery or addition, | |
5832 | * prior to any potential DMA mapping and therefore prior to driver probing | |
5833 | * (especially for userspace assigned devices where IOMMU group definition | |
5834 | * cannot be left as a userspace activity). DMA aliases should therefore | |
5835 | * be configured via quirks, such as the PCI fixup header quirk. | |
f0af9593 BH |
5836 | */ |
5837 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn) | |
5838 | { | |
338c3149 | 5839 | if (!dev->dma_alias_mask) |
c6635792 | 5840 | dev->dma_alias_mask = bitmap_zalloc(U8_MAX, GFP_KERNEL); |
338c3149 | 5841 | if (!dev->dma_alias_mask) { |
7506dc79 | 5842 | pci_warn(dev, "Unable to allocate DMA alias mask\n"); |
338c3149 JL |
5843 | return; |
5844 | } | |
5845 | ||
5846 | set_bit(devfn, dev->dma_alias_mask); | |
7506dc79 | 5847 | pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n", |
48c83080 | 5848 | PCI_SLOT(devfn), PCI_FUNC(devfn)); |
f0af9593 BH |
5849 | } |
5850 | ||
338c3149 JL |
5851 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) |
5852 | { | |
5853 | return (dev1->dma_alias_mask && | |
5854 | test_bit(dev2->devfn, dev1->dma_alias_mask)) || | |
5855 | (dev2->dma_alias_mask && | |
5856 | test_bit(dev1->devfn, dev2->dma_alias_mask)); | |
5857 | } | |
5858 | ||
8496e85c RW |
5859 | bool pci_device_is_present(struct pci_dev *pdev) |
5860 | { | |
5861 | u32 v; | |
5862 | ||
fe2bd75b KB |
5863 | if (pci_dev_is_disconnected(pdev)) |
5864 | return false; | |
8496e85c RW |
5865 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); |
5866 | } | |
5867 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
5868 | ||
08249651 RW |
5869 | void pci_ignore_hotplug(struct pci_dev *dev) |
5870 | { | |
5871 | struct pci_dev *bridge = dev->bus->self; | |
5872 | ||
5873 | dev->ignore_hotplug = 1; | |
5874 | /* Propagate the "ignore hotplug" setting to the parent bridge. */ | |
5875 | if (bridge) | |
5876 | bridge->ignore_hotplug = 1; | |
5877 | } | |
5878 | EXPORT_SYMBOL_GPL(pci_ignore_hotplug); | |
5879 | ||
0a701aa6 YX |
5880 | resource_size_t __weak pcibios_default_alignment(void) |
5881 | { | |
5882 | return 0; | |
5883 | } | |
5884 | ||
32a9a682 YS |
5885 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
5886 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 5887 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
5888 | |
5889 | /** | |
5890 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
5891 | * @dev: the PCI device to get | |
e3adec72 | 5892 | * @resize: whether or not to change resources' size when reassigning alignment |
32a9a682 YS |
5893 | * |
5894 | * RETURNS: Resource alignment if it is specified. | |
5895 | * Zero if it is not specified. | |
5896 | */ | |
e3adec72 YX |
5897 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, |
5898 | bool *resize) | |
32a9a682 | 5899 | { |
07d8d7e5 | 5900 | int align_order, count; |
0a701aa6 | 5901 | resource_size_t align = pcibios_default_alignment(); |
07d8d7e5 LG |
5902 | const char *p; |
5903 | int ret; | |
32a9a682 YS |
5904 | |
5905 | spin_lock(&resource_alignment_lock); | |
5906 | p = resource_alignment_param; | |
0a701aa6 | 5907 | if (!*p && !align) |
f0b99f70 YX |
5908 | goto out; |
5909 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
0a701aa6 | 5910 | align = 0; |
f0b99f70 YX |
5911 | pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n"); |
5912 | goto out; | |
5913 | } | |
5914 | ||
32a9a682 YS |
5915 | while (*p) { |
5916 | count = 0; | |
5917 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
5918 | p[count] == '@') { | |
5919 | p += count + 1; | |
5920 | } else { | |
5921 | align_order = -1; | |
5922 | } | |
07d8d7e5 LG |
5923 | |
5924 | ret = pci_dev_str_match(dev, p, &p); | |
5925 | if (ret == 1) { | |
5926 | *resize = true; | |
5927 | if (align_order == -1) | |
5928 | align = PAGE_SIZE; | |
5929 | else | |
5930 | align = 1 << align_order; | |
5931 | break; | |
5932 | } else if (ret < 0) { | |
5933 | pr_err("PCI: Can't parse resource_alignment parameter: %s\n", | |
5934 | p); | |
5935 | break; | |
32a9a682 | 5936 | } |
07d8d7e5 | 5937 | |
32a9a682 YS |
5938 | if (*p != ';' && *p != ',') { |
5939 | /* End of param or invalid format */ | |
5940 | break; | |
5941 | } | |
5942 | p++; | |
5943 | } | |
f0b99f70 | 5944 | out: |
32a9a682 YS |
5945 | spin_unlock(&resource_alignment_lock); |
5946 | return align; | |
5947 | } | |
5948 | ||
81a5e70e | 5949 | static void pci_request_resource_alignment(struct pci_dev *dev, int bar, |
e3adec72 | 5950 | resource_size_t align, bool resize) |
81a5e70e BH |
5951 | { |
5952 | struct resource *r = &dev->resource[bar]; | |
5953 | resource_size_t size; | |
5954 | ||
5955 | if (!(r->flags & IORESOURCE_MEM)) | |
5956 | return; | |
5957 | ||
5958 | if (r->flags & IORESOURCE_PCI_FIXED) { | |
7506dc79 | 5959 | pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n", |
81a5e70e BH |
5960 | bar, r, (unsigned long long)align); |
5961 | return; | |
5962 | } | |
5963 | ||
5964 | size = resource_size(r); | |
0dde1c08 BH |
5965 | if (size >= align) |
5966 | return; | |
81a5e70e | 5967 | |
0dde1c08 | 5968 | /* |
e3adec72 YX |
5969 | * Increase the alignment of the resource. There are two ways we |
5970 | * can do this: | |
0dde1c08 | 5971 | * |
e3adec72 YX |
5972 | * 1) Increase the size of the resource. BARs are aligned on their |
5973 | * size, so when we reallocate space for this resource, we'll | |
5974 | * allocate it with the larger alignment. This also prevents | |
5975 | * assignment of any other BARs inside the alignment region, so | |
5976 | * if we're requesting page alignment, this means no other BARs | |
5977 | * will share the page. | |
5978 | * | |
5979 | * The disadvantage is that this makes the resource larger than | |
5980 | * the hardware BAR, which may break drivers that compute things | |
5981 | * based on the resource size, e.g., to find registers at a | |
5982 | * fixed offset before the end of the BAR. | |
5983 | * | |
5984 | * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and | |
5985 | * set r->start to the desired alignment. By itself this | |
5986 | * doesn't prevent other BARs being put inside the alignment | |
5987 | * region, but if we realign *every* resource of every device in | |
5988 | * the system, none of them will share an alignment region. | |
5989 | * | |
5990 | * When the user has requested alignment for only some devices via | |
5991 | * the "pci=resource_alignment" argument, "resize" is true and we | |
5992 | * use the first method. Otherwise we assume we're aligning all | |
5993 | * devices and we use the second. | |
0dde1c08 | 5994 | */ |
e3adec72 | 5995 | |
7506dc79 | 5996 | pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n", |
0dde1c08 | 5997 | bar, r, (unsigned long long)align); |
81a5e70e | 5998 | |
e3adec72 YX |
5999 | if (resize) { |
6000 | r->start = 0; | |
6001 | r->end = align - 1; | |
6002 | } else { | |
6003 | r->flags &= ~IORESOURCE_SIZEALIGN; | |
6004 | r->flags |= IORESOURCE_STARTALIGN; | |
6005 | r->start = align; | |
6006 | r->end = r->start + size - 1; | |
6007 | } | |
0dde1c08 | 6008 | r->flags |= IORESOURCE_UNSET; |
81a5e70e BH |
6009 | } |
6010 | ||
2069ecfb YL |
6011 | /* |
6012 | * This function disables memory decoding and releases memory resources | |
6013 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
6014 | * It also rounds up size to specified alignment. | |
6015 | * Later on, the kernel will assign page-aligned memory resource back | |
6016 | * to the device. | |
6017 | */ | |
6018 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
6019 | { | |
6020 | int i; | |
6021 | struct resource *r; | |
81a5e70e | 6022 | resource_size_t align; |
2069ecfb | 6023 | u16 command; |
e3adec72 | 6024 | bool resize = false; |
2069ecfb | 6025 | |
62d9a78f YX |
6026 | /* |
6027 | * VF BARs are read-only zero according to SR-IOV spec r1.1, sec | |
6028 | * 3.4.1.11. Their resources are allocated from the space | |
6029 | * described by the VF BARx register in the PF's SR-IOV capability. | |
6030 | * We can't influence their alignment here. | |
6031 | */ | |
6032 | if (dev->is_virtfn) | |
6033 | return; | |
6034 | ||
10c463a7 | 6035 | /* check if specified PCI is target device to reassign */ |
e3adec72 | 6036 | align = pci_specified_resource_alignment(dev, &resize); |
10c463a7 | 6037 | if (!align) |
2069ecfb YL |
6038 | return; |
6039 | ||
6040 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
6041 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
7506dc79 | 6042 | pci_warn(dev, "Can't reassign resources to host bridge\n"); |
2069ecfb YL |
6043 | return; |
6044 | } | |
6045 | ||
2069ecfb YL |
6046 | pci_read_config_word(dev, PCI_COMMAND, &command); |
6047 | command &= ~PCI_COMMAND_MEMORY; | |
6048 | pci_write_config_word(dev, PCI_COMMAND, command); | |
6049 | ||
81a5e70e | 6050 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) |
e3adec72 | 6051 | pci_request_resource_alignment(dev, i, align, resize); |
f0b99f70 | 6052 | |
81a5e70e BH |
6053 | /* |
6054 | * Need to disable bridge's resource window, | |
2069ecfb YL |
6055 | * to enable the kernel to reassign new resource |
6056 | * window later on. | |
6057 | */ | |
b2fb5cc5 | 6058 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { |
2069ecfb YL |
6059 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { |
6060 | r = &dev->resource[i]; | |
6061 | if (!(r->flags & IORESOURCE_MEM)) | |
6062 | continue; | |
bd064f0a | 6063 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
6064 | r->end = resource_size(r) - 1; |
6065 | r->start = 0; | |
6066 | } | |
6067 | pci_disable_bridge_window(dev); | |
6068 | } | |
6069 | } | |
6070 | ||
9738abed | 6071 | static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
32a9a682 YS |
6072 | { |
6073 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
6074 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
6075 | spin_lock(&resource_alignment_lock); | |
6076 | strncpy(resource_alignment_param, buf, count); | |
6077 | resource_alignment_param[count] = '\0'; | |
6078 | spin_unlock(&resource_alignment_lock); | |
6079 | return count; | |
6080 | } | |
6081 | ||
9738abed | 6082 | static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
32a9a682 YS |
6083 | { |
6084 | size_t count; | |
6085 | spin_lock(&resource_alignment_lock); | |
6086 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
6087 | spin_unlock(&resource_alignment_lock); | |
6088 | return count; | |
6089 | } | |
6090 | ||
d61dfafc | 6091 | static ssize_t resource_alignment_show(struct bus_type *bus, char *buf) |
32a9a682 YS |
6092 | { |
6093 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
6094 | } | |
6095 | ||
d61dfafc | 6096 | static ssize_t resource_alignment_store(struct bus_type *bus, |
32a9a682 YS |
6097 | const char *buf, size_t count) |
6098 | { | |
6099 | return pci_set_resource_alignment_param(buf, count); | |
6100 | } | |
6101 | ||
d61dfafc | 6102 | static BUS_ATTR_RW(resource_alignment); |
32a9a682 YS |
6103 | |
6104 | static int __init pci_resource_alignment_sysfs_init(void) | |
6105 | { | |
6106 | return bus_create_file(&pci_bus_type, | |
6107 | &bus_attr_resource_alignment); | |
6108 | } | |
32a9a682 YS |
6109 | late_initcall(pci_resource_alignment_sysfs_init); |
6110 | ||
15856ad5 | 6111 | static void pci_no_domains(void) |
32a2eea7 JG |
6112 | { |
6113 | #ifdef CONFIG_PCI_DOMAINS | |
6114 | pci_domains_supported = 0; | |
6115 | #endif | |
6116 | } | |
6117 | ||
ae07b786 | 6118 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
41e5c0f8 LD |
6119 | static atomic_t __domain_nr = ATOMIC_INIT(-1); |
6120 | ||
ae07b786 | 6121 | static int pci_get_new_domain_nr(void) |
41e5c0f8 LD |
6122 | { |
6123 | return atomic_inc_return(&__domain_nr); | |
6124 | } | |
7c674700 | 6125 | |
1a4f93f7 | 6126 | static int of_pci_bus_find_domain_nr(struct device *parent) |
7c674700 LP |
6127 | { |
6128 | static int use_dt_domains = -1; | |
54c6e2dd | 6129 | int domain = -1; |
7c674700 | 6130 | |
54c6e2dd KHC |
6131 | if (parent) |
6132 | domain = of_get_pci_domain_nr(parent->of_node); | |
74356add | 6133 | |
7c674700 LP |
6134 | /* |
6135 | * Check DT domain and use_dt_domains values. | |
6136 | * | |
6137 | * If DT domain property is valid (domain >= 0) and | |
6138 | * use_dt_domains != 0, the DT assignment is valid since this means | |
6139 | * we have not previously allocated a domain number by using | |
6140 | * pci_get_new_domain_nr(); we should also update use_dt_domains to | |
6141 | * 1, to indicate that we have just assigned a domain number from | |
6142 | * DT. | |
6143 | * | |
6144 | * If DT domain property value is not valid (ie domain < 0), and we | |
6145 | * have not previously assigned a domain number from DT | |
6146 | * (use_dt_domains != 1) we should assign a domain number by | |
6147 | * using the: | |
6148 | * | |
6149 | * pci_get_new_domain_nr() | |
6150 | * | |
6151 | * API and update the use_dt_domains value to keep track of method we | |
6152 | * are using to assign domain numbers (use_dt_domains = 0). | |
6153 | * | |
6154 | * All other combinations imply we have a platform that is trying | |
6155 | * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), | |
6156 | * which is a recipe for domain mishandling and it is prevented by | |
6157 | * invalidating the domain value (domain = -1) and printing a | |
6158 | * corresponding error. | |
6159 | */ | |
6160 | if (domain >= 0 && use_dt_domains) { | |
6161 | use_dt_domains = 1; | |
6162 | } else if (domain < 0 && use_dt_domains != 1) { | |
6163 | use_dt_domains = 0; | |
6164 | domain = pci_get_new_domain_nr(); | |
6165 | } else { | |
9df1c6ec SL |
6166 | if (parent) |
6167 | pr_err("Node %pOF has ", parent->of_node); | |
6168 | pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); | |
7c674700 LP |
6169 | domain = -1; |
6170 | } | |
6171 | ||
9c7cb891 | 6172 | return domain; |
7c674700 | 6173 | } |
1a4f93f7 TN |
6174 | |
6175 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) | |
6176 | { | |
2ab51dde TN |
6177 | return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : |
6178 | acpi_pci_bus_find_domain_nr(bus); | |
7c674700 LP |
6179 | } |
6180 | #endif | |
41e5c0f8 | 6181 | |
0ef5f8f6 | 6182 | /** |
642c92da | 6183 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
6184 | * |
6185 | * Returns 1 if we can access PCI extended config space (offsets | |
6186 | * greater than 0xff). This is the default implementation. Architecture | |
6187 | * implementations can override this. | |
6188 | */ | |
642c92da | 6189 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
6190 | { |
6191 | return 1; | |
6192 | } | |
6193 | ||
2d1c8618 BH |
6194 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
6195 | { | |
6196 | } | |
6197 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
6198 | ||
ad04d31e | 6199 | static int __init pci_setup(char *str) |
1da177e4 LT |
6200 | { |
6201 | while (str) { | |
6202 | char *k = strchr(str, ','); | |
6203 | if (k) | |
6204 | *k++ = 0; | |
6205 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
6206 | if (!strcmp(str, "nomsi")) { |
6207 | pci_no_msi(); | |
cef74409 GK |
6208 | } else if (!strncmp(str, "noats", 5)) { |
6209 | pr_info("PCIe: ATS is disabled\n"); | |
6210 | pcie_ats_disabled = true; | |
7f785763 RD |
6211 | } else if (!strcmp(str, "noaer")) { |
6212 | pci_no_aer(); | |
11eb0e0e SK |
6213 | } else if (!strcmp(str, "earlydump")) { |
6214 | pci_early_dump = true; | |
b55438fd YL |
6215 | } else if (!strncmp(str, "realloc=", 8)) { |
6216 | pci_realloc_get_opt(str + 8); | |
f483d392 | 6217 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 6218 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
6219 | } else if (!strcmp(str, "nodomains")) { |
6220 | pci_no_domains(); | |
6748dcc2 RW |
6221 | } else if (!strncmp(str, "noari", 5)) { |
6222 | pcie_ari_disabled = true; | |
4516a618 AN |
6223 | } else if (!strncmp(str, "cbiosize=", 9)) { |
6224 | pci_cardbus_io_size = memparse(str + 9, &str); | |
6225 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
6226 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
6227 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
6228 | pci_set_resource_alignment_param(str + 19, | |
6229 | strlen(str + 19)); | |
43c16408 AP |
6230 | } else if (!strncmp(str, "ecrc=", 5)) { |
6231 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
6232 | } else if (!strncmp(str, "hpiosize=", 9)) { |
6233 | pci_hotplug_io_size = memparse(str + 9, &str); | |
6234 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
6235 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
e16b4660 KB |
6236 | } else if (!strncmp(str, "hpbussize=", 10)) { |
6237 | pci_hotplug_bus_size = | |
6238 | simple_strtoul(str + 10, &str, 0); | |
6239 | if (pci_hotplug_bus_size > 0xff) | |
6240 | pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
5f39e670 JM |
6241 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
6242 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
6243 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
6244 | pcie_bus_config = PCIE_BUS_SAFE; | |
6245 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
6246 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
6247 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
6248 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
6249 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
6250 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
aaca43fd | 6251 | } else if (!strncmp(str, "disable_acs_redir=", 18)) { |
d5bc73f3 | 6252 | disable_acs_redir_param = str + 18; |
309e57df | 6253 | } else { |
25da8dba | 6254 | pr_err("PCI: Unknown option `%s'\n", str); |
309e57df | 6255 | } |
1da177e4 LT |
6256 | } |
6257 | str = k; | |
6258 | } | |
0637a70a | 6259 | return 0; |
1da177e4 | 6260 | } |
0637a70a | 6261 | early_param("pci", pci_setup); |
d5bc73f3 LG |
6262 | |
6263 | /* | |
6264 | * 'disable_acs_redir_param' is initialized in pci_setup(), above, to point | |
6265 | * to data in the __initdata section which will be freed after the init | |
6266 | * sequence is complete. We can't allocate memory in pci_setup() because some | |
6267 | * architectures do not have any memory allocation service available during | |
6268 | * an early_param() call. So we allocate memory and copy the variable here | |
6269 | * before the init section is freed. | |
6270 | */ | |
6271 | static int __init pci_realloc_setup_params(void) | |
6272 | { | |
6273 | disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL); | |
6274 | ||
6275 | return 0; | |
6276 | } | |
6277 | pure_initcall(pci_realloc_setup_params); |