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23a5fba4 TP |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (C) 2018 Marvell | |
4 | * | |
5 | * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com> | |
6 | * | |
7 | * This file helps PCI controller drivers implement a fake root port | |
8 | * PCI bridge when the HW doesn't provide such a root port PCI | |
9 | * bridge. | |
10 | * | |
11 | * It emulates a PCI bridge by providing a fake PCI configuration | |
12 | * space (and optionally a PCIe capability configuration space) in | |
13 | * memory. By default the read/write operations simply read and update | |
14 | * this fake configuration space in memory. However, PCI controller | |
15 | * drivers can provide through the 'struct pci_sw_bridge_ops' | |
16 | * structure a set of operations to override or complement this | |
17 | * default behavior. | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include "pci-bridge-emul.h" | |
22 | ||
23 | #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF | |
3767a902 | 24 | #define PCI_CAP_SSID_SIZEOF (PCI_SSVID_DEVICE_ID + 2) |
f8ee579d | 25 | #define PCI_CAP_PCIE_SIZEOF (PCI_EXP_SLTSTA2 + 2) |
23a5fba4 | 26 | |
1446978d JD |
27 | /** |
28 | * struct pci_bridge_reg_behavior - register bits behaviors | |
29 | * @ro: Read-Only bits | |
30 | * @rw: Read-Write bits | |
31 | * @w1c: Write-1-to-Clear bits | |
32 | * | |
33 | * Reads and Writes will be filtered by specified behavior. All other bits not | |
34 | * declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0: | |
35 | * "Reserved register fields must be read only and must return 0 (all 0's for | |
36 | * multi-bit fields) when read". | |
37 | */ | |
23a5fba4 TP |
38 | struct pci_bridge_reg_behavior { |
39 | /* Read-only bits */ | |
40 | u32 ro; | |
41 | ||
42 | /* Read-write bits */ | |
43 | u32 rw; | |
44 | ||
45 | /* Write-1-to-clear bits */ | |
46 | u32 w1c; | |
23a5fba4 TP |
47 | }; |
48 | ||
f8ee579d RK |
49 | static const |
50 | struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = { | |
23a5fba4 TP |
51 | [PCI_VENDOR_ID / 4] = { .ro = ~0 }, |
52 | [PCI_COMMAND / 4] = { | |
53 | .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
54 | PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | | |
55 | PCI_COMMAND_SERR), | |
56 | .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | | |
57 | PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT | | |
58 | PCI_COMMAND_FAST_BACK) | | |
59 | (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ | | |
60 | PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16), | |
75e1fd42 | 61 | .w1c = PCI_STATUS_ERROR_BITS << 16, |
23a5fba4 TP |
62 | }, |
63 | [PCI_CLASS_REVISION / 4] = { .ro = ~0 }, | |
64 | ||
65 | /* | |
66 | * Cache Line Size register: implement as read-only, we do not | |
67 | * pretend implementing "Memory Write and Invalidate" | |
68 | * transactions" | |
69 | * | |
70 | * Latency Timer Register: implemented as read-only, as "A | |
71 | * bridge that is not capable of a burst transfer of more than | |
72 | * two data phases on its primary interface is permitted to | |
73 | * hardwire the Latency Timer to a value of 16 or less" | |
74 | * | |
75 | * Header Type: always read-only | |
76 | * | |
77 | * BIST register: implemented as read-only, as "A bridge that | |
78 | * does not support BIST must implement this register as a | |
79 | * read-only register that returns 0 when read" | |
80 | */ | |
81 | [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 }, | |
82 | ||
83 | /* | |
84 | * Base Address registers not used must be implemented as | |
85 | * read-only registers that return 0 when read. | |
86 | */ | |
87 | [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 }, | |
88 | [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 }, | |
89 | ||
90 | [PCI_PRIMARY_BUS / 4] = { | |
91 | /* Primary, secondary and subordinate bus are RW */ | |
92 | .rw = GENMASK(24, 0), | |
93 | /* Secondary latency is read-only */ | |
94 | .ro = GENMASK(31, 24), | |
95 | }, | |
96 | ||
97 | [PCI_IO_BASE / 4] = { | |
98 | /* The high four bits of I/O base/limit are RW */ | |
99 | .rw = (GENMASK(15, 12) | GENMASK(7, 4)), | |
100 | ||
101 | /* The low four bits of I/O base/limit are RO */ | |
102 | .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | | |
103 | PCI_STATUS_DEVSEL_MASK) << 16) | | |
104 | GENMASK(11, 8) | GENMASK(3, 0)), | |
105 | ||
75e1fd42 | 106 | .w1c = PCI_STATUS_ERROR_BITS << 16, |
23a5fba4 TP |
107 | }, |
108 | ||
109 | [PCI_MEMORY_BASE / 4] = { | |
110 | /* The high 12-bits of mem base/limit are RW */ | |
111 | .rw = GENMASK(31, 20) | GENMASK(15, 4), | |
112 | ||
113 | /* The low four bits of mem base/limit are RO */ | |
114 | .ro = GENMASK(19, 16) | GENMASK(3, 0), | |
115 | }, | |
116 | ||
117 | [PCI_PREF_MEMORY_BASE / 4] = { | |
118 | /* The high 12-bits of pref mem base/limit are RW */ | |
119 | .rw = GENMASK(31, 20) | GENMASK(15, 4), | |
120 | ||
121 | /* The low four bits of pref mem base/limit are RO */ | |
122 | .ro = GENMASK(19, 16) | GENMASK(3, 0), | |
123 | }, | |
124 | ||
125 | [PCI_PREF_BASE_UPPER32 / 4] = { | |
126 | .rw = ~0, | |
127 | }, | |
128 | ||
129 | [PCI_PREF_LIMIT_UPPER32 / 4] = { | |
130 | .rw = ~0, | |
131 | }, | |
132 | ||
133 | [PCI_IO_BASE_UPPER16 / 4] = { | |
134 | .rw = ~0, | |
135 | }, | |
136 | ||
137 | [PCI_CAPABILITY_LIST / 4] = { | |
138 | .ro = GENMASK(7, 0), | |
23a5fba4 TP |
139 | }, |
140 | ||
1c1a3b4d PR |
141 | /* |
142 | * If expansion ROM is unsupported then ROM Base Address register must | |
143 | * be implemented as read-only register that return 0 when read, same | |
144 | * as for unused Base Address registers. | |
145 | */ | |
23a5fba4 | 146 | [PCI_ROM_ADDRESS1 / 4] = { |
1c1a3b4d | 147 | .ro = ~0, |
23a5fba4 TP |
148 | }, |
149 | ||
150 | /* | |
151 | * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8) | |
152 | * are RO, and bridge control (31:16) are a mix of RW, RO, | |
153 | * reserved and W1C bits | |
154 | */ | |
155 | [PCI_INTERRUPT_LINE / 4] = { | |
156 | /* Interrupt line is RW */ | |
157 | .rw = (GENMASK(7, 0) | | |
158 | ((PCI_BRIDGE_CTL_PARITY | | |
159 | PCI_BRIDGE_CTL_SERR | | |
160 | PCI_BRIDGE_CTL_ISA | | |
161 | PCI_BRIDGE_CTL_VGA | | |
162 | PCI_BRIDGE_CTL_MASTER_ABORT | | |
163 | PCI_BRIDGE_CTL_BUS_RESET | | |
164 | BIT(8) | BIT(9) | BIT(11)) << 16)), | |
165 | ||
166 | /* Interrupt pin is RO */ | |
167 | .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)), | |
168 | ||
169 | .w1c = BIT(10) << 16, | |
23a5fba4 TP |
170 | }, |
171 | }; | |
172 | ||
f8ee579d RK |
173 | static const |
174 | struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = { | |
23a5fba4 TP |
175 | [PCI_CAP_LIST_ID / 4] = { |
176 | /* | |
177 | * Capability ID, Next Capability Pointer and | |
12998087 PR |
178 | * bits [14:0] of Capabilities register are all read-only. |
179 | * Bit 15 of Capabilities register is reserved. | |
23a5fba4 | 180 | */ |
12998087 | 181 | .ro = GENMASK(30, 0), |
23a5fba4 TP |
182 | }, |
183 | ||
184 | [PCI_EXP_DEVCAP / 4] = { | |
12998087 PR |
185 | /* |
186 | * Bits [31:29] and [17:16] are reserved. | |
187 | * Bits [27:18] are reserved for non-upstream ports. | |
188 | * Bits 28 and [14:6] are reserved for non-endpoint devices. | |
189 | * Other bits are read-only. | |
190 | */ | |
191 | .ro = BIT(15) | GENMASK(5, 0), | |
23a5fba4 TP |
192 | }, |
193 | ||
194 | [PCI_EXP_DEVCTL / 4] = { | |
12998087 PR |
195 | /* |
196 | * Device control register is RW, except bit 15 which is | |
197 | * reserved for non-endpoints or non-PCIe-to-PCI/X bridges. | |
198 | */ | |
199 | .rw = GENMASK(14, 0), | |
23a5fba4 TP |
200 | |
201 | /* | |
29608651 | 202 | * Device status register has bits 6 and [3:0] W1C, [5:4] RO, |
12998087 PR |
203 | * the rest is reserved. Also bit 6 is reserved for non-upstream |
204 | * ports. | |
23a5fba4 | 205 | */ |
12998087 | 206 | .w1c = GENMASK(3, 0) << 16, |
29608651 | 207 | .ro = GENMASK(5, 4) << 16, |
23a5fba4 TP |
208 | }, |
209 | ||
210 | [PCI_EXP_LNKCAP / 4] = { | |
12998087 PR |
211 | /* |
212 | * All bits are RO, except bit 23 which is reserved and | |
213 | * bit 18 which is reserved for non-upstream ports. | |
214 | */ | |
215 | .ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)), | |
23a5fba4 TP |
216 | }, |
217 | ||
218 | [PCI_EXP_LNKCTL / 4] = { | |
219 | /* | |
29608651 | 220 | * Link control has bits [15:14], [11:3] and [1:0] RW, the |
12998087 | 221 | * rest is reserved. Bit 8 is reserved for non-upstream ports. |
29608651 JD |
222 | * |
223 | * Link status has bits [13:0] RO, and bits [15:14] | |
23a5fba4 TP |
224 | * W1C. |
225 | */ | |
12998087 | 226 | .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0), |
23a5fba4 TP |
227 | .ro = GENMASK(13, 0) << 16, |
228 | .w1c = GENMASK(15, 14) << 16, | |
23a5fba4 TP |
229 | }, |
230 | ||
231 | [PCI_EXP_SLTCAP / 4] = { | |
232 | .ro = ~0, | |
233 | }, | |
234 | ||
235 | [PCI_EXP_SLTCTL / 4] = { | |
236 | /* | |
29608651 | 237 | * Slot control has bits [14:0] RW, the rest is |
23a5fba4 TP |
238 | * reserved. |
239 | * | |
29608651 JD |
240 | * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the |
241 | * rest is reserved. | |
23a5fba4 | 242 | */ |
29608651 | 243 | .rw = GENMASK(14, 0), |
23a5fba4 TP |
244 | .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
245 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
246 | PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16, | |
247 | .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS | | |
248 | PCI_EXP_SLTSTA_EIS) << 16, | |
23a5fba4 TP |
249 | }, |
250 | ||
251 | [PCI_EXP_RTCTL / 4] = { | |
252 | /* | |
253 | * Root control has bits [4:0] RW, the rest is | |
254 | * reserved. | |
255 | * | |
f61959b6 | 256 | * Root capabilities has bit 0 RO, the rest is reserved. |
23a5fba4 TP |
257 | */ |
258 | .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | | |
259 | PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE | | |
87f10faf BH |
260 | PCI_EXP_RTCTL_RRS_SVE), |
261 | .ro = PCI_EXP_RTCAP_RRS_SV << 16, | |
23a5fba4 TP |
262 | }, |
263 | ||
264 | [PCI_EXP_RTSTA / 4] = { | |
f61959b6 JD |
265 | /* |
266 | * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest | |
267 | * is reserved. | |
268 | */ | |
23a5fba4 TP |
269 | .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING, |
270 | .w1c = PCI_EXP_RTSTA_PME, | |
23a5fba4 | 271 | }, |
8ea673a8 PR |
272 | |
273 | [PCI_EXP_DEVCAP2 / 4] = { | |
274 | /* | |
275 | * Device capabilities 2 register has reserved bits [30:27]. | |
276 | * Also bits [26:24] are reserved for non-upstream ports. | |
277 | */ | |
278 | .ro = BIT(31) | GENMASK(23, 0), | |
279 | }, | |
280 | ||
281 | [PCI_EXP_DEVCTL2 / 4] = { | |
282 | /* | |
283 | * Device control 2 register is RW. Bit 11 is reserved for | |
284 | * non-upstream ports. | |
285 | * | |
286 | * Device status 2 register is reserved. | |
287 | */ | |
288 | .rw = GENMASK(15, 12) | GENMASK(10, 0), | |
289 | }, | |
290 | ||
291 | [PCI_EXP_LNKCAP2 / 4] = { | |
292 | /* Link capabilities 2 register has reserved bits [30:25] and 0. */ | |
293 | .ro = BIT(31) | GENMASK(24, 1), | |
294 | }, | |
295 | ||
296 | [PCI_EXP_LNKCTL2 / 4] = { | |
297 | /* | |
298 | * Link control 2 register is RW. | |
299 | * | |
300 | * Link status 2 register has bits 5, 15 W1C; | |
301 | * bits 10, 11 reserved and others are RO. | |
302 | */ | |
303 | .rw = GENMASK(15, 0), | |
304 | .w1c = (BIT(15) | BIT(5)) << 16, | |
305 | .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16, | |
306 | }, | |
307 | ||
308 | [PCI_EXP_SLTCAP2 / 4] = { | |
309 | /* Slot capabilities 2 register is reserved. */ | |
310 | }, | |
311 | ||
312 | [PCI_EXP_SLTCTL2 / 4] = { | |
313 | /* Both Slot control 2 and Slot status 2 registers are reserved. */ | |
314 | }, | |
23a5fba4 TP |
315 | }; |
316 | ||
3767a902 PR |
317 | static pci_bridge_emul_read_status_t |
318 | pci_bridge_emul_read_ssid(struct pci_bridge_emul *bridge, int reg, u32 *value) | |
319 | { | |
320 | switch (reg) { | |
321 | case PCI_CAP_LIST_ID: | |
322 | *value = PCI_CAP_ID_SSVID | | |
658aea35 | 323 | ((bridge->pcie_start > bridge->ssid_start) ? (bridge->pcie_start << 8) : 0); |
3767a902 PR |
324 | return PCI_BRIDGE_EMUL_HANDLED; |
325 | ||
326 | case PCI_SSVID_VENDOR_ID: | |
327 | *value = bridge->subsystem_vendor_id | | |
328 | (bridge->subsystem_id << 16); | |
329 | return PCI_BRIDGE_EMUL_HANDLED; | |
330 | ||
331 | default: | |
332 | return PCI_BRIDGE_EMUL_NOT_HANDLED; | |
333 | } | |
334 | } | |
335 | ||
59f81c35 TP |
336 | /* |
337 | * Initialize a pci_bridge_emul structure to represent a fake PCI | |
338 | * bridge configuration space. The caller needs to have initialized | |
339 | * the PCI configuration space with whatever values make sense | |
340 | * (typically at least vendor, device, revision), the ->ops pointer, | |
341 | * and optionally ->data and ->has_pcie. | |
342 | */ | |
33776d05 TP |
343 | int pci_bridge_emul_init(struct pci_bridge_emul *bridge, |
344 | unsigned int flags) | |
59f81c35 | 345 | { |
f8ee579d RK |
346 | BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END); |
347 | ||
9319230a | 348 | /* |
904b10fb PR |
349 | * class_revision: Class is high 24 bits and revision is low 8 bit |
350 | * of this member, while class for PCI Bridge Normal Decode has the | |
351 | * 24-bit value: PCI_CLASS_BRIDGE_PCI_NORMAL | |
9319230a | 352 | */ |
904b10fb PR |
353 | bridge->conf.class_revision |= |
354 | cpu_to_le32(PCI_CLASS_BRIDGE_PCI_NORMAL << 8); | |
59f81c35 TP |
355 | bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE; |
356 | bridge->conf.cache_line_size = 0x10; | |
e0d9d30b | 357 | bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST); |
59f81c35 TP |
358 | bridge->pci_regs_behavior = kmemdup(pci_regs_behavior, |
359 | sizeof(pci_regs_behavior), | |
360 | GFP_KERNEL); | |
361 | if (!bridge->pci_regs_behavior) | |
362 | return -ENOMEM; | |
363 | ||
658aea35 PR |
364 | /* If ssid_start and pcie_start were not specified then choose the lowest possible value. */ |
365 | if (!bridge->ssid_start && !bridge->pcie_start) { | |
366 | if (bridge->subsystem_vendor_id) | |
367 | bridge->ssid_start = PCI_BRIDGE_CONF_END; | |
368 | if (bridge->has_pcie) | |
369 | bridge->pcie_start = bridge->ssid_start + PCI_CAP_SSID_SIZEOF; | |
370 | } else if (!bridge->ssid_start && bridge->subsystem_vendor_id) { | |
371 | if (bridge->pcie_start - PCI_BRIDGE_CONF_END >= PCI_CAP_SSID_SIZEOF) | |
372 | bridge->ssid_start = PCI_BRIDGE_CONF_END; | |
373 | else | |
374 | bridge->ssid_start = bridge->pcie_start + PCI_CAP_PCIE_SIZEOF; | |
375 | } else if (!bridge->pcie_start && bridge->has_pcie) { | |
376 | if (bridge->ssid_start - PCI_BRIDGE_CONF_END >= PCI_CAP_PCIE_SIZEOF) | |
377 | bridge->pcie_start = PCI_BRIDGE_CONF_END; | |
378 | else | |
379 | bridge->pcie_start = bridge->ssid_start + PCI_CAP_SSID_SIZEOF; | |
380 | } | |
381 | ||
382 | bridge->conf.capabilities_pointer = min(bridge->ssid_start, bridge->pcie_start); | |
3767a902 PR |
383 | |
384 | if (bridge->conf.capabilities_pointer) | |
3be9d243 | 385 | bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST); |
3767a902 PR |
386 | |
387 | if (bridge->has_pcie) { | |
59f81c35 | 388 | bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP; |
658aea35 PR |
389 | bridge->pcie_conf.next = (bridge->ssid_start > bridge->pcie_start) ? |
390 | bridge->ssid_start : 0; | |
1f1050c5 | 391 | bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4); |
59f81c35 TP |
392 | bridge->pcie_cap_regs_behavior = |
393 | kmemdup(pcie_cap_regs_behavior, | |
394 | sizeof(pcie_cap_regs_behavior), | |
395 | GFP_KERNEL); | |
396 | if (!bridge->pcie_cap_regs_behavior) { | |
397 | kfree(bridge->pci_regs_behavior); | |
398 | return -ENOMEM; | |
399 | } | |
7b067ac6 PR |
400 | /* These bits are applicable only for PCI and reserved on PCIe */ |
401 | bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &= | |
402 | ~GENMASK(15, 8); | |
403 | bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &= | |
404 | ~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | | |
405 | PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT | | |
406 | PCI_COMMAND_FAST_BACK) | | |
407 | (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | | |
408 | PCI_STATUS_DEVSEL_MASK) << 16); | |
409 | bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &= | |
410 | ~GENMASK(31, 24); | |
411 | bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &= | |
412 | ~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | | |
413 | PCI_STATUS_DEVSEL_MASK) << 16); | |
414 | bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &= | |
415 | ~((PCI_BRIDGE_CTL_MASTER_ABORT | | |
416 | BIT(8) | BIT(9) | BIT(11)) << 16); | |
417 | bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &= | |
418 | ~((PCI_BRIDGE_CTL_FAST_BACK) << 16); | |
419 | bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &= | |
420 | ~(BIT(10) << 16); | |
59f81c35 TP |
421 | } |
422 | ||
d3f332b5 | 423 | if (flags & PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD) { |
33776d05 TP |
424 | bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0; |
425 | bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0; | |
426 | } | |
427 | ||
05241c13 PR |
428 | if (flags & PCI_BRIDGE_EMUL_NO_IO_FORWARD) { |
429 | bridge->pci_regs_behavior[PCI_COMMAND / 4].ro |= PCI_COMMAND_IO; | |
430 | bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO; | |
431 | bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro |= GENMASK(15, 0); | |
432 | bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0); | |
433 | bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].ro = ~0; | |
434 | bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].rw = 0; | |
435 | } | |
436 | ||
59f81c35 TP |
437 | return 0; |
438 | } | |
d39ff8ee | 439 | EXPORT_SYMBOL_GPL(pci_bridge_emul_init); |
59f81c35 TP |
440 | |
441 | /* | |
f6b6aefe | 442 | * Cleanup a pci_bridge_emul structure that was previously initialized |
59f81c35 TP |
443 | * using pci_bridge_emul_init(). |
444 | */ | |
445 | void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge) | |
446 | { | |
447 | if (bridge->has_pcie) | |
448 | kfree(bridge->pcie_cap_regs_behavior); | |
449 | kfree(bridge->pci_regs_behavior); | |
450 | } | |
d39ff8ee | 451 | EXPORT_SYMBOL_GPL(pci_bridge_emul_cleanup); |
59f81c35 | 452 | |
23a5fba4 TP |
453 | /* |
454 | * Should be called by the PCI controller driver when reading the PCI | |
455 | * configuration space of the fake bridge. It will call back the | |
456 | * ->ops->read_base or ->ops->read_pcie operations. | |
457 | */ | |
458 | int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where, | |
459 | int size, u32 *value) | |
460 | { | |
461 | int ret; | |
462 | int reg = where & ~3; | |
463 | pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge, | |
464 | int reg, u32 *value); | |
e0d9d30b | 465 | __le32 *cfgspace; |
23a5fba4 TP |
466 | const struct pci_bridge_reg_behavior *behavior; |
467 | ||
c453bf6f RK |
468 | if (reg < PCI_BRIDGE_CONF_END) { |
469 | /* Emulated PCI space */ | |
470 | read_op = bridge->ops->read_base; | |
471 | cfgspace = (__le32 *) &bridge->conf; | |
472 | behavior = bridge->pci_regs_behavior; | |
658aea35 PR |
473 | } else if (reg >= bridge->ssid_start && reg < bridge->ssid_start + PCI_CAP_SSID_SIZEOF && |
474 | bridge->subsystem_vendor_id) { | |
3767a902 | 475 | /* Emulated PCI Bridge Subsystem Vendor ID capability */ |
658aea35 | 476 | reg -= bridge->ssid_start; |
3767a902 PR |
477 | read_op = pci_bridge_emul_read_ssid; |
478 | cfgspace = NULL; | |
479 | behavior = NULL; | |
658aea35 PR |
480 | } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF && |
481 | bridge->has_pcie) { | |
c453bf6f | 482 | /* Our emulated PCIe capability */ |
658aea35 | 483 | reg -= bridge->pcie_start; |
23a5fba4 | 484 | read_op = bridge->ops->read_pcie; |
e0d9d30b | 485 | cfgspace = (__le32 *) &bridge->pcie_conf; |
59f81c35 | 486 | behavior = bridge->pcie_cap_regs_behavior; |
3767a902 | 487 | } else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) { |
c0bd4197 RK |
488 | /* PCIe extended capability space */ |
489 | reg -= PCI_CFG_SPACE_SIZE; | |
490 | read_op = bridge->ops->read_ext; | |
491 | cfgspace = NULL; | |
492 | behavior = NULL; | |
23a5fba4 | 493 | } else { |
3767a902 PR |
494 | /* Not implemented */ |
495 | *value = 0; | |
496 | return PCIBIOS_SUCCESSFUL; | |
23a5fba4 TP |
497 | } |
498 | ||
499 | if (read_op) | |
500 | ret = read_op(bridge, reg, value); | |
501 | else | |
502 | ret = PCI_BRIDGE_EMUL_NOT_HANDLED; | |
503 | ||
c0bd4197 RK |
504 | if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) { |
505 | if (cfgspace) | |
506 | *value = le32_to_cpu(cfgspace[reg / 4]); | |
507 | else | |
508 | *value = 0; | |
509 | } | |
23a5fba4 TP |
510 | |
511 | /* | |
512 | * Make sure we never return any reserved bit with a value | |
513 | * different from 0. | |
514 | */ | |
c0bd4197 RK |
515 | if (behavior) |
516 | *value &= behavior[reg / 4].ro | behavior[reg / 4].rw | | |
517 | behavior[reg / 4].w1c; | |
23a5fba4 TP |
518 | |
519 | if (size == 1) | |
520 | *value = (*value >> (8 * (where & 3))) & 0xff; | |
521 | else if (size == 2) | |
522 | *value = (*value >> (8 * (where & 3))) & 0xffff; | |
523 | else if (size != 4) | |
524 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
525 | ||
526 | return PCIBIOS_SUCCESSFUL; | |
527 | } | |
d39ff8ee | 528 | EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_read); |
23a5fba4 TP |
529 | |
530 | /* | |
531 | * Should be called by the PCI controller driver when writing the PCI | |
532 | * configuration space of the fake bridge. It will call back the | |
533 | * ->ops->write_base or ->ops->write_pcie operations. | |
534 | */ | |
535 | int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where, | |
536 | int size, u32 value) | |
537 | { | |
538 | int reg = where & ~3; | |
539 | int mask, ret, old, new, shift; | |
540 | void (*write_op)(struct pci_bridge_emul *bridge, int reg, | |
541 | u32 old, u32 new, u32 mask); | |
e0d9d30b | 542 | __le32 *cfgspace; |
23a5fba4 TP |
543 | const struct pci_bridge_reg_behavior *behavior; |
544 | ||
c453bf6f RK |
545 | ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old); |
546 | if (ret != PCIBIOS_SUCCESSFUL) | |
547 | return ret; | |
23a5fba4 | 548 | |
c453bf6f RK |
549 | if (reg < PCI_BRIDGE_CONF_END) { |
550 | /* Emulated PCI space */ | |
551 | write_op = bridge->ops->write_base; | |
552 | cfgspace = (__le32 *) &bridge->conf; | |
553 | behavior = bridge->pci_regs_behavior; | |
658aea35 PR |
554 | } else if (reg >= bridge->pcie_start && reg < bridge->pcie_start + PCI_CAP_PCIE_SIZEOF && |
555 | bridge->has_pcie) { | |
c453bf6f | 556 | /* Our emulated PCIe capability */ |
658aea35 | 557 | reg -= bridge->pcie_start; |
c453bf6f RK |
558 | write_op = bridge->ops->write_pcie; |
559 | cfgspace = (__le32 *) &bridge->pcie_conf; | |
560 | behavior = bridge->pcie_cap_regs_behavior; | |
3767a902 | 561 | } else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) { |
c0bd4197 RK |
562 | /* PCIe extended capability space */ |
563 | reg -= PCI_CFG_SPACE_SIZE; | |
564 | write_op = bridge->ops->write_ext; | |
565 | cfgspace = NULL; | |
566 | behavior = NULL; | |
3767a902 PR |
567 | } else { |
568 | /* Not implemented */ | |
23a5fba4 | 569 | return PCIBIOS_SUCCESSFUL; |
c453bf6f | 570 | } |
23a5fba4 TP |
571 | |
572 | shift = (where & 0x3) * 8; | |
573 | ||
574 | if (size == 4) | |
575 | mask = 0xffffffff; | |
576 | else if (size == 2) | |
577 | mask = 0xffff << shift; | |
578 | else if (size == 1) | |
579 | mask = 0xff << shift; | |
580 | else | |
581 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
582 | ||
c0bd4197 RK |
583 | if (behavior) { |
584 | /* Keep all bits, except the RW bits */ | |
585 | new = old & (~mask | ~behavior[reg / 4].rw); | |
23a5fba4 | 586 | |
c0bd4197 RK |
587 | /* Update the value of the RW bits */ |
588 | new |= (value << shift) & (behavior[reg / 4].rw & mask); | |
23a5fba4 | 589 | |
c0bd4197 RK |
590 | /* Clear the W1C bits */ |
591 | new &= ~((value << shift) & (behavior[reg / 4].w1c & mask)); | |
23a5fba4 | 592 | } else { |
c0bd4197 RK |
593 | new = old & ~mask; |
594 | new |= (value << shift) & mask; | |
23a5fba4 TP |
595 | } |
596 | ||
c0bd4197 RK |
597 | if (cfgspace) { |
598 | /* Save the new value with the cleared W1C bits into the cfgspace */ | |
599 | cfgspace[reg / 4] = cpu_to_le32(new); | |
600 | } | |
23a5fba4 | 601 | |
c0bd4197 RK |
602 | if (behavior) { |
603 | /* | |
604 | * Clear the W1C bits not specified by the write mask, so that the | |
605 | * write_op() does not clear them. | |
606 | */ | |
607 | new &= ~(behavior[reg / 4].w1c & ~mask); | |
7a41ae80 | 608 | |
c0bd4197 RK |
609 | /* |
610 | * Set the W1C bits specified by the write mask, so that write_op() | |
611 | * knows about that they are to be cleared. | |
612 | */ | |
613 | new |= (value << shift) & (behavior[reg / 4].w1c & mask); | |
614 | } | |
7a41ae80 | 615 | |
23a5fba4 TP |
616 | if (write_op) |
617 | write_op(bridge, reg, old, new, mask); | |
618 | ||
619 | return PCIBIOS_SUCCESSFUL; | |
620 | } | |
d39ff8ee | 621 | EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_write); |