[linux-block.git] / drivers / pci / of_property.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
 */

#include <linux/pci.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
#include "pci.h"

#define OF_PCI_ADDRESS_CELLS		3
#define OF_PCI_SIZE_CELLS		2
#define OF_PCI_MAX_INT_PIN		4

struct of_pci_addr_pair {
	u32		phys_addr[OF_PCI_ADDRESS_CELLS];
	u32		size[OF_PCI_SIZE_CELLS];
};

/*
 * Each entry in the ranges table is a tuple containing the child address,
 * the parent address, and the size of the region in the child address space.
 * Thus, for PCI, in each entry parent address is an address on the primary
 * side and the child address is the corresponding address on the secondary
 * side.
 */
struct of_pci_range {
	u32		child_addr[OF_PCI_ADDRESS_CELLS];
	u32		parent_addr[OF_PCI_ADDRESS_CELLS];
	u32		size[OF_PCI_SIZE_CELLS];
};

#define OF_PCI_ADDR_SPACE_IO		0x1
#define OF_PCI_ADDR_SPACE_MEM32		0x2
#define OF_PCI_ADDR_SPACE_MEM64		0x3

#define OF_PCI_ADDR_FIELD_NONRELOC	BIT(31)
#define OF_PCI_ADDR_FIELD_SS		GENMASK(25, 24)
#define OF_PCI_ADDR_FIELD_PREFETCH	BIT(30)
#define OF_PCI_ADDR_FIELD_BUS		GENMASK(23, 16)
#define OF_PCI_ADDR_FIELD_DEV		GENMASK(15, 11)
#define OF_PCI_ADDR_FIELD_FUNC		GENMASK(10, 8)
#define OF_PCI_ADDR_FIELD_REG		GENMASK(7, 0)

enum of_pci_prop_compatible {
	PROP_COMPAT_PCI_VVVV_DDDD,
	PROP_COMPAT_PCICLASS_CCSSPP,
	PROP_COMPAT_PCICLASS_CCSS,
	PROP_COMPAT_NUM,
};

static void of_pci_set_address(struct pci_dev *pdev, u32 *prop, u64 addr,
			       u32 reg_num, u32 flags, bool reloc)
{
	prop[0] = FIELD_PREP(OF_PCI_ADDR_FIELD_BUS, pdev->bus->number) |
		FIELD_PREP(OF_PCI_ADDR_FIELD_DEV, PCI_SLOT(pdev->devfn)) |
		FIELD_PREP(OF_PCI_ADDR_FIELD_FUNC, PCI_FUNC(pdev->devfn));
	prop[0] |= flags | reg_num;
	if (!reloc) {
		prop[0] |= OF_PCI_ADDR_FIELD_NONRELOC;
		prop[1] = upper_32_bits(addr);
		prop[2] = lower_32_bits(addr);
	}
}

static int of_pci_get_addr_flags(struct resource *res, u32 *flags)
{
	u32 ss;

	if (res->flags & IORESOURCE_IO)
		ss = OF_PCI_ADDR_SPACE_IO;
	else if (res->flags & IORESOURCE_MEM_64)
		ss = OF_PCI_ADDR_SPACE_MEM64;
	else if (res->flags & IORESOURCE_MEM)
		ss = OF_PCI_ADDR_SPACE_MEM32;
	else
		return -EINVAL;

	*flags = 0;
	if (res->flags & IORESOURCE_PREFETCH)
		*flags |= OF_PCI_ADDR_FIELD_PREFETCH;

	*flags |= FIELD_PREP(OF_PCI_ADDR_FIELD_SS, ss);

	return 0;
}

static int of_pci_prop_bus_range(struct pci_dev *pdev,
				 struct of_changeset *ocs,
				 struct device_node *np)
{
	u32 bus_range[] = { pdev->subordinate->busn_res.start,
			    pdev->subordinate->busn_res.end };

	return of_changeset_add_prop_u32_array(ocs, np, "bus-range", bus_range,
					       ARRAY_SIZE(bus_range));
}

static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs,
			      struct device_node *np)
{
	struct of_pci_range *rp;
	struct resource *res;
	int i, j, ret;
	u32 flags, num;
	u64 val64;

	if (pci_is_bridge(pdev)) {
		num = PCI_BRIDGE_RESOURCE_NUM;
		res = &pdev->resource[PCI_BRIDGE_RESOURCES];
	} else {
		num = PCI_STD_NUM_BARS;
		res = &pdev->resource[PCI_STD_RESOURCES];
	}

	rp = kcalloc(num, sizeof(*rp), GFP_KERNEL);
	if (!rp)
		return -ENOMEM;

	for (i = 0, j = 0; j < num; j++) {
		if (!resource_size(&res[j]))
			continue;

		if (of_pci_get_addr_flags(&res[j], &flags))
			continue;

		val64 = res[j].start;
		of_pci_set_address(pdev, rp[i].parent_addr, val64, 0, flags,
				   false);
		if (pci_is_bridge(pdev)) {
			memcpy(rp[i].child_addr, rp[i].parent_addr,
			       sizeof(rp[i].child_addr));
		} else {
			/*
			 * For endpoint device, the lower 64-bits of child
			 * address is always zero.
			 */
			rp[i].child_addr[0] = j;
		}

		val64 = resource_size(&res[j]);
		rp[i].size[0] = upper_32_bits(val64);
		rp[i].size[1] = lower_32_bits(val64);

		i++;
	}

	ret = of_changeset_add_prop_u32_array(ocs, np, "ranges", (u32 *)rp,
					      i * sizeof(*rp) / sizeof(u32));
	kfree(rp);

	return ret;
}

static int of_pci_prop_reg(struct pci_dev *pdev, struct of_changeset *ocs,
			   struct device_node *np)
{
	struct of_pci_addr_pair reg = { 0 };

	/* configuration space */
	of_pci_set_address(pdev, reg.phys_addr, 0, 0, 0, true);

	return of_changeset_add_prop_u32_array(ocs, np, "reg", (u32 *)&reg,
					       sizeof(reg) / sizeof(u32));
}

static int of_pci_prop_interrupts(struct pci_dev *pdev,
				  struct of_changeset *ocs,
				  struct device_node *np)
{
	int ret;
	u8 pin;

	ret = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
	if (ret != 0)
		return ret;

	if (!pin)
		return 0;

	return of_changeset_add_prop_u32(ocs, np, "interrupts", (u32)pin);
}

static int of_pci_prop_intr_map(struct pci_dev *pdev, struct of_changeset *ocs,
				struct device_node *np)
{
	struct of_phandle_args out_irq[OF_PCI_MAX_INT_PIN];
	u32 i, addr_sz[OF_PCI_MAX_INT_PIN], map_sz = 0;
	__be32 laddr[OF_PCI_ADDRESS_CELLS] = { 0 };
	u32 int_map_mask[] = { 0xffff00, 0, 0, 7 };
	struct device_node *pnode;
	struct pci_dev *child;
	u32 *int_map, *mapp;
	int ret;
	u8 pin;

	pnode = pci_device_to_OF_node(pdev->bus->self);
	if (!pnode)
		pnode = pci_bus_to_OF_node(pdev->bus);

	if (!pnode) {
		pci_err(pdev, "failed to get parent device node");
		return -EINVAL;
	}

	laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8));
	for (pin = 1; pin <= OF_PCI_MAX_INT_PIN;  pin++) {
		i = pin - 1;
		out_irq[i].np = pnode;
		out_irq[i].args_count = 1;
		out_irq[i].args[0] = pin;
		ret = of_irq_parse_raw(laddr, &out_irq[i]);
		if (ret) {
			pci_err(pdev, "parse irq %d failed, ret %d", pin, ret);
			continue;
		}
		ret = of_property_read_u32(out_irq[i].np, "#address-cells",
					   &addr_sz[i]);
		if (ret)
			addr_sz[i] = 0;
	}

	list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
		for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
			i = pci_swizzle_interrupt_pin(child, pin) - 1;
			map_sz += 5 + addr_sz[i] + out_irq[i].args_count;
		}
	}

	int_map = kcalloc(map_sz, sizeof(u32), GFP_KERNEL);
	mapp = int_map;

	list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
		for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
			*mapp = (child->bus->number << 16) |
				(child->devfn << 8);
			mapp += OF_PCI_ADDRESS_CELLS;
			*mapp = pin;
			mapp++;
			i = pci_swizzle_interrupt_pin(child, pin) - 1;
			*mapp = out_irq[i].np->phandle;
			mapp++;
			if (addr_sz[i]) {
				ret = of_property_read_u32_array(out_irq[i].np,
								 "reg", mapp,
								 addr_sz[i]);
				if (ret)
					goto failed;
			}
			mapp += addr_sz[i];
			memcpy(mapp, out_irq[i].args,
			       out_irq[i].args_count * sizeof(u32));
			mapp += out_irq[i].args_count;
		}
	}

	ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map", int_map,
					      map_sz);
	if (ret)
		goto failed;

	ret = of_changeset_add_prop_u32(ocs, np, "#interrupt-cells", 1);
	if (ret)
		goto failed;

	ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map-mask",
					      int_map_mask,
					      ARRAY_SIZE(int_map_mask));
	if (ret)
		goto failed;

	kfree(int_map);
	return 0;

failed:
	kfree(int_map);
	return ret;
}

static int of_pci_prop_compatible(struct pci_dev *pdev,
				  struct of_changeset *ocs,
				  struct device_node *np)
{
	const char *compat_strs[PROP_COMPAT_NUM] = { 0 };
	int i, ret;

	compat_strs[PROP_COMPAT_PCI_VVVV_DDDD] =
		kasprintf(GFP_KERNEL, "pci%x,%x", pdev->vendor, pdev->device);
	compat_strs[PROP_COMPAT_PCICLASS_CCSSPP] =
		kasprintf(GFP_KERNEL, "pciclass,%06x", pdev->class);
	compat_strs[PROP_COMPAT_PCICLASS_CCSS] =
		kasprintf(GFP_KERNEL, "pciclass,%04x", pdev->class >> 8);

	ret = of_changeset_add_prop_string_array(ocs, np, "compatible",
						 compat_strs, PROP_COMPAT_NUM);
	for (i = 0; i < PROP_COMPAT_NUM; i++)
		kfree(compat_strs[i]);

	return ret;
}

int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
			  struct device_node *np)
{
	int ret;

	/*
	 * The added properties will be released when the
	 * changeset is destroyed.
	 */
	if (pci_is_bridge(pdev)) {
		ret = of_changeset_add_prop_string(ocs, np, "device_type",
						   "pci");
		if (ret)
			return ret;

		ret = of_pci_prop_bus_range(pdev, ocs, np);
		if (ret)
			return ret;

		ret = of_pci_prop_intr_map(pdev, ocs, np);
		if (ret)
			return ret;
	}

	ret = of_pci_prop_ranges(pdev, ocs, np);
	if (ret)
		return ret;

	ret = of_changeset_add_prop_u32(ocs, np, "#address-cells",
					OF_PCI_ADDRESS_CELLS);
	if (ret)
		return ret;

	ret = of_changeset_add_prop_u32(ocs, np, "#size-cells",
					OF_PCI_SIZE_CELLS);
	if (ret)
		return ret;

	ret = of_pci_prop_reg(pdev, ocs, np);
	if (ret)
		return ret;

	ret = of_pci_prop_compatible(pdev, ocs, np);
	if (ret)
		return ret;

	ret = of_pci_prop_interrupts(pdev, ocs, np);
	if (ret)
		return ret;

	return 0;
}
Commit	Line	Data
407d1a51 LH	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
	4	*/
	5
	6	#include <linux/pci.h>
	7	#include <linux/of.h>
	8	#include <linux/of_irq.h>
	9	#include <linux/bitfield.h>
	10	#include <linux/bits.h>
	11	#include "pci.h"
	12
	13	#define OF_PCI_ADDRESS_CELLS 3
	14	#define OF_PCI_SIZE_CELLS 2
	15	#define OF_PCI_MAX_INT_PIN 4
	16
	17	struct of_pci_addr_pair {
	18	u32 phys_addr[OF_PCI_ADDRESS_CELLS];
	19	u32 size[OF_PCI_SIZE_CELLS];
	20	};
	21
	22	/*
	23	* Each entry in the ranges table is a tuple containing the child address,
	24	* the parent address, and the size of the region in the child address space.
	25	* Thus, for PCI, in each entry parent address is an address on the primary
	26	* side and the child address is the corresponding address on the secondary
	27	* side.
	28	*/
	29	struct of_pci_range {
	30	u32 child_addr[OF_PCI_ADDRESS_CELLS];
	31	u32 parent_addr[OF_PCI_ADDRESS_CELLS];
	32	u32 size[OF_PCI_SIZE_CELLS];
	33	};
	34
	35	#define OF_PCI_ADDR_SPACE_IO 0x1
	36	#define OF_PCI_ADDR_SPACE_MEM32 0x2
	37	#define OF_PCI_ADDR_SPACE_MEM64 0x3
	38
	39	#define OF_PCI_ADDR_FIELD_NONRELOC BIT(31)
	40	#define OF_PCI_ADDR_FIELD_SS GENMASK(25, 24)
	41	#define OF_PCI_ADDR_FIELD_PREFETCH BIT(30)
	42	#define OF_PCI_ADDR_FIELD_BUS GENMASK(23, 16)
	43	#define OF_PCI_ADDR_FIELD_DEV GENMASK(15, 11)
	44	#define OF_PCI_ADDR_FIELD_FUNC GENMASK(10, 8)
	45	#define OF_PCI_ADDR_FIELD_REG GENMASK(7, 0)
	46
	47	enum of_pci_prop_compatible {
	48	PROP_COMPAT_PCI_VVVV_DDDD,
	49	PROP_COMPAT_PCICLASS_CCSSPP,
	50	PROP_COMPAT_PCICLASS_CCSS,
	51	PROP_COMPAT_NUM,
	52	};
	53
	54	static void of_pci_set_address(struct pci_dev pdev, u32 prop, u64 addr,
	55	u32 reg_num, u32 flags, bool reloc)
	56	{
	57	prop[0] = FIELD_PREP(OF_PCI_ADDR_FIELD_BUS, pdev->bus->number) \|
	58	FIELD_PREP(OF_PCI_ADDR_FIELD_DEV, PCI_SLOT(pdev->devfn)) \|
	59	FIELD_PREP(OF_PCI_ADDR_FIELD_FUNC, PCI_FUNC(pdev->devfn));
	60	prop[0] \|= flags \| reg_num;
	61	if (!reloc) {
	62	prop[0] \|= OF_PCI_ADDR_FIELD_NONRELOC;
	63	prop[1] = upper_32_bits(addr);
	64	prop[2] = lower_32_bits(addr);
65	}
66	}
67
68	static int of_pci_get_addr_flags(struct resource res, u32 flags)
69	{
70	u32 ss;
71
72	if (res->flags & IORESOURCE_IO)
73	ss = OF_PCI_ADDR_SPACE_IO;
74	else if (res->flags & IORESOURCE_MEM_64)
75	ss = OF_PCI_ADDR_SPACE_MEM64;
76	else if (res->flags & IORESOURCE_MEM)
77	ss = OF_PCI_ADDR_SPACE_MEM32;
78	else
79	return -EINVAL;
80
81	*flags = 0;
82	if (res->flags & IORESOURCE_PREFETCH)
83	*flags \|= OF_PCI_ADDR_FIELD_PREFETCH;
84
85	*flags \|= FIELD_PREP(OF_PCI_ADDR_FIELD_SS, ss);
86
87	return 0;
88	}
89
90	static int of_pci_prop_bus_range(struct pci_dev *pdev,
91	struct of_changeset *ocs,
92	struct device_node *np)
93	{
94	u32 bus_range[] = { pdev->subordinate->busn_res.start,
95	pdev->subordinate->busn_res.end };
96
97	return of_changeset_add_prop_u32_array(ocs, np, "bus-range", bus_range,
98	ARRAY_SIZE(bus_range));
99	}
100
101	static int of_pci_prop_ranges(struct pci_dev pdev, struct of_changeset ocs,
102	struct device_node *np)
103	{
104	struct of_pci_range *rp;
105	struct resource *res;
106	int i, j, ret;
107	u32 flags, num;
108	u64 val64;
109
110	if (pci_is_bridge(pdev)) {
111	num = PCI_BRIDGE_RESOURCE_NUM;
112	res = &pdev->resource[PCI_BRIDGE_RESOURCES];
113	} else {
114	num = PCI_STD_NUM_BARS;
115	res = &pdev->resource[PCI_STD_RESOURCES];
116	}
117
118	rp = kcalloc(num, sizeof(*rp), GFP_KERNEL);
119	if (!rp)
120	return -ENOMEM;
121
122	for (i = 0, j = 0; j < num; j++) {
123	if (!resource_size(&res[j]))
124	continue;
125
126	if (of_pci_get_addr_flags(&res[j], &flags))
127	continue;
128
129	val64 = res[j].start;
130	of_pci_set_address(pdev, rp[i].parent_addr, val64, 0, flags,
131	false);
132	if (pci_is_bridge(pdev)) {
133	memcpy(rp[i].child_addr, rp[i].parent_addr,
134	sizeof(rp[i].child_addr));
135	} else {
136	/*
137	* For endpoint device, the lower 64-bits of child
138	* address is always zero.
139	*/
140	rp[i].child_addr[0] = j;
141	}
142
143	val64 = resource_size(&res[j]);
144	rp[i].size[0] = upper_32_bits(val64);
145	rp[i].size[1] = lower_32_bits(val64);
146
147	i++;
148	}
149
150	ret = of_changeset_add_prop_u32_array(ocs, np, "ranges", (u32 *)rp,
151	i * sizeof(*rp) / sizeof(u32));
152	kfree(rp);
153
154	return ret;
155	}
156
157	static int of_pci_prop_reg(struct pci_dev pdev, struct of_changeset ocs,
158	struct device_node *np)
159	{
160	struct of_pci_addr_pair reg = { 0 };
161
162	/* configuration space */
163	of_pci_set_address(pdev, reg.phys_addr, 0, 0, 0, true);
164
165	return of_changeset_add_prop_u32_array(ocs, np, "reg", (u32 *)&reg,
166	sizeof(reg) / sizeof(u32));
167	}
168
169	static int of_pci_prop_interrupts(struct pci_dev *pdev,
170	struct of_changeset *ocs,
171	struct device_node *np)
172	{
173	int ret;
174	u8 pin;
175
176	ret = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
177	if (ret != 0)
178	return ret;
179
180	if (!pin)
181	return 0;
182
183	return of_changeset_add_prop_u32(ocs, np, "interrupts", (u32)pin);
184	}
185
186	static int of_pci_prop_intr_map(struct pci_dev pdev, struct of_changeset ocs,
187	struct device_node *np)
188	{
189	struct of_phandle_args out_irq[OF_PCI_MAX_INT_PIN];
190	u32 i, addr_sz[OF_PCI_MAX_INT_PIN], map_sz = 0;
191	__be32 laddr[OF_PCI_ADDRESS_CELLS] = { 0 };
192	u32 int_map_mask[] = { 0xffff00, 0, 0, 7 };
193	struct device_node *pnode;
194	struct pci_dev *child;
195	u32 int_map, mapp;
196	int ret;
197	u8 pin;
198
199	pnode = pci_device_to_OF_node(pdev->bus->self);
200	if (!pnode)
201	pnode = pci_bus_to_OF_node(pdev->bus);
202
203	if (!pnode) {
204	pci_err(pdev, "failed to get parent device node");
205	return -EINVAL;
206	}
207
208	laddr[0] = cpu_to_be32((pdev->bus->number << 16) \| (pdev->devfn << 8));
209	for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
210	i = pin - 1;
211	out_irq[i].np = pnode;
212	out_irq[i].args_count = 1;
213	out_irq[i].args[0] = pin;
214	ret = of_irq_parse_raw(laddr, &out_irq[i]);
215	if (ret) {
216	pci_err(pdev, "parse irq %d failed, ret %d", pin, ret);
217	continue;
218	}
219	ret = of_property_read_u32(out_irq[i].np, "#address-cells",
220	&addr_sz[i]);
221	if (ret)
222	addr_sz[i] = 0;
223	}
224
225	list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
226	for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
227	i = pci_swizzle_interrupt_pin(child, pin) - 1;
228	map_sz += 5 + addr_sz[i] + out_irq[i].args_count;
229	}
230	}
231
232	int_map = kcalloc(map_sz, sizeof(u32), GFP_KERNEL);
233	mapp = int_map;
234
235	list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
236	for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
237	*mapp = (child->bus->number << 16) \|
238	(child->devfn << 8);
239	mapp += OF_PCI_ADDRESS_CELLS;
240	*mapp = pin;
241	mapp++;
242	i = pci_swizzle_interrupt_pin(child, pin) - 1;
243	*mapp = out_irq[i].np->phandle;
244	mapp++;
245	if (addr_sz[i]) {
246	ret = of_property_read_u32_array(out_irq[i].np,
247	"reg", mapp,
248	addr_sz[i]);
249	if (ret)
250	goto failed;
251	}
252	mapp += addr_sz[i];
253	memcpy(mapp, out_irq[i].args,
254	out_irq[i].args_count * sizeof(u32));
255	mapp += out_irq[i].args_count;
256	}
257	}
258
259	ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map", int_map,
260	map_sz);
261	if (ret)
262	goto failed;
263
264	ret = of_changeset_add_prop_u32(ocs, np, "#interrupt-cells", 1);
265	if (ret)
266	goto failed;
267
268	ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map-mask",
269	int_map_mask,
270	ARRAY_SIZE(int_map_mask));
271	if (ret)
272	goto failed;
273
274	kfree(int_map);
275	return 0;
276
277	failed:
278	kfree(int_map);
279	return ret;
280	}
281
282	static int of_pci_prop_compatible(struct pci_dev *pdev,
283	struct of_changeset *ocs,
284	struct device_node *np)
285	{
286	const char *compat_strs[PROP_COMPAT_NUM] = { 0 };
287	int i, ret;
288
289	compat_strs[PROP_COMPAT_PCI_VVVV_DDDD] =
290	kasprintf(GFP_KERNEL, "pci%x,%x", pdev->vendor, pdev->device);
291	compat_strs[PROP_COMPAT_PCICLASS_CCSSPP] =
292	kasprintf(GFP_KERNEL, "pciclass,%06x", pdev->class);
293	compat_strs[PROP_COMPAT_PCICLASS_CCSS] =
294	kasprintf(GFP_KERNEL, "pciclass,%04x", pdev->class >> 8);
295
296	ret = of_changeset_add_prop_string_array(ocs, np, "compatible",
297	compat_strs, PROP_COMPAT_NUM);
298	for (i = 0; i < PROP_COMPAT_NUM; i++)
299	kfree(compat_strs[i]);
300
301	return ret;
302	}
303
304	int of_pci_add_properties(struct pci_dev pdev, struct of_changeset ocs,
305	struct device_node *np)
306	{
307	int ret;
308
309	/*
310	* The added properties will be released when the
311	* changeset is destroyed.
312	*/
313	if (pci_is_bridge(pdev)) {
314	ret = of_changeset_add_prop_string(ocs, np, "device_type",
315	"pci");
316	if (ret)
317	return ret;
318
319	ret = of_pci_prop_bus_range(pdev, ocs, np);
320	if (ret)
321	return ret;
322
323	ret = of_pci_prop_intr_map(pdev, ocs, np);
324	if (ret)
325	return ret;
326	}
327
328	ret = of_pci_prop_ranges(pdev, ocs, np);
329	if (ret)
330	return ret;
331
332	ret = of_changeset_add_prop_u32(ocs, np, "#address-cells",
333	OF_PCI_ADDRESS_CELLS);
334	if (ret)
335	return ret;
336
337	ret = of_changeset_add_prop_u32(ocs, np, "#size-cells",
338	OF_PCI_SIZE_CELLS);
339	if (ret)
340	return ret;
341
342	ret = of_pci_prop_reg(pdev, ocs, np);
343	if (ret)
344	return ret;
345
346	ret = of_pci_prop_compatible(pdev, ocs, np);
347	if (ret)
348	return ret;
349
350	ret = of_pci_prop_interrupts(pdev, ocs, np);
351	if (ret)
352	return ret;
353
354	return 0;
355	}