Commit | Line | Data |
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736759ef | 1 | // SPDX-License-Identifier: GPL-2.0+ |
98d9f30c BH |
2 | /* |
3 | * PCI <-> OF mapping helpers | |
4 | * | |
5 | * Copyright 2011 IBM Corp. | |
98d9f30c | 6 | */ |
4670d610 | 7 | #define pr_fmt(fmt) "PCI: OF: " fmt |
98d9f30c | 8 | |
b165e2b6 | 9 | #include <linux/irqdomain.h> |
98d9f30c BH |
10 | #include <linux/kernel.h> |
11 | #include <linux/pci.h> | |
12 | #include <linux/of.h> | |
c8d17588 | 13 | #include <linux/of_irq.h> |
4670d610 | 14 | #include <linux/of_address.h> |
98d9f30c BH |
15 | #include <linux/of_pci.h> |
16 | #include "pci.h" | |
17 | ||
40e5d614 | 18 | #ifdef CONFIG_PCI |
0d21e71a RH |
19 | /** |
20 | * pci_set_of_node - Find and set device's DT device_node | |
21 | * @dev: the PCI device structure to fill | |
22 | * | |
23 | * Returns 0 on success with of_node set or when no device is described in the | |
24 | * DT. Returns -ENODEV if the device is present, but disabled in the DT. | |
25 | */ | |
26 | int pci_set_of_node(struct pci_dev *dev) | |
98d9f30c | 27 | { |
0d21e71a RH |
28 | struct device_node *node; |
29 | ||
98d9f30c | 30 | if (!dev->bus->dev.of_node) |
0d21e71a RH |
31 | return 0; |
32 | ||
33 | node = of_pci_find_child_device(dev->bus->dev.of_node, dev->devfn); | |
34 | if (!node) | |
35 | return 0; | |
36 | ||
c6f54cf4 | 37 | device_set_node(&dev->dev, of_fwnode_handle(node)); |
0d21e71a | 38 | return 0; |
98d9f30c BH |
39 | } |
40 | ||
41 | void pci_release_of_node(struct pci_dev *dev) | |
42 | { | |
43 | of_node_put(dev->dev.of_node); | |
c6f54cf4 | 44 | device_set_node(&dev->dev, NULL); |
98d9f30c BH |
45 | } |
46 | ||
47 | void pci_set_bus_of_node(struct pci_bus *bus) | |
48 | { | |
9cb30a71 JPB |
49 | struct device_node *node; |
50 | ||
51 | if (bus->self == NULL) { | |
52 | node = pcibios_get_phb_of_node(bus); | |
53 | } else { | |
54 | node = of_node_get(bus->self->dev.of_node); | |
55 | if (node && of_property_read_bool(node, "external-facing")) | |
99b50be9 | 56 | bus->self->external_facing = true; |
9cb30a71 | 57 | } |
59b099a6 | 58 | |
c6f54cf4 | 59 | device_set_node(&bus->dev, of_fwnode_handle(node)); |
98d9f30c BH |
60 | } |
61 | ||
62 | void pci_release_bus_of_node(struct pci_bus *bus) | |
63 | { | |
64 | of_node_put(bus->dev.of_node); | |
c6f54cf4 | 65 | device_set_node(&bus->dev, NULL); |
98d9f30c BH |
66 | } |
67 | ||
68 | struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus) | |
69 | { | |
70 | /* This should only be called for PHBs */ | |
71 | if (WARN_ON(bus->self || bus->parent)) | |
72 | return NULL; | |
73 | ||
4670d610 RH |
74 | /* |
75 | * Look for a node pointer in either the intermediary device we | |
76 | * create above the root bus or its own parent. Normally only | |
98d9f30c BH |
77 | * the later is populated. |
78 | */ | |
79 | if (bus->bridge->of_node) | |
80 | return of_node_get(bus->bridge->of_node); | |
69566dd8 | 81 | if (bus->bridge->parent && bus->bridge->parent->of_node) |
98d9f30c BH |
82 | return of_node_get(bus->bridge->parent->of_node); |
83 | return NULL; | |
84 | } | |
b165e2b6 MZ |
85 | |
86 | struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus) | |
87 | { | |
88 | #ifdef CONFIG_IRQ_DOMAIN | |
b165e2b6 MZ |
89 | struct irq_domain *d; |
90 | ||
91 | if (!bus->dev.of_node) | |
92 | return NULL; | |
93 | ||
94 | /* Start looking for a phandle to an MSI controller. */ | |
c8d17588 MZ |
95 | d = of_msi_get_domain(&bus->dev, bus->dev.of_node, DOMAIN_BUS_PCI_MSI); |
96 | if (d) | |
97 | return d; | |
471c931c MZ |
98 | |
99 | /* | |
100 | * If we don't have an msi-parent property, look for a domain | |
101 | * directly attached to the host bridge. | |
102 | */ | |
c8d17588 | 103 | d = irq_find_matching_host(bus->dev.of_node, DOMAIN_BUS_PCI_MSI); |
b165e2b6 MZ |
104 | if (d) |
105 | return d; | |
106 | ||
c8d17588 | 107 | return irq_find_host(bus->dev.of_node); |
b165e2b6 MZ |
108 | #else |
109 | return NULL; | |
110 | #endif | |
111 | } | |
4670d610 | 112 | |
85aabbd7 JPB |
113 | bool pci_host_of_has_msi_map(struct device *dev) |
114 | { | |
115 | if (dev && dev->of_node) | |
116 | return of_get_property(dev->of_node, "msi-map", NULL); | |
117 | return false; | |
118 | } | |
119 | ||
4670d610 RH |
120 | static inline int __of_pci_pci_compare(struct device_node *node, |
121 | unsigned int data) | |
122 | { | |
123 | int devfn; | |
124 | ||
125 | devfn = of_pci_get_devfn(node); | |
126 | if (devfn < 0) | |
127 | return 0; | |
128 | ||
129 | return devfn == data; | |
130 | } | |
131 | ||
132 | struct device_node *of_pci_find_child_device(struct device_node *parent, | |
133 | unsigned int devfn) | |
134 | { | |
135 | struct device_node *node, *node2; | |
136 | ||
137 | for_each_child_of_node(parent, node) { | |
138 | if (__of_pci_pci_compare(node, devfn)) | |
139 | return node; | |
140 | /* | |
141 | * Some OFs create a parent node "multifunc-device" as | |
142 | * a fake root for all functions of a multi-function | |
143 | * device we go down them as well. | |
144 | */ | |
83a50d3a | 145 | if (of_node_name_eq(node, "multifunc-device")) { |
4670d610 RH |
146 | for_each_child_of_node(node, node2) { |
147 | if (__of_pci_pci_compare(node2, devfn)) { | |
148 | of_node_put(node); | |
149 | return node2; | |
150 | } | |
151 | } | |
152 | } | |
153 | } | |
154 | return NULL; | |
155 | } | |
156 | EXPORT_SYMBOL_GPL(of_pci_find_child_device); | |
157 | ||
158 | /** | |
159 | * of_pci_get_devfn() - Get device and function numbers for a device node | |
160 | * @np: device node | |
161 | * | |
162 | * Parses a standard 5-cell PCI resource and returns an 8-bit value that can | |
163 | * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device | |
164 | * and function numbers respectively. On error a negative error code is | |
165 | * returned. | |
166 | */ | |
167 | int of_pci_get_devfn(struct device_node *np) | |
168 | { | |
169 | u32 reg[5]; | |
170 | int error; | |
171 | ||
172 | error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg)); | |
173 | if (error) | |
174 | return error; | |
175 | ||
176 | return (reg[0] >> 8) & 0xff; | |
177 | } | |
178 | EXPORT_SYMBOL_GPL(of_pci_get_devfn); | |
179 | ||
180 | /** | |
181 | * of_pci_parse_bus_range() - parse the bus-range property of a PCI device | |
182 | * @node: device node | |
183 | * @res: address to a struct resource to return the bus-range | |
184 | * | |
185 | * Returns 0 on success or a negative error-code on failure. | |
186 | */ | |
187 | int of_pci_parse_bus_range(struct device_node *node, struct resource *res) | |
188 | { | |
189 | u32 bus_range[2]; | |
190 | int error; | |
191 | ||
192 | error = of_property_read_u32_array(node, "bus-range", bus_range, | |
193 | ARRAY_SIZE(bus_range)); | |
194 | if (error) | |
195 | return error; | |
196 | ||
197 | res->name = node->name; | |
198 | res->start = bus_range[0]; | |
199 | res->end = bus_range[1]; | |
200 | res->flags = IORESOURCE_BUS; | |
201 | ||
202 | return 0; | |
203 | } | |
204 | EXPORT_SYMBOL_GPL(of_pci_parse_bus_range); | |
205 | ||
206 | /** | |
43395d9e KW |
207 | * of_get_pci_domain_nr - Find the host bridge domain number |
208 | * of the given device node. | |
209 | * @node: Device tree node with the domain information. | |
4670d610 | 210 | * |
43395d9e KW |
211 | * This function will try to obtain the host bridge domain number by finding |
212 | * a property called "linux,pci-domain" of the given device node. | |
213 | * | |
214 | * Return: | |
215 | * * > 0 - On success, an associated domain number. | |
216 | * * -EINVAL - The property "linux,pci-domain" does not exist. | |
217 | * * -ENODATA - The linux,pci-domain" property does not have value. | |
218 | * * -EOVERFLOW - Invalid "linux,pci-domain" property value. | |
4670d610 RH |
219 | * |
220 | * Returns the associated domain number from DT in the range [0-0xffff], or | |
221 | * a negative value if the required property is not found. | |
222 | */ | |
223 | int of_get_pci_domain_nr(struct device_node *node) | |
224 | { | |
225 | u32 domain; | |
226 | int error; | |
227 | ||
228 | error = of_property_read_u32(node, "linux,pci-domain", &domain); | |
229 | if (error) | |
230 | return error; | |
231 | ||
232 | return (u16)domain; | |
233 | } | |
234 | EXPORT_SYMBOL_GPL(of_get_pci_domain_nr); | |
235 | ||
4670d610 RH |
236 | /** |
237 | * of_pci_check_probe_only - Setup probe only mode if linux,pci-probe-only | |
238 | * is present and valid | |
239 | */ | |
240 | void of_pci_check_probe_only(void) | |
241 | { | |
242 | u32 val; | |
243 | int ret; | |
244 | ||
245 | ret = of_property_read_u32(of_chosen, "linux,pci-probe-only", &val); | |
246 | if (ret) { | |
247 | if (ret == -ENODATA || ret == -EOVERFLOW) | |
248 | pr_warn("linux,pci-probe-only without valid value, ignoring\n"); | |
249 | return; | |
250 | } | |
251 | ||
252 | if (val) | |
253 | pci_add_flags(PCI_PROBE_ONLY); | |
254 | else | |
255 | pci_clear_flags(PCI_PROBE_ONLY); | |
256 | ||
ccd36795 | 257 | pr_info("PROBE_ONLY %s\n", val ? "enabled" : "disabled"); |
4670d610 RH |
258 | } |
259 | EXPORT_SYMBOL_GPL(of_pci_check_probe_only); | |
260 | ||
4670d610 | 261 | /** |
5bd51b35 JK |
262 | * devm_of_pci_get_host_bridge_resources() - Resource-managed parsing of PCI |
263 | * host bridge resources from DT | |
055f87a2 | 264 | * @dev: host bridge device |
4670d610 RH |
265 | * @busno: bus number associated with the bridge root bus |
266 | * @bus_max: maximum number of buses for this bridge | |
267 | * @resources: list where the range of resources will be added after DT parsing | |
9b41d19a KK |
268 | * @ib_resources: list where the range of inbound resources (with addresses |
269 | * from 'dma-ranges') will be added after DT parsing | |
4670d610 RH |
270 | * @io_base: pointer to a variable that will contain on return the physical |
271 | * address for the start of the I/O range. Can be NULL if the caller doesn't | |
272 | * expect I/O ranges to be present in the device tree. | |
273 | * | |
4670d610 RH |
274 | * This function will parse the "ranges" property of a PCI host bridge device |
275 | * node and setup the resource mapping based on its content. It is expected | |
276 | * that the property conforms with the Power ePAPR document. | |
277 | * | |
278 | * It returns zero if the range parsing has been successful or a standard error | |
279 | * value if it failed. | |
280 | */ | |
3b55809c | 281 | static int devm_of_pci_get_host_bridge_resources(struct device *dev, |
4670d610 | 282 | unsigned char busno, unsigned char bus_max, |
331f6345 RH |
283 | struct list_head *resources, |
284 | struct list_head *ib_resources, | |
285 | resource_size_t *io_base) | |
4670d610 | 286 | { |
055f87a2 | 287 | struct device_node *dev_node = dev->of_node; |
93c9a7f8 | 288 | struct resource *res, tmp_res; |
4670d610 RH |
289 | struct resource *bus_range; |
290 | struct of_pci_range range; | |
291 | struct of_pci_range_parser parser; | |
331f6345 | 292 | const char *range_type; |
4670d610 RH |
293 | int err; |
294 | ||
295 | if (io_base) | |
296 | *io_base = (resource_size_t)OF_BAD_ADDR; | |
297 | ||
5bd51b35 | 298 | bus_range = devm_kzalloc(dev, sizeof(*bus_range), GFP_KERNEL); |
4670d610 RH |
299 | if (!bus_range) |
300 | return -ENOMEM; | |
301 | ||
d9c5d5ac | 302 | dev_info(dev, "host bridge %pOF ranges:\n", dev_node); |
4670d610 | 303 | |
126b7de6 | 304 | err = of_pci_parse_bus_range(dev_node, bus_range); |
4670d610 RH |
305 | if (err) { |
306 | bus_range->start = busno; | |
307 | bus_range->end = bus_max; | |
308 | bus_range->flags = IORESOURCE_BUS; | |
d9c5d5ac JK |
309 | dev_info(dev, " No bus range found for %pOF, using %pR\n", |
310 | dev_node, bus_range); | |
4670d610 RH |
311 | } else { |
312 | if (bus_range->end > bus_range->start + bus_max) | |
313 | bus_range->end = bus_range->start + bus_max; | |
314 | } | |
315 | pci_add_resource(resources, bus_range); | |
316 | ||
317 | /* Check for ranges property */ | |
126b7de6 | 318 | err = of_pci_range_parser_init(&parser, dev_node); |
4670d610 | 319 | if (err) |
d277f6e8 | 320 | return 0; |
4670d610 | 321 | |
d9c5d5ac | 322 | dev_dbg(dev, "Parsing ranges property...\n"); |
4670d610 RH |
323 | for_each_of_pci_range(&parser, &range) { |
324 | /* Read next ranges element */ | |
325 | if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO) | |
331f6345 | 326 | range_type = "IO"; |
4670d610 | 327 | else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM) |
331f6345 | 328 | range_type = "MEM"; |
4670d610 | 329 | else |
331f6345 RH |
330 | range_type = "err"; |
331 | dev_info(dev, " %6s %#012llx..%#012llx -> %#012llx\n", | |
d9c5d5ac JK |
332 | range_type, range.cpu_addr, |
333 | range.cpu_addr + range.size - 1, range.pci_addr); | |
4670d610 RH |
334 | |
335 | /* | |
336 | * If we failed translation or got a zero-sized region | |
337 | * then skip this range | |
338 | */ | |
339 | if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) | |
340 | continue; | |
341 | ||
93c9a7f8 JK |
342 | err = of_pci_range_to_resource(&range, dev_node, &tmp_res); |
343 | if (err) | |
344 | continue; | |
345 | ||
346 | res = devm_kmemdup(dev, &tmp_res, sizeof(tmp_res), GFP_KERNEL); | |
4670d610 RH |
347 | if (!res) { |
348 | err = -ENOMEM; | |
5bd51b35 | 349 | goto failed; |
4670d610 RH |
350 | } |
351 | ||
4670d610 RH |
352 | if (resource_type(res) == IORESOURCE_IO) { |
353 | if (!io_base) { | |
d9c5d5ac | 354 | dev_err(dev, "I/O range found for %pOF. Please provide an io_base pointer to save CPU base address\n", |
126b7de6 | 355 | dev_node); |
4670d610 | 356 | err = -EINVAL; |
5bd51b35 | 357 | goto failed; |
4670d610 RH |
358 | } |
359 | if (*io_base != (resource_size_t)OF_BAD_ADDR) | |
d9c5d5ac JK |
360 | dev_warn(dev, "More than one I/O resource converted for %pOF. CPU base address for old range lost!\n", |
361 | dev_node); | |
4670d610 | 362 | *io_base = range.cpu_addr; |
3bd6b827 PA |
363 | } else if (resource_type(res) == IORESOURCE_MEM) { |
364 | res->flags &= ~IORESOURCE_MEM_64; | |
4670d610 RH |
365 | } |
366 | ||
367 | pci_add_resource_offset(resources, res, res->start - range.pci_addr); | |
368 | } | |
369 | ||
331f6345 RH |
370 | /* Check for dma-ranges property */ |
371 | if (!ib_resources) | |
372 | return 0; | |
373 | err = of_pci_dma_range_parser_init(&parser, dev_node); | |
374 | if (err) | |
375 | return 0; | |
376 | ||
377 | dev_dbg(dev, "Parsing dma-ranges property...\n"); | |
378 | for_each_of_pci_range(&parser, &range) { | |
331f6345 RH |
379 | /* |
380 | * If we failed translation or got a zero-sized region | |
381 | * then skip this range | |
382 | */ | |
383 | if (((range.flags & IORESOURCE_TYPE_BITS) != IORESOURCE_MEM) || | |
384 | range.cpu_addr == OF_BAD_ADDR || range.size == 0) | |
385 | continue; | |
386 | ||
387 | dev_info(dev, " %6s %#012llx..%#012llx -> %#012llx\n", | |
388 | "IB MEM", range.cpu_addr, | |
389 | range.cpu_addr + range.size - 1, range.pci_addr); | |
390 | ||
391 | ||
392 | err = of_pci_range_to_resource(&range, dev_node, &tmp_res); | |
393 | if (err) | |
394 | continue; | |
395 | ||
396 | res = devm_kmemdup(dev, &tmp_res, sizeof(tmp_res), GFP_KERNEL); | |
397 | if (!res) { | |
398 | err = -ENOMEM; | |
399 | goto failed; | |
400 | } | |
401 | ||
b8397a8f | 402 | pci_add_resource_offset(ib_resources, res, |
331f6345 RH |
403 | res->start - range.pci_addr); |
404 | } | |
405 | ||
4670d610 RH |
406 | return 0; |
407 | ||
5bd51b35 | 408 | failed: |
4670d610 RH |
409 | pci_free_resource_list(resources); |
410 | return err; | |
411 | } | |
4670d610 | 412 | |
4670d610 RH |
413 | #if IS_ENABLED(CONFIG_OF_IRQ) |
414 | /** | |
415 | * of_irq_parse_pci - Resolve the interrupt for a PCI device | |
416 | * @pdev: the device whose interrupt is to be resolved | |
b071c1fd | 417 | * @out_irq: structure of_phandle_args filled by this function |
4670d610 RH |
418 | * |
419 | * This function resolves the PCI interrupt for a given PCI device. If a | |
420 | * device-node exists for a given pci_dev, it will use normal OF tree | |
421 | * walking. If not, it will implement standard swizzling and walk up the | |
422 | * PCI tree until an device-node is found, at which point it will finish | |
423 | * resolving using the OF tree walking. | |
424 | */ | |
7e297843 | 425 | static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq) |
4670d610 | 426 | { |
978fd005 | 427 | struct device_node *dn, *ppnode = NULL; |
4670d610 RH |
428 | struct pci_dev *ppdev; |
429 | __be32 laddr[3]; | |
430 | u8 pin; | |
431 | int rc; | |
432 | ||
433 | /* | |
434 | * Check if we have a device node, if yes, fallback to standard | |
435 | * device tree parsing | |
436 | */ | |
437 | dn = pci_device_to_OF_node(pdev); | |
438 | if (dn) { | |
439 | rc = of_irq_parse_one(dn, 0, out_irq); | |
440 | if (!rc) | |
441 | return rc; | |
442 | } | |
443 | ||
444 | /* | |
445 | * Ok, we don't, time to have fun. Let's start by building up an | |
446 | * interrupt spec. we assume #interrupt-cells is 1, which is standard | |
447 | * for PCI. If you do different, then don't use that routine. | |
448 | */ | |
449 | rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin); | |
450 | if (rc != 0) | |
451 | goto err; | |
452 | /* No pin, exit with no error message. */ | |
453 | if (pin == 0) | |
454 | return -ENODEV; | |
455 | ||
978fd005 | 456 | /* Local interrupt-map in the device node? Use it! */ |
9195ee1a | 457 | if (of_property_present(dn, "interrupt-map")) { |
978fd005 MZ |
458 | pin = pci_swizzle_interrupt_pin(pdev, pin); |
459 | ppnode = dn; | |
460 | } | |
461 | ||
4670d610 | 462 | /* Now we walk up the PCI tree */ |
978fd005 | 463 | while (!ppnode) { |
4670d610 RH |
464 | /* Get the pci_dev of our parent */ |
465 | ppdev = pdev->bus->self; | |
466 | ||
467 | /* Ouch, it's a host bridge... */ | |
468 | if (ppdev == NULL) { | |
469 | ppnode = pci_bus_to_OF_node(pdev->bus); | |
470 | ||
471 | /* No node for host bridge ? give up */ | |
472 | if (ppnode == NULL) { | |
473 | rc = -EINVAL; | |
474 | goto err; | |
475 | } | |
476 | } else { | |
477 | /* We found a P2P bridge, check if it has a node */ | |
478 | ppnode = pci_device_to_OF_node(ppdev); | |
479 | } | |
480 | ||
481 | /* | |
482 | * Ok, we have found a parent with a device-node, hand over to | |
483 | * the OF parsing code. | |
484 | * We build a unit address from the linux device to be used for | |
485 | * resolution. Note that we use the linux bus number which may | |
486 | * not match your firmware bus numbering. | |
487 | * Fortunately, in most cases, interrupt-map-mask doesn't | |
488 | * include the bus number as part of the matching. | |
489 | * You should still be careful about that though if you intend | |
490 | * to rely on this function (you ship a firmware that doesn't | |
491 | * create device nodes for all PCI devices). | |
492 | */ | |
493 | if (ppnode) | |
494 | break; | |
495 | ||
496 | /* | |
497 | * We can only get here if we hit a P2P bridge with no node; | |
498 | * let's do standard swizzling and try again | |
499 | */ | |
500 | pin = pci_swizzle_interrupt_pin(pdev, pin); | |
501 | pdev = ppdev; | |
502 | } | |
503 | ||
504 | out_irq->np = ppnode; | |
505 | out_irq->args_count = 1; | |
506 | out_irq->args[0] = pin; | |
507 | laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8)); | |
508 | laddr[1] = laddr[2] = cpu_to_be32(0); | |
509 | rc = of_irq_parse_raw(laddr, out_irq); | |
510 | if (rc) | |
511 | goto err; | |
512 | return 0; | |
513 | err: | |
514 | if (rc == -ENOENT) { | |
515 | dev_warn(&pdev->dev, | |
516 | "%s: no interrupt-map found, INTx interrupts not available\n", | |
517 | __func__); | |
518 | pr_warn_once("%s: possibly some PCI slots don't have level triggered interrupts capability\n", | |
519 | __func__); | |
520 | } else { | |
521 | dev_err(&pdev->dev, "%s: failed with rc=%d\n", __func__, rc); | |
522 | } | |
523 | return rc; | |
524 | } | |
4670d610 RH |
525 | |
526 | /** | |
527 | * of_irq_parse_and_map_pci() - Decode a PCI IRQ from the device tree and map to a VIRQ | |
528 | * @dev: The PCI device needing an IRQ | |
529 | * @slot: PCI slot number; passed when used as map_irq callback. Unused | |
530 | * @pin: PCI IRQ pin number; passed when used as map_irq callback. Unused | |
531 | * | |
532 | * @slot and @pin are unused, but included in the function so that this | |
533 | * function can be used directly as the map_irq callback to | |
534 | * pci_assign_irq() and struct pci_host_bridge.map_irq pointer | |
535 | */ | |
536 | int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) | |
537 | { | |
538 | struct of_phandle_args oirq; | |
539 | int ret; | |
540 | ||
541 | ret = of_irq_parse_pci(dev, &oirq); | |
542 | if (ret) | |
543 | return 0; /* Proper return code 0 == NO_IRQ */ | |
544 | ||
545 | return irq_create_of_mapping(&oirq); | |
546 | } | |
547 | EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci); | |
548 | #endif /* CONFIG_OF_IRQ */ | |
c7f75aec | 549 | |
669cbc70 RH |
550 | static int pci_parse_request_of_pci_ranges(struct device *dev, |
551 | struct pci_host_bridge *bridge) | |
3a8f77e4 CP |
552 | { |
553 | int err, res_valid = 0; | |
3a8f77e4 CP |
554 | resource_size_t iobase; |
555 | struct resource_entry *win, *tmp; | |
556 | ||
669cbc70 RH |
557 | INIT_LIST_HEAD(&bridge->windows); |
558 | INIT_LIST_HEAD(&bridge->dma_ranges); | |
559 | ||
560 | err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &bridge->windows, | |
561 | &bridge->dma_ranges, &iobase); | |
3a8f77e4 CP |
562 | if (err) |
563 | return err; | |
564 | ||
669cbc70 | 565 | err = devm_request_pci_bus_resources(dev, &bridge->windows); |
3a8f77e4 | 566 | if (err) |
669cbc70 | 567 | return err; |
3a8f77e4 | 568 | |
669cbc70 | 569 | resource_list_for_each_entry_safe(win, tmp, &bridge->windows) { |
3a8f77e4 CP |
570 | struct resource *res = win->res; |
571 | ||
572 | switch (resource_type(res)) { | |
573 | case IORESOURCE_IO: | |
a5fb9fb0 | 574 | err = devm_pci_remap_iospace(dev, res, iobase); |
3a8f77e4 CP |
575 | if (err) { |
576 | dev_warn(dev, "error %d: failed to map resource %pR\n", | |
577 | err, res); | |
578 | resource_list_destroy_entry(win); | |
579 | } | |
580 | break; | |
581 | case IORESOURCE_MEM: | |
582 | res_valid |= !(res->flags & IORESOURCE_PREFETCH); | |
fede8526 VS |
583 | |
584 | if (!(res->flags & IORESOURCE_PREFETCH)) | |
585 | if (upper_32_bits(resource_size(res))) | |
586 | dev_warn(dev, "Memory resource size exceeds max for 32 bits\n"); | |
587 | ||
3a8f77e4 | 588 | break; |
3a8f77e4 CP |
589 | } |
590 | } | |
591 | ||
4cb18d13 RH |
592 | if (!res_valid) |
593 | dev_warn(dev, "non-prefetchable memory resource required\n"); | |
3a8f77e4 | 594 | |
4cb18d13 | 595 | return 0; |
669cbc70 | 596 | } |
3a8f77e4 | 597 | |
669cbc70 RH |
598 | int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) |
599 | { | |
600 | if (!dev->of_node) | |
3a8f77e4 CP |
601 | return 0; |
602 | ||
b64aa11e RH |
603 | bridge->swizzle_irq = pci_common_swizzle; |
604 | bridge->map_irq = of_irq_parse_and_map_pci; | |
3a8f77e4 | 605 | |
669cbc70 | 606 | return pci_parse_request_of_pci_ranges(dev, bridge); |
3a8f77e4 | 607 | } |
c7f75aec | 608 | |
40e5d614 KVA |
609 | #endif /* CONFIG_PCI */ |
610 | ||
611 | /** | |
43395d9e KW |
612 | * of_pci_get_max_link_speed - Find the maximum link speed of the given device node. |
613 | * @node: Device tree node with the maximum link speed information. | |
614 | * | |
40e5d614 KVA |
615 | * This function will try to find the limitation of link speed by finding |
616 | * a property called "max-link-speed" of the given device node. | |
617 | * | |
43395d9e KW |
618 | * Return: |
619 | * * > 0 - On success, a maximum link speed. | |
620 | * * -EINVAL - Invalid "max-link-speed" property value, or failure to access | |
621 | * the property of the device tree node. | |
40e5d614 KVA |
622 | * |
623 | * Returns the associated max link speed from DT, or a negative value if the | |
624 | * required property is not found or is invalid. | |
625 | */ | |
626 | int of_pci_get_max_link_speed(struct device_node *node) | |
627 | { | |
628 | u32 max_link_speed; | |
629 | ||
630 | if (of_property_read_u32(node, "max-link-speed", &max_link_speed) || | |
2dd9072e | 631 | max_link_speed == 0 || max_link_speed > 4) |
40e5d614 KVA |
632 | return -EINVAL; |
633 | ||
634 | return max_link_speed; | |
635 | } | |
636 | EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); | |
35662423 PR |
637 | |
638 | /** | |
639 | * of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt" | |
640 | * property. | |
641 | * | |
642 | * @node: device tree node with the slot power limit information | |
643 | * @slot_power_limit_value: pointer where the value should be stored in PCIe | |
644 | * Slot Capabilities Register format | |
645 | * @slot_power_limit_scale: pointer where the scale should be stored in PCIe | |
646 | * Slot Capabilities Register format | |
647 | * | |
648 | * Returns the slot power limit in milliwatts and if @slot_power_limit_value | |
649 | * and @slot_power_limit_scale pointers are non-NULL, fills in the value and | |
650 | * scale in format used by PCIe Slot Capabilities Register. | |
651 | * | |
652 | * If the property is not found or is invalid, returns 0. | |
653 | */ | |
654 | u32 of_pci_get_slot_power_limit(struct device_node *node, | |
655 | u8 *slot_power_limit_value, | |
656 | u8 *slot_power_limit_scale) | |
657 | { | |
658 | u32 slot_power_limit_mw; | |
659 | u8 value, scale; | |
660 | ||
661 | if (of_property_read_u32(node, "slot-power-limit-milliwatt", | |
662 | &slot_power_limit_mw)) | |
663 | slot_power_limit_mw = 0; | |
664 | ||
665 | /* Calculate Slot Power Limit Value and Slot Power Limit Scale */ | |
666 | if (slot_power_limit_mw == 0) { | |
667 | value = 0x00; | |
668 | scale = 0; | |
669 | } else if (slot_power_limit_mw <= 255) { | |
670 | value = slot_power_limit_mw; | |
671 | scale = 3; | |
672 | } else if (slot_power_limit_mw <= 255*10) { | |
673 | value = slot_power_limit_mw / 10; | |
674 | scale = 2; | |
675 | slot_power_limit_mw = slot_power_limit_mw / 10 * 10; | |
676 | } else if (slot_power_limit_mw <= 255*100) { | |
677 | value = slot_power_limit_mw / 100; | |
678 | scale = 1; | |
679 | slot_power_limit_mw = slot_power_limit_mw / 100 * 100; | |
680 | } else if (slot_power_limit_mw <= 239*1000) { | |
681 | value = slot_power_limit_mw / 1000; | |
682 | scale = 0; | |
683 | slot_power_limit_mw = slot_power_limit_mw / 1000 * 1000; | |
684 | } else if (slot_power_limit_mw < 250*1000) { | |
685 | value = 0xEF; | |
686 | scale = 0; | |
687 | slot_power_limit_mw = 239*1000; | |
688 | } else if (slot_power_limit_mw <= 600*1000) { | |
689 | value = 0xF0 + (slot_power_limit_mw / 1000 - 250) / 25; | |
690 | scale = 0; | |
691 | slot_power_limit_mw = slot_power_limit_mw / (1000*25) * (1000*25); | |
692 | } else { | |
693 | value = 0xFE; | |
694 | scale = 0; | |
695 | slot_power_limit_mw = 600*1000; | |
696 | } | |
697 | ||
698 | if (slot_power_limit_value) | |
699 | *slot_power_limit_value = value; | |
700 | ||
701 | if (slot_power_limit_scale) | |
702 | *slot_power_limit_scale = scale; | |
703 | ||
704 | return slot_power_limit_mw; | |
705 | } | |
706 | EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); |