Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
9 | #include <linux/mm.h> | |
10 | #include <linux/irq.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/config.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
18 | ||
19 | #include <asm/errno.h> | |
20 | #include <asm/io.h> | |
21 | #include <asm/smp.h> | |
22 | ||
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
b4033c17 AR |
26 | #define MSI_TARGET_CPU first_cpu(cpu_online_map) |
27 | ||
1da177e4 LT |
28 | static DEFINE_SPINLOCK(msi_lock); |
29 | static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; | |
30 | static kmem_cache_t* msi_cachep; | |
31 | ||
32 | static int pci_msi_enable = 1; | |
70549ad9 GKH |
33 | static int last_alloc_vector; |
34 | static int nr_released_vectors; | |
1da177e4 | 35 | static int nr_reserved_vectors = NR_HP_RESERVED_VECTORS; |
70549ad9 | 36 | static int nr_msix_devices; |
1da177e4 LT |
37 | |
38 | #ifndef CONFIG_X86_IO_APIC | |
39 | int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1}; | |
40 | u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 }; | |
41 | #endif | |
42 | ||
43 | static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags) | |
44 | { | |
45 | memset(p, 0, NR_IRQS * sizeof(struct msi_desc)); | |
46 | } | |
47 | ||
48 | static int msi_cache_init(void) | |
49 | { | |
50 | msi_cachep = kmem_cache_create("msi_cache", | |
51 | NR_IRQS * sizeof(struct msi_desc), | |
52 | 0, SLAB_HWCACHE_ALIGN, msi_cache_ctor, NULL); | |
53 | if (!msi_cachep) | |
54 | return -ENOMEM; | |
55 | ||
56 | return 0; | |
57 | } | |
58 | ||
59 | static void msi_set_mask_bit(unsigned int vector, int flag) | |
60 | { | |
61 | struct msi_desc *entry; | |
62 | ||
63 | entry = (struct msi_desc *)msi_desc[vector]; | |
64 | if (!entry || !entry->dev || !entry->mask_base) | |
65 | return; | |
66 | switch (entry->msi_attrib.type) { | |
67 | case PCI_CAP_ID_MSI: | |
68 | { | |
69 | int pos; | |
70 | u32 mask_bits; | |
71 | ||
72 | pos = (long)entry->mask_base; | |
73 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
74 | mask_bits &= ~(1); | |
75 | mask_bits |= flag; | |
76 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
77 | break; | |
78 | } | |
79 | case PCI_CAP_ID_MSIX: | |
80 | { | |
81 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
82 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
83 | writel(flag, entry->mask_base + offset); | |
84 | break; | |
85 | } | |
86 | default: | |
87 | break; | |
88 | } | |
89 | } | |
90 | ||
91 | #ifdef CONFIG_SMP | |
92 | static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask) | |
93 | { | |
94 | struct msi_desc *entry; | |
95 | struct msg_address address; | |
54d5d424 | 96 | unsigned int irq = vector; |
b4033c17 | 97 | unsigned int dest_cpu = first_cpu(cpu_mask); |
1da177e4 LT |
98 | |
99 | entry = (struct msi_desc *)msi_desc[vector]; | |
100 | if (!entry || !entry->dev) | |
101 | return; | |
102 | ||
103 | switch (entry->msi_attrib.type) { | |
104 | case PCI_CAP_ID_MSI: | |
105 | { | |
b64c05e7 | 106 | int pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI); |
1da177e4 | 107 | |
b64c05e7 | 108 | if (!pos) |
1da177e4 LT |
109 | return; |
110 | ||
111 | pci_read_config_dword(entry->dev, msi_lower_address_reg(pos), | |
112 | &address.lo_address.value); | |
113 | address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK; | |
b4033c17 AR |
114 | address.lo_address.value |= (cpu_physical_id(dest_cpu) << |
115 | MSI_TARGET_CPU_SHIFT); | |
116 | entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu); | |
1da177e4 LT |
117 | pci_write_config_dword(entry->dev, msi_lower_address_reg(pos), |
118 | address.lo_address.value); | |
54d5d424 | 119 | set_native_irq_info(irq, cpu_mask); |
1da177e4 LT |
120 | break; |
121 | } | |
122 | case PCI_CAP_ID_MSIX: | |
123 | { | |
124 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
125 | PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET; | |
126 | ||
127 | address.lo_address.value = readl(entry->mask_base + offset); | |
128 | address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK; | |
b4033c17 AR |
129 | address.lo_address.value |= (cpu_physical_id(dest_cpu) << |
130 | MSI_TARGET_CPU_SHIFT); | |
131 | entry->msi_attrib.current_cpu = cpu_physical_id(dest_cpu); | |
1da177e4 | 132 | writel(address.lo_address.value, entry->mask_base + offset); |
54d5d424 | 133 | set_native_irq_info(irq, cpu_mask); |
1da177e4 LT |
134 | break; |
135 | } | |
136 | default: | |
137 | break; | |
138 | } | |
139 | } | |
8169b5d2 GG |
140 | #else |
141 | #define set_msi_affinity NULL | |
1da177e4 LT |
142 | #endif /* CONFIG_SMP */ |
143 | ||
144 | static void mask_MSI_irq(unsigned int vector) | |
145 | { | |
146 | msi_set_mask_bit(vector, 1); | |
147 | } | |
148 | ||
149 | static void unmask_MSI_irq(unsigned int vector) | |
150 | { | |
151 | msi_set_mask_bit(vector, 0); | |
152 | } | |
153 | ||
154 | static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector) | |
155 | { | |
156 | struct msi_desc *entry; | |
157 | unsigned long flags; | |
158 | ||
159 | spin_lock_irqsave(&msi_lock, flags); | |
160 | entry = msi_desc[vector]; | |
161 | if (!entry || !entry->dev) { | |
162 | spin_unlock_irqrestore(&msi_lock, flags); | |
163 | return 0; | |
164 | } | |
165 | entry->msi_attrib.state = 1; /* Mark it active */ | |
166 | spin_unlock_irqrestore(&msi_lock, flags); | |
167 | ||
168 | return 0; /* never anything pending */ | |
169 | } | |
170 | ||
70549ad9 | 171 | static unsigned int startup_msi_irq_w_maskbit(unsigned int vector) |
1da177e4 | 172 | { |
70549ad9 GKH |
173 | startup_msi_irq_wo_maskbit(vector); |
174 | unmask_MSI_irq(vector); | |
175 | return 0; /* never anything pending */ | |
1da177e4 LT |
176 | } |
177 | ||
70549ad9 | 178 | static void shutdown_msi_irq(unsigned int vector) |
1da177e4 LT |
179 | { |
180 | struct msi_desc *entry; | |
181 | unsigned long flags; | |
182 | ||
183 | spin_lock_irqsave(&msi_lock, flags); | |
184 | entry = msi_desc[vector]; | |
70549ad9 GKH |
185 | if (entry && entry->dev) |
186 | entry->msi_attrib.state = 0; /* Mark it not active */ | |
1da177e4 | 187 | spin_unlock_irqrestore(&msi_lock, flags); |
1da177e4 LT |
188 | } |
189 | ||
70549ad9 GKH |
190 | static void end_msi_irq_wo_maskbit(unsigned int vector) |
191 | { | |
54d5d424 | 192 | move_native_irq(vector); |
70549ad9 GKH |
193 | ack_APIC_irq(); |
194 | } | |
1da177e4 LT |
195 | |
196 | static void end_msi_irq_w_maskbit(unsigned int vector) | |
197 | { | |
54d5d424 | 198 | move_native_irq(vector); |
1da177e4 LT |
199 | unmask_MSI_irq(vector); |
200 | ack_APIC_irq(); | |
201 | } | |
202 | ||
70549ad9 GKH |
203 | static void do_nothing(unsigned int vector) |
204 | { | |
205 | } | |
206 | ||
1da177e4 LT |
207 | /* |
208 | * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices, | |
209 | * which implement the MSI-X Capability Structure. | |
210 | */ | |
211 | static struct hw_interrupt_type msix_irq_type = { | |
212 | .typename = "PCI-MSI-X", | |
213 | .startup = startup_msi_irq_w_maskbit, | |
70549ad9 GKH |
214 | .shutdown = shutdown_msi_irq, |
215 | .enable = unmask_MSI_irq, | |
216 | .disable = mask_MSI_irq, | |
217 | .ack = mask_MSI_irq, | |
1da177e4 | 218 | .end = end_msi_irq_w_maskbit, |
8169b5d2 | 219 | .set_affinity = set_msi_affinity |
1da177e4 LT |
220 | }; |
221 | ||
222 | /* | |
223 | * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, | |
224 | * which implement the MSI Capability Structure with | |
225 | * Mask-and-Pending Bits. | |
226 | */ | |
227 | static struct hw_interrupt_type msi_irq_w_maskbit_type = { | |
228 | .typename = "PCI-MSI", | |
229 | .startup = startup_msi_irq_w_maskbit, | |
70549ad9 GKH |
230 | .shutdown = shutdown_msi_irq, |
231 | .enable = unmask_MSI_irq, | |
232 | .disable = mask_MSI_irq, | |
233 | .ack = mask_MSI_irq, | |
1da177e4 | 234 | .end = end_msi_irq_w_maskbit, |
8169b5d2 | 235 | .set_affinity = set_msi_affinity |
1da177e4 LT |
236 | }; |
237 | ||
238 | /* | |
239 | * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, | |
240 | * which implement the MSI Capability Structure without | |
241 | * Mask-and-Pending Bits. | |
242 | */ | |
243 | static struct hw_interrupt_type msi_irq_wo_maskbit_type = { | |
244 | .typename = "PCI-MSI", | |
245 | .startup = startup_msi_irq_wo_maskbit, | |
70549ad9 GKH |
246 | .shutdown = shutdown_msi_irq, |
247 | .enable = do_nothing, | |
248 | .disable = do_nothing, | |
249 | .ack = do_nothing, | |
1da177e4 | 250 | .end = end_msi_irq_wo_maskbit, |
8169b5d2 | 251 | .set_affinity = set_msi_affinity |
1da177e4 LT |
252 | }; |
253 | ||
254 | static void msi_data_init(struct msg_data *msi_data, | |
255 | unsigned int vector) | |
256 | { | |
257 | memset(msi_data, 0, sizeof(struct msg_data)); | |
258 | msi_data->vector = (u8)vector; | |
259 | msi_data->delivery_mode = MSI_DELIVERY_MODE; | |
260 | msi_data->level = MSI_LEVEL_MODE; | |
261 | msi_data->trigger = MSI_TRIGGER_MODE; | |
262 | } | |
263 | ||
264 | static void msi_address_init(struct msg_address *msi_address) | |
265 | { | |
266 | unsigned int dest_id; | |
b4033c17 | 267 | unsigned long dest_phys_id = cpu_physical_id(MSI_TARGET_CPU); |
1da177e4 LT |
268 | |
269 | memset(msi_address, 0, sizeof(struct msg_address)); | |
270 | msi_address->hi_address = (u32)0; | |
271 | dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT); | |
b4033c17 | 272 | msi_address->lo_address.u.dest_mode = MSI_PHYSICAL_MODE; |
1da177e4 LT |
273 | msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE; |
274 | msi_address->lo_address.u.dest_id = dest_id; | |
b4033c17 | 275 | msi_address->lo_address.value |= (dest_phys_id << MSI_TARGET_CPU_SHIFT); |
1da177e4 LT |
276 | } |
277 | ||
278 | static int msi_free_vector(struct pci_dev* dev, int vector, int reassign); | |
279 | static int assign_msi_vector(void) | |
280 | { | |
281 | static int new_vector_avail = 1; | |
282 | int vector; | |
283 | unsigned long flags; | |
284 | ||
285 | /* | |
286 | * msi_lock is provided to ensure that successful allocation of MSI | |
287 | * vector is assigned unique among drivers. | |
288 | */ | |
289 | spin_lock_irqsave(&msi_lock, flags); | |
290 | ||
291 | if (!new_vector_avail) { | |
292 | int free_vector = 0; | |
293 | ||
294 | /* | |
295 | * vector_irq[] = -1 indicates that this specific vector is: | |
296 | * - assigned for MSI (since MSI have no associated IRQ) or | |
297 | * - assigned for legacy if less than 16, or | |
298 | * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping | |
299 | * vector_irq[] = 0 indicates that this vector, previously | |
300 | * assigned for MSI, is freed by hotplug removed operations. | |
301 | * This vector will be reused for any subsequent hotplug added | |
302 | * operations. | |
303 | * vector_irq[] > 0 indicates that this vector is assigned for | |
304 | * IOxAPIC IRQs. This vector and its value provides a 1-to-1 | |
305 | * vector-to-IOxAPIC IRQ mapping. | |
306 | */ | |
307 | for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) { | |
308 | if (vector_irq[vector] != 0) | |
309 | continue; | |
310 | free_vector = vector; | |
311 | if (!msi_desc[vector]) | |
312 | break; | |
313 | else | |
314 | continue; | |
315 | } | |
316 | if (!free_vector) { | |
317 | spin_unlock_irqrestore(&msi_lock, flags); | |
318 | return -EBUSY; | |
319 | } | |
320 | vector_irq[free_vector] = -1; | |
321 | nr_released_vectors--; | |
322 | spin_unlock_irqrestore(&msi_lock, flags); | |
323 | if (msi_desc[free_vector] != NULL) { | |
324 | struct pci_dev *dev; | |
325 | int tail; | |
326 | ||
327 | /* free all linked vectors before re-assign */ | |
328 | do { | |
329 | spin_lock_irqsave(&msi_lock, flags); | |
330 | dev = msi_desc[free_vector]->dev; | |
331 | tail = msi_desc[free_vector]->link.tail; | |
332 | spin_unlock_irqrestore(&msi_lock, flags); | |
333 | msi_free_vector(dev, tail, 1); | |
334 | } while (free_vector != tail); | |
335 | } | |
336 | ||
337 | return free_vector; | |
338 | } | |
339 | vector = assign_irq_vector(AUTO_ASSIGN); | |
340 | last_alloc_vector = vector; | |
341 | if (vector == LAST_DEVICE_VECTOR) | |
342 | new_vector_avail = 0; | |
343 | ||
344 | spin_unlock_irqrestore(&msi_lock, flags); | |
345 | return vector; | |
346 | } | |
347 | ||
348 | static int get_new_vector(void) | |
349 | { | |
b64c05e7 | 350 | int vector = assign_msi_vector(); |
1da177e4 | 351 | |
b64c05e7 | 352 | if (vector > 0) |
1da177e4 LT |
353 | set_intr_gate(vector, interrupt[vector]); |
354 | ||
355 | return vector; | |
356 | } | |
357 | ||
358 | static int msi_init(void) | |
359 | { | |
360 | static int status = -ENOMEM; | |
361 | ||
362 | if (!status) | |
363 | return status; | |
364 | ||
365 | if (pci_msi_quirk) { | |
366 | pci_msi_enable = 0; | |
367 | printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n"); | |
368 | status = -EINVAL; | |
369 | return status; | |
370 | } | |
371 | ||
b64c05e7 GG |
372 | status = msi_cache_init(); |
373 | if (status < 0) { | |
1da177e4 LT |
374 | pci_msi_enable = 0; |
375 | printk(KERN_WARNING "PCI: MSI cache init failed\n"); | |
376 | return status; | |
377 | } | |
378 | last_alloc_vector = assign_irq_vector(AUTO_ASSIGN); | |
379 | if (last_alloc_vector < 0) { | |
380 | pci_msi_enable = 0; | |
381 | printk(KERN_WARNING "PCI: No interrupt vectors available for MSI\n"); | |
382 | status = -EBUSY; | |
383 | return status; | |
384 | } | |
385 | vector_irq[last_alloc_vector] = 0; | |
386 | nr_released_vectors++; | |
387 | ||
388 | return status; | |
389 | } | |
390 | ||
391 | static int get_msi_vector(struct pci_dev *dev) | |
392 | { | |
393 | return get_new_vector(); | |
394 | } | |
395 | ||
396 | static struct msi_desc* alloc_msi_entry(void) | |
397 | { | |
398 | struct msi_desc *entry; | |
399 | ||
70549ad9 | 400 | entry = kmem_cache_alloc(msi_cachep, SLAB_KERNEL); |
1da177e4 LT |
401 | if (!entry) |
402 | return NULL; | |
403 | ||
404 | memset(entry, 0, sizeof(struct msi_desc)); | |
405 | entry->link.tail = entry->link.head = 0; /* single message */ | |
406 | entry->dev = NULL; | |
407 | ||
408 | return entry; | |
409 | } | |
410 | ||
411 | static void attach_msi_entry(struct msi_desc *entry, int vector) | |
412 | { | |
413 | unsigned long flags; | |
414 | ||
415 | spin_lock_irqsave(&msi_lock, flags); | |
416 | msi_desc[vector] = entry; | |
417 | spin_unlock_irqrestore(&msi_lock, flags); | |
418 | } | |
419 | ||
420 | static void irq_handler_init(int cap_id, int pos, int mask) | |
421 | { | |
f6bc2666 IM |
422 | unsigned long flags; |
423 | ||
424 | spin_lock_irqsave(&irq_desc[pos].lock, flags); | |
1da177e4 LT |
425 | if (cap_id == PCI_CAP_ID_MSIX) |
426 | irq_desc[pos].handler = &msix_irq_type; | |
427 | else { | |
428 | if (!mask) | |
429 | irq_desc[pos].handler = &msi_irq_wo_maskbit_type; | |
430 | else | |
431 | irq_desc[pos].handler = &msi_irq_w_maskbit_type; | |
432 | } | |
f6bc2666 | 433 | spin_unlock_irqrestore(&irq_desc[pos].lock, flags); |
1da177e4 LT |
434 | } |
435 | ||
436 | static void enable_msi_mode(struct pci_dev *dev, int pos, int type) | |
437 | { | |
438 | u16 control; | |
439 | ||
440 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
441 | if (type == PCI_CAP_ID_MSI) { | |
442 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
443 | msi_enable(control, 1); | |
444 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
445 | } else { | |
446 | msix_enable(control); | |
447 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
448 | } | |
449 | if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { | |
450 | /* PCI Express Endpoint device detected */ | |
a04ce0ff | 451 | pci_intx(dev, 0); /* disable intx */ |
1da177e4 LT |
452 | } |
453 | } | |
454 | ||
4602b88d | 455 | void disable_msi_mode(struct pci_dev *dev, int pos, int type) |
1da177e4 LT |
456 | { |
457 | u16 control; | |
458 | ||
459 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
460 | if (type == PCI_CAP_ID_MSI) { | |
461 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
462 | msi_disable(control); | |
463 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
464 | } else { | |
465 | msix_disable(control); | |
466 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
467 | } | |
468 | if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { | |
469 | /* PCI Express Endpoint device detected */ | |
a04ce0ff | 470 | pci_intx(dev, 1); /* enable intx */ |
1da177e4 LT |
471 | } |
472 | } | |
473 | ||
474 | static int msi_lookup_vector(struct pci_dev *dev, int type) | |
475 | { | |
476 | int vector; | |
477 | unsigned long flags; | |
478 | ||
479 | spin_lock_irqsave(&msi_lock, flags); | |
480 | for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) { | |
481 | if (!msi_desc[vector] || msi_desc[vector]->dev != dev || | |
482 | msi_desc[vector]->msi_attrib.type != type || | |
483 | msi_desc[vector]->msi_attrib.default_vector != dev->irq) | |
484 | continue; | |
485 | spin_unlock_irqrestore(&msi_lock, flags); | |
486 | /* This pre-assigned MSI vector for this device | |
487 | already exits. Override dev->irq with this vector */ | |
488 | dev->irq = vector; | |
489 | return 0; | |
490 | } | |
491 | spin_unlock_irqrestore(&msi_lock, flags); | |
492 | ||
493 | return -EACCES; | |
494 | } | |
495 | ||
496 | void pci_scan_msi_device(struct pci_dev *dev) | |
497 | { | |
498 | if (!dev) | |
499 | return; | |
500 | ||
501 | if (pci_find_capability(dev, PCI_CAP_ID_MSIX) > 0) | |
502 | nr_msix_devices++; | |
503 | else if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0) | |
504 | nr_reserved_vectors++; | |
505 | } | |
506 | ||
507 | /** | |
508 | * msi_capability_init - configure device's MSI capability structure | |
509 | * @dev: pointer to the pci_dev data structure of MSI device function | |
510 | * | |
eaae4b3a | 511 | * Setup the MSI capability structure of device function with a single |
1da177e4 LT |
512 | * MSI vector, regardless of device function is capable of handling |
513 | * multiple messages. A return of zero indicates the successful setup | |
514 | * of an entry zero with the new MSI vector or non-zero for otherwise. | |
515 | **/ | |
516 | static int msi_capability_init(struct pci_dev *dev) | |
517 | { | |
518 | struct msi_desc *entry; | |
519 | struct msg_address address; | |
520 | struct msg_data data; | |
521 | int pos, vector; | |
522 | u16 control; | |
523 | ||
524 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
525 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
526 | /* MSI Entry Initialization */ | |
b64c05e7 GG |
527 | entry = alloc_msi_entry(); |
528 | if (!entry) | |
1da177e4 LT |
529 | return -ENOMEM; |
530 | ||
b64c05e7 GG |
531 | vector = get_msi_vector(dev); |
532 | if (vector < 0) { | |
1da177e4 LT |
533 | kmem_cache_free(msi_cachep, entry); |
534 | return -EBUSY; | |
535 | } | |
536 | entry->link.head = vector; | |
537 | entry->link.tail = vector; | |
538 | entry->msi_attrib.type = PCI_CAP_ID_MSI; | |
539 | entry->msi_attrib.state = 0; /* Mark it not active */ | |
540 | entry->msi_attrib.entry_nr = 0; | |
541 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
542 | entry->msi_attrib.default_vector = dev->irq; /* Save IOAPIC IRQ */ | |
543 | dev->irq = vector; | |
544 | entry->dev = dev; | |
545 | if (is_mask_bit_support(control)) { | |
546 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
547 | is_64bit_address(control)); | |
548 | } | |
549 | /* Replace with MSI handler */ | |
550 | irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit); | |
551 | /* Configure MSI capability structure */ | |
552 | msi_address_init(&address); | |
553 | msi_data_init(&data, vector); | |
554 | entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >> | |
555 | MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK); | |
556 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
557 | address.lo_address.value); | |
558 | if (is_64bit_address(control)) { | |
559 | pci_write_config_dword(dev, | |
560 | msi_upper_address_reg(pos), address.hi_address); | |
561 | pci_write_config_word(dev, | |
562 | msi_data_reg(pos, 1), *((u32*)&data)); | |
563 | } else | |
564 | pci_write_config_word(dev, | |
565 | msi_data_reg(pos, 0), *((u32*)&data)); | |
566 | if (entry->msi_attrib.maskbit) { | |
567 | unsigned int maskbits, temp; | |
568 | /* All MSIs are unmasked by default, Mask them all */ | |
569 | pci_read_config_dword(dev, | |
570 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
571 | &maskbits); | |
572 | temp = (1 << multi_msi_capable(control)); | |
573 | temp = ((temp - 1) & ~temp); | |
574 | maskbits |= temp; | |
575 | pci_write_config_dword(dev, | |
576 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
577 | maskbits); | |
578 | } | |
579 | attach_msi_entry(entry, vector); | |
580 | /* Set MSI enabled bits */ | |
581 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
586 | /** | |
587 | * msix_capability_init - configure device's MSI-X capability | |
588 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
589 | * @entries: pointer to an array of struct msix_entry entries |
590 | * @nvec: number of @entries | |
1da177e4 | 591 | * |
eaae4b3a | 592 | * Setup the MSI-X capability structure of device function with a |
1da177e4 LT |
593 | * single MSI-X vector. A return of zero indicates the successful setup of |
594 | * requested MSI-X entries with allocated vectors or non-zero for otherwise. | |
595 | **/ | |
596 | static int msix_capability_init(struct pci_dev *dev, | |
597 | struct msix_entry *entries, int nvec) | |
598 | { | |
599 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
600 | struct msg_address address; | |
601 | struct msg_data data; | |
602 | int vector, pos, i, j, nr_entries, temp = 0; | |
a0454b40 GG |
603 | unsigned long phys_addr; |
604 | u32 table_offset; | |
1da177e4 LT |
605 | u16 control; |
606 | u8 bir; | |
607 | void __iomem *base; | |
608 | ||
609 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
610 | /* Request & Map MSI-X table region */ | |
611 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
612 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
613 | |
614 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 615 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
616 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
617 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
618 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
619 | if (base == NULL) | |
620 | return -ENOMEM; | |
621 | ||
622 | /* MSI-X Table Initialization */ | |
623 | for (i = 0; i < nvec; i++) { | |
624 | entry = alloc_msi_entry(); | |
625 | if (!entry) | |
626 | break; | |
b64c05e7 GG |
627 | vector = get_msi_vector(dev); |
628 | if (vector < 0) | |
1da177e4 LT |
629 | break; |
630 | ||
631 | j = entries[i].entry; | |
632 | entries[i].vector = vector; | |
633 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; | |
634 | entry->msi_attrib.state = 0; /* Mark it not active */ | |
635 | entry->msi_attrib.entry_nr = j; | |
636 | entry->msi_attrib.maskbit = 1; | |
637 | entry->msi_attrib.default_vector = dev->irq; | |
638 | entry->dev = dev; | |
639 | entry->mask_base = base; | |
640 | if (!head) { | |
641 | entry->link.head = vector; | |
642 | entry->link.tail = vector; | |
643 | head = entry; | |
644 | } else { | |
645 | entry->link.head = temp; | |
646 | entry->link.tail = tail->link.tail; | |
647 | tail->link.tail = vector; | |
648 | head->link.head = vector; | |
649 | } | |
650 | temp = vector; | |
651 | tail = entry; | |
652 | /* Replace with MSI-X handler */ | |
653 | irq_handler_init(PCI_CAP_ID_MSIX, vector, 1); | |
654 | /* Configure MSI-X capability structure */ | |
655 | msi_address_init(&address); | |
656 | msi_data_init(&data, vector); | |
657 | entry->msi_attrib.current_cpu = | |
658 | ((address.lo_address.u.dest_id >> | |
659 | MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK); | |
660 | writel(address.lo_address.value, | |
661 | base + j * PCI_MSIX_ENTRY_SIZE + | |
662 | PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
663 | writel(address.hi_address, | |
664 | base + j * PCI_MSIX_ENTRY_SIZE + | |
665 | PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
666 | writel(*(u32*)&data, | |
667 | base + j * PCI_MSIX_ENTRY_SIZE + | |
668 | PCI_MSIX_ENTRY_DATA_OFFSET); | |
669 | attach_msi_entry(entry, vector); | |
670 | } | |
671 | if (i != nvec) { | |
672 | i--; | |
673 | for (; i >= 0; i--) { | |
674 | vector = (entries + i)->vector; | |
675 | msi_free_vector(dev, vector, 0); | |
676 | (entries + i)->vector = 0; | |
677 | } | |
678 | return -EBUSY; | |
679 | } | |
680 | /* Set MSI-X enabled bits */ | |
681 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
686 | /** | |
687 | * pci_enable_msi - configure device's MSI capability structure | |
688 | * @dev: pointer to the pci_dev data structure of MSI device function | |
689 | * | |
690 | * Setup the MSI capability structure of device function with | |
691 | * a single MSI vector upon its software driver call to request for | |
692 | * MSI mode enabled on its hardware device function. A return of zero | |
693 | * indicates the successful setup of an entry zero with the new MSI | |
694 | * vector or non-zero for otherwise. | |
695 | **/ | |
696 | int pci_enable_msi(struct pci_dev* dev) | |
697 | { | |
698 | int pos, temp, status = -EINVAL; | |
699 | u16 control; | |
700 | ||
701 | if (!pci_msi_enable || !dev) | |
702 | return status; | |
703 | ||
4602b88d KA |
704 | if (dev->no_msi) |
705 | return status; | |
706 | ||
6e325a62 MT |
707 | if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) |
708 | return -EINVAL; | |
709 | ||
1da177e4 LT |
710 | temp = dev->irq; |
711 | ||
b64c05e7 GG |
712 | status = msi_init(); |
713 | if (status < 0) | |
1da177e4 LT |
714 | return status; |
715 | ||
b64c05e7 GG |
716 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
717 | if (!pos) | |
1da177e4 LT |
718 | return -EINVAL; |
719 | ||
720 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
721 | if (control & PCI_MSI_FLAGS_ENABLE) | |
722 | return 0; /* Already in MSI mode */ | |
723 | ||
724 | if (!msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { | |
725 | /* Lookup Sucess */ | |
726 | unsigned long flags; | |
727 | ||
728 | spin_lock_irqsave(&msi_lock, flags); | |
729 | if (!vector_irq[dev->irq]) { | |
730 | msi_desc[dev->irq]->msi_attrib.state = 0; | |
731 | vector_irq[dev->irq] = -1; | |
732 | nr_released_vectors--; | |
733 | spin_unlock_irqrestore(&msi_lock, flags); | |
734 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
735 | return 0; | |
736 | } | |
737 | spin_unlock_irqrestore(&msi_lock, flags); | |
738 | dev->irq = temp; | |
739 | } | |
740 | /* Check whether driver already requested for MSI-X vectors */ | |
b64c05e7 GG |
741 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
742 | if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { | |
1da177e4 LT |
743 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " |
744 | "Device already has MSI-X vectors assigned\n", | |
745 | pci_name(dev)); | |
746 | dev->irq = temp; | |
747 | return -EINVAL; | |
748 | } | |
749 | status = msi_capability_init(dev); | |
750 | if (!status) { | |
751 | if (!pos) | |
752 | nr_reserved_vectors--; /* Only MSI capable */ | |
753 | else if (nr_msix_devices > 0) | |
754 | nr_msix_devices--; /* Both MSI and MSI-X capable, | |
755 | but choose enabling MSI */ | |
756 | } | |
757 | ||
758 | return status; | |
759 | } | |
760 | ||
761 | void pci_disable_msi(struct pci_dev* dev) | |
762 | { | |
763 | struct msi_desc *entry; | |
764 | int pos, default_vector; | |
765 | u16 control; | |
766 | unsigned long flags; | |
767 | ||
309e57df MW |
768 | if (!pci_msi_enable) |
769 | return; | |
b64c05e7 GG |
770 | if (!dev) |
771 | return; | |
309e57df | 772 | |
b64c05e7 GG |
773 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
774 | if (!pos) | |
1da177e4 LT |
775 | return; |
776 | ||
777 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
778 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
779 | return; | |
780 | ||
781 | spin_lock_irqsave(&msi_lock, flags); | |
782 | entry = msi_desc[dev->irq]; | |
783 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { | |
784 | spin_unlock_irqrestore(&msi_lock, flags); | |
785 | return; | |
786 | } | |
787 | if (entry->msi_attrib.state) { | |
788 | spin_unlock_irqrestore(&msi_lock, flags); | |
789 | printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " | |
790 | "free_irq() on MSI vector %d\n", | |
791 | pci_name(dev), dev->irq); | |
792 | BUG_ON(entry->msi_attrib.state > 0); | |
793 | } else { | |
794 | vector_irq[dev->irq] = 0; /* free it */ | |
795 | nr_released_vectors++; | |
796 | default_vector = entry->msi_attrib.default_vector; | |
797 | spin_unlock_irqrestore(&msi_lock, flags); | |
798 | /* Restore dev->irq to its default pin-assertion vector */ | |
799 | dev->irq = default_vector; | |
800 | disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), | |
801 | PCI_CAP_ID_MSI); | |
802 | } | |
803 | } | |
804 | ||
1da177e4 LT |
805 | static int msi_free_vector(struct pci_dev* dev, int vector, int reassign) |
806 | { | |
807 | struct msi_desc *entry; | |
808 | int head, entry_nr, type; | |
809 | void __iomem *base; | |
810 | unsigned long flags; | |
811 | ||
812 | spin_lock_irqsave(&msi_lock, flags); | |
813 | entry = msi_desc[vector]; | |
814 | if (!entry || entry->dev != dev) { | |
815 | spin_unlock_irqrestore(&msi_lock, flags); | |
816 | return -EINVAL; | |
817 | } | |
818 | type = entry->msi_attrib.type; | |
819 | entry_nr = entry->msi_attrib.entry_nr; | |
820 | head = entry->link.head; | |
821 | base = entry->mask_base; | |
822 | msi_desc[entry->link.head]->link.tail = entry->link.tail; | |
823 | msi_desc[entry->link.tail]->link.head = entry->link.head; | |
824 | entry->dev = NULL; | |
825 | if (!reassign) { | |
826 | vector_irq[vector] = 0; | |
827 | nr_released_vectors++; | |
828 | } | |
829 | msi_desc[vector] = NULL; | |
830 | spin_unlock_irqrestore(&msi_lock, flags); | |
831 | ||
832 | kmem_cache_free(msi_cachep, entry); | |
833 | ||
834 | if (type == PCI_CAP_ID_MSIX) { | |
835 | if (!reassign) | |
836 | writel(1, base + | |
837 | entry_nr * PCI_MSIX_ENTRY_SIZE + | |
838 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
839 | ||
840 | if (head == vector) { | |
841 | /* | |
842 | * Detect last MSI-X vector to be released. | |
843 | * Release the MSI-X memory-mapped table. | |
844 | */ | |
a0454b40 | 845 | #if 0 |
1da177e4 | 846 | int pos, nr_entries; |
a0454b40 GG |
847 | unsigned long phys_addr; |
848 | u32 table_offset; | |
1da177e4 LT |
849 | u16 control; |
850 | u8 bir; | |
851 | ||
852 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
853 | pci_read_config_word(dev, msi_control_reg(pos), | |
854 | &control); | |
855 | nr_entries = multi_msix_capable(control); | |
856 | pci_read_config_dword(dev, msix_table_offset_reg(pos), | |
857 | &table_offset); | |
858 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
a0454b40 GG |
859 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
860 | phys_addr = pci_resource_start(dev, bir) + table_offset; | |
861 | /* | |
862 | * FIXME! and what did you want to do with phys_addr? | |
863 | */ | |
864 | #endif | |
1da177e4 LT |
865 | iounmap(base); |
866 | } | |
867 | } | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
872 | static int reroute_msix_table(int head, struct msix_entry *entries, int *nvec) | |
873 | { | |
874 | int vector = head, tail = 0; | |
875 | int i, j = 0, nr_entries = 0; | |
876 | void __iomem *base; | |
877 | unsigned long flags; | |
878 | ||
879 | spin_lock_irqsave(&msi_lock, flags); | |
880 | while (head != tail) { | |
881 | nr_entries++; | |
882 | tail = msi_desc[vector]->link.tail; | |
883 | if (entries[0].entry == msi_desc[vector]->msi_attrib.entry_nr) | |
884 | j = vector; | |
885 | vector = tail; | |
886 | } | |
887 | if (*nvec > nr_entries) { | |
888 | spin_unlock_irqrestore(&msi_lock, flags); | |
889 | *nvec = nr_entries; | |
890 | return -EINVAL; | |
891 | } | |
892 | vector = ((j > 0) ? j : head); | |
893 | for (i = 0; i < *nvec; i++) { | |
894 | j = msi_desc[vector]->msi_attrib.entry_nr; | |
895 | msi_desc[vector]->msi_attrib.state = 0; /* Mark it not active */ | |
896 | vector_irq[vector] = -1; /* Mark it busy */ | |
897 | nr_released_vectors--; | |
898 | entries[i].vector = vector; | |
899 | if (j != (entries + i)->entry) { | |
900 | base = msi_desc[vector]->mask_base; | |
901 | msi_desc[vector]->msi_attrib.entry_nr = | |
902 | (entries + i)->entry; | |
903 | writel( readl(base + j * PCI_MSIX_ENTRY_SIZE + | |
904 | PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET), base + | |
905 | (entries + i)->entry * PCI_MSIX_ENTRY_SIZE + | |
906 | PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
907 | writel( readl(base + j * PCI_MSIX_ENTRY_SIZE + | |
908 | PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET), base + | |
909 | (entries + i)->entry * PCI_MSIX_ENTRY_SIZE + | |
910 | PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
911 | writel( (readl(base + j * PCI_MSIX_ENTRY_SIZE + | |
912 | PCI_MSIX_ENTRY_DATA_OFFSET) & 0xff00) | vector, | |
913 | base + (entries+i)->entry*PCI_MSIX_ENTRY_SIZE + | |
914 | PCI_MSIX_ENTRY_DATA_OFFSET); | |
915 | } | |
916 | vector = msi_desc[vector]->link.tail; | |
917 | } | |
918 | spin_unlock_irqrestore(&msi_lock, flags); | |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
923 | /** | |
924 | * pci_enable_msix - configure device's MSI-X capability structure | |
925 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 926 | * @entries: pointer to an array of MSI-X entries |
1da177e4 LT |
927 | * @nvec: number of MSI-X vectors requested for allocation by device driver |
928 | * | |
929 | * Setup the MSI-X capability structure of device function with the number | |
930 | * of requested vectors upon its software driver call to request for | |
931 | * MSI-X mode enabled on its hardware device function. A return of zero | |
932 | * indicates the successful configuration of MSI-X capability structure | |
933 | * with new allocated MSI-X vectors. A return of < 0 indicates a failure. | |
934 | * Or a return of > 0 indicates that driver request is exceeding the number | |
935 | * of vectors available. Driver should use the returned value to re-send | |
936 | * its request. | |
937 | **/ | |
938 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
939 | { | |
940 | int status, pos, nr_entries, free_vectors; | |
941 | int i, j, temp; | |
942 | u16 control; | |
943 | unsigned long flags; | |
944 | ||
945 | if (!pci_msi_enable || !dev || !entries) | |
946 | return -EINVAL; | |
947 | ||
b64c05e7 GG |
948 | status = msi_init(); |
949 | if (status < 0) | |
1da177e4 LT |
950 | return status; |
951 | ||
b64c05e7 GG |
952 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
953 | if (!pos) | |
1da177e4 LT |
954 | return -EINVAL; |
955 | ||
956 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
957 | if (control & PCI_MSIX_FLAGS_ENABLE) | |
958 | return -EINVAL; /* Already in MSI-X mode */ | |
959 | ||
960 | nr_entries = multi_msix_capable(control); | |
961 | if (nvec > nr_entries) | |
962 | return -EINVAL; | |
963 | ||
964 | /* Check for any invalid entries */ | |
965 | for (i = 0; i < nvec; i++) { | |
966 | if (entries[i].entry >= nr_entries) | |
967 | return -EINVAL; /* invalid entry */ | |
968 | for (j = i + 1; j < nvec; j++) { | |
969 | if (entries[i].entry == entries[j].entry) | |
970 | return -EINVAL; /* duplicate entry */ | |
971 | } | |
972 | } | |
973 | temp = dev->irq; | |
974 | if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { | |
975 | /* Lookup Sucess */ | |
976 | nr_entries = nvec; | |
977 | /* Reroute MSI-X table */ | |
978 | if (reroute_msix_table(dev->irq, entries, &nr_entries)) { | |
979 | /* #requested > #previous-assigned */ | |
980 | dev->irq = temp; | |
981 | return nr_entries; | |
982 | } | |
983 | dev->irq = temp; | |
984 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
985 | return 0; | |
986 | } | |
987 | /* Check whether driver already requested for MSI vector */ | |
988 | if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && | |
989 | !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { | |
990 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " | |
991 | "Device already has an MSI vector assigned\n", | |
992 | pci_name(dev)); | |
993 | dev->irq = temp; | |
994 | return -EINVAL; | |
995 | } | |
996 | ||
997 | spin_lock_irqsave(&msi_lock, flags); | |
998 | /* | |
999 | * msi_lock is provided to ensure that enough vectors resources are | |
1000 | * available before granting. | |
1001 | */ | |
1002 | free_vectors = pci_vector_resources(last_alloc_vector, | |
1003 | nr_released_vectors); | |
1004 | /* Ensure that each MSI/MSI-X device has one vector reserved by | |
1005 | default to avoid any MSI-X driver to take all available | |
1006 | resources */ | |
1007 | free_vectors -= nr_reserved_vectors; | |
1008 | /* Find the average of free vectors among MSI-X devices */ | |
1009 | if (nr_msix_devices > 0) | |
1010 | free_vectors /= nr_msix_devices; | |
1011 | spin_unlock_irqrestore(&msi_lock, flags); | |
1012 | ||
1013 | if (nvec > free_vectors) { | |
1014 | if (free_vectors > 0) | |
1015 | return free_vectors; | |
1016 | else | |
1017 | return -EBUSY; | |
1018 | } | |
1019 | ||
1020 | status = msix_capability_init(dev, entries, nvec); | |
1021 | if (!status && nr_msix_devices > 0) | |
1022 | nr_msix_devices--; | |
1023 | ||
1024 | return status; | |
1025 | } | |
1026 | ||
1027 | void pci_disable_msix(struct pci_dev* dev) | |
1028 | { | |
1029 | int pos, temp; | |
1030 | u16 control; | |
1031 | ||
309e57df MW |
1032 | if (!pci_msi_enable) |
1033 | return; | |
b64c05e7 GG |
1034 | if (!dev) |
1035 | return; | |
1036 | ||
1037 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1038 | if (!pos) | |
1da177e4 LT |
1039 | return; |
1040 | ||
1041 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1042 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
1043 | return; | |
1044 | ||
1045 | temp = dev->irq; | |
1046 | if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { | |
1047 | int state, vector, head, tail = 0, warning = 0; | |
1048 | unsigned long flags; | |
1049 | ||
1050 | vector = head = dev->irq; | |
1051 | spin_lock_irqsave(&msi_lock, flags); | |
1052 | while (head != tail) { | |
1053 | state = msi_desc[vector]->msi_attrib.state; | |
1054 | if (state) | |
1055 | warning = 1; | |
1056 | else { | |
1057 | vector_irq[vector] = 0; /* free it */ | |
1058 | nr_released_vectors++; | |
1059 | } | |
1060 | tail = msi_desc[vector]->link.tail; | |
1061 | vector = tail; | |
1062 | } | |
1063 | spin_unlock_irqrestore(&msi_lock, flags); | |
1064 | if (warning) { | |
1065 | dev->irq = temp; | |
1066 | printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " | |
1067 | "free_irq() on all MSI-X vectors\n", | |
1068 | pci_name(dev)); | |
1069 | BUG_ON(warning > 0); | |
1070 | } else { | |
1071 | dev->irq = temp; | |
1072 | disable_msi_mode(dev, | |
1073 | pci_find_capability(dev, PCI_CAP_ID_MSIX), | |
1074 | PCI_CAP_ID_MSIX); | |
1075 | ||
1076 | } | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | /** | |
1081 | * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state | |
1082 | * @dev: pointer to the pci_dev data structure of MSI(X) device function | |
1083 | * | |
eaae4b3a | 1084 | * Being called during hotplug remove, from which the device function |
1da177e4 LT |
1085 | * is hot-removed. All previous assigned MSI/MSI-X vectors, if |
1086 | * allocated for this device function, are reclaimed to unused state, | |
1087 | * which may be used later on. | |
1088 | **/ | |
1089 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
1090 | { | |
1091 | int state, pos, temp; | |
1092 | unsigned long flags; | |
1093 | ||
1094 | if (!pci_msi_enable || !dev) | |
1095 | return; | |
1096 | ||
1097 | temp = dev->irq; /* Save IOAPIC IRQ */ | |
b64c05e7 GG |
1098 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1099 | if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { | |
1da177e4 LT |
1100 | spin_lock_irqsave(&msi_lock, flags); |
1101 | state = msi_desc[dev->irq]->msi_attrib.state; | |
1102 | spin_unlock_irqrestore(&msi_lock, flags); | |
1103 | if (state) { | |
1104 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1105 | "called without free_irq() on MSI vector %d\n", | |
1106 | pci_name(dev), dev->irq); | |
1107 | BUG_ON(state > 0); | |
1108 | } else /* Release MSI vector assigned to this device */ | |
1109 | msi_free_vector(dev, dev->irq, 0); | |
1110 | dev->irq = temp; /* Restore IOAPIC IRQ */ | |
1111 | } | |
b64c05e7 GG |
1112 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1113 | if (pos > 0 && !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { | |
1da177e4 LT |
1114 | int vector, head, tail = 0, warning = 0; |
1115 | void __iomem *base = NULL; | |
1116 | ||
1117 | vector = head = dev->irq; | |
1118 | while (head != tail) { | |
1119 | spin_lock_irqsave(&msi_lock, flags); | |
1120 | state = msi_desc[vector]->msi_attrib.state; | |
1121 | tail = msi_desc[vector]->link.tail; | |
1122 | base = msi_desc[vector]->mask_base; | |
1123 | spin_unlock_irqrestore(&msi_lock, flags); | |
1124 | if (state) | |
1125 | warning = 1; | |
1126 | else if (vector != head) /* Release MSI-X vector */ | |
1127 | msi_free_vector(dev, vector, 0); | |
1128 | vector = tail; | |
1129 | } | |
1130 | msi_free_vector(dev, vector, 0); | |
1131 | if (warning) { | |
1132 | /* Force to release the MSI-X memory-mapped table */ | |
a0454b40 GG |
1133 | #if 0 |
1134 | unsigned long phys_addr; | |
1135 | u32 table_offset; | |
1da177e4 LT |
1136 | u16 control; |
1137 | u8 bir; | |
1138 | ||
1139 | pci_read_config_word(dev, msi_control_reg(pos), | |
1140 | &control); | |
1141 | pci_read_config_dword(dev, msix_table_offset_reg(pos), | |
1142 | &table_offset); | |
1143 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
a0454b40 GG |
1144 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
1145 | phys_addr = pci_resource_start(dev, bir) + table_offset; | |
1146 | /* | |
1147 | * FIXME! and what did you want to do with phys_addr? | |
1148 | */ | |
1149 | #endif | |
1da177e4 LT |
1150 | iounmap(base); |
1151 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1152 | "called without free_irq() on all MSI-X vectors\n", | |
1153 | pci_name(dev)); | |
1154 | BUG_ON(warning > 0); | |
1155 | } | |
1156 | dev->irq = temp; /* Restore IOAPIC IRQ */ | |
1157 | } | |
1158 | } | |
1159 | ||
309e57df MW |
1160 | void pci_no_msi(void) |
1161 | { | |
1162 | pci_msi_enable = 0; | |
1163 | } | |
1164 | ||
1da177e4 LT |
1165 | EXPORT_SYMBOL(pci_enable_msi); |
1166 | EXPORT_SYMBOL(pci_disable_msi); | |
1167 | EXPORT_SYMBOL(pci_enable_msix); | |
1168 | EXPORT_SYMBOL(pci_disable_msix); |