Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
1da177e4 | 25 | |
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
527eee29 BH |
28 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
29 | ||
30 | ||
6a9e7f20 AB |
31 | /* Arch hooks */ |
32 | ||
4287d824 TP |
33 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
34 | { | |
0cbdcfcf TR |
35 | struct msi_chip *chip = dev->bus->msi; |
36 | int err; | |
37 | ||
38 | if (!chip || !chip->setup_irq) | |
39 | return -EINVAL; | |
40 | ||
41 | err = chip->setup_irq(chip, dev, desc); | |
42 | if (err < 0) | |
43 | return err; | |
44 | ||
45 | irq_set_chip_data(desc->irq, chip); | |
46 | ||
47 | return 0; | |
4287d824 TP |
48 | } |
49 | ||
50 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 51 | { |
0cbdcfcf TR |
52 | struct msi_chip *chip = irq_get_chip_data(irq); |
53 | ||
54 | if (!chip || !chip->teardown_irq) | |
55 | return; | |
56 | ||
57 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
58 | } |
59 | ||
4287d824 TP |
60 | int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) |
61 | { | |
0cbdcfcf TR |
62 | struct msi_chip *chip = dev->bus->msi; |
63 | ||
64 | if (!chip || !chip->check_device) | |
65 | return 0; | |
66 | ||
67 | return chip->check_device(chip, dev, nvec, type); | |
4287d824 | 68 | } |
1525bf0d | 69 | |
4287d824 | 70 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
71 | { |
72 | struct msi_desc *entry; | |
73 | int ret; | |
74 | ||
1c8d7b0a MW |
75 | /* |
76 | * If an architecture wants to support multiple MSI, it needs to | |
77 | * override arch_setup_msi_irqs() | |
78 | */ | |
79 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
80 | return 1; | |
81 | ||
6a9e7f20 AB |
82 | list_for_each_entry(entry, &dev->msi_list, list) { |
83 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 84 | if (ret < 0) |
6a9e7f20 | 85 | return ret; |
b5fbf533 ME |
86 | if (ret > 0) |
87 | return -ENOSPC; | |
6a9e7f20 AB |
88 | } |
89 | ||
90 | return 0; | |
91 | } | |
1525bf0d | 92 | |
4287d824 TP |
93 | /* |
94 | * We have a default implementation available as a separate non-weak | |
95 | * function, as it is used by the Xen x86 PCI code | |
96 | */ | |
1525bf0d | 97 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
98 | { |
99 | struct msi_desc *entry; | |
100 | ||
101 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
102 | int i, nvec; |
103 | if (entry->irq == 0) | |
104 | continue; | |
65f6ae66 AG |
105 | if (entry->nvec_used) |
106 | nvec = entry->nvec_used; | |
107 | else | |
108 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
109 | for (i = 0; i < nvec; i++) |
110 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
111 | } |
112 | } | |
113 | ||
4287d824 TP |
114 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
115 | { | |
116 | return default_teardown_msi_irqs(dev); | |
117 | } | |
76ccc297 | 118 | |
ac8344c4 | 119 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
120 | { |
121 | struct msi_desc *entry; | |
122 | ||
123 | entry = NULL; | |
124 | if (dev->msix_enabled) { | |
125 | list_for_each_entry(entry, &dev->msi_list, list) { | |
126 | if (irq == entry->irq) | |
127 | break; | |
128 | } | |
129 | } else if (dev->msi_enabled) { | |
130 | entry = irq_get_msi_desc(irq); | |
131 | } | |
132 | ||
133 | if (entry) | |
134 | write_msi_msg(irq, &entry->msg); | |
135 | } | |
4287d824 | 136 | |
ac8344c4 | 137 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 138 | { |
ac8344c4 | 139 | return default_restore_msi_irqs(dev); |
4287d824 | 140 | } |
76ccc297 | 141 | |
e375b561 | 142 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 143 | { |
b1cbf4e4 EB |
144 | u16 control; |
145 | ||
e375b561 | 146 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
147 | control &= ~PCI_MSI_FLAGS_ENABLE; |
148 | if (enable) | |
149 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 150 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
151 | } |
152 | ||
b1cbf4e4 EB |
153 | static void msix_set_enable(struct pci_dev *dev, int enable) |
154 | { | |
b1cbf4e4 EB |
155 | u16 control; |
156 | ||
e375b561 GS |
157 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
158 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
159 | if (enable) | |
160 | control |= PCI_MSIX_FLAGS_ENABLE; | |
161 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); | |
b1cbf4e4 EB |
162 | } |
163 | ||
bffac3c5 MW |
164 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
165 | { | |
0b49ec37 MW |
166 | /* Don't shift by >= width of type */ |
167 | if (x >= 5) | |
168 | return 0xffffffff; | |
169 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
170 | } |
171 | ||
f2440d9a | 172 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 173 | { |
f2440d9a MW |
174 | return msi_mask((control >> 1) & 7); |
175 | } | |
988cbb15 | 176 | |
f2440d9a MW |
177 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
178 | { | |
179 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
180 | } |
181 | ||
ce6fce42 MW |
182 | /* |
183 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
184 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
185 | * reliably as devices without an INTx disable bit will then generate a | |
186 | * level IRQ which will never be cleared. | |
ce6fce42 | 187 | */ |
0e4ccb15 | 188 | u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 189 | { |
f2440d9a | 190 | u32 mask_bits = desc->masked; |
1da177e4 | 191 | |
f2440d9a | 192 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 193 | return 0; |
f2440d9a MW |
194 | |
195 | mask_bits &= ~mask; | |
196 | mask_bits |= flag; | |
197 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
198 | |
199 | return mask_bits; | |
200 | } | |
201 | ||
0e4ccb15 KRW |
202 | __weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
203 | { | |
204 | return default_msi_mask_irq(desc, mask, flag); | |
205 | } | |
206 | ||
12abb8ba HS |
207 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
208 | { | |
0e4ccb15 | 209 | desc->masked = arch_msi_mask_irq(desc, mask, flag); |
f2440d9a MW |
210 | } |
211 | ||
212 | /* | |
213 | * This internal function does not flush PCI writes to the device. | |
214 | * All users must ensure that they read from the device before either | |
215 | * assuming that the device state is up to date, or returning out of this | |
216 | * file. This saves a few milliseconds when initialising devices with lots | |
217 | * of MSI-X interrupts. | |
218 | */ | |
0e4ccb15 | 219 | u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
220 | { |
221 | u32 mask_bits = desc->masked; | |
222 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 223 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
224 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
225 | if (flag) | |
226 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 227 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
228 | |
229 | return mask_bits; | |
230 | } | |
231 | ||
0e4ccb15 KRW |
232 | __weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag) |
233 | { | |
234 | return default_msix_mask_irq(desc, flag); | |
235 | } | |
236 | ||
12abb8ba HS |
237 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) |
238 | { | |
0e4ccb15 | 239 | desc->masked = arch_msix_mask_irq(desc, flag); |
f2440d9a | 240 | } |
24d27553 | 241 | |
1c9db525 | 242 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 243 | { |
1c9db525 | 244 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 245 | |
f2440d9a MW |
246 | if (desc->msi_attrib.is_msix) { |
247 | msix_mask_irq(desc, flag); | |
248 | readl(desc->mask_base); /* Flush write to device */ | |
249 | } else { | |
1c9db525 | 250 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 251 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 252 | } |
f2440d9a MW |
253 | } |
254 | ||
1c9db525 | 255 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 256 | { |
1c9db525 | 257 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
258 | } |
259 | ||
1c9db525 | 260 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 261 | { |
1c9db525 | 262 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
263 | } |
264 | ||
ac8344c4 D |
265 | void default_restore_msi_irqs(struct pci_dev *dev) |
266 | { | |
267 | struct msi_desc *entry; | |
268 | ||
269 | list_for_each_entry(entry, &dev->msi_list, list) { | |
270 | default_restore_msi_irq(dev, entry->irq); | |
271 | } | |
272 | } | |
273 | ||
39431acb | 274 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 275 | { |
30da5524 BH |
276 | BUG_ON(entry->dev->current_state != PCI_D0); |
277 | ||
278 | if (entry->msi_attrib.is_msix) { | |
279 | void __iomem *base = entry->mask_base + | |
280 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
281 | ||
282 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
283 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
284 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
285 | } else { | |
286 | struct pci_dev *dev = entry->dev; | |
f5322169 | 287 | int pos = dev->msi_cap; |
30da5524 BH |
288 | u16 data; |
289 | ||
9925ad0c BH |
290 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
291 | &msg->address_lo); | |
30da5524 | 292 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
293 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
294 | &msg->address_hi); | |
2f221349 | 295 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
296 | } else { |
297 | msg->address_hi = 0; | |
2f221349 | 298 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
299 | } |
300 | msg->data = data; | |
301 | } | |
302 | } | |
303 | ||
304 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
305 | { | |
dced35ae | 306 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 307 | |
39431acb | 308 | __read_msi_msg(entry, msg); |
30da5524 BH |
309 | } |
310 | ||
39431acb | 311 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 312 | { |
30da5524 | 313 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
314 | * valid messages are not all-zeroes. */ |
315 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
316 | entry->msg.data)); | |
0366f8f7 | 317 | |
fcd097f3 | 318 | *msg = entry->msg; |
0366f8f7 | 319 | } |
1da177e4 | 320 | |
30da5524 | 321 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 322 | { |
dced35ae | 323 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 324 | |
39431acb | 325 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
326 | } |
327 | ||
39431acb | 328 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 329 | { |
fcd097f3 BH |
330 | if (entry->dev->current_state != PCI_D0) { |
331 | /* Don't touch the hardware now */ | |
332 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
333 | void __iomem *base; |
334 | base = entry->mask_base + | |
335 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
336 | ||
2c21fd4b HS |
337 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
338 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
339 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 340 | } else { |
0366f8f7 | 341 | struct pci_dev *dev = entry->dev; |
f5322169 | 342 | int pos = dev->msi_cap; |
1c8d7b0a MW |
343 | u16 msgctl; |
344 | ||
f84ecd28 | 345 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
346 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
347 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 348 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 349 | |
9925ad0c BH |
350 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
351 | msg->address_lo); | |
0366f8f7 | 352 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
353 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
354 | msg->address_hi); | |
2f221349 BH |
355 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
356 | msg->data); | |
0366f8f7 | 357 | } else { |
2f221349 BH |
358 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
359 | msg->data); | |
0366f8f7 | 360 | } |
1da177e4 | 361 | } |
392ee1e6 | 362 | entry->msg = *msg; |
1da177e4 | 363 | } |
0366f8f7 | 364 | |
3145e941 YL |
365 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
366 | { | |
dced35ae | 367 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 368 | |
39431acb | 369 | __write_msi_msg(entry, msg); |
3145e941 YL |
370 | } |
371 | ||
f56e4481 HS |
372 | static void free_msi_irqs(struct pci_dev *dev) |
373 | { | |
374 | struct msi_desc *entry, *tmp; | |
375 | ||
376 | list_for_each_entry(entry, &dev->msi_list, list) { | |
377 | int i, nvec; | |
378 | if (!entry->irq) | |
379 | continue; | |
65f6ae66 AG |
380 | if (entry->nvec_used) |
381 | nvec = entry->nvec_used; | |
382 | else | |
383 | nvec = 1 << entry->msi_attrib.multiple; | |
f56e4481 HS |
384 | for (i = 0; i < nvec; i++) |
385 | BUG_ON(irq_has_action(entry->irq + i)); | |
386 | } | |
387 | ||
388 | arch_teardown_msi_irqs(dev); | |
389 | ||
390 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
391 | if (entry->msi_attrib.is_msix) { | |
392 | if (list_is_last(&entry->list, &dev->msi_list)) | |
393 | iounmap(entry->mask_base); | |
394 | } | |
424eb391 NH |
395 | |
396 | /* | |
397 | * Its possible that we get into this path | |
398 | * When populate_msi_sysfs fails, which means the entries | |
399 | * were not registered with sysfs. In that case don't | |
400 | * unregister them. | |
401 | */ | |
402 | if (entry->kobj.parent) { | |
403 | kobject_del(&entry->kobj); | |
404 | kobject_put(&entry->kobj); | |
405 | } | |
406 | ||
f56e4481 HS |
407 | list_del(&entry->list); |
408 | kfree(entry); | |
409 | } | |
410 | } | |
c54c1879 | 411 | |
379f5327 | 412 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 413 | { |
379f5327 MW |
414 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
415 | if (!desc) | |
1da177e4 LT |
416 | return NULL; |
417 | ||
379f5327 MW |
418 | INIT_LIST_HEAD(&desc->list); |
419 | desc->dev = dev; | |
1da177e4 | 420 | |
379f5327 | 421 | return desc; |
1da177e4 LT |
422 | } |
423 | ||
ba698ad4 DM |
424 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
425 | { | |
426 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
427 | pci_intx(dev, enable); | |
428 | } | |
429 | ||
8fed4b65 | 430 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 431 | { |
41017f0c | 432 | u16 control; |
392ee1e6 | 433 | struct msi_desc *entry; |
41017f0c | 434 | |
b1cbf4e4 EB |
435 | if (!dev->msi_enabled) |
436 | return; | |
437 | ||
dced35ae | 438 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 439 | |
ba698ad4 | 440 | pci_intx_for_msi(dev, 0); |
e375b561 | 441 | msi_set_enable(dev, 0); |
ac8344c4 | 442 | arch_restore_msi_irqs(dev); |
392ee1e6 | 443 | |
f5322169 | 444 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
f2440d9a | 445 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 446 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 447 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 448 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
449 | } |
450 | ||
451 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 452 | { |
41017f0c | 453 | struct msi_desc *entry; |
392ee1e6 | 454 | u16 control; |
41017f0c | 455 | |
ded86d8d EB |
456 | if (!dev->msix_enabled) |
457 | return; | |
f598282f | 458 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 459 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f5322169 | 460 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
ded86d8d | 461 | |
41017f0c | 462 | /* route the table */ |
ba698ad4 | 463 | pci_intx_for_msi(dev, 0); |
f598282f | 464 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 465 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 466 | |
ac8344c4 | 467 | arch_restore_msi_irqs(dev); |
4aa9bc95 | 468 | list_for_each_entry(entry, &dev->msi_list, list) { |
f2440d9a | 469 | msix_mask_irq(entry, entry->masked); |
41017f0c | 470 | } |
41017f0c | 471 | |
392ee1e6 | 472 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 473 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 474 | } |
8fed4b65 ME |
475 | |
476 | void pci_restore_msi_state(struct pci_dev *dev) | |
477 | { | |
478 | __pci_restore_msi_state(dev); | |
479 | __pci_restore_msix_state(dev); | |
480 | } | |
94688cf2 | 481 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 482 | |
da8d1c8b NH |
483 | |
484 | #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr) | |
485 | #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj) | |
486 | ||
487 | struct msi_attribute { | |
488 | struct attribute attr; | |
489 | ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr, | |
490 | char *buf); | |
491 | ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr, | |
492 | const char *buf, size_t count); | |
493 | }; | |
494 | ||
495 | static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr, | |
496 | char *buf) | |
497 | { | |
498 | return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi"); | |
499 | } | |
500 | ||
501 | static ssize_t msi_irq_attr_show(struct kobject *kobj, | |
502 | struct attribute *attr, char *buf) | |
503 | { | |
504 | struct msi_attribute *attribute = to_msi_attr(attr); | |
505 | struct msi_desc *entry = to_msi_desc(kobj); | |
506 | ||
507 | if (!attribute->show) | |
508 | return -EIO; | |
509 | ||
510 | return attribute->show(entry, attribute, buf); | |
511 | } | |
512 | ||
513 | static const struct sysfs_ops msi_irq_sysfs_ops = { | |
514 | .show = msi_irq_attr_show, | |
515 | }; | |
516 | ||
517 | static struct msi_attribute mode_attribute = | |
518 | __ATTR(mode, S_IRUGO, show_msi_mode, NULL); | |
519 | ||
520 | ||
9738abed | 521 | static struct attribute *msi_irq_default_attrs[] = { |
da8d1c8b NH |
522 | &mode_attribute.attr, |
523 | NULL | |
524 | }; | |
525 | ||
9738abed | 526 | static void msi_kobj_release(struct kobject *kobj) |
da8d1c8b NH |
527 | { |
528 | struct msi_desc *entry = to_msi_desc(kobj); | |
529 | ||
530 | pci_dev_put(entry->dev); | |
531 | } | |
532 | ||
533 | static struct kobj_type msi_irq_ktype = { | |
534 | .release = msi_kobj_release, | |
535 | .sysfs_ops = &msi_irq_sysfs_ops, | |
536 | .default_attrs = msi_irq_default_attrs, | |
537 | }; | |
538 | ||
539 | static int populate_msi_sysfs(struct pci_dev *pdev) | |
540 | { | |
541 | struct msi_desc *entry; | |
542 | struct kobject *kobj; | |
543 | int ret; | |
544 | int count = 0; | |
545 | ||
546 | pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj); | |
547 | if (!pdev->msi_kset) | |
548 | return -ENOMEM; | |
549 | ||
550 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
551 | kobj = &entry->kobj; | |
552 | kobj->kset = pdev->msi_kset; | |
553 | pci_dev_get(pdev); | |
554 | ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL, | |
555 | "%u", entry->irq); | |
556 | if (ret) | |
557 | goto out_unroll; | |
558 | ||
559 | count++; | |
560 | } | |
561 | ||
562 | return 0; | |
563 | ||
564 | out_unroll: | |
565 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
566 | if (!count) | |
567 | break; | |
568 | kobject_del(&entry->kobj); | |
569 | kobject_put(&entry->kobj); | |
570 | count--; | |
571 | } | |
572 | return ret; | |
573 | } | |
574 | ||
1da177e4 LT |
575 | /** |
576 | * msi_capability_init - configure device's MSI capability structure | |
577 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 578 | * @nvec: number of interrupts to allocate |
1da177e4 | 579 | * |
1c8d7b0a MW |
580 | * Setup the MSI capability structure of the device with the requested |
581 | * number of interrupts. A return value of zero indicates the successful | |
582 | * setup of an entry with the new MSI irq. A negative return value indicates | |
583 | * an error, and a positive return value indicates the number of interrupts | |
584 | * which could have been allocated. | |
585 | */ | |
586 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
587 | { |
588 | struct msi_desc *entry; | |
f465136d | 589 | int ret; |
1da177e4 | 590 | u16 control; |
f2440d9a | 591 | unsigned mask; |
1da177e4 | 592 | |
e375b561 | 593 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 594 | |
f84ecd28 | 595 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
1da177e4 | 596 | /* MSI Entry Initialization */ |
379f5327 | 597 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
598 | if (!entry) |
599 | return -ENOMEM; | |
1ce03373 | 600 | |
500559a9 | 601 | entry->msi_attrib.is_msix = 0; |
4987ce82 | 602 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); |
500559a9 | 603 | entry->msi_attrib.entry_nr = 0; |
4987ce82 | 604 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); |
500559a9 | 605 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
f465136d | 606 | entry->msi_attrib.pos = dev->msi_cap; |
f2440d9a | 607 | |
e5f66eaf DC |
608 | if (control & PCI_MSI_FLAGS_64BIT) |
609 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
610 | else | |
611 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
f2440d9a MW |
612 | /* All MSIs are unmasked by default, Mask them all */ |
613 | if (entry->msi_attrib.maskbit) | |
614 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
615 | mask = msi_capable_mask(control); | |
616 | msi_mask_irq(entry, mask, mask); | |
617 | ||
0dd11f9b | 618 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 619 | |
1da177e4 | 620 | /* Configure MSI capability structure */ |
1c8d7b0a | 621 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 622 | if (ret) { |
7ba1930d | 623 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 624 | free_msi_irqs(dev); |
7fe3730d | 625 | return ret; |
fd58e55f | 626 | } |
f7feaca7 | 627 | |
da8d1c8b NH |
628 | ret = populate_msi_sysfs(dev); |
629 | if (ret) { | |
630 | msi_mask_irq(entry, mask, ~mask); | |
631 | free_msi_irqs(dev); | |
632 | return ret; | |
633 | } | |
634 | ||
1da177e4 | 635 | /* Set MSI enabled bits */ |
ba698ad4 | 636 | pci_intx_for_msi(dev, 0); |
e375b561 | 637 | msi_set_enable(dev, 1); |
b1cbf4e4 | 638 | dev->msi_enabled = 1; |
1da177e4 | 639 | |
7fe3730d | 640 | dev->irq = entry->irq; |
1da177e4 LT |
641 | return 0; |
642 | } | |
643 | ||
520fe9dc | 644 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 645 | { |
4302e0fb | 646 | resource_size_t phys_addr; |
5a05a9d8 HS |
647 | u32 table_offset; |
648 | u8 bir; | |
649 | ||
909094c6 BH |
650 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
651 | &table_offset); | |
4d18760c BH |
652 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
653 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
654 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
655 | ||
656 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
657 | } | |
658 | ||
520fe9dc GS |
659 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
660 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
661 | { |
662 | struct msi_desc *entry; | |
663 | int i; | |
664 | ||
665 | for (i = 0; i < nvec; i++) { | |
666 | entry = alloc_msi_entry(dev); | |
667 | if (!entry) { | |
668 | if (!i) | |
669 | iounmap(base); | |
670 | else | |
671 | free_msi_irqs(dev); | |
672 | /* No enough memory. Don't try again */ | |
673 | return -ENOMEM; | |
674 | } | |
675 | ||
676 | entry->msi_attrib.is_msix = 1; | |
677 | entry->msi_attrib.is_64 = 1; | |
678 | entry->msi_attrib.entry_nr = entries[i].entry; | |
679 | entry->msi_attrib.default_irq = dev->irq; | |
520fe9dc | 680 | entry->msi_attrib.pos = dev->msix_cap; |
d9d7070e HS |
681 | entry->mask_base = base; |
682 | ||
683 | list_add_tail(&entry->list, &dev->msi_list); | |
684 | } | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
75cb3426 | 689 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 690 | struct msix_entry *entries) |
75cb3426 HS |
691 | { |
692 | struct msi_desc *entry; | |
693 | int i = 0; | |
694 | ||
695 | list_for_each_entry(entry, &dev->msi_list, list) { | |
696 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
697 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
698 | ||
699 | entries[i].vector = entry->irq; | |
dced35ae | 700 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
701 | entry->masked = readl(entry->mask_base + offset); |
702 | msix_mask_irq(entry, 1); | |
703 | i++; | |
704 | } | |
705 | } | |
706 | ||
1da177e4 LT |
707 | /** |
708 | * msix_capability_init - configure device's MSI-X capability | |
709 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
710 | * @entries: pointer to an array of struct msix_entry entries |
711 | * @nvec: number of @entries | |
1da177e4 | 712 | * |
eaae4b3a | 713 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
714 | * single MSI-X irq. A return of zero indicates the successful setup of |
715 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
716 | **/ |
717 | static int msix_capability_init(struct pci_dev *dev, | |
718 | struct msix_entry *entries, int nvec) | |
719 | { | |
520fe9dc | 720 | int ret; |
5a05a9d8 | 721 | u16 control; |
1da177e4 LT |
722 | void __iomem *base; |
723 | ||
520fe9dc | 724 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
f598282f MW |
725 | |
726 | /* Ensure MSI-X is disabled while it is set up */ | |
727 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 728 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 729 | |
1da177e4 | 730 | /* Request & Map MSI-X table region */ |
527eee29 | 731 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 732 | if (!base) |
1da177e4 LT |
733 | return -ENOMEM; |
734 | ||
520fe9dc | 735 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
736 | if (ret) |
737 | return ret; | |
9c831334 ME |
738 | |
739 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
740 | if (ret) |
741 | goto error; | |
9c831334 | 742 | |
f598282f MW |
743 | /* |
744 | * Some devices require MSI-X to be enabled before we can touch the | |
745 | * MSI-X registers. We need to mask all the vectors to prevent | |
746 | * interrupts coming in before they're fully set up. | |
747 | */ | |
748 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 749 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 750 | |
75cb3426 | 751 | msix_program_entries(dev, entries); |
f598282f | 752 | |
da8d1c8b NH |
753 | ret = populate_msi_sysfs(dev); |
754 | if (ret) { | |
755 | ret = 0; | |
756 | goto error; | |
757 | } | |
758 | ||
f598282f | 759 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 760 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 761 | dev->msix_enabled = 1; |
1da177e4 | 762 | |
f598282f | 763 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
520fe9dc | 764 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
8d181018 | 765 | |
1da177e4 | 766 | return 0; |
583871d4 HS |
767 | |
768 | error: | |
769 | if (ret < 0) { | |
770 | /* | |
771 | * If we had some success, report the number of irqs | |
772 | * we succeeded in setting up. | |
773 | */ | |
d9d7070e | 774 | struct msi_desc *entry; |
583871d4 HS |
775 | int avail = 0; |
776 | ||
777 | list_for_each_entry(entry, &dev->msi_list, list) { | |
778 | if (entry->irq != 0) | |
779 | avail++; | |
780 | } | |
781 | if (avail != 0) | |
782 | ret = avail; | |
783 | } | |
784 | ||
785 | free_msi_irqs(dev); | |
786 | ||
787 | return ret; | |
1da177e4 LT |
788 | } |
789 | ||
24334a12 | 790 | /** |
17bbc12a | 791 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 792 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 793 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 794 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 795 | * |
f7625980 | 796 | * Look at global flags, the device itself, and its parent buses |
17bbc12a ME |
797 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
798 | * supported return 0, else return an error code. | |
24334a12 | 799 | **/ |
500559a9 | 800 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
801 | { |
802 | struct pci_bus *bus; | |
c9953a73 | 803 | int ret; |
24334a12 | 804 | |
0306ebfa | 805 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
806 | if (!pci_msi_enable || !dev || dev->no_msi) |
807 | return -EINVAL; | |
808 | ||
314e77b3 ME |
809 | /* |
810 | * You can't ask to have 0 or less MSIs configured. | |
811 | * a) it's stupid .. | |
812 | * b) the list manipulation code assumes nvec >= 1. | |
813 | */ | |
814 | if (nvec < 1) | |
815 | return -ERANGE; | |
816 | ||
500559a9 HS |
817 | /* |
818 | * Any bridge which does NOT route MSI transactions from its | |
819 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
820 | * the secondary pci_bus. |
821 | * We expect only arch-specific PCI host bus controller driver | |
822 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
823 | */ | |
24334a12 BG |
824 | for (bus = dev->bus; bus; bus = bus->parent) |
825 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
826 | return -EINVAL; | |
827 | ||
c9953a73 ME |
828 | ret = arch_msi_check_device(dev, nvec, type); |
829 | if (ret) | |
830 | return ret; | |
831 | ||
24334a12 BG |
832 | return 0; |
833 | } | |
834 | ||
1da177e4 | 835 | /** |
1c8d7b0a MW |
836 | * pci_enable_msi_block - configure device's MSI capability structure |
837 | * @dev: device to configure | |
838 | * @nvec: number of interrupts to configure | |
1da177e4 | 839 | * |
1c8d7b0a MW |
840 | * Allocate IRQs for a device with the MSI capability. |
841 | * This function returns a negative errno if an error occurs. If it | |
842 | * is unable to allocate the number of interrupts requested, it returns | |
843 | * the number of interrupts it might be able to allocate. If it successfully | |
844 | * allocates at least the number of interrupts requested, it returns 0 and | |
845 | * updates the @dev's irq member to the lowest new interrupt number; the | |
846 | * other interrupt numbers allocated to this device are consecutive. | |
847 | */ | |
848 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 849 | { |
f465136d | 850 | int status, maxvec; |
1c8d7b0a MW |
851 | u16 msgctl; |
852 | ||
869a1615 | 853 | if (!dev->msi_cap || dev->current_state != PCI_D0) |
1c8d7b0a | 854 | return -EINVAL; |
f465136d GS |
855 | |
856 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
1c8d7b0a MW |
857 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
858 | if (nvec > maxvec) | |
859 | return maxvec; | |
1da177e4 | 860 | |
1c8d7b0a | 861 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
862 | if (status) |
863 | return status; | |
1da177e4 | 864 | |
ded86d8d | 865 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 866 | |
1c8d7b0a | 867 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 868 | if (dev->msix_enabled) { |
80ccba11 BH |
869 | dev_info(&dev->dev, "can't enable MSI " |
870 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 871 | return -EINVAL; |
1da177e4 | 872 | } |
1c8d7b0a MW |
873 | |
874 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
875 | return status; |
876 | } | |
1c8d7b0a | 877 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 878 | |
08261d87 AG |
879 | int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) |
880 | { | |
f465136d | 881 | int ret, nvec; |
08261d87 AG |
882 | u16 msgctl; |
883 | ||
869a1615 | 884 | if (!dev->msi_cap || dev->current_state != PCI_D0) |
08261d87 AG |
885 | return -EINVAL; |
886 | ||
f465136d | 887 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); |
08261d87 AG |
888 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
889 | ||
890 | if (maxvec) | |
891 | *maxvec = ret; | |
892 | ||
893 | do { | |
894 | nvec = ret; | |
895 | ret = pci_enable_msi_block(dev, nvec); | |
896 | } while (ret > 0); | |
897 | ||
898 | if (ret < 0) | |
899 | return ret; | |
900 | return nvec; | |
901 | } | |
902 | EXPORT_SYMBOL(pci_enable_msi_block_auto); | |
903 | ||
f2440d9a | 904 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 905 | { |
f2440d9a MW |
906 | struct msi_desc *desc; |
907 | u32 mask; | |
908 | u16 ctrl; | |
1da177e4 | 909 | |
128bc5fc | 910 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
911 | return; |
912 | ||
110828c9 MW |
913 | BUG_ON(list_empty(&dev->msi_list)); |
914 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 915 | |
e375b561 | 916 | msi_set_enable(dev, 0); |
ba698ad4 | 917 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 918 | dev->msi_enabled = 0; |
7bd007e4 | 919 | |
12abb8ba | 920 | /* Return the device with MSI unmasked as initial states */ |
f5322169 | 921 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 922 | mask = msi_capable_mask(ctrl); |
12abb8ba | 923 | /* Keep cached state to be restored */ |
0e4ccb15 | 924 | arch_msi_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
925 | |
926 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 927 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 928 | } |
24d27553 | 929 | |
500559a9 | 930 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 931 | { |
d52877c7 YL |
932 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
933 | return; | |
934 | ||
935 | pci_msi_shutdown(dev); | |
f56e4481 | 936 | free_msi_irqs(dev); |
da8d1c8b NH |
937 | kset_unregister(dev->msi_kset); |
938 | dev->msi_kset = NULL; | |
1da177e4 | 939 | } |
4cc086fa | 940 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 941 | |
a52e2e35 RW |
942 | /** |
943 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
944 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
945 | */ | |
946 | int pci_msix_table_size(struct pci_dev *dev) | |
947 | { | |
a52e2e35 RW |
948 | u16 control; |
949 | ||
520fe9dc | 950 | if (!dev->msix_cap) |
a52e2e35 RW |
951 | return 0; |
952 | ||
f84ecd28 | 953 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 954 | return msix_table_size(control); |
a52e2e35 RW |
955 | } |
956 | ||
1da177e4 LT |
957 | /** |
958 | * pci_enable_msix - configure device's MSI-X capability structure | |
959 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 960 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 961 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
962 | * |
963 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 964 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
965 | * MSI-X mode enabled on its hardware device function. A return of zero |
966 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 967 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 968 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
969 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
970 | * re-send its request. | |
1da177e4 | 971 | **/ |
500559a9 | 972 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 973 | { |
a52e2e35 | 974 | int status, nr_entries; |
ded86d8d | 975 | int i, j; |
1da177e4 | 976 | |
869a1615 | 977 | if (!entries || !dev->msix_cap || dev->current_state != PCI_D0) |
500559a9 | 978 | return -EINVAL; |
1da177e4 | 979 | |
c9953a73 ME |
980 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
981 | if (status) | |
982 | return status; | |
983 | ||
a52e2e35 | 984 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 985 | if (nvec > nr_entries) |
57fbf52c | 986 | return nr_entries; |
1da177e4 LT |
987 | |
988 | /* Check for any invalid entries */ | |
989 | for (i = 0; i < nvec; i++) { | |
990 | if (entries[i].entry >= nr_entries) | |
991 | return -EINVAL; /* invalid entry */ | |
992 | for (j = i + 1; j < nvec; j++) { | |
993 | if (entries[i].entry == entries[j].entry) | |
994 | return -EINVAL; /* duplicate entry */ | |
995 | } | |
996 | } | |
ded86d8d | 997 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 998 | |
1ce03373 | 999 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 1000 | if (dev->msi_enabled) { |
80ccba11 BH |
1001 | dev_info(&dev->dev, "can't enable MSI-X " |
1002 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
1003 | return -EINVAL; |
1004 | } | |
1da177e4 | 1005 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
1006 | return status; |
1007 | } | |
4cc086fa | 1008 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 1009 | |
500559a9 | 1010 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 1011 | { |
12abb8ba HS |
1012 | struct msi_desc *entry; |
1013 | ||
128bc5fc | 1014 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
1015 | return; |
1016 | ||
12abb8ba HS |
1017 | /* Return the device with MSI-X masked as initial states */ |
1018 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1019 | /* Keep cached states to be restored */ | |
0e4ccb15 | 1020 | arch_msix_mask_irq(entry, 1); |
12abb8ba HS |
1021 | } |
1022 | ||
b1cbf4e4 | 1023 | msix_set_enable(dev, 0); |
ba698ad4 | 1024 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1025 | dev->msix_enabled = 0; |
d52877c7 | 1026 | } |
c901851f | 1027 | |
500559a9 | 1028 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1029 | { |
1030 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1031 | return; | |
1032 | ||
1033 | pci_msix_shutdown(dev); | |
f56e4481 | 1034 | free_msi_irqs(dev); |
da8d1c8b NH |
1035 | kset_unregister(dev->msi_kset); |
1036 | dev->msi_kset = NULL; | |
1da177e4 | 1037 | } |
4cc086fa | 1038 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
1039 | |
1040 | /** | |
1ce03373 | 1041 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1042 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1043 | * | |
eaae4b3a | 1044 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1045 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1046 | * allocated for this device function, are reclaimed to unused state, |
1047 | * which may be used later on. | |
1048 | **/ | |
500559a9 | 1049 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 1050 | { |
1da177e4 | 1051 | if (!pci_msi_enable || !dev) |
500559a9 | 1052 | return; |
1da177e4 | 1053 | |
f56e4481 HS |
1054 | if (dev->msi_enabled || dev->msix_enabled) |
1055 | free_msi_irqs(dev); | |
1da177e4 LT |
1056 | } |
1057 | ||
309e57df MW |
1058 | void pci_no_msi(void) |
1059 | { | |
1060 | pci_msi_enable = 0; | |
1061 | } | |
c9953a73 | 1062 | |
07ae95f9 AP |
1063 | /** |
1064 | * pci_msi_enabled - is MSI enabled? | |
1065 | * | |
1066 | * Returns true if MSI has not been disabled by the command-line option | |
1067 | * pci=nomsi. | |
1068 | **/ | |
1069 | int pci_msi_enabled(void) | |
d389fec6 | 1070 | { |
07ae95f9 | 1071 | return pci_msi_enable; |
d389fec6 | 1072 | } |
07ae95f9 | 1073 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1074 | |
07ae95f9 | 1075 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1076 | { |
07ae95f9 | 1077 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1078 | |
1079 | /* Disable the msi hardware to avoid screaming interrupts | |
1080 | * during boot. This is the power on reset default so | |
1081 | * usually this should be a noop. | |
1082 | */ | |
e375b561 GS |
1083 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1084 | if (dev->msi_cap) | |
1085 | msi_set_enable(dev, 0); | |
1086 | ||
1087 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1088 | if (dev->msix_cap) | |
1089 | msix_set_enable(dev, 0); | |
d389fec6 | 1090 | } |