Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
1da177e4 | 25 | |
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
527eee29 BH |
28 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
29 | ||
30 | ||
6a9e7f20 AB |
31 | /* Arch hooks */ |
32 | ||
4287d824 TP |
33 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
34 | { | |
0cbdcfcf TR |
35 | struct msi_chip *chip = dev->bus->msi; |
36 | int err; | |
37 | ||
38 | if (!chip || !chip->setup_irq) | |
39 | return -EINVAL; | |
40 | ||
41 | err = chip->setup_irq(chip, dev, desc); | |
42 | if (err < 0) | |
43 | return err; | |
44 | ||
45 | irq_set_chip_data(desc->irq, chip); | |
46 | ||
47 | return 0; | |
4287d824 TP |
48 | } |
49 | ||
50 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 51 | { |
0cbdcfcf TR |
52 | struct msi_chip *chip = irq_get_chip_data(irq); |
53 | ||
54 | if (!chip || !chip->teardown_irq) | |
55 | return; | |
56 | ||
57 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
58 | } |
59 | ||
4287d824 TP |
60 | int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) |
61 | { | |
0cbdcfcf TR |
62 | struct msi_chip *chip = dev->bus->msi; |
63 | ||
64 | if (!chip || !chip->check_device) | |
65 | return 0; | |
66 | ||
67 | return chip->check_device(chip, dev, nvec, type); | |
4287d824 | 68 | } |
1525bf0d | 69 | |
4287d824 | 70 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
71 | { |
72 | struct msi_desc *entry; | |
73 | int ret; | |
74 | ||
1c8d7b0a MW |
75 | /* |
76 | * If an architecture wants to support multiple MSI, it needs to | |
77 | * override arch_setup_msi_irqs() | |
78 | */ | |
79 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
80 | return 1; | |
81 | ||
6a9e7f20 AB |
82 | list_for_each_entry(entry, &dev->msi_list, list) { |
83 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 84 | if (ret < 0) |
6a9e7f20 | 85 | return ret; |
b5fbf533 ME |
86 | if (ret > 0) |
87 | return -ENOSPC; | |
6a9e7f20 AB |
88 | } |
89 | ||
90 | return 0; | |
91 | } | |
1525bf0d | 92 | |
4287d824 TP |
93 | /* |
94 | * We have a default implementation available as a separate non-weak | |
95 | * function, as it is used by the Xen x86 PCI code | |
96 | */ | |
1525bf0d | 97 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
98 | { |
99 | struct msi_desc *entry; | |
100 | ||
101 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
102 | int i, nvec; |
103 | if (entry->irq == 0) | |
104 | continue; | |
65f6ae66 AG |
105 | if (entry->nvec_used) |
106 | nvec = entry->nvec_used; | |
107 | else | |
108 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
109 | for (i = 0; i < nvec; i++) |
110 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
111 | } |
112 | } | |
113 | ||
4287d824 TP |
114 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
115 | { | |
116 | return default_teardown_msi_irqs(dev); | |
117 | } | |
76ccc297 | 118 | |
76ccc297 KRW |
119 | void default_restore_msi_irqs(struct pci_dev *dev, int irq) |
120 | { | |
121 | struct msi_desc *entry; | |
122 | ||
123 | entry = NULL; | |
124 | if (dev->msix_enabled) { | |
125 | list_for_each_entry(entry, &dev->msi_list, list) { | |
126 | if (irq == entry->irq) | |
127 | break; | |
128 | } | |
129 | } else if (dev->msi_enabled) { | |
130 | entry = irq_get_msi_desc(irq); | |
131 | } | |
132 | ||
133 | if (entry) | |
134 | write_msi_msg(irq, &entry->msg); | |
135 | } | |
4287d824 TP |
136 | |
137 | void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq) | |
138 | { | |
139 | return default_restore_msi_irqs(dev, irq); | |
140 | } | |
76ccc297 | 141 | |
e375b561 | 142 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 143 | { |
b1cbf4e4 EB |
144 | u16 control; |
145 | ||
e375b561 | 146 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
147 | control &= ~PCI_MSI_FLAGS_ENABLE; |
148 | if (enable) | |
149 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 150 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
151 | } |
152 | ||
b1cbf4e4 EB |
153 | static void msix_set_enable(struct pci_dev *dev, int enable) |
154 | { | |
b1cbf4e4 EB |
155 | u16 control; |
156 | ||
e375b561 GS |
157 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
158 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
159 | if (enable) | |
160 | control |= PCI_MSIX_FLAGS_ENABLE; | |
161 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); | |
b1cbf4e4 EB |
162 | } |
163 | ||
bffac3c5 MW |
164 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
165 | { | |
0b49ec37 MW |
166 | /* Don't shift by >= width of type */ |
167 | if (x >= 5) | |
168 | return 0xffffffff; | |
169 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
170 | } |
171 | ||
f2440d9a | 172 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 173 | { |
f2440d9a MW |
174 | return msi_mask((control >> 1) & 7); |
175 | } | |
988cbb15 | 176 | |
f2440d9a MW |
177 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
178 | { | |
179 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
180 | } |
181 | ||
ce6fce42 MW |
182 | /* |
183 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
184 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
185 | * reliably as devices without an INTx disable bit will then generate a | |
186 | * level IRQ which will never be cleared. | |
ce6fce42 | 187 | */ |
0e4ccb15 | 188 | u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 189 | { |
f2440d9a | 190 | u32 mask_bits = desc->masked; |
1da177e4 | 191 | |
f2440d9a | 192 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 193 | return 0; |
f2440d9a MW |
194 | |
195 | mask_bits &= ~mask; | |
196 | mask_bits |= flag; | |
197 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
198 | |
199 | return mask_bits; | |
200 | } | |
201 | ||
0e4ccb15 KRW |
202 | __weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
203 | { | |
204 | return default_msi_mask_irq(desc, mask, flag); | |
205 | } | |
206 | ||
12abb8ba HS |
207 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
208 | { | |
0e4ccb15 | 209 | desc->masked = arch_msi_mask_irq(desc, mask, flag); |
f2440d9a MW |
210 | } |
211 | ||
212 | /* | |
213 | * This internal function does not flush PCI writes to the device. | |
214 | * All users must ensure that they read from the device before either | |
215 | * assuming that the device state is up to date, or returning out of this | |
216 | * file. This saves a few milliseconds when initialising devices with lots | |
217 | * of MSI-X interrupts. | |
218 | */ | |
0e4ccb15 | 219 | u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
220 | { |
221 | u32 mask_bits = desc->masked; | |
222 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 223 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
224 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
225 | if (flag) | |
226 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 227 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
228 | |
229 | return mask_bits; | |
230 | } | |
231 | ||
0e4ccb15 KRW |
232 | __weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag) |
233 | { | |
234 | return default_msix_mask_irq(desc, flag); | |
235 | } | |
236 | ||
12abb8ba HS |
237 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) |
238 | { | |
0e4ccb15 | 239 | desc->masked = arch_msix_mask_irq(desc, flag); |
f2440d9a | 240 | } |
24d27553 | 241 | |
1c9db525 | 242 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 243 | { |
1c9db525 | 244 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 245 | |
f2440d9a MW |
246 | if (desc->msi_attrib.is_msix) { |
247 | msix_mask_irq(desc, flag); | |
248 | readl(desc->mask_base); /* Flush write to device */ | |
249 | } else { | |
1c9db525 | 250 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 251 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 252 | } |
f2440d9a MW |
253 | } |
254 | ||
1c9db525 | 255 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 256 | { |
1c9db525 | 257 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
258 | } |
259 | ||
1c9db525 | 260 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 261 | { |
1c9db525 | 262 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
263 | } |
264 | ||
39431acb | 265 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 266 | { |
30da5524 BH |
267 | BUG_ON(entry->dev->current_state != PCI_D0); |
268 | ||
269 | if (entry->msi_attrib.is_msix) { | |
270 | void __iomem *base = entry->mask_base + | |
271 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
272 | ||
273 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
274 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
275 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
276 | } else { | |
277 | struct pci_dev *dev = entry->dev; | |
f5322169 | 278 | int pos = dev->msi_cap; |
30da5524 BH |
279 | u16 data; |
280 | ||
9925ad0c BH |
281 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
282 | &msg->address_lo); | |
30da5524 | 283 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
284 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
285 | &msg->address_hi); | |
2f221349 | 286 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
287 | } else { |
288 | msg->address_hi = 0; | |
2f221349 | 289 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
290 | } |
291 | msg->data = data; | |
292 | } | |
293 | } | |
294 | ||
295 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
296 | { | |
dced35ae | 297 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 298 | |
39431acb | 299 | __read_msi_msg(entry, msg); |
30da5524 BH |
300 | } |
301 | ||
39431acb | 302 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 303 | { |
30da5524 | 304 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
305 | * valid messages are not all-zeroes. */ |
306 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
307 | entry->msg.data)); | |
0366f8f7 | 308 | |
fcd097f3 | 309 | *msg = entry->msg; |
0366f8f7 | 310 | } |
1da177e4 | 311 | |
30da5524 | 312 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 313 | { |
dced35ae | 314 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 315 | |
39431acb | 316 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
317 | } |
318 | ||
39431acb | 319 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 320 | { |
fcd097f3 BH |
321 | if (entry->dev->current_state != PCI_D0) { |
322 | /* Don't touch the hardware now */ | |
323 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
324 | void __iomem *base; |
325 | base = entry->mask_base + | |
326 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
327 | ||
2c21fd4b HS |
328 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
329 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
330 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 331 | } else { |
0366f8f7 | 332 | struct pci_dev *dev = entry->dev; |
f5322169 | 333 | int pos = dev->msi_cap; |
1c8d7b0a MW |
334 | u16 msgctl; |
335 | ||
f84ecd28 | 336 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
337 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
338 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 339 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 340 | |
9925ad0c BH |
341 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
342 | msg->address_lo); | |
0366f8f7 | 343 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
344 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
345 | msg->address_hi); | |
2f221349 BH |
346 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
347 | msg->data); | |
0366f8f7 | 348 | } else { |
2f221349 BH |
349 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
350 | msg->data); | |
0366f8f7 | 351 | } |
1da177e4 | 352 | } |
392ee1e6 | 353 | entry->msg = *msg; |
1da177e4 | 354 | } |
0366f8f7 | 355 | |
3145e941 YL |
356 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
357 | { | |
dced35ae | 358 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 359 | |
39431acb | 360 | __write_msi_msg(entry, msg); |
3145e941 YL |
361 | } |
362 | ||
f56e4481 HS |
363 | static void free_msi_irqs(struct pci_dev *dev) |
364 | { | |
365 | struct msi_desc *entry, *tmp; | |
366 | ||
367 | list_for_each_entry(entry, &dev->msi_list, list) { | |
368 | int i, nvec; | |
369 | if (!entry->irq) | |
370 | continue; | |
65f6ae66 AG |
371 | if (entry->nvec_used) |
372 | nvec = entry->nvec_used; | |
373 | else | |
374 | nvec = 1 << entry->msi_attrib.multiple; | |
f56e4481 HS |
375 | for (i = 0; i < nvec; i++) |
376 | BUG_ON(irq_has_action(entry->irq + i)); | |
377 | } | |
378 | ||
379 | arch_teardown_msi_irqs(dev); | |
380 | ||
381 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
382 | if (entry->msi_attrib.is_msix) { | |
383 | if (list_is_last(&entry->list, &dev->msi_list)) | |
384 | iounmap(entry->mask_base); | |
385 | } | |
424eb391 NH |
386 | |
387 | /* | |
388 | * Its possible that we get into this path | |
389 | * When populate_msi_sysfs fails, which means the entries | |
390 | * were not registered with sysfs. In that case don't | |
391 | * unregister them. | |
392 | */ | |
393 | if (entry->kobj.parent) { | |
394 | kobject_del(&entry->kobj); | |
395 | kobject_put(&entry->kobj); | |
396 | } | |
397 | ||
f56e4481 HS |
398 | list_del(&entry->list); |
399 | kfree(entry); | |
400 | } | |
401 | } | |
c54c1879 | 402 | |
379f5327 | 403 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 404 | { |
379f5327 MW |
405 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
406 | if (!desc) | |
1da177e4 LT |
407 | return NULL; |
408 | ||
379f5327 MW |
409 | INIT_LIST_HEAD(&desc->list); |
410 | desc->dev = dev; | |
1da177e4 | 411 | |
379f5327 | 412 | return desc; |
1da177e4 LT |
413 | } |
414 | ||
ba698ad4 DM |
415 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
416 | { | |
417 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
418 | pci_intx(dev, enable); | |
419 | } | |
420 | ||
8fed4b65 | 421 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 422 | { |
41017f0c | 423 | u16 control; |
392ee1e6 | 424 | struct msi_desc *entry; |
41017f0c | 425 | |
b1cbf4e4 EB |
426 | if (!dev->msi_enabled) |
427 | return; | |
428 | ||
dced35ae | 429 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 430 | |
ba698ad4 | 431 | pci_intx_for_msi(dev, 0); |
e375b561 | 432 | msi_set_enable(dev, 0); |
76ccc297 | 433 | arch_restore_msi_irqs(dev, dev->irq); |
392ee1e6 | 434 | |
f5322169 | 435 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
f2440d9a | 436 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 437 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 438 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 439 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
440 | } |
441 | ||
442 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 443 | { |
41017f0c | 444 | struct msi_desc *entry; |
392ee1e6 | 445 | u16 control; |
41017f0c | 446 | |
ded86d8d EB |
447 | if (!dev->msix_enabled) |
448 | return; | |
f598282f | 449 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 450 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f5322169 | 451 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
ded86d8d | 452 | |
41017f0c | 453 | /* route the table */ |
ba698ad4 | 454 | pci_intx_for_msi(dev, 0); |
f598282f | 455 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 456 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 457 | |
4aa9bc95 | 458 | list_for_each_entry(entry, &dev->msi_list, list) { |
76ccc297 | 459 | arch_restore_msi_irqs(dev, entry->irq); |
f2440d9a | 460 | msix_mask_irq(entry, entry->masked); |
41017f0c | 461 | } |
41017f0c | 462 | |
392ee1e6 | 463 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 464 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 465 | } |
8fed4b65 ME |
466 | |
467 | void pci_restore_msi_state(struct pci_dev *dev) | |
468 | { | |
469 | __pci_restore_msi_state(dev); | |
470 | __pci_restore_msix_state(dev); | |
471 | } | |
94688cf2 | 472 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 473 | |
da8d1c8b NH |
474 | |
475 | #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr) | |
476 | #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj) | |
477 | ||
478 | struct msi_attribute { | |
479 | struct attribute attr; | |
480 | ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr, | |
481 | char *buf); | |
482 | ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr, | |
483 | const char *buf, size_t count); | |
484 | }; | |
485 | ||
486 | static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr, | |
487 | char *buf) | |
488 | { | |
489 | return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi"); | |
490 | } | |
491 | ||
492 | static ssize_t msi_irq_attr_show(struct kobject *kobj, | |
493 | struct attribute *attr, char *buf) | |
494 | { | |
495 | struct msi_attribute *attribute = to_msi_attr(attr); | |
496 | struct msi_desc *entry = to_msi_desc(kobj); | |
497 | ||
498 | if (!attribute->show) | |
499 | return -EIO; | |
500 | ||
501 | return attribute->show(entry, attribute, buf); | |
502 | } | |
503 | ||
504 | static const struct sysfs_ops msi_irq_sysfs_ops = { | |
505 | .show = msi_irq_attr_show, | |
506 | }; | |
507 | ||
508 | static struct msi_attribute mode_attribute = | |
509 | __ATTR(mode, S_IRUGO, show_msi_mode, NULL); | |
510 | ||
511 | ||
9738abed | 512 | static struct attribute *msi_irq_default_attrs[] = { |
da8d1c8b NH |
513 | &mode_attribute.attr, |
514 | NULL | |
515 | }; | |
516 | ||
9738abed | 517 | static void msi_kobj_release(struct kobject *kobj) |
da8d1c8b NH |
518 | { |
519 | struct msi_desc *entry = to_msi_desc(kobj); | |
520 | ||
521 | pci_dev_put(entry->dev); | |
522 | } | |
523 | ||
524 | static struct kobj_type msi_irq_ktype = { | |
525 | .release = msi_kobj_release, | |
526 | .sysfs_ops = &msi_irq_sysfs_ops, | |
527 | .default_attrs = msi_irq_default_attrs, | |
528 | }; | |
529 | ||
530 | static int populate_msi_sysfs(struct pci_dev *pdev) | |
531 | { | |
532 | struct msi_desc *entry; | |
533 | struct kobject *kobj; | |
534 | int ret; | |
535 | int count = 0; | |
536 | ||
537 | pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj); | |
538 | if (!pdev->msi_kset) | |
539 | return -ENOMEM; | |
540 | ||
541 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
542 | kobj = &entry->kobj; | |
543 | kobj->kset = pdev->msi_kset; | |
544 | pci_dev_get(pdev); | |
545 | ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL, | |
546 | "%u", entry->irq); | |
547 | if (ret) | |
548 | goto out_unroll; | |
549 | ||
550 | count++; | |
551 | } | |
552 | ||
553 | return 0; | |
554 | ||
555 | out_unroll: | |
556 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
557 | if (!count) | |
558 | break; | |
559 | kobject_del(&entry->kobj); | |
560 | kobject_put(&entry->kobj); | |
561 | count--; | |
562 | } | |
563 | return ret; | |
564 | } | |
565 | ||
1da177e4 LT |
566 | /** |
567 | * msi_capability_init - configure device's MSI capability structure | |
568 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 569 | * @nvec: number of interrupts to allocate |
1da177e4 | 570 | * |
1c8d7b0a MW |
571 | * Setup the MSI capability structure of the device with the requested |
572 | * number of interrupts. A return value of zero indicates the successful | |
573 | * setup of an entry with the new MSI irq. A negative return value indicates | |
574 | * an error, and a positive return value indicates the number of interrupts | |
575 | * which could have been allocated. | |
576 | */ | |
577 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
578 | { |
579 | struct msi_desc *entry; | |
f465136d | 580 | int ret; |
1da177e4 | 581 | u16 control; |
f2440d9a | 582 | unsigned mask; |
1da177e4 | 583 | |
e375b561 | 584 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 585 | |
f84ecd28 | 586 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
1da177e4 | 587 | /* MSI Entry Initialization */ |
379f5327 | 588 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
589 | if (!entry) |
590 | return -ENOMEM; | |
1ce03373 | 591 | |
500559a9 | 592 | entry->msi_attrib.is_msix = 0; |
4987ce82 | 593 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); |
500559a9 | 594 | entry->msi_attrib.entry_nr = 0; |
4987ce82 | 595 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); |
500559a9 | 596 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
f465136d | 597 | entry->msi_attrib.pos = dev->msi_cap; |
f2440d9a | 598 | |
e5f66eaf DC |
599 | if (control & PCI_MSI_FLAGS_64BIT) |
600 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
601 | else | |
602 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
f2440d9a MW |
603 | /* All MSIs are unmasked by default, Mask them all */ |
604 | if (entry->msi_attrib.maskbit) | |
605 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
606 | mask = msi_capable_mask(control); | |
607 | msi_mask_irq(entry, mask, mask); | |
608 | ||
0dd11f9b | 609 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 610 | |
1da177e4 | 611 | /* Configure MSI capability structure */ |
1c8d7b0a | 612 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 613 | if (ret) { |
7ba1930d | 614 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 615 | free_msi_irqs(dev); |
7fe3730d | 616 | return ret; |
fd58e55f | 617 | } |
f7feaca7 | 618 | |
da8d1c8b NH |
619 | ret = populate_msi_sysfs(dev); |
620 | if (ret) { | |
621 | msi_mask_irq(entry, mask, ~mask); | |
622 | free_msi_irqs(dev); | |
623 | return ret; | |
624 | } | |
625 | ||
1da177e4 | 626 | /* Set MSI enabled bits */ |
ba698ad4 | 627 | pci_intx_for_msi(dev, 0); |
e375b561 | 628 | msi_set_enable(dev, 1); |
b1cbf4e4 | 629 | dev->msi_enabled = 1; |
1da177e4 | 630 | |
7fe3730d | 631 | dev->irq = entry->irq; |
1da177e4 LT |
632 | return 0; |
633 | } | |
634 | ||
520fe9dc | 635 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 636 | { |
4302e0fb | 637 | resource_size_t phys_addr; |
5a05a9d8 HS |
638 | u32 table_offset; |
639 | u8 bir; | |
640 | ||
909094c6 BH |
641 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
642 | &table_offset); | |
4d18760c BH |
643 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
644 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
645 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
646 | ||
647 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
648 | } | |
649 | ||
520fe9dc GS |
650 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
651 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
652 | { |
653 | struct msi_desc *entry; | |
654 | int i; | |
655 | ||
656 | for (i = 0; i < nvec; i++) { | |
657 | entry = alloc_msi_entry(dev); | |
658 | if (!entry) { | |
659 | if (!i) | |
660 | iounmap(base); | |
661 | else | |
662 | free_msi_irqs(dev); | |
663 | /* No enough memory. Don't try again */ | |
664 | return -ENOMEM; | |
665 | } | |
666 | ||
667 | entry->msi_attrib.is_msix = 1; | |
668 | entry->msi_attrib.is_64 = 1; | |
669 | entry->msi_attrib.entry_nr = entries[i].entry; | |
670 | entry->msi_attrib.default_irq = dev->irq; | |
520fe9dc | 671 | entry->msi_attrib.pos = dev->msix_cap; |
d9d7070e HS |
672 | entry->mask_base = base; |
673 | ||
674 | list_add_tail(&entry->list, &dev->msi_list); | |
675 | } | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
75cb3426 | 680 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 681 | struct msix_entry *entries) |
75cb3426 HS |
682 | { |
683 | struct msi_desc *entry; | |
684 | int i = 0; | |
685 | ||
686 | list_for_each_entry(entry, &dev->msi_list, list) { | |
687 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
688 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
689 | ||
690 | entries[i].vector = entry->irq; | |
dced35ae | 691 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
692 | entry->masked = readl(entry->mask_base + offset); |
693 | msix_mask_irq(entry, 1); | |
694 | i++; | |
695 | } | |
696 | } | |
697 | ||
1da177e4 LT |
698 | /** |
699 | * msix_capability_init - configure device's MSI-X capability | |
700 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
701 | * @entries: pointer to an array of struct msix_entry entries |
702 | * @nvec: number of @entries | |
1da177e4 | 703 | * |
eaae4b3a | 704 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
705 | * single MSI-X irq. A return of zero indicates the successful setup of |
706 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
707 | **/ |
708 | static int msix_capability_init(struct pci_dev *dev, | |
709 | struct msix_entry *entries, int nvec) | |
710 | { | |
520fe9dc | 711 | int ret; |
5a05a9d8 | 712 | u16 control; |
1da177e4 LT |
713 | void __iomem *base; |
714 | ||
520fe9dc | 715 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
f598282f MW |
716 | |
717 | /* Ensure MSI-X is disabled while it is set up */ | |
718 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 719 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 720 | |
1da177e4 | 721 | /* Request & Map MSI-X table region */ |
527eee29 | 722 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 723 | if (!base) |
1da177e4 LT |
724 | return -ENOMEM; |
725 | ||
520fe9dc | 726 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
727 | if (ret) |
728 | return ret; | |
9c831334 ME |
729 | |
730 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
731 | if (ret) |
732 | goto error; | |
9c831334 | 733 | |
f598282f MW |
734 | /* |
735 | * Some devices require MSI-X to be enabled before we can touch the | |
736 | * MSI-X registers. We need to mask all the vectors to prevent | |
737 | * interrupts coming in before they're fully set up. | |
738 | */ | |
739 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 740 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 741 | |
75cb3426 | 742 | msix_program_entries(dev, entries); |
f598282f | 743 | |
da8d1c8b NH |
744 | ret = populate_msi_sysfs(dev); |
745 | if (ret) { | |
746 | ret = 0; | |
747 | goto error; | |
748 | } | |
749 | ||
f598282f | 750 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 751 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 752 | dev->msix_enabled = 1; |
1da177e4 | 753 | |
f598282f | 754 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
520fe9dc | 755 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
8d181018 | 756 | |
1da177e4 | 757 | return 0; |
583871d4 HS |
758 | |
759 | error: | |
760 | if (ret < 0) { | |
761 | /* | |
762 | * If we had some success, report the number of irqs | |
763 | * we succeeded in setting up. | |
764 | */ | |
d9d7070e | 765 | struct msi_desc *entry; |
583871d4 HS |
766 | int avail = 0; |
767 | ||
768 | list_for_each_entry(entry, &dev->msi_list, list) { | |
769 | if (entry->irq != 0) | |
770 | avail++; | |
771 | } | |
772 | if (avail != 0) | |
773 | ret = avail; | |
774 | } | |
775 | ||
776 | free_msi_irqs(dev); | |
777 | ||
778 | return ret; | |
1da177e4 LT |
779 | } |
780 | ||
24334a12 | 781 | /** |
17bbc12a | 782 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 783 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 784 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 785 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 786 | * |
f7625980 | 787 | * Look at global flags, the device itself, and its parent buses |
17bbc12a ME |
788 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
789 | * supported return 0, else return an error code. | |
24334a12 | 790 | **/ |
500559a9 | 791 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
792 | { |
793 | struct pci_bus *bus; | |
c9953a73 | 794 | int ret; |
24334a12 | 795 | |
0306ebfa | 796 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
797 | if (!pci_msi_enable || !dev || dev->no_msi) |
798 | return -EINVAL; | |
799 | ||
314e77b3 ME |
800 | /* |
801 | * You can't ask to have 0 or less MSIs configured. | |
802 | * a) it's stupid .. | |
803 | * b) the list manipulation code assumes nvec >= 1. | |
804 | */ | |
805 | if (nvec < 1) | |
806 | return -ERANGE; | |
807 | ||
500559a9 HS |
808 | /* |
809 | * Any bridge which does NOT route MSI transactions from its | |
810 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
811 | * the secondary pci_bus. |
812 | * We expect only arch-specific PCI host bus controller driver | |
813 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
814 | */ | |
24334a12 BG |
815 | for (bus = dev->bus; bus; bus = bus->parent) |
816 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
817 | return -EINVAL; | |
818 | ||
c9953a73 ME |
819 | ret = arch_msi_check_device(dev, nvec, type); |
820 | if (ret) | |
821 | return ret; | |
822 | ||
24334a12 BG |
823 | return 0; |
824 | } | |
825 | ||
1da177e4 | 826 | /** |
1c8d7b0a MW |
827 | * pci_enable_msi_block - configure device's MSI capability structure |
828 | * @dev: device to configure | |
829 | * @nvec: number of interrupts to configure | |
1da177e4 | 830 | * |
1c8d7b0a MW |
831 | * Allocate IRQs for a device with the MSI capability. |
832 | * This function returns a negative errno if an error occurs. If it | |
833 | * is unable to allocate the number of interrupts requested, it returns | |
834 | * the number of interrupts it might be able to allocate. If it successfully | |
835 | * allocates at least the number of interrupts requested, it returns 0 and | |
836 | * updates the @dev's irq member to the lowest new interrupt number; the | |
837 | * other interrupt numbers allocated to this device are consecutive. | |
838 | */ | |
839 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 840 | { |
f465136d | 841 | int status, maxvec; |
1c8d7b0a MW |
842 | u16 msgctl; |
843 | ||
869a1615 | 844 | if (!dev->msi_cap || dev->current_state != PCI_D0) |
1c8d7b0a | 845 | return -EINVAL; |
f465136d GS |
846 | |
847 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
1c8d7b0a MW |
848 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
849 | if (nvec > maxvec) | |
850 | return maxvec; | |
1da177e4 | 851 | |
1c8d7b0a | 852 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
853 | if (status) |
854 | return status; | |
1da177e4 | 855 | |
ded86d8d | 856 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 857 | |
1c8d7b0a | 858 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 859 | if (dev->msix_enabled) { |
80ccba11 BH |
860 | dev_info(&dev->dev, "can't enable MSI " |
861 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 862 | return -EINVAL; |
1da177e4 | 863 | } |
1c8d7b0a MW |
864 | |
865 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
866 | return status; |
867 | } | |
1c8d7b0a | 868 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 869 | |
08261d87 AG |
870 | int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) |
871 | { | |
f465136d | 872 | int ret, nvec; |
08261d87 AG |
873 | u16 msgctl; |
874 | ||
869a1615 | 875 | if (!dev->msi_cap || dev->current_state != PCI_D0) |
08261d87 AG |
876 | return -EINVAL; |
877 | ||
f465136d | 878 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); |
08261d87 AG |
879 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
880 | ||
881 | if (maxvec) | |
882 | *maxvec = ret; | |
883 | ||
884 | do { | |
885 | nvec = ret; | |
886 | ret = pci_enable_msi_block(dev, nvec); | |
887 | } while (ret > 0); | |
888 | ||
889 | if (ret < 0) | |
890 | return ret; | |
891 | return nvec; | |
892 | } | |
893 | EXPORT_SYMBOL(pci_enable_msi_block_auto); | |
894 | ||
f2440d9a | 895 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 896 | { |
f2440d9a MW |
897 | struct msi_desc *desc; |
898 | u32 mask; | |
899 | u16 ctrl; | |
1da177e4 | 900 | |
128bc5fc | 901 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
902 | return; |
903 | ||
110828c9 MW |
904 | BUG_ON(list_empty(&dev->msi_list)); |
905 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 906 | |
e375b561 | 907 | msi_set_enable(dev, 0); |
ba698ad4 | 908 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 909 | dev->msi_enabled = 0; |
7bd007e4 | 910 | |
12abb8ba | 911 | /* Return the device with MSI unmasked as initial states */ |
f5322169 | 912 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 913 | mask = msi_capable_mask(ctrl); |
12abb8ba | 914 | /* Keep cached state to be restored */ |
0e4ccb15 | 915 | arch_msi_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
916 | |
917 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 918 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 919 | } |
24d27553 | 920 | |
500559a9 | 921 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 922 | { |
d52877c7 YL |
923 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
924 | return; | |
925 | ||
926 | pci_msi_shutdown(dev); | |
f56e4481 | 927 | free_msi_irqs(dev); |
da8d1c8b NH |
928 | kset_unregister(dev->msi_kset); |
929 | dev->msi_kset = NULL; | |
1da177e4 | 930 | } |
4cc086fa | 931 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 932 | |
a52e2e35 RW |
933 | /** |
934 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
935 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
936 | */ | |
937 | int pci_msix_table_size(struct pci_dev *dev) | |
938 | { | |
a52e2e35 RW |
939 | u16 control; |
940 | ||
520fe9dc | 941 | if (!dev->msix_cap) |
a52e2e35 RW |
942 | return 0; |
943 | ||
f84ecd28 | 944 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 945 | return msix_table_size(control); |
a52e2e35 RW |
946 | } |
947 | ||
1da177e4 LT |
948 | /** |
949 | * pci_enable_msix - configure device's MSI-X capability structure | |
950 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 951 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 952 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
953 | * |
954 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 955 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
956 | * MSI-X mode enabled on its hardware device function. A return of zero |
957 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 958 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 959 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
960 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
961 | * re-send its request. | |
1da177e4 | 962 | **/ |
500559a9 | 963 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 964 | { |
a52e2e35 | 965 | int status, nr_entries; |
ded86d8d | 966 | int i, j; |
1da177e4 | 967 | |
869a1615 | 968 | if (!entries || !dev->msix_cap || dev->current_state != PCI_D0) |
500559a9 | 969 | return -EINVAL; |
1da177e4 | 970 | |
c9953a73 ME |
971 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
972 | if (status) | |
973 | return status; | |
974 | ||
a52e2e35 | 975 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 976 | if (nvec > nr_entries) |
57fbf52c | 977 | return nr_entries; |
1da177e4 LT |
978 | |
979 | /* Check for any invalid entries */ | |
980 | for (i = 0; i < nvec; i++) { | |
981 | if (entries[i].entry >= nr_entries) | |
982 | return -EINVAL; /* invalid entry */ | |
983 | for (j = i + 1; j < nvec; j++) { | |
984 | if (entries[i].entry == entries[j].entry) | |
985 | return -EINVAL; /* duplicate entry */ | |
986 | } | |
987 | } | |
ded86d8d | 988 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 989 | |
1ce03373 | 990 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 991 | if (dev->msi_enabled) { |
80ccba11 BH |
992 | dev_info(&dev->dev, "can't enable MSI-X " |
993 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
994 | return -EINVAL; |
995 | } | |
1da177e4 | 996 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
997 | return status; |
998 | } | |
4cc086fa | 999 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 1000 | |
500559a9 | 1001 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 1002 | { |
12abb8ba HS |
1003 | struct msi_desc *entry; |
1004 | ||
128bc5fc | 1005 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
1006 | return; |
1007 | ||
12abb8ba HS |
1008 | /* Return the device with MSI-X masked as initial states */ |
1009 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1010 | /* Keep cached states to be restored */ | |
0e4ccb15 | 1011 | arch_msix_mask_irq(entry, 1); |
12abb8ba HS |
1012 | } |
1013 | ||
b1cbf4e4 | 1014 | msix_set_enable(dev, 0); |
ba698ad4 | 1015 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1016 | dev->msix_enabled = 0; |
d52877c7 | 1017 | } |
c901851f | 1018 | |
500559a9 | 1019 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1020 | { |
1021 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1022 | return; | |
1023 | ||
1024 | pci_msix_shutdown(dev); | |
f56e4481 | 1025 | free_msi_irqs(dev); |
da8d1c8b NH |
1026 | kset_unregister(dev->msi_kset); |
1027 | dev->msi_kset = NULL; | |
1da177e4 | 1028 | } |
4cc086fa | 1029 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
1030 | |
1031 | /** | |
1ce03373 | 1032 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1033 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1034 | * | |
eaae4b3a | 1035 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1036 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1037 | * allocated for this device function, are reclaimed to unused state, |
1038 | * which may be used later on. | |
1039 | **/ | |
500559a9 | 1040 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 1041 | { |
1da177e4 | 1042 | if (!pci_msi_enable || !dev) |
500559a9 | 1043 | return; |
1da177e4 | 1044 | |
f56e4481 HS |
1045 | if (dev->msi_enabled || dev->msix_enabled) |
1046 | free_msi_irqs(dev); | |
1da177e4 LT |
1047 | } |
1048 | ||
309e57df MW |
1049 | void pci_no_msi(void) |
1050 | { | |
1051 | pci_msi_enable = 0; | |
1052 | } | |
c9953a73 | 1053 | |
07ae95f9 AP |
1054 | /** |
1055 | * pci_msi_enabled - is MSI enabled? | |
1056 | * | |
1057 | * Returns true if MSI has not been disabled by the command-line option | |
1058 | * pci=nomsi. | |
1059 | **/ | |
1060 | int pci_msi_enabled(void) | |
d389fec6 | 1061 | { |
07ae95f9 | 1062 | return pci_msi_enable; |
d389fec6 | 1063 | } |
07ae95f9 | 1064 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1065 | |
07ae95f9 | 1066 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1067 | { |
07ae95f9 | 1068 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1069 | |
1070 | /* Disable the msi hardware to avoid screaming interrupts | |
1071 | * during boot. This is the power on reset default so | |
1072 | * usually this should be a noop. | |
1073 | */ | |
e375b561 GS |
1074 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1075 | if (dev->msi_cap) | |
1076 | msi_set_enable(dev, 0); | |
1077 | ||
1078 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1079 | if (dev->msix_cap) | |
1080 | msix_set_enable(dev, 0); | |
d389fec6 | 1081 | } |