Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
b1cbf4e4 EB |
28 | static void msi_set_enable(struct pci_dev *dev, int enable) |
29 | { | |
30 | int pos; | |
31 | u16 control; | |
32 | ||
33 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
34 | if (pos) { | |
35 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
36 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
37 | if (enable) | |
38 | control |= PCI_MSI_FLAGS_ENABLE; | |
39 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
40 | } | |
41 | } | |
42 | ||
43 | static void msix_set_enable(struct pci_dev *dev, int enable) | |
44 | { | |
45 | int pos; | |
46 | u16 control; | |
47 | ||
48 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
49 | if (pos) { | |
50 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
51 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
52 | if (enable) | |
53 | control |= PCI_MSIX_FLAGS_ENABLE; | |
54 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
55 | } | |
56 | } | |
57 | ||
988cbb15 MW |
58 | static void msix_flush_writes(unsigned int irq) |
59 | { | |
60 | struct msi_desc *entry; | |
61 | ||
62 | entry = get_irq_msi(irq); | |
63 | BUG_ON(!entry || !entry->dev); | |
64 | switch (entry->msi_attrib.type) { | |
65 | case PCI_CAP_ID_MSI: | |
66 | /* nothing to do */ | |
67 | break; | |
68 | case PCI_CAP_ID_MSIX: | |
69 | { | |
70 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
71 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
72 | readl(entry->mask_base + offset); | |
73 | break; | |
74 | } | |
75 | default: | |
76 | BUG(); | |
77 | break; | |
78 | } | |
79 | } | |
80 | ||
1ce03373 | 81 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
82 | { |
83 | struct msi_desc *entry; | |
84 | ||
5b912c10 | 85 | entry = get_irq_msi(irq); |
277bc33b | 86 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
87 | switch (entry->msi_attrib.type) { |
88 | case PCI_CAP_ID_MSI: | |
277bc33b | 89 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
90 | int pos; |
91 | u32 mask_bits; | |
277bc33b EB |
92 | |
93 | pos = (long)entry->mask_base; | |
94 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
95 | mask_bits &= ~(1); | |
96 | mask_bits |= flag; | |
97 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
58e0543e EB |
98 | } else { |
99 | msi_set_enable(entry->dev, !flag); | |
277bc33b | 100 | } |
1da177e4 | 101 | break; |
1da177e4 LT |
102 | case PCI_CAP_ID_MSIX: |
103 | { | |
104 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
105 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
106 | writel(flag, entry->mask_base + offset); | |
348e3fd1 | 107 | readl(entry->mask_base + offset); |
1da177e4 LT |
108 | break; |
109 | } | |
110 | default: | |
277bc33b | 111 | BUG(); |
1da177e4 LT |
112 | break; |
113 | } | |
392ee1e6 | 114 | entry->msi_attrib.masked = !!flag; |
1da177e4 LT |
115 | } |
116 | ||
3b7d1921 | 117 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 118 | { |
5b912c10 | 119 | struct msi_desc *entry = get_irq_msi(irq); |
0366f8f7 EB |
120 | switch(entry->msi_attrib.type) { |
121 | case PCI_CAP_ID_MSI: | |
122 | { | |
123 | struct pci_dev *dev = entry->dev; | |
124 | int pos = entry->msi_attrib.pos; | |
125 | u16 data; | |
126 | ||
127 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
128 | &msg->address_lo); | |
129 | if (entry->msi_attrib.is_64) { | |
130 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
131 | &msg->address_hi); | |
132 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
133 | } else { | |
134 | msg->address_hi = 0; | |
cbf5d9e6 | 135 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
136 | } |
137 | msg->data = data; | |
138 | break; | |
139 | } | |
140 | case PCI_CAP_ID_MSIX: | |
141 | { | |
142 | void __iomem *base; | |
143 | base = entry->mask_base + | |
144 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
145 | ||
146 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
147 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
148 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
149 | break; | |
150 | } | |
151 | default: | |
152 | BUG(); | |
153 | } | |
154 | } | |
1da177e4 | 155 | |
3b7d1921 | 156 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 157 | { |
5b912c10 | 158 | struct msi_desc *entry = get_irq_msi(irq); |
1da177e4 LT |
159 | switch (entry->msi_attrib.type) { |
160 | case PCI_CAP_ID_MSI: | |
161 | { | |
0366f8f7 EB |
162 | struct pci_dev *dev = entry->dev; |
163 | int pos = entry->msi_attrib.pos; | |
164 | ||
165 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
166 | msg->address_lo); | |
167 | if (entry->msi_attrib.is_64) { | |
168 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
169 | msg->address_hi); | |
170 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
171 | msg->data); | |
172 | } else { | |
173 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
174 | msg->data); | |
175 | } | |
1da177e4 LT |
176 | break; |
177 | } | |
178 | case PCI_CAP_ID_MSIX: | |
179 | { | |
0366f8f7 EB |
180 | void __iomem *base; |
181 | base = entry->mask_base + | |
182 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
183 | ||
184 | writel(msg->address_lo, | |
185 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
186 | writel(msg->address_hi, | |
187 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
188 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
189 | break; |
190 | } | |
191 | default: | |
0366f8f7 | 192 | BUG(); |
1da177e4 | 193 | } |
392ee1e6 | 194 | entry->msg = *msg; |
1da177e4 | 195 | } |
0366f8f7 | 196 | |
3b7d1921 | 197 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 198 | { |
1ce03373 | 199 | msi_set_mask_bit(irq, 1); |
988cbb15 | 200 | msix_flush_writes(irq); |
1da177e4 LT |
201 | } |
202 | ||
3b7d1921 | 203 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 204 | { |
1ce03373 | 205 | msi_set_mask_bit(irq, 0); |
988cbb15 | 206 | msix_flush_writes(irq); |
1da177e4 LT |
207 | } |
208 | ||
032de8e2 | 209 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 210 | |
1da177e4 | 211 | |
1da177e4 LT |
212 | static struct msi_desc* alloc_msi_entry(void) |
213 | { | |
214 | struct msi_desc *entry; | |
215 | ||
3e916c05 | 216 | entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL); |
1da177e4 LT |
217 | if (!entry) |
218 | return NULL; | |
219 | ||
4aa9bc95 ME |
220 | INIT_LIST_HEAD(&entry->list); |
221 | entry->irq = 0; | |
1da177e4 LT |
222 | entry->dev = NULL; |
223 | ||
224 | return entry; | |
225 | } | |
226 | ||
ba698ad4 DM |
227 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
228 | { | |
229 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
230 | pci_intx(dev, enable); | |
231 | } | |
232 | ||
8fed4b65 | 233 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 234 | { |
392ee1e6 | 235 | int pos; |
41017f0c | 236 | u16 control; |
392ee1e6 | 237 | struct msi_desc *entry; |
41017f0c | 238 | |
b1cbf4e4 EB |
239 | if (!dev->msi_enabled) |
240 | return; | |
241 | ||
392ee1e6 EB |
242 | entry = get_irq_msi(dev->irq); |
243 | pos = entry->msi_attrib.pos; | |
41017f0c | 244 | |
ba698ad4 | 245 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 246 | msi_set_enable(dev, 0); |
392ee1e6 EB |
247 | write_msi_msg(dev->irq, &entry->msg); |
248 | if (entry->msi_attrib.maskbit) | |
249 | msi_set_mask_bit(dev->irq, entry->msi_attrib.masked); | |
250 | ||
251 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
252 | control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE); | |
253 | if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked) | |
254 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 255 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
256 | } |
257 | ||
258 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 259 | { |
41017f0c | 260 | int pos; |
41017f0c | 261 | struct msi_desc *entry; |
392ee1e6 | 262 | u16 control; |
41017f0c | 263 | |
ded86d8d EB |
264 | if (!dev->msix_enabled) |
265 | return; | |
266 | ||
41017f0c | 267 | /* route the table */ |
ba698ad4 | 268 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 269 | msix_set_enable(dev, 0); |
41017f0c | 270 | |
4aa9bc95 ME |
271 | list_for_each_entry(entry, &dev->msi_list, list) { |
272 | write_msi_msg(entry->irq, &entry->msg); | |
273 | msi_set_mask_bit(entry->irq, entry->msi_attrib.masked); | |
41017f0c | 274 | } |
41017f0c | 275 | |
314e77b3 ME |
276 | BUG_ON(list_empty(&dev->msi_list)); |
277 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
4aa9bc95 | 278 | pos = entry->msi_attrib.pos; |
392ee1e6 EB |
279 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
280 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
281 | control |= PCI_MSIX_FLAGS_ENABLE; | |
282 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 283 | } |
8fed4b65 ME |
284 | |
285 | void pci_restore_msi_state(struct pci_dev *dev) | |
286 | { | |
287 | __pci_restore_msi_state(dev); | |
288 | __pci_restore_msix_state(dev); | |
289 | } | |
94688cf2 | 290 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 291 | |
1da177e4 LT |
292 | /** |
293 | * msi_capability_init - configure device's MSI capability structure | |
294 | * @dev: pointer to the pci_dev data structure of MSI device function | |
295 | * | |
eaae4b3a | 296 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 297 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 298 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 299 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
300 | **/ |
301 | static int msi_capability_init(struct pci_dev *dev) | |
302 | { | |
303 | struct msi_desc *entry; | |
7fe3730d | 304 | int pos, ret; |
1da177e4 LT |
305 | u16 control; |
306 | ||
b1cbf4e4 EB |
307 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
308 | ||
1da177e4 LT |
309 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
310 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
311 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
312 | entry = alloc_msi_entry(); |
313 | if (!entry) | |
314 | return -ENOMEM; | |
1ce03373 | 315 | |
1da177e4 | 316 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 317 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
318 | entry->msi_attrib.entry_nr = 0; |
319 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 320 | entry->msi_attrib.masked = 1; |
1ce03373 | 321 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 322 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
323 | if (is_mask_bit_support(control)) { |
324 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
325 | is_64bit_address(control)); | |
326 | } | |
3b7d1921 EB |
327 | entry->dev = dev; |
328 | if (entry->msi_attrib.maskbit) { | |
329 | unsigned int maskbits, temp; | |
330 | /* All MSIs are unmasked by default, Mask them all */ | |
331 | pci_read_config_dword(dev, | |
332 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
333 | &maskbits); | |
334 | temp = (1 << multi_msi_capable(control)); | |
335 | temp = ((temp - 1) & ~temp); | |
336 | maskbits |= temp; | |
337 | pci_write_config_dword(dev, | |
338 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
339 | maskbits); | |
340 | } | |
0dd11f9b | 341 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 342 | |
1da177e4 | 343 | /* Configure MSI capability structure */ |
9c831334 | 344 | ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI); |
7fe3730d | 345 | if (ret) { |
032de8e2 | 346 | msi_free_irqs(dev); |
7fe3730d | 347 | return ret; |
fd58e55f | 348 | } |
f7feaca7 | 349 | |
1da177e4 | 350 | /* Set MSI enabled bits */ |
ba698ad4 | 351 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
352 | msi_set_enable(dev, 1); |
353 | dev->msi_enabled = 1; | |
1da177e4 | 354 | |
7fe3730d | 355 | dev->irq = entry->irq; |
1da177e4 LT |
356 | return 0; |
357 | } | |
358 | ||
359 | /** | |
360 | * msix_capability_init - configure device's MSI-X capability | |
361 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
362 | * @entries: pointer to an array of struct msix_entry entries |
363 | * @nvec: number of @entries | |
1da177e4 | 364 | * |
eaae4b3a | 365 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
366 | * single MSI-X irq. A return of zero indicates the successful setup of |
367 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
368 | **/ |
369 | static int msix_capability_init(struct pci_dev *dev, | |
370 | struct msix_entry *entries, int nvec) | |
371 | { | |
4aa9bc95 | 372 | struct msi_desc *entry; |
9c831334 | 373 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
374 | unsigned long phys_addr; |
375 | u32 table_offset; | |
1da177e4 LT |
376 | u16 control; |
377 | u8 bir; | |
378 | void __iomem *base; | |
379 | ||
b1cbf4e4 EB |
380 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
381 | ||
1da177e4 LT |
382 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
383 | /* Request & Map MSI-X table region */ | |
384 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
385 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
386 | |
387 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 388 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
389 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
390 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
391 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
392 | if (base == NULL) | |
393 | return -ENOMEM; | |
394 | ||
395 | /* MSI-X Table Initialization */ | |
396 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
397 | entry = alloc_msi_entry(); |
398 | if (!entry) | |
1da177e4 | 399 | break; |
1da177e4 LT |
400 | |
401 | j = entries[i].entry; | |
1da177e4 | 402 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 403 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
404 | entry->msi_attrib.entry_nr = j; |
405 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 406 | entry->msi_attrib.masked = 1; |
1ce03373 | 407 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 408 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
409 | entry->dev = dev; |
410 | entry->mask_base = base; | |
f7feaca7 | 411 | |
0dd11f9b | 412 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 413 | } |
9c831334 ME |
414 | |
415 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
416 | if (ret) { | |
417 | int avail = 0; | |
418 | list_for_each_entry(entry, &dev->msi_list, list) { | |
419 | if (entry->irq != 0) { | |
420 | avail++; | |
9c831334 | 421 | } |
1da177e4 | 422 | } |
9c831334 | 423 | |
032de8e2 ME |
424 | msi_free_irqs(dev); |
425 | ||
92db6d10 EB |
426 | /* If we had some success report the number of irqs |
427 | * we succeeded in setting up. | |
428 | */ | |
9c831334 ME |
429 | if (avail == 0) |
430 | avail = ret; | |
92db6d10 | 431 | return avail; |
1da177e4 | 432 | } |
9c831334 ME |
433 | |
434 | i = 0; | |
435 | list_for_each_entry(entry, &dev->msi_list, list) { | |
436 | entries[i].vector = entry->irq; | |
437 | set_irq_msi(entry->irq, entry); | |
438 | i++; | |
439 | } | |
1da177e4 | 440 | /* Set MSI-X enabled bits */ |
ba698ad4 | 441 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
442 | msix_set_enable(dev, 1); |
443 | dev->msix_enabled = 1; | |
1da177e4 LT |
444 | |
445 | return 0; | |
446 | } | |
447 | ||
24334a12 | 448 | /** |
17bbc12a | 449 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 450 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 451 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 452 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 453 | * |
0306ebfa | 454 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
455 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
456 | * supported return 0, else return an error code. | |
24334a12 | 457 | **/ |
c9953a73 | 458 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
459 | { |
460 | struct pci_bus *bus; | |
c9953a73 | 461 | int ret; |
24334a12 | 462 | |
0306ebfa | 463 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
464 | if (!pci_msi_enable || !dev || dev->no_msi) |
465 | return -EINVAL; | |
466 | ||
314e77b3 ME |
467 | /* |
468 | * You can't ask to have 0 or less MSIs configured. | |
469 | * a) it's stupid .. | |
470 | * b) the list manipulation code assumes nvec >= 1. | |
471 | */ | |
472 | if (nvec < 1) | |
473 | return -ERANGE; | |
474 | ||
0306ebfa BG |
475 | /* Any bridge which does NOT route MSI transactions from it's |
476 | * secondary bus to it's primary bus must set NO_MSI flag on | |
477 | * the secondary pci_bus. | |
478 | * We expect only arch-specific PCI host bus controller driver | |
479 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
480 | */ | |
24334a12 BG |
481 | for (bus = dev->bus; bus; bus = bus->parent) |
482 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
483 | return -EINVAL; | |
484 | ||
c9953a73 ME |
485 | ret = arch_msi_check_device(dev, nvec, type); |
486 | if (ret) | |
487 | return ret; | |
488 | ||
b1e2303d ME |
489 | if (!pci_find_capability(dev, type)) |
490 | return -EINVAL; | |
491 | ||
24334a12 BG |
492 | return 0; |
493 | } | |
494 | ||
1da177e4 LT |
495 | /** |
496 | * pci_enable_msi - configure device's MSI capability structure | |
497 | * @dev: pointer to the pci_dev data structure of MSI device function | |
498 | * | |
499 | * Setup the MSI capability structure of device function with | |
1ce03373 | 500 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
501 | * MSI mode enabled on its hardware device function. A return of zero |
502 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 503 | * irq or non-zero for otherwise. |
1da177e4 LT |
504 | **/ |
505 | int pci_enable_msi(struct pci_dev* dev) | |
506 | { | |
b1e2303d | 507 | int status; |
1da177e4 | 508 | |
c9953a73 ME |
509 | status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI); |
510 | if (status) | |
511 | return status; | |
1da177e4 | 512 | |
ded86d8d | 513 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 514 | |
1ce03373 | 515 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 EB |
516 | if (dev->msix_enabled) { |
517 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " | |
518 | "Device already has MSI-X enabled\n", | |
519 | pci_name(dev)); | |
520 | return -EINVAL; | |
1da177e4 LT |
521 | } |
522 | status = msi_capability_init(dev); | |
1da177e4 LT |
523 | return status; |
524 | } | |
4cc086fa | 525 | EXPORT_SYMBOL(pci_enable_msi); |
1da177e4 LT |
526 | |
527 | void pci_disable_msi(struct pci_dev* dev) | |
528 | { | |
529 | struct msi_desc *entry; | |
b1cbf4e4 | 530 | int default_irq; |
1da177e4 | 531 | |
128bc5fc | 532 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
533 | return; |
534 | ||
b1cbf4e4 | 535 | msi_set_enable(dev, 0); |
ba698ad4 | 536 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 537 | dev->msi_enabled = 0; |
7bd007e4 | 538 | |
314e77b3 ME |
539 | BUG_ON(list_empty(&dev->msi_list)); |
540 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
541 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { | |
1da177e4 LT |
542 | return; |
543 | } | |
e387b9ee | 544 | |
e387b9ee | 545 | default_irq = entry->msi_attrib.default_irq; |
032de8e2 | 546 | msi_free_irqs(dev); |
e387b9ee ME |
547 | |
548 | /* Restore dev->irq to its default pin-assertion irq */ | |
549 | dev->irq = default_irq; | |
1da177e4 | 550 | } |
4cc086fa | 551 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 552 | |
032de8e2 | 553 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 554 | { |
032de8e2 | 555 | struct msi_desc *entry, *tmp; |
7ede9c1f | 556 | |
b3b7cc7b DM |
557 | list_for_each_entry(entry, &dev->msi_list, list) { |
558 | if (entry->irq) | |
559 | BUG_ON(irq_has_action(entry->irq)); | |
560 | } | |
1da177e4 | 561 | |
032de8e2 | 562 | arch_teardown_msi_irqs(dev); |
1da177e4 | 563 | |
032de8e2 ME |
564 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
565 | if (entry->msi_attrib.type == PCI_CAP_ID_MSIX) { | |
032de8e2 ME |
566 | writel(1, entry->mask_base + entry->msi_attrib.entry_nr |
567 | * PCI_MSIX_ENTRY_SIZE | |
568 | + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
78b7611c EB |
569 | |
570 | if (list_is_last(&entry->list, &dev->msi_list)) | |
571 | iounmap(entry->mask_base); | |
032de8e2 ME |
572 | } |
573 | list_del(&entry->list); | |
574 | kfree(entry); | |
1da177e4 LT |
575 | } |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
1da177e4 LT |
580 | /** |
581 | * pci_enable_msix - configure device's MSI-X capability structure | |
582 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 583 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 584 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
585 | * |
586 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 587 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
588 | * MSI-X mode enabled on its hardware device function. A return of zero |
589 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 590 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 591 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 592 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
593 | * its request. |
594 | **/ | |
595 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
596 | { | |
92db6d10 | 597 | int status, pos, nr_entries; |
ded86d8d | 598 | int i, j; |
1da177e4 | 599 | u16 control; |
1da177e4 | 600 | |
c9953a73 | 601 | if (!entries) |
1da177e4 LT |
602 | return -EINVAL; |
603 | ||
c9953a73 ME |
604 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
605 | if (status) | |
606 | return status; | |
607 | ||
b64c05e7 | 608 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1da177e4 | 609 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
1da177e4 LT |
610 | nr_entries = multi_msix_capable(control); |
611 | if (nvec > nr_entries) | |
612 | return -EINVAL; | |
613 | ||
614 | /* Check for any invalid entries */ | |
615 | for (i = 0; i < nvec; i++) { | |
616 | if (entries[i].entry >= nr_entries) | |
617 | return -EINVAL; /* invalid entry */ | |
618 | for (j = i + 1; j < nvec; j++) { | |
619 | if (entries[i].entry == entries[j].entry) | |
620 | return -EINVAL; /* duplicate entry */ | |
621 | } | |
622 | } | |
ded86d8d | 623 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 624 | |
1ce03373 | 625 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 626 | if (dev->msi_enabled) { |
1da177e4 | 627 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 628 | "Device already has an MSI irq assigned\n", |
1da177e4 | 629 | pci_name(dev)); |
1da177e4 LT |
630 | return -EINVAL; |
631 | } | |
1da177e4 | 632 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
633 | return status; |
634 | } | |
4cc086fa | 635 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 636 | |
fc4afc7b | 637 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 638 | { |
032de8e2 | 639 | msi_free_irqs(dev); |
fc4afc7b ME |
640 | } |
641 | ||
642 | void pci_disable_msix(struct pci_dev* dev) | |
643 | { | |
128bc5fc | 644 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
645 | return; |
646 | ||
b1cbf4e4 | 647 | msix_set_enable(dev, 0); |
ba698ad4 | 648 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 649 | dev->msix_enabled = 0; |
7bd007e4 | 650 | |
fc4afc7b | 651 | msix_free_all_irqs(dev); |
1da177e4 | 652 | } |
4cc086fa | 653 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
654 | |
655 | /** | |
1ce03373 | 656 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
657 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
658 | * | |
eaae4b3a | 659 | * Being called during hotplug remove, from which the device function |
1ce03373 | 660 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
661 | * allocated for this device function, are reclaimed to unused state, |
662 | * which may be used later on. | |
663 | **/ | |
664 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
665 | { | |
1da177e4 LT |
666 | if (!pci_msi_enable || !dev) |
667 | return; | |
668 | ||
032de8e2 ME |
669 | if (dev->msi_enabled) |
670 | msi_free_irqs(dev); | |
1da177e4 | 671 | |
fc4afc7b ME |
672 | if (dev->msix_enabled) |
673 | msix_free_all_irqs(dev); | |
1da177e4 LT |
674 | } |
675 | ||
309e57df MW |
676 | void pci_no_msi(void) |
677 | { | |
678 | pci_msi_enable = 0; | |
679 | } | |
c9953a73 | 680 | |
4aa9bc95 ME |
681 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
682 | { | |
683 | INIT_LIST_HEAD(&dev->msi_list); | |
684 | } | |
685 | ||
c9953a73 ME |
686 | |
687 | /* Arch hooks */ | |
688 | ||
689 | int __attribute__ ((weak)) | |
690 | arch_msi_check_device(struct pci_dev* dev, int nvec, int type) | |
691 | { | |
692 | return 0; | |
693 | } | |
694 | ||
9c831334 ME |
695 | int __attribute__ ((weak)) |
696 | arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *entry) | |
697 | { | |
698 | return 0; | |
699 | } | |
700 | ||
701 | int __attribute__ ((weak)) | |
702 | arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
703 | { | |
704 | struct msi_desc *entry; | |
705 | int ret; | |
706 | ||
707 | list_for_each_entry(entry, &dev->msi_list, list) { | |
708 | ret = arch_setup_msi_irq(dev, entry); | |
709 | if (ret) | |
710 | return ret; | |
711 | } | |
712 | ||
713 | return 0; | |
714 | } | |
032de8e2 ME |
715 | |
716 | void __attribute__ ((weak)) arch_teardown_msi_irq(unsigned int irq) | |
717 | { | |
718 | return; | |
719 | } | |
720 | ||
721 | void __attribute__ ((weak)) | |
722 | arch_teardown_msi_irqs(struct pci_dev *dev) | |
723 | { | |
724 | struct msi_desc *entry; | |
725 | ||
726 | list_for_each_entry(entry, &dev->msi_list, list) { | |
727 | if (entry->irq != 0) | |
728 | arch_teardown_msi_irq(entry->irq); | |
729 | } | |
730 | } |