Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 LT |
14 | #include <linux/ioport.h> |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/smp.h> | |
23 | ||
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
e18b890b | 27 | static struct kmem_cache* msi_cachep; |
1da177e4 LT |
28 | |
29 | static int pci_msi_enable = 1; | |
1da177e4 | 30 | |
1da177e4 LT |
31 | static int msi_cache_init(void) |
32 | { | |
57181784 PE |
33 | msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), |
34 | 0, SLAB_HWCACHE_ALIGN, NULL, NULL); | |
1da177e4 LT |
35 | if (!msi_cachep) |
36 | return -ENOMEM; | |
37 | ||
38 | return 0; | |
39 | } | |
40 | ||
1ce03373 | 41 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
42 | { |
43 | struct msi_desc *entry; | |
44 | ||
5b912c10 | 45 | entry = get_irq_msi(irq); |
277bc33b | 46 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
47 | switch (entry->msi_attrib.type) { |
48 | case PCI_CAP_ID_MSI: | |
277bc33b | 49 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
50 | int pos; |
51 | u32 mask_bits; | |
277bc33b EB |
52 | |
53 | pos = (long)entry->mask_base; | |
54 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
55 | mask_bits &= ~(1); | |
56 | mask_bits |= flag; | |
57 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
58 | } | |
1da177e4 | 59 | break; |
1da177e4 LT |
60 | case PCI_CAP_ID_MSIX: |
61 | { | |
62 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
63 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
64 | writel(flag, entry->mask_base + offset); | |
65 | break; | |
66 | } | |
67 | default: | |
277bc33b | 68 | BUG(); |
1da177e4 LT |
69 | break; |
70 | } | |
71 | } | |
72 | ||
3b7d1921 | 73 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 74 | { |
5b912c10 | 75 | struct msi_desc *entry = get_irq_msi(irq); |
0366f8f7 EB |
76 | switch(entry->msi_attrib.type) { |
77 | case PCI_CAP_ID_MSI: | |
78 | { | |
79 | struct pci_dev *dev = entry->dev; | |
80 | int pos = entry->msi_attrib.pos; | |
81 | u16 data; | |
82 | ||
83 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
84 | &msg->address_lo); | |
85 | if (entry->msi_attrib.is_64) { | |
86 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
87 | &msg->address_hi); | |
88 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
89 | } else { | |
90 | msg->address_hi = 0; | |
91 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
92 | } | |
93 | msg->data = data; | |
94 | break; | |
95 | } | |
96 | case PCI_CAP_ID_MSIX: | |
97 | { | |
98 | void __iomem *base; | |
99 | base = entry->mask_base + | |
100 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
101 | ||
102 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
103 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
104 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
105 | break; | |
106 | } | |
107 | default: | |
108 | BUG(); | |
109 | } | |
110 | } | |
1da177e4 | 111 | |
3b7d1921 | 112 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 113 | { |
5b912c10 | 114 | struct msi_desc *entry = get_irq_msi(irq); |
1da177e4 LT |
115 | switch (entry->msi_attrib.type) { |
116 | case PCI_CAP_ID_MSI: | |
117 | { | |
0366f8f7 EB |
118 | struct pci_dev *dev = entry->dev; |
119 | int pos = entry->msi_attrib.pos; | |
120 | ||
121 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
122 | msg->address_lo); | |
123 | if (entry->msi_attrib.is_64) { | |
124 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
125 | msg->address_hi); | |
126 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
127 | msg->data); | |
128 | } else { | |
129 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
130 | msg->data); | |
131 | } | |
1da177e4 LT |
132 | break; |
133 | } | |
134 | case PCI_CAP_ID_MSIX: | |
135 | { | |
0366f8f7 EB |
136 | void __iomem *base; |
137 | base = entry->mask_base + | |
138 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
139 | ||
140 | writel(msg->address_lo, | |
141 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
142 | writel(msg->address_hi, | |
143 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
144 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
145 | break; |
146 | } | |
147 | default: | |
0366f8f7 | 148 | BUG(); |
1da177e4 LT |
149 | } |
150 | } | |
0366f8f7 | 151 | |
3b7d1921 | 152 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 153 | { |
1ce03373 | 154 | msi_set_mask_bit(irq, 1); |
1da177e4 LT |
155 | } |
156 | ||
3b7d1921 | 157 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 158 | { |
1ce03373 | 159 | msi_set_mask_bit(irq, 0); |
1da177e4 LT |
160 | } |
161 | ||
1ce03373 | 162 | static int msi_free_irq(struct pci_dev* dev, int irq); |
c54c1879 | 163 | |
1da177e4 LT |
164 | static int msi_init(void) |
165 | { | |
166 | static int status = -ENOMEM; | |
167 | ||
168 | if (!status) | |
169 | return status; | |
170 | ||
b64c05e7 GG |
171 | status = msi_cache_init(); |
172 | if (status < 0) { | |
1da177e4 LT |
173 | pci_msi_enable = 0; |
174 | printk(KERN_WARNING "PCI: MSI cache init failed\n"); | |
175 | return status; | |
176 | } | |
fd58e55f | 177 | |
1da177e4 LT |
178 | return status; |
179 | } | |
180 | ||
1da177e4 LT |
181 | static struct msi_desc* alloc_msi_entry(void) |
182 | { | |
183 | struct msi_desc *entry; | |
184 | ||
57181784 | 185 | entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); |
1da177e4 LT |
186 | if (!entry) |
187 | return NULL; | |
188 | ||
1da177e4 LT |
189 | entry->link.tail = entry->link.head = 0; /* single message */ |
190 | entry->dev = NULL; | |
191 | ||
192 | return entry; | |
193 | } | |
194 | ||
3b7d1921 | 195 | static int create_msi_irq(void) |
1da177e4 | 196 | { |
1ce03373 EB |
197 | struct msi_desc *entry; |
198 | int irq; | |
199 | ||
200 | entry = alloc_msi_entry(); | |
201 | if (!entry) | |
202 | return -ENOMEM; | |
f6bc2666 | 203 | |
1ce03373 EB |
204 | irq = create_irq(); |
205 | if (irq < 0) { | |
206 | kmem_cache_free(msi_cachep, entry); | |
207 | return -EBUSY; | |
1da177e4 | 208 | } |
1ce03373 | 209 | |
5b912c10 | 210 | set_irq_msi(irq, entry); |
1ce03373 EB |
211 | |
212 | return irq; | |
213 | } | |
214 | ||
215 | static void destroy_msi_irq(unsigned int irq) | |
216 | { | |
217 | struct msi_desc *entry; | |
218 | ||
5b912c10 | 219 | entry = get_irq_msi(irq); |
1ce03373 | 220 | set_irq_chip(irq, NULL); |
5b912c10 | 221 | set_irq_msi(irq, NULL); |
1ce03373 EB |
222 | destroy_irq(irq); |
223 | kmem_cache_free(msi_cachep, entry); | |
1da177e4 LT |
224 | } |
225 | ||
226 | static void enable_msi_mode(struct pci_dev *dev, int pos, int type) | |
227 | { | |
228 | u16 control; | |
229 | ||
230 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
231 | if (type == PCI_CAP_ID_MSI) { | |
232 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
233 | msi_enable(control, 1); | |
234 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 235 | dev->msi_enabled = 1; |
1da177e4 LT |
236 | } else { |
237 | msix_enable(control); | |
238 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 239 | dev->msix_enabled = 1; |
1da177e4 | 240 | } |
1769b46a JG |
241 | |
242 | pci_intx(dev, 0); /* disable intx */ | |
1da177e4 LT |
243 | } |
244 | ||
4602b88d | 245 | void disable_msi_mode(struct pci_dev *dev, int pos, int type) |
1da177e4 LT |
246 | { |
247 | u16 control; | |
248 | ||
249 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
250 | if (type == PCI_CAP_ID_MSI) { | |
251 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
252 | msi_disable(control); | |
253 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 254 | dev->msi_enabled = 0; |
1da177e4 LT |
255 | } else { |
256 | msix_disable(control); | |
257 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 258 | dev->msix_enabled = 0; |
1da177e4 | 259 | } |
1769b46a JG |
260 | |
261 | pci_intx(dev, 1); /* enable intx */ | |
1da177e4 LT |
262 | } |
263 | ||
41017f0c | 264 | #ifdef CONFIG_PM |
8fed4b65 | 265 | static int __pci_save_msi_state(struct pci_dev *dev) |
41017f0c SL |
266 | { |
267 | int pos, i = 0; | |
268 | u16 control; | |
269 | struct pci_cap_saved_state *save_state; | |
270 | u32 *cap; | |
271 | ||
272 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
273 | if (pos <= 0 || dev->no_msi) | |
274 | return 0; | |
275 | ||
276 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
277 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
278 | return 0; | |
279 | ||
280 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, | |
281 | GFP_KERNEL); | |
282 | if (!save_state) { | |
283 | printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); | |
284 | return -ENOMEM; | |
285 | } | |
286 | cap = &save_state->data[0]; | |
287 | ||
288 | pci_read_config_dword(dev, pos, &cap[i++]); | |
289 | control = cap[0] >> 16; | |
290 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); | |
291 | if (control & PCI_MSI_FLAGS_64BIT) { | |
292 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); | |
293 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); | |
294 | } else | |
295 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); | |
296 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
297 | pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); | |
41017f0c SL |
298 | save_state->cap_nr = PCI_CAP_ID_MSI; |
299 | pci_add_saved_cap(dev, save_state); | |
300 | return 0; | |
301 | } | |
302 | ||
8fed4b65 | 303 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c SL |
304 | { |
305 | int i = 0, pos; | |
306 | u16 control; | |
307 | struct pci_cap_saved_state *save_state; | |
308 | u32 *cap; | |
309 | ||
310 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); | |
311 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
312 | if (!save_state || pos <= 0) | |
313 | return; | |
314 | cap = &save_state->data[0]; | |
315 | ||
316 | control = cap[i++] >> 16; | |
317 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); | |
318 | if (control & PCI_MSI_FLAGS_64BIT) { | |
319 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); | |
320 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); | |
321 | } else | |
322 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); | |
323 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
324 | pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); | |
325 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
326 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
327 | pci_remove_saved_cap(save_state); | |
328 | kfree(save_state); | |
329 | } | |
330 | ||
8fed4b65 | 331 | static int __pci_save_msix_state(struct pci_dev *dev) |
41017f0c SL |
332 | { |
333 | int pos; | |
1ce03373 | 334 | int irq, head, tail = 0; |
41017f0c SL |
335 | u16 control; |
336 | struct pci_cap_saved_state *save_state; | |
337 | ||
ded86d8d EB |
338 | if (!dev->msix_enabled) |
339 | return 0; | |
340 | ||
41017f0c SL |
341 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
342 | if (pos <= 0 || dev->no_msi) | |
343 | return 0; | |
344 | ||
fd58e55f | 345 | /* save the capability */ |
41017f0c SL |
346 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
347 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
348 | return 0; | |
349 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), | |
350 | GFP_KERNEL); | |
351 | if (!save_state) { | |
352 | printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); | |
353 | return -ENOMEM; | |
354 | } | |
355 | *((u16 *)&save_state->data[0]) = control; | |
356 | ||
fd58e55f | 357 | /* save the table */ |
ded86d8d | 358 | irq = head = dev->first_msi_irq; |
fd58e55f | 359 | while (head != tail) { |
fd58e55f MM |
360 | struct msi_desc *entry; |
361 | ||
5b912c10 | 362 | entry = get_irq_msi(irq); |
3b7d1921 | 363 | read_msi_msg(irq, &entry->msg_save); |
fd58e55f | 364 | |
5b912c10 | 365 | tail = entry->link.tail; |
1ce03373 | 366 | irq = tail; |
fd58e55f | 367 | } |
fd58e55f | 368 | |
41017f0c SL |
369 | save_state->cap_nr = PCI_CAP_ID_MSIX; |
370 | pci_add_saved_cap(dev, save_state); | |
371 | return 0; | |
372 | } | |
373 | ||
8fed4b65 ME |
374 | int pci_save_msi_state(struct pci_dev *dev) |
375 | { | |
376 | int rc; | |
377 | ||
378 | rc = __pci_save_msi_state(dev); | |
379 | if (rc) | |
380 | return rc; | |
381 | ||
382 | rc = __pci_save_msix_state(dev); | |
383 | ||
384 | return rc; | |
385 | } | |
386 | ||
387 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c SL |
388 | { |
389 | u16 save; | |
390 | int pos; | |
1ce03373 | 391 | int irq, head, tail = 0; |
41017f0c | 392 | struct msi_desc *entry; |
41017f0c SL |
393 | struct pci_cap_saved_state *save_state; |
394 | ||
ded86d8d EB |
395 | if (!dev->msix_enabled) |
396 | return; | |
397 | ||
41017f0c SL |
398 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); |
399 | if (!save_state) | |
400 | return; | |
401 | save = *((u16 *)&save_state->data[0]); | |
402 | pci_remove_saved_cap(save_state); | |
403 | kfree(save_state); | |
404 | ||
405 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
406 | if (pos <= 0) | |
407 | return; | |
408 | ||
409 | /* route the table */ | |
ded86d8d | 410 | irq = head = dev->first_msi_irq; |
41017f0c | 411 | while (head != tail) { |
5b912c10 | 412 | entry = get_irq_msi(irq); |
3b7d1921 | 413 | write_msi_msg(irq, &entry->msg_save); |
41017f0c | 414 | |
5b912c10 | 415 | tail = entry->link.tail; |
1ce03373 | 416 | irq = tail; |
41017f0c | 417 | } |
41017f0c SL |
418 | |
419 | pci_write_config_word(dev, msi_control_reg(pos), save); | |
420 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
421 | } | |
8fed4b65 ME |
422 | |
423 | void pci_restore_msi_state(struct pci_dev *dev) | |
424 | { | |
425 | __pci_restore_msi_state(dev); | |
426 | __pci_restore_msix_state(dev); | |
427 | } | |
c54c1879 | 428 | #endif /* CONFIG_PM */ |
41017f0c | 429 | |
1da177e4 LT |
430 | /** |
431 | * msi_capability_init - configure device's MSI capability structure | |
432 | * @dev: pointer to the pci_dev data structure of MSI device function | |
433 | * | |
eaae4b3a | 434 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 435 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 436 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 437 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
438 | **/ |
439 | static int msi_capability_init(struct pci_dev *dev) | |
440 | { | |
fd58e55f | 441 | int status; |
1da177e4 | 442 | struct msi_desc *entry; |
1ce03373 | 443 | int pos, irq; |
1da177e4 LT |
444 | u16 control; |
445 | ||
446 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
447 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
448 | /* MSI Entry Initialization */ | |
3b7d1921 | 449 | irq = create_msi_irq(); |
1ce03373 EB |
450 | if (irq < 0) |
451 | return irq; | |
452 | ||
5b912c10 | 453 | entry = get_irq_msi(irq); |
1ce03373 EB |
454 | entry->link.head = irq; |
455 | entry->link.tail = irq; | |
1da177e4 | 456 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 457 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
458 | entry->msi_attrib.entry_nr = 0; |
459 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 460 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 461 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
462 | if (is_mask_bit_support(control)) { |
463 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
464 | is_64bit_address(control)); | |
465 | } | |
3b7d1921 EB |
466 | entry->dev = dev; |
467 | if (entry->msi_attrib.maskbit) { | |
468 | unsigned int maskbits, temp; | |
469 | /* All MSIs are unmasked by default, Mask them all */ | |
470 | pci_read_config_dword(dev, | |
471 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
472 | &maskbits); | |
473 | temp = (1 << multi_msi_capable(control)); | |
474 | temp = ((temp - 1) & ~temp); | |
475 | maskbits |= temp; | |
476 | pci_write_config_dword(dev, | |
477 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
478 | maskbits); | |
479 | } | |
1da177e4 | 480 | /* Configure MSI capability structure */ |
3b7d1921 EB |
481 | status = arch_setup_msi_irq(irq, dev); |
482 | if (status < 0) { | |
1ce03373 | 483 | destroy_msi_irq(irq); |
fd58e55f MM |
484 | return status; |
485 | } | |
41017f0c | 486 | |
ded86d8d | 487 | dev->first_msi_irq = irq; |
5b912c10 | 488 | set_irq_msi(irq, entry); |
1da177e4 LT |
489 | /* Set MSI enabled bits */ |
490 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
491 | ||
3b7d1921 | 492 | dev->irq = irq; |
1da177e4 LT |
493 | return 0; |
494 | } | |
495 | ||
496 | /** | |
497 | * msix_capability_init - configure device's MSI-X capability | |
498 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
499 | * @entries: pointer to an array of struct msix_entry entries |
500 | * @nvec: number of @entries | |
1da177e4 | 501 | * |
eaae4b3a | 502 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
503 | * single MSI-X irq. A return of zero indicates the successful setup of |
504 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
505 | **/ |
506 | static int msix_capability_init(struct pci_dev *dev, | |
507 | struct msix_entry *entries, int nvec) | |
508 | { | |
509 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
fd58e55f | 510 | int status; |
1ce03373 | 511 | int irq, pos, i, j, nr_entries, temp = 0; |
a0454b40 GG |
512 | unsigned long phys_addr; |
513 | u32 table_offset; | |
1da177e4 LT |
514 | u16 control; |
515 | u8 bir; | |
516 | void __iomem *base; | |
517 | ||
518 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
519 | /* Request & Map MSI-X table region */ | |
520 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
521 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
522 | |
523 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 524 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
525 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
526 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
527 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
528 | if (base == NULL) | |
529 | return -ENOMEM; | |
530 | ||
531 | /* MSI-X Table Initialization */ | |
532 | for (i = 0; i < nvec; i++) { | |
3b7d1921 | 533 | irq = create_msi_irq(); |
1ce03373 | 534 | if (irq < 0) |
1da177e4 | 535 | break; |
1da177e4 | 536 | |
5b912c10 | 537 | entry = get_irq_msi(irq); |
1da177e4 | 538 | j = entries[i].entry; |
1ce03373 | 539 | entries[i].vector = irq; |
1da177e4 | 540 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 541 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
542 | entry->msi_attrib.entry_nr = j; |
543 | entry->msi_attrib.maskbit = 1; | |
1ce03373 | 544 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 545 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
546 | entry->dev = dev; |
547 | entry->mask_base = base; | |
548 | if (!head) { | |
1ce03373 EB |
549 | entry->link.head = irq; |
550 | entry->link.tail = irq; | |
1da177e4 LT |
551 | head = entry; |
552 | } else { | |
553 | entry->link.head = temp; | |
554 | entry->link.tail = tail->link.tail; | |
1ce03373 EB |
555 | tail->link.tail = irq; |
556 | head->link.head = irq; | |
1da177e4 | 557 | } |
1ce03373 | 558 | temp = irq; |
1da177e4 | 559 | tail = entry; |
1da177e4 | 560 | /* Configure MSI-X capability structure */ |
3b7d1921 | 561 | status = arch_setup_msi_irq(irq, dev); |
1ce03373 EB |
562 | if (status < 0) { |
563 | destroy_msi_irq(irq); | |
fd58e55f | 564 | break; |
1ce03373 | 565 | } |
fd58e55f | 566 | |
5b912c10 | 567 | set_irq_msi(irq, entry); |
1da177e4 LT |
568 | } |
569 | if (i != nvec) { | |
92db6d10 | 570 | int avail = i - 1; |
1da177e4 LT |
571 | i--; |
572 | for (; i >= 0; i--) { | |
1ce03373 EB |
573 | irq = (entries + i)->vector; |
574 | msi_free_irq(dev, irq); | |
1da177e4 LT |
575 | (entries + i)->vector = 0; |
576 | } | |
92db6d10 EB |
577 | /* If we had some success report the number of irqs |
578 | * we succeeded in setting up. | |
579 | */ | |
580 | if (avail <= 0) | |
581 | avail = -EBUSY; | |
582 | return avail; | |
1da177e4 | 583 | } |
ded86d8d | 584 | dev->first_msi_irq = entries[0].vector; |
1da177e4 LT |
585 | /* Set MSI-X enabled bits */ |
586 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
24334a12 BG |
591 | /** |
592 | * pci_msi_supported - check whether MSI may be enabled on device | |
593 | * @dev: pointer to the pci_dev data structure of MSI device function | |
594 | * | |
0306ebfa BG |
595 | * Look at global flags, the device itself, and its parent busses |
596 | * to return 0 if MSI are supported for the device. | |
24334a12 BG |
597 | **/ |
598 | static | |
599 | int pci_msi_supported(struct pci_dev * dev) | |
600 | { | |
601 | struct pci_bus *bus; | |
602 | ||
0306ebfa | 603 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
604 | if (!pci_msi_enable || !dev || dev->no_msi) |
605 | return -EINVAL; | |
606 | ||
0306ebfa BG |
607 | /* Any bridge which does NOT route MSI transactions from it's |
608 | * secondary bus to it's primary bus must set NO_MSI flag on | |
609 | * the secondary pci_bus. | |
610 | * We expect only arch-specific PCI host bus controller driver | |
611 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
612 | */ | |
24334a12 BG |
613 | for (bus = dev->bus; bus; bus = bus->parent) |
614 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
615 | return -EINVAL; | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
1da177e4 LT |
620 | /** |
621 | * pci_enable_msi - configure device's MSI capability structure | |
622 | * @dev: pointer to the pci_dev data structure of MSI device function | |
623 | * | |
624 | * Setup the MSI capability structure of device function with | |
1ce03373 | 625 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
626 | * MSI mode enabled on its hardware device function. A return of zero |
627 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 628 | * irq or non-zero for otherwise. |
1da177e4 LT |
629 | **/ |
630 | int pci_enable_msi(struct pci_dev* dev) | |
631 | { | |
ded86d8d | 632 | int pos, status; |
1da177e4 | 633 | |
24334a12 BG |
634 | if (pci_msi_supported(dev) < 0) |
635 | return -EINVAL; | |
6e325a62 | 636 | |
b64c05e7 GG |
637 | status = msi_init(); |
638 | if (status < 0) | |
1da177e4 LT |
639 | return status; |
640 | ||
b64c05e7 GG |
641 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
642 | if (!pos) | |
1da177e4 LT |
643 | return -EINVAL; |
644 | ||
ded86d8d | 645 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 646 | |
1ce03373 | 647 | /* Check whether driver already requested for MSI-X irqs */ |
b64c05e7 | 648 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
ded86d8d | 649 | if (pos > 0 && dev->msix_enabled) { |
1da177e4 | 650 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " |
ded86d8d | 651 | "Device already has MSI-X enabled\n", |
1da177e4 | 652 | pci_name(dev)); |
1da177e4 LT |
653 | return -EINVAL; |
654 | } | |
655 | status = msi_capability_init(dev); | |
1da177e4 LT |
656 | return status; |
657 | } | |
658 | ||
659 | void pci_disable_msi(struct pci_dev* dev) | |
660 | { | |
661 | struct msi_desc *entry; | |
1ce03373 | 662 | int pos, default_irq; |
1da177e4 | 663 | u16 control; |
1da177e4 | 664 | |
309e57df MW |
665 | if (!pci_msi_enable) |
666 | return; | |
b64c05e7 GG |
667 | if (!dev) |
668 | return; | |
309e57df | 669 | |
ded86d8d EB |
670 | if (!dev->msi_enabled) |
671 | return; | |
672 | ||
b64c05e7 GG |
673 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
674 | if (!pos) | |
1da177e4 LT |
675 | return; |
676 | ||
677 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
678 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
679 | return; | |
680 | ||
ded86d8d | 681 | |
7bd007e4 EB |
682 | disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); |
683 | ||
5b912c10 | 684 | entry = get_irq_msi(dev->first_msi_irq); |
1da177e4 | 685 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { |
1da177e4 LT |
686 | return; |
687 | } | |
ded86d8d | 688 | if (irq_has_action(dev->first_msi_irq)) { |
1da177e4 | 689 | printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " |
1ce03373 | 690 | "free_irq() on MSI irq %d\n", |
ded86d8d EB |
691 | pci_name(dev), dev->first_msi_irq); |
692 | BUG_ON(irq_has_action(dev->first_msi_irq)); | |
1da177e4 | 693 | } else { |
1ce03373 | 694 | default_irq = entry->msi_attrib.default_irq; |
ded86d8d | 695 | msi_free_irq(dev, dev->first_msi_irq); |
7bd007e4 | 696 | |
1ce03373 EB |
697 | /* Restore dev->irq to its default pin-assertion irq */ |
698 | dev->irq = default_irq; | |
1da177e4 | 699 | } |
ded86d8d | 700 | dev->first_msi_irq = 0; |
1da177e4 LT |
701 | } |
702 | ||
1ce03373 | 703 | static int msi_free_irq(struct pci_dev* dev, int irq) |
1da177e4 LT |
704 | { |
705 | struct msi_desc *entry; | |
706 | int head, entry_nr, type; | |
707 | void __iomem *base; | |
1da177e4 | 708 | |
3b7d1921 | 709 | arch_teardown_msi_irq(irq); |
fd58e55f | 710 | |
5b912c10 | 711 | entry = get_irq_msi(irq); |
1da177e4 | 712 | if (!entry || entry->dev != dev) { |
1da177e4 LT |
713 | return -EINVAL; |
714 | } | |
715 | type = entry->msi_attrib.type; | |
716 | entry_nr = entry->msi_attrib.entry_nr; | |
717 | head = entry->link.head; | |
718 | base = entry->mask_base; | |
5b912c10 EB |
719 | get_irq_msi(entry->link.head)->link.tail = entry->link.tail; |
720 | get_irq_msi(entry->link.tail)->link.head = entry->link.head; | |
1da177e4 | 721 | entry->dev = NULL; |
1da177e4 | 722 | |
1ce03373 | 723 | destroy_msi_irq(irq); |
1da177e4 LT |
724 | |
725 | if (type == PCI_CAP_ID_MSIX) { | |
1ce03373 EB |
726 | writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + |
727 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
1da177e4 | 728 | |
1ce03373 | 729 | if (head == irq) |
1da177e4 | 730 | iounmap(base); |
1da177e4 LT |
731 | } |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
1da177e4 LT |
736 | /** |
737 | * pci_enable_msix - configure device's MSI-X capability structure | |
738 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 739 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 740 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
741 | * |
742 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 743 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
744 | * MSI-X mode enabled on its hardware device function. A return of zero |
745 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 746 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 747 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 748 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
749 | * its request. |
750 | **/ | |
751 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
752 | { | |
92db6d10 | 753 | int status, pos, nr_entries; |
ded86d8d | 754 | int i, j; |
1da177e4 | 755 | u16 control; |
1da177e4 | 756 | |
24334a12 | 757 | if (!entries || pci_msi_supported(dev) < 0) |
1da177e4 LT |
758 | return -EINVAL; |
759 | ||
b64c05e7 GG |
760 | status = msi_init(); |
761 | if (status < 0) | |
1da177e4 LT |
762 | return status; |
763 | ||
b64c05e7 GG |
764 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
765 | if (!pos) | |
1da177e4 LT |
766 | return -EINVAL; |
767 | ||
768 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1da177e4 LT |
769 | nr_entries = multi_msix_capable(control); |
770 | if (nvec > nr_entries) | |
771 | return -EINVAL; | |
772 | ||
773 | /* Check for any invalid entries */ | |
774 | for (i = 0; i < nvec; i++) { | |
775 | if (entries[i].entry >= nr_entries) | |
776 | return -EINVAL; /* invalid entry */ | |
777 | for (j = i + 1; j < nvec; j++) { | |
778 | if (entries[i].entry == entries[j].entry) | |
779 | return -EINVAL; /* duplicate entry */ | |
780 | } | |
781 | } | |
ded86d8d | 782 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 783 | |
1ce03373 | 784 | /* Check whether driver already requested for MSI irq */ |
1da177e4 | 785 | if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && |
ded86d8d | 786 | dev->msi_enabled) { |
1da177e4 | 787 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 788 | "Device already has an MSI irq assigned\n", |
1da177e4 | 789 | pci_name(dev)); |
1da177e4 LT |
790 | return -EINVAL; |
791 | } | |
1da177e4 | 792 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
793 | return status; |
794 | } | |
795 | ||
796 | void pci_disable_msix(struct pci_dev* dev) | |
797 | { | |
ded86d8d | 798 | int irq, head, tail = 0, warning = 0; |
ded86d8d | 799 | int pos; |
1da177e4 LT |
800 | u16 control; |
801 | ||
309e57df MW |
802 | if (!pci_msi_enable) |
803 | return; | |
b64c05e7 GG |
804 | if (!dev) |
805 | return; | |
806 | ||
ded86d8d EB |
807 | if (!dev->msix_enabled) |
808 | return; | |
809 | ||
b64c05e7 GG |
810 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
811 | if (!pos) | |
1da177e4 LT |
812 | return; |
813 | ||
814 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
815 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
816 | return; | |
817 | ||
7bd007e4 EB |
818 | disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); |
819 | ||
ded86d8d EB |
820 | irq = head = dev->first_msi_irq; |
821 | while (head != tail) { | |
5b912c10 | 822 | tail = get_irq_msi(irq)->link.tail; |
ded86d8d EB |
823 | if (irq_has_action(irq)) |
824 | warning = 1; | |
825 | else if (irq != head) /* Release MSI-X irq */ | |
826 | msi_free_irq(dev, irq); | |
827 | irq = tail; | |
828 | } | |
829 | msi_free_irq(dev, irq); | |
830 | if (warning) { | |
831 | printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " | |
832 | "free_irq() on all MSI-X irqs\n", | |
833 | pci_name(dev)); | |
834 | BUG_ON(warning > 0); | |
1da177e4 | 835 | } |
ded86d8d | 836 | dev->first_msi_irq = 0; |
1da177e4 LT |
837 | } |
838 | ||
839 | /** | |
1ce03373 | 840 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
841 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
842 | * | |
eaae4b3a | 843 | * Being called during hotplug remove, from which the device function |
1ce03373 | 844 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
845 | * allocated for this device function, are reclaimed to unused state, |
846 | * which may be used later on. | |
847 | **/ | |
848 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
849 | { | |
1da177e4 LT |
850 | if (!pci_msi_enable || !dev) |
851 | return; | |
852 | ||
866a8c87 | 853 | if (dev->msi_enabled) { |
ded86d8d | 854 | if (irq_has_action(dev->first_msi_irq)) { |
1da177e4 | 855 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " |
1ce03373 | 856 | "called without free_irq() on MSI irq %d\n", |
ded86d8d EB |
857 | pci_name(dev), dev->first_msi_irq); |
858 | BUG_ON(irq_has_action(dev->first_msi_irq)); | |
1ce03373 | 859 | } else /* Release MSI irq assigned to this device */ |
ded86d8d | 860 | msi_free_irq(dev, dev->first_msi_irq); |
1da177e4 | 861 | } |
866a8c87 | 862 | if (dev->msix_enabled) { |
1ce03373 | 863 | int irq, head, tail = 0, warning = 0; |
1da177e4 LT |
864 | void __iomem *base = NULL; |
865 | ||
ded86d8d | 866 | irq = head = dev->first_msi_irq; |
1da177e4 | 867 | while (head != tail) { |
5b912c10 EB |
868 | tail = get_irq_msi(irq)->link.tail; |
869 | base = get_irq_msi(irq)->mask_base; | |
1f80025e | 870 | if (irq_has_action(irq)) |
1da177e4 | 871 | warning = 1; |
1ce03373 EB |
872 | else if (irq != head) /* Release MSI-X irq */ |
873 | msi_free_irq(dev, irq); | |
874 | irq = tail; | |
1da177e4 | 875 | } |
1ce03373 | 876 | msi_free_irq(dev, irq); |
1da177e4 | 877 | if (warning) { |
1da177e4 LT |
878 | iounmap(base); |
879 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1ce03373 | 880 | "called without free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
881 | pci_name(dev)); |
882 | BUG_ON(warning > 0); | |
883 | } | |
1da177e4 LT |
884 | } |
885 | } | |
886 | ||
309e57df MW |
887 | void pci_no_msi(void) |
888 | { | |
889 | pci_msi_enable = 0; | |
890 | } | |
891 | ||
1da177e4 LT |
892 | EXPORT_SYMBOL(pci_enable_msi); |
893 | EXPORT_SYMBOL(pci_disable_msi); | |
894 | EXPORT_SYMBOL(pci_enable_msix); | |
895 | EXPORT_SYMBOL(pci_disable_msix); |