Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 LT |
14 | #include <linux/ioport.h> |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/smp.h> | |
23 | ||
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
e18b890b | 27 | static struct kmem_cache* msi_cachep; |
1da177e4 LT |
28 | |
29 | static int pci_msi_enable = 1; | |
1da177e4 | 30 | |
1da177e4 LT |
31 | static int msi_cache_init(void) |
32 | { | |
57181784 PE |
33 | msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), |
34 | 0, SLAB_HWCACHE_ALIGN, NULL, NULL); | |
1da177e4 LT |
35 | if (!msi_cachep) |
36 | return -ENOMEM; | |
37 | ||
38 | return 0; | |
39 | } | |
40 | ||
b1cbf4e4 EB |
41 | static void msi_set_enable(struct pci_dev *dev, int enable) |
42 | { | |
43 | int pos; | |
44 | u16 control; | |
45 | ||
46 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
47 | if (pos) { | |
48 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
49 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
50 | if (enable) | |
51 | control |= PCI_MSI_FLAGS_ENABLE; | |
52 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
53 | } | |
54 | } | |
55 | ||
56 | static void msix_set_enable(struct pci_dev *dev, int enable) | |
57 | { | |
58 | int pos; | |
59 | u16 control; | |
60 | ||
61 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
62 | if (pos) { | |
63 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
64 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
65 | if (enable) | |
66 | control |= PCI_MSIX_FLAGS_ENABLE; | |
67 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
68 | } | |
69 | } | |
70 | ||
988cbb15 MW |
71 | static void msix_flush_writes(unsigned int irq) |
72 | { | |
73 | struct msi_desc *entry; | |
74 | ||
75 | entry = get_irq_msi(irq); | |
76 | BUG_ON(!entry || !entry->dev); | |
77 | switch (entry->msi_attrib.type) { | |
78 | case PCI_CAP_ID_MSI: | |
79 | /* nothing to do */ | |
80 | break; | |
81 | case PCI_CAP_ID_MSIX: | |
82 | { | |
83 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
84 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
85 | readl(entry->mask_base + offset); | |
86 | break; | |
87 | } | |
88 | default: | |
89 | BUG(); | |
90 | break; | |
91 | } | |
92 | } | |
93 | ||
1ce03373 | 94 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
95 | { |
96 | struct msi_desc *entry; | |
97 | ||
5b912c10 | 98 | entry = get_irq_msi(irq); |
277bc33b | 99 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
100 | switch (entry->msi_attrib.type) { |
101 | case PCI_CAP_ID_MSI: | |
277bc33b | 102 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
103 | int pos; |
104 | u32 mask_bits; | |
277bc33b EB |
105 | |
106 | pos = (long)entry->mask_base; | |
107 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
108 | mask_bits &= ~(1); | |
109 | mask_bits |= flag; | |
110 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
58e0543e EB |
111 | } else { |
112 | msi_set_enable(entry->dev, !flag); | |
277bc33b | 113 | } |
1da177e4 | 114 | break; |
1da177e4 LT |
115 | case PCI_CAP_ID_MSIX: |
116 | { | |
117 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
118 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
119 | writel(flag, entry->mask_base + offset); | |
348e3fd1 | 120 | readl(entry->mask_base + offset); |
1da177e4 LT |
121 | break; |
122 | } | |
123 | default: | |
277bc33b | 124 | BUG(); |
1da177e4 LT |
125 | break; |
126 | } | |
392ee1e6 | 127 | entry->msi_attrib.masked = !!flag; |
1da177e4 LT |
128 | } |
129 | ||
3b7d1921 | 130 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 131 | { |
5b912c10 | 132 | struct msi_desc *entry = get_irq_msi(irq); |
0366f8f7 EB |
133 | switch(entry->msi_attrib.type) { |
134 | case PCI_CAP_ID_MSI: | |
135 | { | |
136 | struct pci_dev *dev = entry->dev; | |
137 | int pos = entry->msi_attrib.pos; | |
138 | u16 data; | |
139 | ||
140 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
141 | &msg->address_lo); | |
142 | if (entry->msi_attrib.is_64) { | |
143 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
144 | &msg->address_hi); | |
145 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
146 | } else { | |
147 | msg->address_hi = 0; | |
148 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
149 | } | |
150 | msg->data = data; | |
151 | break; | |
152 | } | |
153 | case PCI_CAP_ID_MSIX: | |
154 | { | |
155 | void __iomem *base; | |
156 | base = entry->mask_base + | |
157 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
158 | ||
159 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
160 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
161 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
162 | break; | |
163 | } | |
164 | default: | |
165 | BUG(); | |
166 | } | |
167 | } | |
1da177e4 | 168 | |
3b7d1921 | 169 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 170 | { |
5b912c10 | 171 | struct msi_desc *entry = get_irq_msi(irq); |
1da177e4 LT |
172 | switch (entry->msi_attrib.type) { |
173 | case PCI_CAP_ID_MSI: | |
174 | { | |
0366f8f7 EB |
175 | struct pci_dev *dev = entry->dev; |
176 | int pos = entry->msi_attrib.pos; | |
177 | ||
178 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
179 | msg->address_lo); | |
180 | if (entry->msi_attrib.is_64) { | |
181 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
182 | msg->address_hi); | |
183 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
184 | msg->data); | |
185 | } else { | |
186 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
187 | msg->data); | |
188 | } | |
1da177e4 LT |
189 | break; |
190 | } | |
191 | case PCI_CAP_ID_MSIX: | |
192 | { | |
0366f8f7 EB |
193 | void __iomem *base; |
194 | base = entry->mask_base + | |
195 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
196 | ||
197 | writel(msg->address_lo, | |
198 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
199 | writel(msg->address_hi, | |
200 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
201 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
202 | break; |
203 | } | |
204 | default: | |
0366f8f7 | 205 | BUG(); |
1da177e4 | 206 | } |
392ee1e6 | 207 | entry->msg = *msg; |
1da177e4 | 208 | } |
0366f8f7 | 209 | |
3b7d1921 | 210 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 211 | { |
1ce03373 | 212 | msi_set_mask_bit(irq, 1); |
988cbb15 | 213 | msix_flush_writes(irq); |
1da177e4 LT |
214 | } |
215 | ||
3b7d1921 | 216 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 217 | { |
1ce03373 | 218 | msi_set_mask_bit(irq, 0); |
988cbb15 | 219 | msix_flush_writes(irq); |
1da177e4 LT |
220 | } |
221 | ||
1ce03373 | 222 | static int msi_free_irq(struct pci_dev* dev, int irq); |
c54c1879 | 223 | |
1da177e4 LT |
224 | static int msi_init(void) |
225 | { | |
226 | static int status = -ENOMEM; | |
227 | ||
228 | if (!status) | |
229 | return status; | |
230 | ||
b64c05e7 GG |
231 | status = msi_cache_init(); |
232 | if (status < 0) { | |
1da177e4 LT |
233 | pci_msi_enable = 0; |
234 | printk(KERN_WARNING "PCI: MSI cache init failed\n"); | |
235 | return status; | |
236 | } | |
fd58e55f | 237 | |
1da177e4 LT |
238 | return status; |
239 | } | |
240 | ||
1da177e4 LT |
241 | static struct msi_desc* alloc_msi_entry(void) |
242 | { | |
243 | struct msi_desc *entry; | |
244 | ||
57181784 | 245 | entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); |
1da177e4 LT |
246 | if (!entry) |
247 | return NULL; | |
248 | ||
1da177e4 LT |
249 | entry->link.tail = entry->link.head = 0; /* single message */ |
250 | entry->dev = NULL; | |
251 | ||
252 | return entry; | |
253 | } | |
254 | ||
41017f0c | 255 | #ifdef CONFIG_PM |
8fed4b65 | 256 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 257 | { |
392ee1e6 | 258 | int pos; |
41017f0c | 259 | u16 control; |
392ee1e6 | 260 | struct msi_desc *entry; |
41017f0c | 261 | |
b1cbf4e4 EB |
262 | if (!dev->msi_enabled) |
263 | return; | |
264 | ||
392ee1e6 EB |
265 | entry = get_irq_msi(dev->irq); |
266 | pos = entry->msi_attrib.pos; | |
41017f0c | 267 | |
b1cbf4e4 | 268 | pci_intx(dev, 0); /* disable intx */ |
b1cbf4e4 | 269 | msi_set_enable(dev, 0); |
392ee1e6 EB |
270 | write_msi_msg(dev->irq, &entry->msg); |
271 | if (entry->msi_attrib.maskbit) | |
272 | msi_set_mask_bit(dev->irq, entry->msi_attrib.masked); | |
273 | ||
274 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
275 | control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE); | |
276 | if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked) | |
277 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 278 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
279 | } |
280 | ||
281 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 282 | { |
41017f0c | 283 | int pos; |
1ce03373 | 284 | int irq, head, tail = 0; |
41017f0c | 285 | struct msi_desc *entry; |
392ee1e6 | 286 | u16 control; |
41017f0c | 287 | |
ded86d8d EB |
288 | if (!dev->msix_enabled) |
289 | return; | |
290 | ||
41017f0c | 291 | /* route the table */ |
b1cbf4e4 EB |
292 | pci_intx(dev, 0); /* disable intx */ |
293 | msix_set_enable(dev, 0); | |
ded86d8d | 294 | irq = head = dev->first_msi_irq; |
392ee1e6 EB |
295 | entry = get_irq_msi(irq); |
296 | pos = entry->msi_attrib.pos; | |
41017f0c | 297 | while (head != tail) { |
5b912c10 | 298 | entry = get_irq_msi(irq); |
392ee1e6 EB |
299 | write_msi_msg(irq, &entry->msg); |
300 | msi_set_mask_bit(irq, entry->msi_attrib.masked); | |
41017f0c | 301 | |
5b912c10 | 302 | tail = entry->link.tail; |
1ce03373 | 303 | irq = tail; |
41017f0c | 304 | } |
41017f0c | 305 | |
392ee1e6 EB |
306 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
307 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
308 | control |= PCI_MSIX_FLAGS_ENABLE; | |
309 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 310 | } |
8fed4b65 ME |
311 | |
312 | void pci_restore_msi_state(struct pci_dev *dev) | |
313 | { | |
314 | __pci_restore_msi_state(dev); | |
315 | __pci_restore_msix_state(dev); | |
316 | } | |
c54c1879 | 317 | #endif /* CONFIG_PM */ |
41017f0c | 318 | |
1da177e4 LT |
319 | /** |
320 | * msi_capability_init - configure device's MSI capability structure | |
321 | * @dev: pointer to the pci_dev data structure of MSI device function | |
322 | * | |
eaae4b3a | 323 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 324 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 325 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 326 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
327 | **/ |
328 | static int msi_capability_init(struct pci_dev *dev) | |
329 | { | |
330 | struct msi_desc *entry; | |
1ce03373 | 331 | int pos, irq; |
1da177e4 LT |
332 | u16 control; |
333 | ||
b1cbf4e4 EB |
334 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
335 | ||
1da177e4 LT |
336 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
337 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
338 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
339 | entry = alloc_msi_entry(); |
340 | if (!entry) | |
341 | return -ENOMEM; | |
1ce03373 | 342 | |
1da177e4 | 343 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 344 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
345 | entry->msi_attrib.entry_nr = 0; |
346 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 347 | entry->msi_attrib.masked = 1; |
1ce03373 | 348 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 349 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
350 | if (is_mask_bit_support(control)) { |
351 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
352 | is_64bit_address(control)); | |
353 | } | |
3b7d1921 EB |
354 | entry->dev = dev; |
355 | if (entry->msi_attrib.maskbit) { | |
356 | unsigned int maskbits, temp; | |
357 | /* All MSIs are unmasked by default, Mask them all */ | |
358 | pci_read_config_dword(dev, | |
359 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
360 | &maskbits); | |
361 | temp = (1 << multi_msi_capable(control)); | |
362 | temp = ((temp - 1) & ~temp); | |
363 | maskbits |= temp; | |
364 | pci_write_config_dword(dev, | |
365 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
366 | maskbits); | |
367 | } | |
1da177e4 | 368 | /* Configure MSI capability structure */ |
f7feaca7 EB |
369 | irq = arch_setup_msi_irq(dev, entry); |
370 | if (irq < 0) { | |
371 | kmem_cache_free(msi_cachep, entry); | |
372 | return irq; | |
fd58e55f | 373 | } |
f7feaca7 EB |
374 | entry->link.head = irq; |
375 | entry->link.tail = irq; | |
ded86d8d | 376 | dev->first_msi_irq = irq; |
5b912c10 | 377 | set_irq_msi(irq, entry); |
f7feaca7 | 378 | |
1da177e4 | 379 | /* Set MSI enabled bits */ |
b1cbf4e4 EB |
380 | pci_intx(dev, 0); /* disable intx */ |
381 | msi_set_enable(dev, 1); | |
382 | dev->msi_enabled = 1; | |
1da177e4 | 383 | |
3b7d1921 | 384 | dev->irq = irq; |
1da177e4 LT |
385 | return 0; |
386 | } | |
387 | ||
388 | /** | |
389 | * msix_capability_init - configure device's MSI-X capability | |
390 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
391 | * @entries: pointer to an array of struct msix_entry entries |
392 | * @nvec: number of @entries | |
1da177e4 | 393 | * |
eaae4b3a | 394 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
395 | * single MSI-X irq. A return of zero indicates the successful setup of |
396 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
397 | **/ |
398 | static int msix_capability_init(struct pci_dev *dev, | |
399 | struct msix_entry *entries, int nvec) | |
400 | { | |
401 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
1ce03373 | 402 | int irq, pos, i, j, nr_entries, temp = 0; |
a0454b40 GG |
403 | unsigned long phys_addr; |
404 | u32 table_offset; | |
1da177e4 LT |
405 | u16 control; |
406 | u8 bir; | |
407 | void __iomem *base; | |
408 | ||
b1cbf4e4 EB |
409 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
410 | ||
1da177e4 LT |
411 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
412 | /* Request & Map MSI-X table region */ | |
413 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
414 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
415 | |
416 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 417 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
418 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
419 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
420 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
421 | if (base == NULL) | |
422 | return -ENOMEM; | |
423 | ||
424 | /* MSI-X Table Initialization */ | |
425 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
426 | entry = alloc_msi_entry(); |
427 | if (!entry) | |
1da177e4 | 428 | break; |
1da177e4 LT |
429 | |
430 | j = entries[i].entry; | |
1da177e4 | 431 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 432 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
433 | entry->msi_attrib.entry_nr = j; |
434 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 435 | entry->msi_attrib.masked = 1; |
1ce03373 | 436 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 437 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
438 | entry->dev = dev; |
439 | entry->mask_base = base; | |
f7feaca7 EB |
440 | |
441 | /* Configure MSI-X capability structure */ | |
442 | irq = arch_setup_msi_irq(dev, entry); | |
443 | if (irq < 0) { | |
444 | kmem_cache_free(msi_cachep, entry); | |
445 | break; | |
446 | } | |
447 | entries[i].vector = irq; | |
1da177e4 | 448 | if (!head) { |
1ce03373 EB |
449 | entry->link.head = irq; |
450 | entry->link.tail = irq; | |
1da177e4 LT |
451 | head = entry; |
452 | } else { | |
453 | entry->link.head = temp; | |
454 | entry->link.tail = tail->link.tail; | |
1ce03373 EB |
455 | tail->link.tail = irq; |
456 | head->link.head = irq; | |
1da177e4 | 457 | } |
1ce03373 | 458 | temp = irq; |
1da177e4 | 459 | tail = entry; |
fd58e55f | 460 | |
5b912c10 | 461 | set_irq_msi(irq, entry); |
1da177e4 LT |
462 | } |
463 | if (i != nvec) { | |
92db6d10 | 464 | int avail = i - 1; |
1da177e4 LT |
465 | i--; |
466 | for (; i >= 0; i--) { | |
1ce03373 EB |
467 | irq = (entries + i)->vector; |
468 | msi_free_irq(dev, irq); | |
1da177e4 LT |
469 | (entries + i)->vector = 0; |
470 | } | |
92db6d10 EB |
471 | /* If we had some success report the number of irqs |
472 | * we succeeded in setting up. | |
473 | */ | |
474 | if (avail <= 0) | |
475 | avail = -EBUSY; | |
476 | return avail; | |
1da177e4 | 477 | } |
ded86d8d | 478 | dev->first_msi_irq = entries[0].vector; |
1da177e4 | 479 | /* Set MSI-X enabled bits */ |
b1cbf4e4 EB |
480 | pci_intx(dev, 0); /* disable intx */ |
481 | msix_set_enable(dev, 1); | |
482 | dev->msix_enabled = 1; | |
1da177e4 LT |
483 | |
484 | return 0; | |
485 | } | |
486 | ||
24334a12 BG |
487 | /** |
488 | * pci_msi_supported - check whether MSI may be enabled on device | |
489 | * @dev: pointer to the pci_dev data structure of MSI device function | |
490 | * | |
0306ebfa BG |
491 | * Look at global flags, the device itself, and its parent busses |
492 | * to return 0 if MSI are supported for the device. | |
24334a12 BG |
493 | **/ |
494 | static | |
495 | int pci_msi_supported(struct pci_dev * dev) | |
496 | { | |
497 | struct pci_bus *bus; | |
498 | ||
0306ebfa | 499 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
500 | if (!pci_msi_enable || !dev || dev->no_msi) |
501 | return -EINVAL; | |
502 | ||
0306ebfa BG |
503 | /* Any bridge which does NOT route MSI transactions from it's |
504 | * secondary bus to it's primary bus must set NO_MSI flag on | |
505 | * the secondary pci_bus. | |
506 | * We expect only arch-specific PCI host bus controller driver | |
507 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
508 | */ | |
24334a12 BG |
509 | for (bus = dev->bus; bus; bus = bus->parent) |
510 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
511 | return -EINVAL; | |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
1da177e4 LT |
516 | /** |
517 | * pci_enable_msi - configure device's MSI capability structure | |
518 | * @dev: pointer to the pci_dev data structure of MSI device function | |
519 | * | |
520 | * Setup the MSI capability structure of device function with | |
1ce03373 | 521 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
522 | * MSI mode enabled on its hardware device function. A return of zero |
523 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 524 | * irq or non-zero for otherwise. |
1da177e4 LT |
525 | **/ |
526 | int pci_enable_msi(struct pci_dev* dev) | |
527 | { | |
ded86d8d | 528 | int pos, status; |
1da177e4 | 529 | |
24334a12 BG |
530 | if (pci_msi_supported(dev) < 0) |
531 | return -EINVAL; | |
6e325a62 | 532 | |
b64c05e7 GG |
533 | status = msi_init(); |
534 | if (status < 0) | |
1da177e4 LT |
535 | return status; |
536 | ||
b64c05e7 GG |
537 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
538 | if (!pos) | |
1da177e4 LT |
539 | return -EINVAL; |
540 | ||
ded86d8d | 541 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 542 | |
1ce03373 | 543 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 EB |
544 | if (dev->msix_enabled) { |
545 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " | |
546 | "Device already has MSI-X enabled\n", | |
547 | pci_name(dev)); | |
548 | return -EINVAL; | |
1da177e4 LT |
549 | } |
550 | status = msi_capability_init(dev); | |
1da177e4 LT |
551 | return status; |
552 | } | |
553 | ||
554 | void pci_disable_msi(struct pci_dev* dev) | |
555 | { | |
556 | struct msi_desc *entry; | |
b1cbf4e4 | 557 | int default_irq; |
1da177e4 | 558 | |
309e57df MW |
559 | if (!pci_msi_enable) |
560 | return; | |
b64c05e7 GG |
561 | if (!dev) |
562 | return; | |
309e57df | 563 | |
ded86d8d EB |
564 | if (!dev->msi_enabled) |
565 | return; | |
566 | ||
b1cbf4e4 EB |
567 | msi_set_enable(dev, 0); |
568 | pci_intx(dev, 1); /* enable intx */ | |
569 | dev->msi_enabled = 0; | |
7bd007e4 | 570 | |
5b912c10 | 571 | entry = get_irq_msi(dev->first_msi_irq); |
1da177e4 | 572 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { |
1da177e4 LT |
573 | return; |
574 | } | |
ded86d8d | 575 | if (irq_has_action(dev->first_msi_irq)) { |
1da177e4 | 576 | printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " |
1ce03373 | 577 | "free_irq() on MSI irq %d\n", |
ded86d8d EB |
578 | pci_name(dev), dev->first_msi_irq); |
579 | BUG_ON(irq_has_action(dev->first_msi_irq)); | |
1da177e4 | 580 | } else { |
1ce03373 | 581 | default_irq = entry->msi_attrib.default_irq; |
ded86d8d | 582 | msi_free_irq(dev, dev->first_msi_irq); |
7bd007e4 | 583 | |
1ce03373 EB |
584 | /* Restore dev->irq to its default pin-assertion irq */ |
585 | dev->irq = default_irq; | |
1da177e4 | 586 | } |
ded86d8d | 587 | dev->first_msi_irq = 0; |
1da177e4 LT |
588 | } |
589 | ||
1ce03373 | 590 | static int msi_free_irq(struct pci_dev* dev, int irq) |
1da177e4 LT |
591 | { |
592 | struct msi_desc *entry; | |
593 | int head, entry_nr, type; | |
594 | void __iomem *base; | |
1da177e4 | 595 | |
5b912c10 | 596 | entry = get_irq_msi(irq); |
1da177e4 | 597 | if (!entry || entry->dev != dev) { |
1da177e4 LT |
598 | return -EINVAL; |
599 | } | |
600 | type = entry->msi_attrib.type; | |
601 | entry_nr = entry->msi_attrib.entry_nr; | |
602 | head = entry->link.head; | |
603 | base = entry->mask_base; | |
5b912c10 EB |
604 | get_irq_msi(entry->link.head)->link.tail = entry->link.tail; |
605 | get_irq_msi(entry->link.tail)->link.head = entry->link.head; | |
1da177e4 | 606 | |
f7feaca7 EB |
607 | arch_teardown_msi_irq(irq); |
608 | kmem_cache_free(msi_cachep, entry); | |
1da177e4 LT |
609 | |
610 | if (type == PCI_CAP_ID_MSIX) { | |
1ce03373 EB |
611 | writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + |
612 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
1da177e4 | 613 | |
1ce03373 | 614 | if (head == irq) |
1da177e4 | 615 | iounmap(base); |
1da177e4 LT |
616 | } |
617 | ||
618 | return 0; | |
619 | } | |
620 | ||
1da177e4 LT |
621 | /** |
622 | * pci_enable_msix - configure device's MSI-X capability structure | |
623 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 624 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 625 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
626 | * |
627 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 628 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
629 | * MSI-X mode enabled on its hardware device function. A return of zero |
630 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 631 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 632 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 633 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
634 | * its request. |
635 | **/ | |
636 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
637 | { | |
92db6d10 | 638 | int status, pos, nr_entries; |
ded86d8d | 639 | int i, j; |
1da177e4 | 640 | u16 control; |
1da177e4 | 641 | |
24334a12 | 642 | if (!entries || pci_msi_supported(dev) < 0) |
1da177e4 LT |
643 | return -EINVAL; |
644 | ||
b64c05e7 GG |
645 | status = msi_init(); |
646 | if (status < 0) | |
1da177e4 LT |
647 | return status; |
648 | ||
b64c05e7 GG |
649 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
650 | if (!pos) | |
1da177e4 LT |
651 | return -EINVAL; |
652 | ||
653 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1da177e4 LT |
654 | nr_entries = multi_msix_capable(control); |
655 | if (nvec > nr_entries) | |
656 | return -EINVAL; | |
657 | ||
658 | /* Check for any invalid entries */ | |
659 | for (i = 0; i < nvec; i++) { | |
660 | if (entries[i].entry >= nr_entries) | |
661 | return -EINVAL; /* invalid entry */ | |
662 | for (j = i + 1; j < nvec; j++) { | |
663 | if (entries[i].entry == entries[j].entry) | |
664 | return -EINVAL; /* duplicate entry */ | |
665 | } | |
666 | } | |
ded86d8d | 667 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 668 | |
1ce03373 | 669 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 670 | if (dev->msi_enabled) { |
1da177e4 | 671 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 672 | "Device already has an MSI irq assigned\n", |
1da177e4 | 673 | pci_name(dev)); |
1da177e4 LT |
674 | return -EINVAL; |
675 | } | |
1da177e4 | 676 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
677 | return status; |
678 | } | |
679 | ||
680 | void pci_disable_msix(struct pci_dev* dev) | |
681 | { | |
ded86d8d | 682 | int irq, head, tail = 0, warning = 0; |
1da177e4 | 683 | |
309e57df MW |
684 | if (!pci_msi_enable) |
685 | return; | |
b64c05e7 GG |
686 | if (!dev) |
687 | return; | |
688 | ||
ded86d8d EB |
689 | if (!dev->msix_enabled) |
690 | return; | |
691 | ||
b1cbf4e4 EB |
692 | msix_set_enable(dev, 0); |
693 | pci_intx(dev, 1); /* enable intx */ | |
694 | dev->msix_enabled = 0; | |
7bd007e4 | 695 | |
ded86d8d EB |
696 | irq = head = dev->first_msi_irq; |
697 | while (head != tail) { | |
5b912c10 | 698 | tail = get_irq_msi(irq)->link.tail; |
ded86d8d EB |
699 | if (irq_has_action(irq)) |
700 | warning = 1; | |
701 | else if (irq != head) /* Release MSI-X irq */ | |
702 | msi_free_irq(dev, irq); | |
703 | irq = tail; | |
704 | } | |
705 | msi_free_irq(dev, irq); | |
706 | if (warning) { | |
707 | printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " | |
708 | "free_irq() on all MSI-X irqs\n", | |
709 | pci_name(dev)); | |
710 | BUG_ON(warning > 0); | |
1da177e4 | 711 | } |
ded86d8d | 712 | dev->first_msi_irq = 0; |
1da177e4 LT |
713 | } |
714 | ||
715 | /** | |
1ce03373 | 716 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
717 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
718 | * | |
eaae4b3a | 719 | * Being called during hotplug remove, from which the device function |
1ce03373 | 720 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
721 | * allocated for this device function, are reclaimed to unused state, |
722 | * which may be used later on. | |
723 | **/ | |
724 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
725 | { | |
1da177e4 LT |
726 | if (!pci_msi_enable || !dev) |
727 | return; | |
728 | ||
866a8c87 | 729 | if (dev->msi_enabled) { |
ded86d8d | 730 | if (irq_has_action(dev->first_msi_irq)) { |
1da177e4 | 731 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " |
1ce03373 | 732 | "called without free_irq() on MSI irq %d\n", |
ded86d8d EB |
733 | pci_name(dev), dev->first_msi_irq); |
734 | BUG_ON(irq_has_action(dev->first_msi_irq)); | |
1ce03373 | 735 | } else /* Release MSI irq assigned to this device */ |
ded86d8d | 736 | msi_free_irq(dev, dev->first_msi_irq); |
1da177e4 | 737 | } |
866a8c87 | 738 | if (dev->msix_enabled) { |
1ce03373 | 739 | int irq, head, tail = 0, warning = 0; |
1da177e4 LT |
740 | void __iomem *base = NULL; |
741 | ||
ded86d8d | 742 | irq = head = dev->first_msi_irq; |
1da177e4 | 743 | while (head != tail) { |
5b912c10 EB |
744 | tail = get_irq_msi(irq)->link.tail; |
745 | base = get_irq_msi(irq)->mask_base; | |
1f80025e | 746 | if (irq_has_action(irq)) |
1da177e4 | 747 | warning = 1; |
1ce03373 EB |
748 | else if (irq != head) /* Release MSI-X irq */ |
749 | msi_free_irq(dev, irq); | |
750 | irq = tail; | |
1da177e4 | 751 | } |
1ce03373 | 752 | msi_free_irq(dev, irq); |
1da177e4 | 753 | if (warning) { |
1da177e4 LT |
754 | iounmap(base); |
755 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1ce03373 | 756 | "called without free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
757 | pci_name(dev)); |
758 | BUG_ON(warning > 0); | |
759 | } | |
1da177e4 LT |
760 | } |
761 | } | |
762 | ||
309e57df MW |
763 | void pci_no_msi(void) |
764 | { | |
765 | pci_msi_enable = 0; | |
766 | } | |
767 | ||
1da177e4 LT |
768 | EXPORT_SYMBOL(pci_enable_msi); |
769 | EXPORT_SYMBOL(pci_disable_msi); | |
770 | EXPORT_SYMBOL(pci_enable_msix); | |
771 | EXPORT_SYMBOL(pci_disable_msix); |