Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 LT |
14 | #include <linux/ioport.h> |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/smp.h> | |
23 | ||
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
1da177e4 | 27 | static int pci_msi_enable = 1; |
1da177e4 | 28 | |
b1cbf4e4 EB |
29 | static void msi_set_enable(struct pci_dev *dev, int enable) |
30 | { | |
31 | int pos; | |
32 | u16 control; | |
33 | ||
34 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
35 | if (pos) { | |
36 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
37 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
38 | if (enable) | |
39 | control |= PCI_MSI_FLAGS_ENABLE; | |
40 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
41 | } | |
42 | } | |
43 | ||
44 | static void msix_set_enable(struct pci_dev *dev, int enable) | |
45 | { | |
46 | int pos; | |
47 | u16 control; | |
48 | ||
49 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
50 | if (pos) { | |
51 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
52 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
53 | if (enable) | |
54 | control |= PCI_MSIX_FLAGS_ENABLE; | |
55 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
56 | } | |
57 | } | |
58 | ||
988cbb15 MW |
59 | static void msix_flush_writes(unsigned int irq) |
60 | { | |
61 | struct msi_desc *entry; | |
62 | ||
63 | entry = get_irq_msi(irq); | |
64 | BUG_ON(!entry || !entry->dev); | |
65 | switch (entry->msi_attrib.type) { | |
66 | case PCI_CAP_ID_MSI: | |
67 | /* nothing to do */ | |
68 | break; | |
69 | case PCI_CAP_ID_MSIX: | |
70 | { | |
71 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
72 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
73 | readl(entry->mask_base + offset); | |
74 | break; | |
75 | } | |
76 | default: | |
77 | BUG(); | |
78 | break; | |
79 | } | |
80 | } | |
81 | ||
1ce03373 | 82 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
83 | { |
84 | struct msi_desc *entry; | |
85 | ||
5b912c10 | 86 | entry = get_irq_msi(irq); |
277bc33b | 87 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
88 | switch (entry->msi_attrib.type) { |
89 | case PCI_CAP_ID_MSI: | |
277bc33b | 90 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
91 | int pos; |
92 | u32 mask_bits; | |
277bc33b EB |
93 | |
94 | pos = (long)entry->mask_base; | |
95 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
96 | mask_bits &= ~(1); | |
97 | mask_bits |= flag; | |
98 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
58e0543e EB |
99 | } else { |
100 | msi_set_enable(entry->dev, !flag); | |
277bc33b | 101 | } |
1da177e4 | 102 | break; |
1da177e4 LT |
103 | case PCI_CAP_ID_MSIX: |
104 | { | |
105 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
106 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
107 | writel(flag, entry->mask_base + offset); | |
348e3fd1 | 108 | readl(entry->mask_base + offset); |
1da177e4 LT |
109 | break; |
110 | } | |
111 | default: | |
277bc33b | 112 | BUG(); |
1da177e4 LT |
113 | break; |
114 | } | |
392ee1e6 | 115 | entry->msi_attrib.masked = !!flag; |
1da177e4 LT |
116 | } |
117 | ||
3b7d1921 | 118 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 119 | { |
5b912c10 | 120 | struct msi_desc *entry = get_irq_msi(irq); |
0366f8f7 EB |
121 | switch(entry->msi_attrib.type) { |
122 | case PCI_CAP_ID_MSI: | |
123 | { | |
124 | struct pci_dev *dev = entry->dev; | |
125 | int pos = entry->msi_attrib.pos; | |
126 | u16 data; | |
127 | ||
128 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
129 | &msg->address_lo); | |
130 | if (entry->msi_attrib.is_64) { | |
131 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
132 | &msg->address_hi); | |
133 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
134 | } else { | |
135 | msg->address_hi = 0; | |
136 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
137 | } | |
138 | msg->data = data; | |
139 | break; | |
140 | } | |
141 | case PCI_CAP_ID_MSIX: | |
142 | { | |
143 | void __iomem *base; | |
144 | base = entry->mask_base + | |
145 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
146 | ||
147 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
148 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
149 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
150 | break; | |
151 | } | |
152 | default: | |
153 | BUG(); | |
154 | } | |
155 | } | |
1da177e4 | 156 | |
3b7d1921 | 157 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 158 | { |
5b912c10 | 159 | struct msi_desc *entry = get_irq_msi(irq); |
1da177e4 LT |
160 | switch (entry->msi_attrib.type) { |
161 | case PCI_CAP_ID_MSI: | |
162 | { | |
0366f8f7 EB |
163 | struct pci_dev *dev = entry->dev; |
164 | int pos = entry->msi_attrib.pos; | |
165 | ||
166 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
167 | msg->address_lo); | |
168 | if (entry->msi_attrib.is_64) { | |
169 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
170 | msg->address_hi); | |
171 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
172 | msg->data); | |
173 | } else { | |
174 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
175 | msg->data); | |
176 | } | |
1da177e4 LT |
177 | break; |
178 | } | |
179 | case PCI_CAP_ID_MSIX: | |
180 | { | |
0366f8f7 EB |
181 | void __iomem *base; |
182 | base = entry->mask_base + | |
183 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
184 | ||
185 | writel(msg->address_lo, | |
186 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
187 | writel(msg->address_hi, | |
188 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
189 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
190 | break; |
191 | } | |
192 | default: | |
0366f8f7 | 193 | BUG(); |
1da177e4 | 194 | } |
392ee1e6 | 195 | entry->msg = *msg; |
1da177e4 | 196 | } |
0366f8f7 | 197 | |
3b7d1921 | 198 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 199 | { |
1ce03373 | 200 | msi_set_mask_bit(irq, 1); |
988cbb15 | 201 | msix_flush_writes(irq); |
1da177e4 LT |
202 | } |
203 | ||
3b7d1921 | 204 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 205 | { |
1ce03373 | 206 | msi_set_mask_bit(irq, 0); |
988cbb15 | 207 | msix_flush_writes(irq); |
1da177e4 LT |
208 | } |
209 | ||
1ce03373 | 210 | static int msi_free_irq(struct pci_dev* dev, int irq); |
c54c1879 | 211 | |
1da177e4 | 212 | |
1da177e4 LT |
213 | static struct msi_desc* alloc_msi_entry(void) |
214 | { | |
215 | struct msi_desc *entry; | |
216 | ||
3e916c05 | 217 | entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL); |
1da177e4 LT |
218 | if (!entry) |
219 | return NULL; | |
220 | ||
4aa9bc95 ME |
221 | INIT_LIST_HEAD(&entry->list); |
222 | entry->irq = 0; | |
1da177e4 LT |
223 | entry->dev = NULL; |
224 | ||
225 | return entry; | |
226 | } | |
227 | ||
41017f0c | 228 | #ifdef CONFIG_PM |
8fed4b65 | 229 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 230 | { |
392ee1e6 | 231 | int pos; |
41017f0c | 232 | u16 control; |
392ee1e6 | 233 | struct msi_desc *entry; |
41017f0c | 234 | |
b1cbf4e4 EB |
235 | if (!dev->msi_enabled) |
236 | return; | |
237 | ||
392ee1e6 EB |
238 | entry = get_irq_msi(dev->irq); |
239 | pos = entry->msi_attrib.pos; | |
41017f0c | 240 | |
b1cbf4e4 | 241 | pci_intx(dev, 0); /* disable intx */ |
b1cbf4e4 | 242 | msi_set_enable(dev, 0); |
392ee1e6 EB |
243 | write_msi_msg(dev->irq, &entry->msg); |
244 | if (entry->msi_attrib.maskbit) | |
245 | msi_set_mask_bit(dev->irq, entry->msi_attrib.masked); | |
246 | ||
247 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
248 | control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE); | |
249 | if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked) | |
250 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 251 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
252 | } |
253 | ||
254 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 255 | { |
41017f0c | 256 | int pos; |
41017f0c | 257 | struct msi_desc *entry; |
392ee1e6 | 258 | u16 control; |
41017f0c | 259 | |
ded86d8d EB |
260 | if (!dev->msix_enabled) |
261 | return; | |
262 | ||
41017f0c | 263 | /* route the table */ |
b1cbf4e4 EB |
264 | pci_intx(dev, 0); /* disable intx */ |
265 | msix_set_enable(dev, 0); | |
41017f0c | 266 | |
4aa9bc95 ME |
267 | list_for_each_entry(entry, &dev->msi_list, list) { |
268 | write_msi_msg(entry->irq, &entry->msg); | |
269 | msi_set_mask_bit(entry->irq, entry->msi_attrib.masked); | |
41017f0c | 270 | } |
41017f0c | 271 | |
4aa9bc95 ME |
272 | entry = get_irq_msi(dev->first_msi_irq); |
273 | pos = entry->msi_attrib.pos; | |
392ee1e6 EB |
274 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
275 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
276 | control |= PCI_MSIX_FLAGS_ENABLE; | |
277 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 278 | } |
8fed4b65 ME |
279 | |
280 | void pci_restore_msi_state(struct pci_dev *dev) | |
281 | { | |
282 | __pci_restore_msi_state(dev); | |
283 | __pci_restore_msix_state(dev); | |
284 | } | |
c54c1879 | 285 | #endif /* CONFIG_PM */ |
41017f0c | 286 | |
1da177e4 LT |
287 | /** |
288 | * msi_capability_init - configure device's MSI capability structure | |
289 | * @dev: pointer to the pci_dev data structure of MSI device function | |
290 | * | |
eaae4b3a | 291 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 292 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 293 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 294 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
295 | **/ |
296 | static int msi_capability_init(struct pci_dev *dev) | |
297 | { | |
298 | struct msi_desc *entry; | |
1ce03373 | 299 | int pos, irq; |
1da177e4 LT |
300 | u16 control; |
301 | ||
b1cbf4e4 EB |
302 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
303 | ||
1da177e4 LT |
304 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
305 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
306 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
307 | entry = alloc_msi_entry(); |
308 | if (!entry) | |
309 | return -ENOMEM; | |
1ce03373 | 310 | |
1da177e4 | 311 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 312 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
313 | entry->msi_attrib.entry_nr = 0; |
314 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 315 | entry->msi_attrib.masked = 1; |
1ce03373 | 316 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 317 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
318 | if (is_mask_bit_support(control)) { |
319 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
320 | is_64bit_address(control)); | |
321 | } | |
3b7d1921 EB |
322 | entry->dev = dev; |
323 | if (entry->msi_attrib.maskbit) { | |
324 | unsigned int maskbits, temp; | |
325 | /* All MSIs are unmasked by default, Mask them all */ | |
326 | pci_read_config_dword(dev, | |
327 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
328 | &maskbits); | |
329 | temp = (1 << multi_msi_capable(control)); | |
330 | temp = ((temp - 1) & ~temp); | |
331 | maskbits |= temp; | |
332 | pci_write_config_dword(dev, | |
333 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
334 | maskbits); | |
335 | } | |
1da177e4 | 336 | /* Configure MSI capability structure */ |
f7feaca7 EB |
337 | irq = arch_setup_msi_irq(dev, entry); |
338 | if (irq < 0) { | |
3e916c05 | 339 | kfree(entry); |
f7feaca7 | 340 | return irq; |
fd58e55f | 341 | } |
4aa9bc95 ME |
342 | entry->irq = irq; |
343 | list_add(&entry->list, &dev->msi_list); | |
ded86d8d | 344 | dev->first_msi_irq = irq; |
5b912c10 | 345 | set_irq_msi(irq, entry); |
f7feaca7 | 346 | |
1da177e4 | 347 | /* Set MSI enabled bits */ |
b1cbf4e4 EB |
348 | pci_intx(dev, 0); /* disable intx */ |
349 | msi_set_enable(dev, 1); | |
350 | dev->msi_enabled = 1; | |
1da177e4 | 351 | |
3b7d1921 | 352 | dev->irq = irq; |
1da177e4 LT |
353 | return 0; |
354 | } | |
355 | ||
356 | /** | |
357 | * msix_capability_init - configure device's MSI-X capability | |
358 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
359 | * @entries: pointer to an array of struct msix_entry entries |
360 | * @nvec: number of @entries | |
1da177e4 | 361 | * |
eaae4b3a | 362 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
363 | * single MSI-X irq. A return of zero indicates the successful setup of |
364 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
365 | **/ |
366 | static int msix_capability_init(struct pci_dev *dev, | |
367 | struct msix_entry *entries, int nvec) | |
368 | { | |
4aa9bc95 ME |
369 | struct msi_desc *entry; |
370 | int irq, pos, i, j, nr_entries; | |
a0454b40 GG |
371 | unsigned long phys_addr; |
372 | u32 table_offset; | |
1da177e4 LT |
373 | u16 control; |
374 | u8 bir; | |
375 | void __iomem *base; | |
376 | ||
b1cbf4e4 EB |
377 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
378 | ||
1da177e4 LT |
379 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
380 | /* Request & Map MSI-X table region */ | |
381 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
382 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
383 | |
384 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 385 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
386 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
387 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
388 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
389 | if (base == NULL) | |
390 | return -ENOMEM; | |
391 | ||
392 | /* MSI-X Table Initialization */ | |
393 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
394 | entry = alloc_msi_entry(); |
395 | if (!entry) | |
1da177e4 | 396 | break; |
1da177e4 LT |
397 | |
398 | j = entries[i].entry; | |
1da177e4 | 399 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 400 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
401 | entry->msi_attrib.entry_nr = j; |
402 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 403 | entry->msi_attrib.masked = 1; |
1ce03373 | 404 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 405 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
406 | entry->dev = dev; |
407 | entry->mask_base = base; | |
f7feaca7 EB |
408 | |
409 | /* Configure MSI-X capability structure */ | |
410 | irq = arch_setup_msi_irq(dev, entry); | |
411 | if (irq < 0) { | |
3e916c05 | 412 | kfree(entry); |
f7feaca7 EB |
413 | break; |
414 | } | |
4aa9bc95 | 415 | entry->irq = irq; |
f7feaca7 | 416 | entries[i].vector = irq; |
4aa9bc95 | 417 | list_add(&entry->list, &dev->msi_list); |
fd58e55f | 418 | |
5b912c10 | 419 | set_irq_msi(irq, entry); |
1da177e4 LT |
420 | } |
421 | if (i != nvec) { | |
92db6d10 | 422 | int avail = i - 1; |
1da177e4 LT |
423 | i--; |
424 | for (; i >= 0; i--) { | |
1ce03373 EB |
425 | irq = (entries + i)->vector; |
426 | msi_free_irq(dev, irq); | |
1da177e4 LT |
427 | (entries + i)->vector = 0; |
428 | } | |
92db6d10 EB |
429 | /* If we had some success report the number of irqs |
430 | * we succeeded in setting up. | |
431 | */ | |
432 | if (avail <= 0) | |
433 | avail = -EBUSY; | |
434 | return avail; | |
1da177e4 | 435 | } |
ded86d8d | 436 | dev->first_msi_irq = entries[0].vector; |
1da177e4 | 437 | /* Set MSI-X enabled bits */ |
b1cbf4e4 EB |
438 | pci_intx(dev, 0); /* disable intx */ |
439 | msix_set_enable(dev, 1); | |
440 | dev->msix_enabled = 1; | |
1da177e4 LT |
441 | |
442 | return 0; | |
443 | } | |
444 | ||
24334a12 | 445 | /** |
17bbc12a | 446 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 447 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 448 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 449 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 450 | * |
0306ebfa | 451 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
452 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
453 | * supported return 0, else return an error code. | |
24334a12 | 454 | **/ |
c9953a73 | 455 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
456 | { |
457 | struct pci_bus *bus; | |
c9953a73 | 458 | int ret; |
24334a12 | 459 | |
0306ebfa | 460 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
461 | if (!pci_msi_enable || !dev || dev->no_msi) |
462 | return -EINVAL; | |
463 | ||
0306ebfa BG |
464 | /* Any bridge which does NOT route MSI transactions from it's |
465 | * secondary bus to it's primary bus must set NO_MSI flag on | |
466 | * the secondary pci_bus. | |
467 | * We expect only arch-specific PCI host bus controller driver | |
468 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
469 | */ | |
24334a12 BG |
470 | for (bus = dev->bus; bus; bus = bus->parent) |
471 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
472 | return -EINVAL; | |
473 | ||
c9953a73 ME |
474 | ret = arch_msi_check_device(dev, nvec, type); |
475 | if (ret) | |
476 | return ret; | |
477 | ||
b1e2303d ME |
478 | if (!pci_find_capability(dev, type)) |
479 | return -EINVAL; | |
480 | ||
24334a12 BG |
481 | return 0; |
482 | } | |
483 | ||
1da177e4 LT |
484 | /** |
485 | * pci_enable_msi - configure device's MSI capability structure | |
486 | * @dev: pointer to the pci_dev data structure of MSI device function | |
487 | * | |
488 | * Setup the MSI capability structure of device function with | |
1ce03373 | 489 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
490 | * MSI mode enabled on its hardware device function. A return of zero |
491 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 492 | * irq or non-zero for otherwise. |
1da177e4 LT |
493 | **/ |
494 | int pci_enable_msi(struct pci_dev* dev) | |
495 | { | |
b1e2303d | 496 | int status; |
1da177e4 | 497 | |
c9953a73 ME |
498 | status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI); |
499 | if (status) | |
500 | return status; | |
1da177e4 | 501 | |
ded86d8d | 502 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 503 | |
1ce03373 | 504 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 EB |
505 | if (dev->msix_enabled) { |
506 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " | |
507 | "Device already has MSI-X enabled\n", | |
508 | pci_name(dev)); | |
509 | return -EINVAL; | |
1da177e4 LT |
510 | } |
511 | status = msi_capability_init(dev); | |
1da177e4 LT |
512 | return status; |
513 | } | |
4cc086fa | 514 | EXPORT_SYMBOL(pci_enable_msi); |
1da177e4 LT |
515 | |
516 | void pci_disable_msi(struct pci_dev* dev) | |
517 | { | |
518 | struct msi_desc *entry; | |
b1cbf4e4 | 519 | int default_irq; |
1da177e4 | 520 | |
128bc5fc | 521 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
522 | return; |
523 | ||
b1cbf4e4 EB |
524 | msi_set_enable(dev, 0); |
525 | pci_intx(dev, 1); /* enable intx */ | |
526 | dev->msi_enabled = 0; | |
7bd007e4 | 527 | |
5b912c10 | 528 | entry = get_irq_msi(dev->first_msi_irq); |
1da177e4 | 529 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { |
1da177e4 LT |
530 | return; |
531 | } | |
e387b9ee | 532 | |
e387b9ee ME |
533 | default_irq = entry->msi_attrib.default_irq; |
534 | msi_free_irq(dev, dev->first_msi_irq); | |
535 | ||
536 | /* Restore dev->irq to its default pin-assertion irq */ | |
537 | dev->irq = default_irq; | |
538 | ||
ded86d8d | 539 | dev->first_msi_irq = 0; |
1da177e4 | 540 | } |
4cc086fa | 541 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 542 | |
1ce03373 | 543 | static int msi_free_irq(struct pci_dev* dev, int irq) |
1da177e4 LT |
544 | { |
545 | struct msi_desc *entry; | |
4aa9bc95 | 546 | int entry_nr, type; |
1da177e4 | 547 | void __iomem *base; |
1da177e4 | 548 | |
7ede9c1f ME |
549 | BUG_ON(irq_has_action(irq)); |
550 | ||
5b912c10 | 551 | entry = get_irq_msi(irq); |
1da177e4 | 552 | if (!entry || entry->dev != dev) { |
1da177e4 LT |
553 | return -EINVAL; |
554 | } | |
555 | type = entry->msi_attrib.type; | |
556 | entry_nr = entry->msi_attrib.entry_nr; | |
1da177e4 | 557 | base = entry->mask_base; |
4aa9bc95 | 558 | list_del(&entry->list); |
1da177e4 | 559 | |
f7feaca7 | 560 | arch_teardown_msi_irq(irq); |
3e916c05 | 561 | kfree(entry); |
1da177e4 LT |
562 | |
563 | if (type == PCI_CAP_ID_MSIX) { | |
1ce03373 EB |
564 | writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + |
565 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
1da177e4 | 566 | |
4aa9bc95 | 567 | if (list_empty(&dev->msi_list)) |
1da177e4 | 568 | iounmap(base); |
1da177e4 LT |
569 | } |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
1da177e4 LT |
574 | /** |
575 | * pci_enable_msix - configure device's MSI-X capability structure | |
576 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 577 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 578 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
579 | * |
580 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 581 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
582 | * MSI-X mode enabled on its hardware device function. A return of zero |
583 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 584 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 585 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 586 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
587 | * its request. |
588 | **/ | |
589 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
590 | { | |
92db6d10 | 591 | int status, pos, nr_entries; |
ded86d8d | 592 | int i, j; |
1da177e4 | 593 | u16 control; |
1da177e4 | 594 | |
c9953a73 | 595 | if (!entries) |
1da177e4 LT |
596 | return -EINVAL; |
597 | ||
c9953a73 ME |
598 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
599 | if (status) | |
600 | return status; | |
601 | ||
b64c05e7 | 602 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1da177e4 | 603 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
1da177e4 LT |
604 | nr_entries = multi_msix_capable(control); |
605 | if (nvec > nr_entries) | |
606 | return -EINVAL; | |
607 | ||
608 | /* Check for any invalid entries */ | |
609 | for (i = 0; i < nvec; i++) { | |
610 | if (entries[i].entry >= nr_entries) | |
611 | return -EINVAL; /* invalid entry */ | |
612 | for (j = i + 1; j < nvec; j++) { | |
613 | if (entries[i].entry == entries[j].entry) | |
614 | return -EINVAL; /* duplicate entry */ | |
615 | } | |
616 | } | |
ded86d8d | 617 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 618 | |
1ce03373 | 619 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 620 | if (dev->msi_enabled) { |
1da177e4 | 621 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 622 | "Device already has an MSI irq assigned\n", |
1da177e4 | 623 | pci_name(dev)); |
1da177e4 LT |
624 | return -EINVAL; |
625 | } | |
1da177e4 | 626 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
627 | return status; |
628 | } | |
4cc086fa | 629 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 630 | |
fc4afc7b | 631 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 632 | { |
4aa9bc95 | 633 | struct msi_desc *entry; |
fc4afc7b | 634 | |
4aa9bc95 ME |
635 | list_for_each_entry(entry, &dev->msi_list, list) |
636 | msi_free_irq(dev, entry->irq); | |
fc4afc7b ME |
637 | dev->first_msi_irq = 0; |
638 | } | |
639 | ||
640 | void pci_disable_msix(struct pci_dev* dev) | |
641 | { | |
128bc5fc | 642 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
643 | return; |
644 | ||
b1cbf4e4 EB |
645 | msix_set_enable(dev, 0); |
646 | pci_intx(dev, 1); /* enable intx */ | |
647 | dev->msix_enabled = 0; | |
7bd007e4 | 648 | |
fc4afc7b | 649 | msix_free_all_irqs(dev); |
1da177e4 | 650 | } |
4cc086fa | 651 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
652 | |
653 | /** | |
1ce03373 | 654 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
655 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
656 | * | |
eaae4b3a | 657 | * Being called during hotplug remove, from which the device function |
1ce03373 | 658 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
659 | * allocated for this device function, are reclaimed to unused state, |
660 | * which may be used later on. | |
661 | **/ | |
662 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
663 | { | |
1da177e4 LT |
664 | if (!pci_msi_enable || !dev) |
665 | return; | |
666 | ||
7ede9c1f | 667 | if (dev->msi_enabled) |
c31af398 | 668 | msi_free_irq(dev, dev->first_msi_irq); |
1da177e4 | 669 | |
fc4afc7b ME |
670 | if (dev->msix_enabled) |
671 | msix_free_all_irqs(dev); | |
1da177e4 LT |
672 | } |
673 | ||
309e57df MW |
674 | void pci_no_msi(void) |
675 | { | |
676 | pci_msi_enable = 0; | |
677 | } | |
c9953a73 | 678 | |
4aa9bc95 ME |
679 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
680 | { | |
681 | INIT_LIST_HEAD(&dev->msi_list); | |
682 | } | |
683 | ||
c9953a73 ME |
684 | |
685 | /* Arch hooks */ | |
686 | ||
687 | int __attribute__ ((weak)) | |
688 | arch_msi_check_device(struct pci_dev* dev, int nvec, int type) | |
689 | { | |
690 | return 0; | |
691 | } | |
692 |