Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
11df1f05 ME |
30 | #ifndef arch_msi_check_device |
31 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
32 | { |
33 | return 0; | |
34 | } | |
11df1f05 | 35 | #endif |
6a9e7f20 | 36 | |
11df1f05 ME |
37 | #ifndef arch_setup_msi_irqs |
38 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
39 | { |
40 | struct msi_desc *entry; | |
41 | int ret; | |
42 | ||
1c8d7b0a MW |
43 | /* |
44 | * If an architecture wants to support multiple MSI, it needs to | |
45 | * override arch_setup_msi_irqs() | |
46 | */ | |
47 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
48 | return 1; | |
49 | ||
6a9e7f20 AB |
50 | list_for_each_entry(entry, &dev->msi_list, list) { |
51 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 52 | if (ret < 0) |
6a9e7f20 | 53 | return ret; |
b5fbf533 ME |
54 | if (ret > 0) |
55 | return -ENOSPC; | |
6a9e7f20 AB |
56 | } |
57 | ||
58 | return 0; | |
59 | } | |
11df1f05 | 60 | #endif |
6a9e7f20 | 61 | |
11df1f05 ME |
62 | #ifndef arch_teardown_msi_irqs |
63 | void arch_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
64 | { |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
68 | int i, nvec; |
69 | if (entry->irq == 0) | |
70 | continue; | |
71 | nvec = 1 << entry->msi_attrib.multiple; | |
72 | for (i = 0; i < nvec; i++) | |
73 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
74 | } |
75 | } | |
11df1f05 | 76 | #endif |
6a9e7f20 | 77 | |
110828c9 | 78 | static void msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 79 | { |
b1cbf4e4 EB |
80 | u16 control; |
81 | ||
110828c9 | 82 | BUG_ON(!pos); |
b1cbf4e4 | 83 | |
110828c9 MW |
84 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
85 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
86 | if (enable) | |
87 | control |= PCI_MSI_FLAGS_ENABLE; | |
88 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
5ca5c02f HS |
89 | } |
90 | ||
b1cbf4e4 EB |
91 | static void msix_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | int pos; | |
94 | u16 control; | |
95 | ||
96 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
97 | if (pos) { | |
98 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
99 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
100 | if (enable) | |
101 | control |= PCI_MSIX_FLAGS_ENABLE; | |
102 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
103 | } | |
104 | } | |
105 | ||
bffac3c5 MW |
106 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
107 | { | |
0b49ec37 MW |
108 | /* Don't shift by >= width of type */ |
109 | if (x >= 5) | |
110 | return 0xffffffff; | |
111 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
112 | } |
113 | ||
f2440d9a | 114 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 115 | { |
f2440d9a MW |
116 | return msi_mask((control >> 1) & 7); |
117 | } | |
988cbb15 | 118 | |
f2440d9a MW |
119 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
120 | { | |
121 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
122 | } |
123 | ||
ce6fce42 MW |
124 | /* |
125 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
126 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
127 | * reliably as devices without an INTx disable bit will then generate a | |
128 | * level IRQ which will never be cleared. | |
ce6fce42 | 129 | */ |
f2440d9a | 130 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 131 | { |
f2440d9a | 132 | u32 mask_bits = desc->masked; |
1da177e4 | 133 | |
f2440d9a MW |
134 | if (!desc->msi_attrib.maskbit) |
135 | return; | |
136 | ||
137 | mask_bits &= ~mask; | |
138 | mask_bits |= flag; | |
139 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
140 | desc->masked = mask_bits; | |
141 | } | |
142 | ||
143 | /* | |
144 | * This internal function does not flush PCI writes to the device. | |
145 | * All users must ensure that they read from the device before either | |
146 | * assuming that the device state is up to date, or returning out of this | |
147 | * file. This saves a few milliseconds when initialising devices with lots | |
148 | * of MSI-X interrupts. | |
149 | */ | |
150 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
151 | { | |
152 | u32 mask_bits = desc->masked; | |
153 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 154 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
f2440d9a MW |
155 | mask_bits &= ~1; |
156 | mask_bits |= flag; | |
157 | writel(mask_bits, desc->mask_base + offset); | |
158 | desc->masked = mask_bits; | |
159 | } | |
24d27553 | 160 | |
f2440d9a MW |
161 | static void msi_set_mask_bit(unsigned irq, u32 flag) |
162 | { | |
163 | struct msi_desc *desc = get_irq_msi(irq); | |
24d27553 | 164 | |
f2440d9a MW |
165 | if (desc->msi_attrib.is_msix) { |
166 | msix_mask_irq(desc, flag); | |
167 | readl(desc->mask_base); /* Flush write to device */ | |
168 | } else { | |
1c8d7b0a MW |
169 | unsigned offset = irq - desc->dev->irq; |
170 | msi_mask_irq(desc, 1 << offset, flag << offset); | |
1da177e4 | 171 | } |
f2440d9a MW |
172 | } |
173 | ||
174 | void mask_msi_irq(unsigned int irq) | |
175 | { | |
176 | msi_set_mask_bit(irq, 1); | |
177 | } | |
178 | ||
179 | void unmask_msi_irq(unsigned int irq) | |
180 | { | |
181 | msi_set_mask_bit(irq, 0); | |
1da177e4 LT |
182 | } |
183 | ||
3145e941 | 184 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 185 | { |
3145e941 | 186 | struct msi_desc *entry = get_irq_desc_msi(desc); |
24d27553 MW |
187 | if (entry->msi_attrib.is_msix) { |
188 | void __iomem *base = entry->mask_base + | |
189 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
190 | ||
2c21fd4b HS |
191 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); |
192 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
193 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 194 | } else { |
0366f8f7 EB |
195 | struct pci_dev *dev = entry->dev; |
196 | int pos = entry->msi_attrib.pos; | |
197 | u16 data; | |
198 | ||
199 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
200 | &msg->address_lo); | |
201 | if (entry->msi_attrib.is_64) { | |
202 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
203 | &msg->address_hi); | |
204 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
205 | } else { | |
206 | msg->address_hi = 0; | |
cbf5d9e6 | 207 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
208 | } |
209 | msg->data = data; | |
0366f8f7 EB |
210 | } |
211 | } | |
1da177e4 | 212 | |
3145e941 | 213 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 214 | { |
3145e941 YL |
215 | struct irq_desc *desc = irq_to_desc(irq); |
216 | ||
217 | read_msi_msg_desc(desc, msg); | |
218 | } | |
219 | ||
220 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
221 | { | |
222 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
24d27553 MW |
223 | if (entry->msi_attrib.is_msix) { |
224 | void __iomem *base; | |
225 | base = entry->mask_base + | |
226 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
227 | ||
2c21fd4b HS |
228 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
229 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
230 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 231 | } else { |
0366f8f7 EB |
232 | struct pci_dev *dev = entry->dev; |
233 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
234 | u16 msgctl; |
235 | ||
236 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
237 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
238 | msgctl |= entry->msi_attrib.multiple << 4; | |
239 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
240 | |
241 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
242 | msg->address_lo); | |
243 | if (entry->msi_attrib.is_64) { | |
244 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
245 | msg->address_hi); | |
246 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
247 | msg->data); | |
248 | } else { | |
249 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
250 | msg->data); | |
251 | } | |
1da177e4 | 252 | } |
392ee1e6 | 253 | entry->msg = *msg; |
1da177e4 | 254 | } |
0366f8f7 | 255 | |
3145e941 YL |
256 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
257 | { | |
258 | struct irq_desc *desc = irq_to_desc(irq); | |
259 | ||
260 | write_msi_msg_desc(desc, msg); | |
261 | } | |
262 | ||
032de8e2 | 263 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 264 | |
379f5327 | 265 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 266 | { |
379f5327 MW |
267 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
268 | if (!desc) | |
1da177e4 LT |
269 | return NULL; |
270 | ||
379f5327 MW |
271 | INIT_LIST_HEAD(&desc->list); |
272 | desc->dev = dev; | |
1da177e4 | 273 | |
379f5327 | 274 | return desc; |
1da177e4 LT |
275 | } |
276 | ||
ba698ad4 DM |
277 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
278 | { | |
279 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
280 | pci_intx(dev, enable); | |
281 | } | |
282 | ||
8fed4b65 | 283 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 284 | { |
392ee1e6 | 285 | int pos; |
41017f0c | 286 | u16 control; |
392ee1e6 | 287 | struct msi_desc *entry; |
41017f0c | 288 | |
b1cbf4e4 EB |
289 | if (!dev->msi_enabled) |
290 | return; | |
291 | ||
392ee1e6 EB |
292 | entry = get_irq_msi(dev->irq); |
293 | pos = entry->msi_attrib.pos; | |
41017f0c | 294 | |
ba698ad4 | 295 | pci_intx_for_msi(dev, 0); |
110828c9 | 296 | msi_set_enable(dev, pos, 0); |
392ee1e6 | 297 | write_msi_msg(dev->irq, &entry->msg); |
392ee1e6 EB |
298 | |
299 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 300 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 301 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 302 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 303 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
304 | } |
305 | ||
306 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 307 | { |
41017f0c | 308 | int pos; |
41017f0c | 309 | struct msi_desc *entry; |
392ee1e6 | 310 | u16 control; |
41017f0c | 311 | |
ded86d8d EB |
312 | if (!dev->msix_enabled) |
313 | return; | |
f598282f MW |
314 | BUG_ON(list_empty(&dev->msi_list)); |
315 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
316 | pos = entry->msi_attrib.pos; | |
317 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
ded86d8d | 318 | |
41017f0c | 319 | /* route the table */ |
ba698ad4 | 320 | pci_intx_for_msi(dev, 0); |
f598282f MW |
321 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
322 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 323 | |
4aa9bc95 ME |
324 | list_for_each_entry(entry, &dev->msi_list, list) { |
325 | write_msi_msg(entry->irq, &entry->msg); | |
f2440d9a | 326 | msix_mask_irq(entry, entry->masked); |
41017f0c | 327 | } |
41017f0c | 328 | |
392ee1e6 | 329 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
392ee1e6 | 330 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
41017f0c | 331 | } |
8fed4b65 ME |
332 | |
333 | void pci_restore_msi_state(struct pci_dev *dev) | |
334 | { | |
335 | __pci_restore_msi_state(dev); | |
336 | __pci_restore_msix_state(dev); | |
337 | } | |
94688cf2 | 338 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 339 | |
1da177e4 LT |
340 | /** |
341 | * msi_capability_init - configure device's MSI capability structure | |
342 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 343 | * @nvec: number of interrupts to allocate |
1da177e4 | 344 | * |
1c8d7b0a MW |
345 | * Setup the MSI capability structure of the device with the requested |
346 | * number of interrupts. A return value of zero indicates the successful | |
347 | * setup of an entry with the new MSI irq. A negative return value indicates | |
348 | * an error, and a positive return value indicates the number of interrupts | |
349 | * which could have been allocated. | |
350 | */ | |
351 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
352 | { |
353 | struct msi_desc *entry; | |
7fe3730d | 354 | int pos, ret; |
1da177e4 | 355 | u16 control; |
f2440d9a | 356 | unsigned mask; |
1da177e4 LT |
357 | |
358 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
110828c9 MW |
359 | msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ |
360 | ||
1da177e4 LT |
361 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
362 | /* MSI Entry Initialization */ | |
379f5327 | 363 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
364 | if (!entry) |
365 | return -ENOMEM; | |
1ce03373 | 366 | |
24d27553 | 367 | entry->msi_attrib.is_msix = 0; |
0366f8f7 | 368 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
369 | entry->msi_attrib.entry_nr = 0; |
370 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 371 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 372 | entry->msi_attrib.pos = pos; |
f2440d9a | 373 | |
67b5db65 | 374 | entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); |
f2440d9a MW |
375 | /* All MSIs are unmasked by default, Mask them all */ |
376 | if (entry->msi_attrib.maskbit) | |
377 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
378 | mask = msi_capable_mask(control); | |
379 | msi_mask_irq(entry, mask, mask); | |
380 | ||
0dd11f9b | 381 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 382 | |
1da177e4 | 383 | /* Configure MSI capability structure */ |
1c8d7b0a | 384 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 385 | if (ret) { |
032de8e2 | 386 | msi_free_irqs(dev); |
7fe3730d | 387 | return ret; |
fd58e55f | 388 | } |
f7feaca7 | 389 | |
1da177e4 | 390 | /* Set MSI enabled bits */ |
ba698ad4 | 391 | pci_intx_for_msi(dev, 0); |
110828c9 | 392 | msi_set_enable(dev, pos, 1); |
b1cbf4e4 | 393 | dev->msi_enabled = 1; |
1da177e4 | 394 | |
7fe3730d | 395 | dev->irq = entry->irq; |
1da177e4 LT |
396 | return 0; |
397 | } | |
398 | ||
399 | /** | |
400 | * msix_capability_init - configure device's MSI-X capability | |
401 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
402 | * @entries: pointer to an array of struct msix_entry entries |
403 | * @nvec: number of @entries | |
1da177e4 | 404 | * |
eaae4b3a | 405 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
406 | * single MSI-X irq. A return of zero indicates the successful setup of |
407 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
408 | **/ |
409 | static int msix_capability_init(struct pci_dev *dev, | |
410 | struct msix_entry *entries, int nvec) | |
411 | { | |
4aa9bc95 | 412 | struct msi_desc *entry; |
9c831334 | 413 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
414 | unsigned long phys_addr; |
415 | u32 table_offset; | |
1da177e4 LT |
416 | u16 control; |
417 | u8 bir; | |
418 | void __iomem *base; | |
419 | ||
420 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
f598282f MW |
421 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
422 | ||
423 | /* Ensure MSI-X is disabled while it is set up */ | |
424 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
425 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
426 | ||
1da177e4 | 427 | /* Request & Map MSI-X table region */ |
1da177e4 | 428 | nr_entries = multi_msix_capable(control); |
a0454b40 GG |
429 | |
430 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 431 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
432 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
433 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
434 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
435 | if (base == NULL) | |
436 | return -ENOMEM; | |
437 | ||
1da177e4 | 438 | for (i = 0; i < nvec; i++) { |
379f5327 | 439 | entry = alloc_msi_entry(dev); |
0d073489 HS |
440 | if (!entry) { |
441 | if (!i) | |
442 | iounmap(base); | |
443 | else | |
444 | msi_free_irqs(dev); | |
445 | /* No enough memory. Don't try again */ | |
446 | return -ENOMEM; | |
447 | } | |
1da177e4 LT |
448 | |
449 | j = entries[i].entry; | |
24d27553 | 450 | entry->msi_attrib.is_msix = 1; |
0366f8f7 | 451 | entry->msi_attrib.is_64 = 1; |
1da177e4 | 452 | entry->msi_attrib.entry_nr = j; |
1ce03373 | 453 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 454 | entry->msi_attrib.pos = pos; |
1da177e4 | 455 | entry->mask_base = base; |
f7feaca7 | 456 | |
0dd11f9b | 457 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 458 | } |
9c831334 ME |
459 | |
460 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
b5fbf533 ME |
461 | if (ret < 0) { |
462 | /* If we had some success report the number of irqs | |
463 | * we succeeded in setting up. */ | |
9c831334 ME |
464 | int avail = 0; |
465 | list_for_each_entry(entry, &dev->msi_list, list) { | |
466 | if (entry->irq != 0) { | |
467 | avail++; | |
9c831334 | 468 | } |
1da177e4 | 469 | } |
9c831334 | 470 | |
b5fbf533 ME |
471 | if (avail != 0) |
472 | ret = avail; | |
473 | } | |
032de8e2 | 474 | |
b5fbf533 ME |
475 | if (ret) { |
476 | msi_free_irqs(dev); | |
477 | return ret; | |
1da177e4 | 478 | } |
9c831334 | 479 | |
f598282f MW |
480 | /* |
481 | * Some devices require MSI-X to be enabled before we can touch the | |
482 | * MSI-X registers. We need to mask all the vectors to prevent | |
483 | * interrupts coming in before they're fully set up. | |
484 | */ | |
485 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
486 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
487 | ||
9c831334 ME |
488 | i = 0; |
489 | list_for_each_entry(entry, &dev->msi_list, list) { | |
490 | entries[i].vector = entry->irq; | |
491 | set_irq_msi(entry->irq, entry); | |
f598282f MW |
492 | j = entries[i].entry; |
493 | entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 494 | PCI_MSIX_ENTRY_VECTOR_CTRL); |
f598282f | 495 | msix_mask_irq(entry, 1); |
9c831334 ME |
496 | i++; |
497 | } | |
f598282f MW |
498 | |
499 | /* Set MSI-X enabled bits and unmask the function */ | |
ba698ad4 | 500 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 501 | dev->msix_enabled = 1; |
1da177e4 | 502 | |
f598282f MW |
503 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
504 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
8d181018 | 505 | |
1da177e4 LT |
506 | return 0; |
507 | } | |
508 | ||
24334a12 | 509 | /** |
17bbc12a | 510 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 511 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 512 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 513 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 514 | * |
0306ebfa | 515 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
516 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
517 | * supported return 0, else return an error code. | |
24334a12 | 518 | **/ |
c9953a73 | 519 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
520 | { |
521 | struct pci_bus *bus; | |
c9953a73 | 522 | int ret; |
24334a12 | 523 | |
0306ebfa | 524 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
525 | if (!pci_msi_enable || !dev || dev->no_msi) |
526 | return -EINVAL; | |
527 | ||
314e77b3 ME |
528 | /* |
529 | * You can't ask to have 0 or less MSIs configured. | |
530 | * a) it's stupid .. | |
531 | * b) the list manipulation code assumes nvec >= 1. | |
532 | */ | |
533 | if (nvec < 1) | |
534 | return -ERANGE; | |
535 | ||
0306ebfa BG |
536 | /* Any bridge which does NOT route MSI transactions from it's |
537 | * secondary bus to it's primary bus must set NO_MSI flag on | |
538 | * the secondary pci_bus. | |
539 | * We expect only arch-specific PCI host bus controller driver | |
540 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
541 | */ | |
24334a12 BG |
542 | for (bus = dev->bus; bus; bus = bus->parent) |
543 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
544 | return -EINVAL; | |
545 | ||
c9953a73 ME |
546 | ret = arch_msi_check_device(dev, nvec, type); |
547 | if (ret) | |
548 | return ret; | |
549 | ||
b1e2303d ME |
550 | if (!pci_find_capability(dev, type)) |
551 | return -EINVAL; | |
552 | ||
24334a12 BG |
553 | return 0; |
554 | } | |
555 | ||
1da177e4 | 556 | /** |
1c8d7b0a MW |
557 | * pci_enable_msi_block - configure device's MSI capability structure |
558 | * @dev: device to configure | |
559 | * @nvec: number of interrupts to configure | |
1da177e4 | 560 | * |
1c8d7b0a MW |
561 | * Allocate IRQs for a device with the MSI capability. |
562 | * This function returns a negative errno if an error occurs. If it | |
563 | * is unable to allocate the number of interrupts requested, it returns | |
564 | * the number of interrupts it might be able to allocate. If it successfully | |
565 | * allocates at least the number of interrupts requested, it returns 0 and | |
566 | * updates the @dev's irq member to the lowest new interrupt number; the | |
567 | * other interrupt numbers allocated to this device are consecutive. | |
568 | */ | |
569 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 570 | { |
1c8d7b0a MW |
571 | int status, pos, maxvec; |
572 | u16 msgctl; | |
573 | ||
574 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
575 | if (!pos) | |
576 | return -EINVAL; | |
577 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
578 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
579 | if (nvec > maxvec) | |
580 | return maxvec; | |
1da177e4 | 581 | |
1c8d7b0a | 582 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
583 | if (status) |
584 | return status; | |
1da177e4 | 585 | |
ded86d8d | 586 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 587 | |
1c8d7b0a | 588 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 589 | if (dev->msix_enabled) { |
80ccba11 BH |
590 | dev_info(&dev->dev, "can't enable MSI " |
591 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 592 | return -EINVAL; |
1da177e4 | 593 | } |
1c8d7b0a MW |
594 | |
595 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
596 | return status; |
597 | } | |
1c8d7b0a | 598 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 599 | |
f2440d9a | 600 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 601 | { |
f2440d9a MW |
602 | struct msi_desc *desc; |
603 | u32 mask; | |
604 | u16 ctrl; | |
110828c9 | 605 | unsigned pos; |
1da177e4 | 606 | |
128bc5fc | 607 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
608 | return; |
609 | ||
110828c9 MW |
610 | BUG_ON(list_empty(&dev->msi_list)); |
611 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
612 | pos = desc->msi_attrib.pos; | |
613 | ||
614 | msi_set_enable(dev, pos, 0); | |
ba698ad4 | 615 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 616 | dev->msi_enabled = 0; |
7bd007e4 | 617 | |
110828c9 | 618 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a MW |
619 | mask = msi_capable_mask(ctrl); |
620 | msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
621 | |
622 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 623 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 624 | } |
24d27553 | 625 | |
d52877c7 YL |
626 | void pci_disable_msi(struct pci_dev* dev) |
627 | { | |
628 | struct msi_desc *entry; | |
629 | ||
630 | if (!pci_msi_enable || !dev || !dev->msi_enabled) | |
631 | return; | |
632 | ||
633 | pci_msi_shutdown(dev); | |
634 | ||
635 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
379f5327 | 636 | if (entry->msi_attrib.is_msix) |
d52877c7 YL |
637 | return; |
638 | ||
639 | msi_free_irqs(dev); | |
1da177e4 | 640 | } |
4cc086fa | 641 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 642 | |
032de8e2 | 643 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 644 | { |
032de8e2 | 645 | struct msi_desc *entry, *tmp; |
7ede9c1f | 646 | |
b3b7cc7b | 647 | list_for_each_entry(entry, &dev->msi_list, list) { |
1c8d7b0a MW |
648 | int i, nvec; |
649 | if (!entry->irq) | |
650 | continue; | |
651 | nvec = 1 << entry->msi_attrib.multiple; | |
652 | for (i = 0; i < nvec; i++) | |
653 | BUG_ON(irq_has_action(entry->irq + i)); | |
b3b7cc7b | 654 | } |
1da177e4 | 655 | |
032de8e2 | 656 | arch_teardown_msi_irqs(dev); |
1da177e4 | 657 | |
032de8e2 | 658 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
24d27553 | 659 | if (entry->msi_attrib.is_msix) { |
2af5066f | 660 | msix_mask_irq(entry, 1); |
78b7611c EB |
661 | if (list_is_last(&entry->list, &dev->msi_list)) |
662 | iounmap(entry->mask_base); | |
032de8e2 ME |
663 | } |
664 | list_del(&entry->list); | |
665 | kfree(entry); | |
1da177e4 LT |
666 | } |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
a52e2e35 RW |
671 | /** |
672 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
673 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
674 | */ | |
675 | int pci_msix_table_size(struct pci_dev *dev) | |
676 | { | |
677 | int pos; | |
678 | u16 control; | |
679 | ||
680 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
681 | if (!pos) | |
682 | return 0; | |
683 | ||
684 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
685 | return multi_msix_capable(control); | |
686 | } | |
687 | ||
1da177e4 LT |
688 | /** |
689 | * pci_enable_msix - configure device's MSI-X capability structure | |
690 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 691 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 692 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
693 | * |
694 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 695 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
696 | * MSI-X mode enabled on its hardware device function. A return of zero |
697 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 698 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 699 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
700 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
701 | * re-send its request. | |
1da177e4 LT |
702 | **/ |
703 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
704 | { | |
a52e2e35 | 705 | int status, nr_entries; |
ded86d8d | 706 | int i, j; |
1da177e4 | 707 | |
c9953a73 | 708 | if (!entries) |
1da177e4 LT |
709 | return -EINVAL; |
710 | ||
c9953a73 ME |
711 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
712 | if (status) | |
713 | return status; | |
714 | ||
a52e2e35 | 715 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 716 | if (nvec > nr_entries) |
57fbf52c | 717 | return nr_entries; |
1da177e4 LT |
718 | |
719 | /* Check for any invalid entries */ | |
720 | for (i = 0; i < nvec; i++) { | |
721 | if (entries[i].entry >= nr_entries) | |
722 | return -EINVAL; /* invalid entry */ | |
723 | for (j = i + 1; j < nvec; j++) { | |
724 | if (entries[i].entry == entries[j].entry) | |
725 | return -EINVAL; /* duplicate entry */ | |
726 | } | |
727 | } | |
ded86d8d | 728 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 729 | |
1ce03373 | 730 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 731 | if (dev->msi_enabled) { |
80ccba11 BH |
732 | dev_info(&dev->dev, "can't enable MSI-X " |
733 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
734 | return -EINVAL; |
735 | } | |
1da177e4 | 736 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
737 | return status; |
738 | } | |
4cc086fa | 739 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 740 | |
fc4afc7b | 741 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 742 | { |
032de8e2 | 743 | msi_free_irqs(dev); |
fc4afc7b ME |
744 | } |
745 | ||
d52877c7 | 746 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 747 | { |
128bc5fc | 748 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
749 | return; |
750 | ||
b1cbf4e4 | 751 | msix_set_enable(dev, 0); |
ba698ad4 | 752 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 753 | dev->msix_enabled = 0; |
d52877c7 YL |
754 | } |
755 | void pci_disable_msix(struct pci_dev* dev) | |
756 | { | |
757 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
758 | return; | |
759 | ||
760 | pci_msix_shutdown(dev); | |
7bd007e4 | 761 | |
fc4afc7b | 762 | msix_free_all_irqs(dev); |
1da177e4 | 763 | } |
4cc086fa | 764 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
765 | |
766 | /** | |
1ce03373 | 767 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
768 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
769 | * | |
eaae4b3a | 770 | * Being called during hotplug remove, from which the device function |
1ce03373 | 771 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
772 | * allocated for this device function, are reclaimed to unused state, |
773 | * which may be used later on. | |
774 | **/ | |
775 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
776 | { | |
1da177e4 LT |
777 | if (!pci_msi_enable || !dev) |
778 | return; | |
779 | ||
032de8e2 ME |
780 | if (dev->msi_enabled) |
781 | msi_free_irqs(dev); | |
1da177e4 | 782 | |
fc4afc7b ME |
783 | if (dev->msix_enabled) |
784 | msix_free_all_irqs(dev); | |
1da177e4 LT |
785 | } |
786 | ||
309e57df MW |
787 | void pci_no_msi(void) |
788 | { | |
789 | pci_msi_enable = 0; | |
790 | } | |
c9953a73 | 791 | |
07ae95f9 AP |
792 | /** |
793 | * pci_msi_enabled - is MSI enabled? | |
794 | * | |
795 | * Returns true if MSI has not been disabled by the command-line option | |
796 | * pci=nomsi. | |
797 | **/ | |
798 | int pci_msi_enabled(void) | |
d389fec6 | 799 | { |
07ae95f9 | 800 | return pci_msi_enable; |
d389fec6 | 801 | } |
07ae95f9 | 802 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 803 | |
07ae95f9 | 804 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 805 | { |
07ae95f9 | 806 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 807 | } |