Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
30 | int __attribute__ ((weak)) | |
31 | arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
32 | { | |
33 | return 0; | |
34 | } | |
35 | ||
36 | int __attribute__ ((weak)) | |
37 | arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *entry) | |
38 | { | |
39 | return 0; | |
40 | } | |
41 | ||
42 | int __attribute__ ((weak)) | |
43 | arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
44 | { | |
45 | struct msi_desc *entry; | |
46 | int ret; | |
47 | ||
48 | list_for_each_entry(entry, &dev->msi_list, list) { | |
49 | ret = arch_setup_msi_irq(dev, entry); | |
50 | if (ret) | |
51 | return ret; | |
52 | } | |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
57 | void __attribute__ ((weak)) arch_teardown_msi_irq(unsigned int irq) | |
58 | { | |
59 | return; | |
60 | } | |
61 | ||
62 | void __attribute__ ((weak)) | |
63 | arch_teardown_msi_irqs(struct pci_dev *dev) | |
64 | { | |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
68 | if (entry->irq != 0) | |
69 | arch_teardown_msi_irq(entry->irq); | |
70 | } | |
71 | } | |
72 | ||
5ca5c02f | 73 | static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 74 | { |
b1cbf4e4 EB |
75 | u16 control; |
76 | ||
b1cbf4e4 EB |
77 | if (pos) { |
78 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
79 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
80 | if (enable) | |
81 | control |= PCI_MSI_FLAGS_ENABLE; | |
82 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
83 | } | |
84 | } | |
85 | ||
5ca5c02f HS |
86 | static void msi_set_enable(struct pci_dev *dev, int enable) |
87 | { | |
88 | __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); | |
89 | } | |
90 | ||
b1cbf4e4 EB |
91 | static void msix_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | int pos; | |
94 | u16 control; | |
95 | ||
96 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
97 | if (pos) { | |
98 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
99 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
100 | if (enable) | |
101 | control |= PCI_MSIX_FLAGS_ENABLE; | |
102 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
103 | } | |
104 | } | |
105 | ||
bffac3c5 MW |
106 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
107 | { | |
0b49ec37 MW |
108 | /* Don't shift by >= width of type */ |
109 | if (x >= 5) | |
110 | return 0xffffffff; | |
111 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
112 | } |
113 | ||
3145e941 | 114 | static void msix_flush_writes(struct irq_desc *desc) |
988cbb15 MW |
115 | { |
116 | struct msi_desc *entry; | |
117 | ||
3145e941 | 118 | entry = get_irq_desc_msi(desc); |
988cbb15 MW |
119 | BUG_ON(!entry || !entry->dev); |
120 | switch (entry->msi_attrib.type) { | |
121 | case PCI_CAP_ID_MSI: | |
122 | /* nothing to do */ | |
123 | break; | |
124 | case PCI_CAP_ID_MSIX: | |
125 | { | |
126 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
127 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
128 | readl(entry->mask_base + offset); | |
129 | break; | |
130 | } | |
131 | default: | |
132 | BUG(); | |
133 | break; | |
134 | } | |
135 | } | |
136 | ||
ce6fce42 MW |
137 | /* |
138 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
139 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
140 | * reliably as devices without an INTx disable bit will then generate a | |
141 | * level IRQ which will never be cleared. | |
142 | * | |
143 | * Returns 1 if it succeeded in masking the interrupt and 0 if the device | |
144 | * doesn't support MSI masking. | |
145 | */ | |
3145e941 | 146 | static int msi_set_mask_bits(struct irq_desc *desc, u32 mask, u32 flag) |
1da177e4 LT |
147 | { |
148 | struct msi_desc *entry; | |
149 | ||
3145e941 | 150 | entry = get_irq_desc_msi(desc); |
277bc33b | 151 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
152 | switch (entry->msi_attrib.type) { |
153 | case PCI_CAP_ID_MSI: | |
277bc33b | 154 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
155 | int pos; |
156 | u32 mask_bits; | |
277bc33b EB |
157 | |
158 | pos = (long)entry->mask_base; | |
159 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
8e149e09 YL |
160 | mask_bits &= ~(mask); |
161 | mask_bits |= flag & mask; | |
277bc33b | 162 | pci_write_config_dword(entry->dev, pos, mask_bits); |
58e0543e | 163 | } else { |
ce6fce42 | 164 | return 0; |
277bc33b | 165 | } |
1da177e4 | 166 | break; |
1da177e4 LT |
167 | case PCI_CAP_ID_MSIX: |
168 | { | |
169 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
170 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
171 | writel(flag, entry->mask_base + offset); | |
348e3fd1 | 172 | readl(entry->mask_base + offset); |
1da177e4 LT |
173 | break; |
174 | } | |
175 | default: | |
277bc33b | 176 | BUG(); |
1da177e4 LT |
177 | break; |
178 | } | |
392ee1e6 | 179 | entry->msi_attrib.masked = !!flag; |
ce6fce42 | 180 | return 1; |
1da177e4 LT |
181 | } |
182 | ||
3145e941 | 183 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 184 | { |
3145e941 | 185 | struct msi_desc *entry = get_irq_desc_msi(desc); |
0366f8f7 EB |
186 | switch(entry->msi_attrib.type) { |
187 | case PCI_CAP_ID_MSI: | |
188 | { | |
189 | struct pci_dev *dev = entry->dev; | |
190 | int pos = entry->msi_attrib.pos; | |
191 | u16 data; | |
192 | ||
193 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
194 | &msg->address_lo); | |
195 | if (entry->msi_attrib.is_64) { | |
196 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
197 | &msg->address_hi); | |
198 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
199 | } else { | |
200 | msg->address_hi = 0; | |
cbf5d9e6 | 201 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
202 | } |
203 | msg->data = data; | |
204 | break; | |
205 | } | |
206 | case PCI_CAP_ID_MSIX: | |
207 | { | |
208 | void __iomem *base; | |
209 | base = entry->mask_base + | |
210 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
211 | ||
212 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
213 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
214 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
215 | break; | |
216 | } | |
217 | default: | |
218 | BUG(); | |
219 | } | |
220 | } | |
1da177e4 | 221 | |
3145e941 | 222 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 223 | { |
3145e941 YL |
224 | struct irq_desc *desc = irq_to_desc(irq); |
225 | ||
226 | read_msi_msg_desc(desc, msg); | |
227 | } | |
228 | ||
229 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
230 | { | |
231 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
1da177e4 LT |
232 | switch (entry->msi_attrib.type) { |
233 | case PCI_CAP_ID_MSI: | |
234 | { | |
0366f8f7 EB |
235 | struct pci_dev *dev = entry->dev; |
236 | int pos = entry->msi_attrib.pos; | |
237 | ||
238 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
239 | msg->address_lo); | |
240 | if (entry->msi_attrib.is_64) { | |
241 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
242 | msg->address_hi); | |
243 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
244 | msg->data); | |
245 | } else { | |
246 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
247 | msg->data); | |
248 | } | |
1da177e4 LT |
249 | break; |
250 | } | |
251 | case PCI_CAP_ID_MSIX: | |
252 | { | |
0366f8f7 EB |
253 | void __iomem *base; |
254 | base = entry->mask_base + | |
255 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
256 | ||
257 | writel(msg->address_lo, | |
258 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
259 | writel(msg->address_hi, | |
260 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
261 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
262 | break; |
263 | } | |
264 | default: | |
0366f8f7 | 265 | BUG(); |
1da177e4 | 266 | } |
392ee1e6 | 267 | entry->msg = *msg; |
1da177e4 | 268 | } |
0366f8f7 | 269 | |
3145e941 YL |
270 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
271 | { | |
272 | struct irq_desc *desc = irq_to_desc(irq); | |
273 | ||
274 | write_msi_msg_desc(desc, msg); | |
275 | } | |
276 | ||
3b7d1921 | 277 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 278 | { |
3145e941 YL |
279 | struct irq_desc *desc = irq_to_desc(irq); |
280 | ||
281 | msi_set_mask_bits(desc, 1, 1); | |
282 | msix_flush_writes(desc); | |
1da177e4 LT |
283 | } |
284 | ||
3b7d1921 | 285 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 286 | { |
3145e941 YL |
287 | struct irq_desc *desc = irq_to_desc(irq); |
288 | ||
289 | msi_set_mask_bits(desc, 1, 0); | |
290 | msix_flush_writes(desc); | |
1da177e4 LT |
291 | } |
292 | ||
032de8e2 | 293 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 294 | |
1da177e4 LT |
295 | static struct msi_desc* alloc_msi_entry(void) |
296 | { | |
297 | struct msi_desc *entry; | |
298 | ||
3e916c05 | 299 | entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL); |
1da177e4 LT |
300 | if (!entry) |
301 | return NULL; | |
302 | ||
4aa9bc95 ME |
303 | INIT_LIST_HEAD(&entry->list); |
304 | entry->irq = 0; | |
1da177e4 LT |
305 | entry->dev = NULL; |
306 | ||
307 | return entry; | |
308 | } | |
309 | ||
ba698ad4 DM |
310 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
311 | { | |
312 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
313 | pci_intx(dev, enable); | |
314 | } | |
315 | ||
8fed4b65 | 316 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 317 | { |
392ee1e6 | 318 | int pos; |
41017f0c | 319 | u16 control; |
392ee1e6 | 320 | struct msi_desc *entry; |
41017f0c | 321 | |
b1cbf4e4 EB |
322 | if (!dev->msi_enabled) |
323 | return; | |
324 | ||
392ee1e6 EB |
325 | entry = get_irq_msi(dev->irq); |
326 | pos = entry->msi_attrib.pos; | |
41017f0c | 327 | |
ba698ad4 | 328 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 329 | msi_set_enable(dev, 0); |
392ee1e6 | 330 | write_msi_msg(dev->irq, &entry->msg); |
3145e941 YL |
331 | if (entry->msi_attrib.maskbit) { |
332 | struct irq_desc *desc = irq_to_desc(dev->irq); | |
333 | msi_set_mask_bits(desc, entry->msi_attrib.maskbits_mask, | |
8e149e09 | 334 | entry->msi_attrib.masked); |
3145e941 | 335 | } |
392ee1e6 EB |
336 | |
337 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
abad2ec9 JB |
338 | control &= ~PCI_MSI_FLAGS_QSIZE; |
339 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 340 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
341 | } |
342 | ||
343 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 344 | { |
41017f0c | 345 | int pos; |
41017f0c | 346 | struct msi_desc *entry; |
392ee1e6 | 347 | u16 control; |
41017f0c | 348 | |
ded86d8d EB |
349 | if (!dev->msix_enabled) |
350 | return; | |
351 | ||
41017f0c | 352 | /* route the table */ |
ba698ad4 | 353 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 354 | msix_set_enable(dev, 0); |
41017f0c | 355 | |
4aa9bc95 | 356 | list_for_each_entry(entry, &dev->msi_list, list) { |
3145e941 | 357 | struct irq_desc *desc = irq_to_desc(entry->irq); |
4aa9bc95 | 358 | write_msi_msg(entry->irq, &entry->msg); |
3145e941 | 359 | msi_set_mask_bits(desc, 1, entry->msi_attrib.masked); |
41017f0c | 360 | } |
41017f0c | 361 | |
314e77b3 ME |
362 | BUG_ON(list_empty(&dev->msi_list)); |
363 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
4aa9bc95 | 364 | pos = entry->msi_attrib.pos; |
392ee1e6 EB |
365 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
366 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
367 | control |= PCI_MSIX_FLAGS_ENABLE; | |
368 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 369 | } |
8fed4b65 ME |
370 | |
371 | void pci_restore_msi_state(struct pci_dev *dev) | |
372 | { | |
373 | __pci_restore_msi_state(dev); | |
374 | __pci_restore_msix_state(dev); | |
375 | } | |
94688cf2 | 376 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 377 | |
1da177e4 LT |
378 | /** |
379 | * msi_capability_init - configure device's MSI capability structure | |
380 | * @dev: pointer to the pci_dev data structure of MSI device function | |
381 | * | |
eaae4b3a | 382 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 383 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 384 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 385 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
386 | **/ |
387 | static int msi_capability_init(struct pci_dev *dev) | |
388 | { | |
389 | struct msi_desc *entry; | |
7fe3730d | 390 | int pos, ret; |
1da177e4 LT |
391 | u16 control; |
392 | ||
b1cbf4e4 EB |
393 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
394 | ||
1da177e4 LT |
395 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
396 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
397 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
398 | entry = alloc_msi_entry(); |
399 | if (!entry) | |
400 | return -ENOMEM; | |
1ce03373 | 401 | |
1da177e4 | 402 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 403 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
404 | entry->msi_attrib.entry_nr = 0; |
405 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 406 | entry->msi_attrib.masked = 1; |
1ce03373 | 407 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 408 | entry->msi_attrib.pos = pos; |
3b7d1921 EB |
409 | entry->dev = dev; |
410 | if (entry->msi_attrib.maskbit) { | |
0db29af1 HS |
411 | unsigned int base, maskbits, temp; |
412 | ||
413 | base = msi_mask_bits_reg(pos, entry->msi_attrib.is_64); | |
414 | entry->mask_base = (void __iomem *)(long)base; | |
415 | ||
3b7d1921 | 416 | /* All MSIs are unmasked by default, Mask them all */ |
0db29af1 | 417 | pci_read_config_dword(dev, base, &maskbits); |
bffac3c5 | 418 | temp = msi_mask((control & PCI_MSI_FLAGS_QMASK) >> 1); |
3b7d1921 | 419 | maskbits |= temp; |
0db29af1 | 420 | pci_write_config_dword(dev, base, maskbits); |
8e149e09 | 421 | entry->msi_attrib.maskbits_mask = temp; |
3b7d1921 | 422 | } |
0dd11f9b | 423 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 424 | |
1da177e4 | 425 | /* Configure MSI capability structure */ |
9c831334 | 426 | ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI); |
7fe3730d | 427 | if (ret) { |
032de8e2 | 428 | msi_free_irqs(dev); |
7fe3730d | 429 | return ret; |
fd58e55f | 430 | } |
f7feaca7 | 431 | |
1da177e4 | 432 | /* Set MSI enabled bits */ |
ba698ad4 | 433 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
434 | msi_set_enable(dev, 1); |
435 | dev->msi_enabled = 1; | |
1da177e4 | 436 | |
7fe3730d | 437 | dev->irq = entry->irq; |
1da177e4 LT |
438 | return 0; |
439 | } | |
440 | ||
441 | /** | |
442 | * msix_capability_init - configure device's MSI-X capability | |
443 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
444 | * @entries: pointer to an array of struct msix_entry entries |
445 | * @nvec: number of @entries | |
1da177e4 | 446 | * |
eaae4b3a | 447 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
448 | * single MSI-X irq. A return of zero indicates the successful setup of |
449 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
450 | **/ |
451 | static int msix_capability_init(struct pci_dev *dev, | |
452 | struct msix_entry *entries, int nvec) | |
453 | { | |
4aa9bc95 | 454 | struct msi_desc *entry; |
9c831334 | 455 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
456 | unsigned long phys_addr; |
457 | u32 table_offset; | |
1da177e4 LT |
458 | u16 control; |
459 | u8 bir; | |
460 | void __iomem *base; | |
461 | ||
b1cbf4e4 EB |
462 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
463 | ||
1da177e4 LT |
464 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
465 | /* Request & Map MSI-X table region */ | |
466 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
467 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
468 | |
469 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 470 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
471 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
472 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
473 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
474 | if (base == NULL) | |
475 | return -ENOMEM; | |
476 | ||
477 | /* MSI-X Table Initialization */ | |
478 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
479 | entry = alloc_msi_entry(); |
480 | if (!entry) | |
1da177e4 | 481 | break; |
1da177e4 LT |
482 | |
483 | j = entries[i].entry; | |
1da177e4 | 484 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 485 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
486 | entry->msi_attrib.entry_nr = j; |
487 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 488 | entry->msi_attrib.masked = 1; |
1ce03373 | 489 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 490 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
491 | entry->dev = dev; |
492 | entry->mask_base = base; | |
f7feaca7 | 493 | |
0dd11f9b | 494 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 495 | } |
9c831334 ME |
496 | |
497 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
498 | if (ret) { | |
499 | int avail = 0; | |
500 | list_for_each_entry(entry, &dev->msi_list, list) { | |
501 | if (entry->irq != 0) { | |
502 | avail++; | |
9c831334 | 503 | } |
1da177e4 | 504 | } |
9c831334 | 505 | |
032de8e2 ME |
506 | msi_free_irqs(dev); |
507 | ||
92db6d10 EB |
508 | /* If we had some success report the number of irqs |
509 | * we succeeded in setting up. | |
510 | */ | |
9c831334 ME |
511 | if (avail == 0) |
512 | avail = ret; | |
92db6d10 | 513 | return avail; |
1da177e4 | 514 | } |
9c831334 ME |
515 | |
516 | i = 0; | |
517 | list_for_each_entry(entry, &dev->msi_list, list) { | |
518 | entries[i].vector = entry->irq; | |
519 | set_irq_msi(entry->irq, entry); | |
520 | i++; | |
521 | } | |
1da177e4 | 522 | /* Set MSI-X enabled bits */ |
ba698ad4 | 523 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
524 | msix_set_enable(dev, 1); |
525 | dev->msix_enabled = 1; | |
1da177e4 LT |
526 | |
527 | return 0; | |
528 | } | |
529 | ||
24334a12 | 530 | /** |
17bbc12a | 531 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 532 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 533 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 534 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 535 | * |
0306ebfa | 536 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
537 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
538 | * supported return 0, else return an error code. | |
24334a12 | 539 | **/ |
c9953a73 | 540 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
541 | { |
542 | struct pci_bus *bus; | |
c9953a73 | 543 | int ret; |
24334a12 | 544 | |
0306ebfa | 545 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
546 | if (!pci_msi_enable || !dev || dev->no_msi) |
547 | return -EINVAL; | |
548 | ||
314e77b3 ME |
549 | /* |
550 | * You can't ask to have 0 or less MSIs configured. | |
551 | * a) it's stupid .. | |
552 | * b) the list manipulation code assumes nvec >= 1. | |
553 | */ | |
554 | if (nvec < 1) | |
555 | return -ERANGE; | |
556 | ||
0306ebfa BG |
557 | /* Any bridge which does NOT route MSI transactions from it's |
558 | * secondary bus to it's primary bus must set NO_MSI flag on | |
559 | * the secondary pci_bus. | |
560 | * We expect only arch-specific PCI host bus controller driver | |
561 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
562 | */ | |
24334a12 BG |
563 | for (bus = dev->bus; bus; bus = bus->parent) |
564 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
565 | return -EINVAL; | |
566 | ||
c9953a73 ME |
567 | ret = arch_msi_check_device(dev, nvec, type); |
568 | if (ret) | |
569 | return ret; | |
570 | ||
b1e2303d ME |
571 | if (!pci_find_capability(dev, type)) |
572 | return -EINVAL; | |
573 | ||
24334a12 BG |
574 | return 0; |
575 | } | |
576 | ||
1da177e4 LT |
577 | /** |
578 | * pci_enable_msi - configure device's MSI capability structure | |
579 | * @dev: pointer to the pci_dev data structure of MSI device function | |
580 | * | |
581 | * Setup the MSI capability structure of device function with | |
1ce03373 | 582 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
583 | * MSI mode enabled on its hardware device function. A return of zero |
584 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 585 | * irq or non-zero for otherwise. |
1da177e4 LT |
586 | **/ |
587 | int pci_enable_msi(struct pci_dev* dev) | |
588 | { | |
b1e2303d | 589 | int status; |
1da177e4 | 590 | |
c9953a73 ME |
591 | status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI); |
592 | if (status) | |
593 | return status; | |
1da177e4 | 594 | |
ded86d8d | 595 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 596 | |
1ce03373 | 597 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 | 598 | if (dev->msix_enabled) { |
80ccba11 BH |
599 | dev_info(&dev->dev, "can't enable MSI " |
600 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 601 | return -EINVAL; |
1da177e4 LT |
602 | } |
603 | status = msi_capability_init(dev); | |
1da177e4 LT |
604 | return status; |
605 | } | |
4cc086fa | 606 | EXPORT_SYMBOL(pci_enable_msi); |
1da177e4 | 607 | |
d52877c7 | 608 | void pci_msi_shutdown(struct pci_dev* dev) |
1da177e4 LT |
609 | { |
610 | struct msi_desc *entry; | |
1da177e4 | 611 | |
128bc5fc | 612 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
613 | return; |
614 | ||
b1cbf4e4 | 615 | msi_set_enable(dev, 0); |
ba698ad4 | 616 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 617 | dev->msi_enabled = 0; |
7bd007e4 | 618 | |
314e77b3 ME |
619 | BUG_ON(list_empty(&dev->msi_list)); |
620 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
8e149e09 YL |
621 | /* Return the the pci reset with msi irqs unmasked */ |
622 | if (entry->msi_attrib.maskbit) { | |
623 | u32 mask = entry->msi_attrib.maskbits_mask; | |
3145e941 YL |
624 | struct irq_desc *desc = irq_to_desc(dev->irq); |
625 | msi_set_mask_bits(desc, mask, ~mask); | |
8e149e09 | 626 | } |
d52877c7 | 627 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) |
1da177e4 | 628 | return; |
e387b9ee ME |
629 | |
630 | /* Restore dev->irq to its default pin-assertion irq */ | |
d52877c7 YL |
631 | dev->irq = entry->msi_attrib.default_irq; |
632 | } | |
633 | void pci_disable_msi(struct pci_dev* dev) | |
634 | { | |
635 | struct msi_desc *entry; | |
636 | ||
637 | if (!pci_msi_enable || !dev || !dev->msi_enabled) | |
638 | return; | |
639 | ||
640 | pci_msi_shutdown(dev); | |
641 | ||
642 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
643 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) | |
644 | return; | |
645 | ||
646 | msi_free_irqs(dev); | |
1da177e4 | 647 | } |
4cc086fa | 648 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 649 | |
032de8e2 | 650 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 651 | { |
032de8e2 | 652 | struct msi_desc *entry, *tmp; |
7ede9c1f | 653 | |
b3b7cc7b DM |
654 | list_for_each_entry(entry, &dev->msi_list, list) { |
655 | if (entry->irq) | |
656 | BUG_ON(irq_has_action(entry->irq)); | |
657 | } | |
1da177e4 | 658 | |
032de8e2 | 659 | arch_teardown_msi_irqs(dev); |
1da177e4 | 660 | |
032de8e2 ME |
661 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
662 | if (entry->msi_attrib.type == PCI_CAP_ID_MSIX) { | |
032de8e2 ME |
663 | writel(1, entry->mask_base + entry->msi_attrib.entry_nr |
664 | * PCI_MSIX_ENTRY_SIZE | |
665 | + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
78b7611c EB |
666 | |
667 | if (list_is_last(&entry->list, &dev->msi_list)) | |
668 | iounmap(entry->mask_base); | |
032de8e2 ME |
669 | } |
670 | list_del(&entry->list); | |
671 | kfree(entry); | |
1da177e4 LT |
672 | } |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
1da177e4 LT |
677 | /** |
678 | * pci_enable_msix - configure device's MSI-X capability structure | |
679 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 680 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 681 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
682 | * |
683 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 684 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
685 | * MSI-X mode enabled on its hardware device function. A return of zero |
686 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 687 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 688 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 689 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
690 | * its request. |
691 | **/ | |
692 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
693 | { | |
92db6d10 | 694 | int status, pos, nr_entries; |
ded86d8d | 695 | int i, j; |
1da177e4 | 696 | u16 control; |
1da177e4 | 697 | |
c9953a73 | 698 | if (!entries) |
1da177e4 LT |
699 | return -EINVAL; |
700 | ||
c9953a73 ME |
701 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
702 | if (status) | |
703 | return status; | |
704 | ||
b64c05e7 | 705 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1da177e4 | 706 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
1da177e4 LT |
707 | nr_entries = multi_msix_capable(control); |
708 | if (nvec > nr_entries) | |
709 | return -EINVAL; | |
710 | ||
711 | /* Check for any invalid entries */ | |
712 | for (i = 0; i < nvec; i++) { | |
713 | if (entries[i].entry >= nr_entries) | |
714 | return -EINVAL; /* invalid entry */ | |
715 | for (j = i + 1; j < nvec; j++) { | |
716 | if (entries[i].entry == entries[j].entry) | |
717 | return -EINVAL; /* duplicate entry */ | |
718 | } | |
719 | } | |
ded86d8d | 720 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 721 | |
1ce03373 | 722 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 723 | if (dev->msi_enabled) { |
80ccba11 BH |
724 | dev_info(&dev->dev, "can't enable MSI-X " |
725 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
726 | return -EINVAL; |
727 | } | |
1da177e4 | 728 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
729 | return status; |
730 | } | |
4cc086fa | 731 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 732 | |
fc4afc7b | 733 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 734 | { |
032de8e2 | 735 | msi_free_irqs(dev); |
fc4afc7b ME |
736 | } |
737 | ||
d52877c7 | 738 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 739 | { |
128bc5fc | 740 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
741 | return; |
742 | ||
b1cbf4e4 | 743 | msix_set_enable(dev, 0); |
ba698ad4 | 744 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 745 | dev->msix_enabled = 0; |
d52877c7 YL |
746 | } |
747 | void pci_disable_msix(struct pci_dev* dev) | |
748 | { | |
749 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
750 | return; | |
751 | ||
752 | pci_msix_shutdown(dev); | |
7bd007e4 | 753 | |
fc4afc7b | 754 | msix_free_all_irqs(dev); |
1da177e4 | 755 | } |
4cc086fa | 756 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
757 | |
758 | /** | |
1ce03373 | 759 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
760 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
761 | * | |
eaae4b3a | 762 | * Being called during hotplug remove, from which the device function |
1ce03373 | 763 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
764 | * allocated for this device function, are reclaimed to unused state, |
765 | * which may be used later on. | |
766 | **/ | |
767 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
768 | { | |
1da177e4 LT |
769 | if (!pci_msi_enable || !dev) |
770 | return; | |
771 | ||
032de8e2 ME |
772 | if (dev->msi_enabled) |
773 | msi_free_irqs(dev); | |
1da177e4 | 774 | |
fc4afc7b ME |
775 | if (dev->msix_enabled) |
776 | msix_free_all_irqs(dev); | |
1da177e4 LT |
777 | } |
778 | ||
309e57df MW |
779 | void pci_no_msi(void) |
780 | { | |
781 | pci_msi_enable = 0; | |
782 | } | |
c9953a73 | 783 | |
07ae95f9 AP |
784 | /** |
785 | * pci_msi_enabled - is MSI enabled? | |
786 | * | |
787 | * Returns true if MSI has not been disabled by the command-line option | |
788 | * pci=nomsi. | |
789 | **/ | |
790 | int pci_msi_enabled(void) | |
d389fec6 | 791 | { |
07ae95f9 | 792 | return pci_msi_enable; |
d389fec6 | 793 | } |
07ae95f9 | 794 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 795 | |
07ae95f9 | 796 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 797 | { |
07ae95f9 | 798 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 799 | } |