Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 LT |
14 | #include <linux/ioport.h> |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/smp.h> | |
23 | ||
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
27 | static DEFINE_SPINLOCK(msi_lock); | |
28 | static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; | |
e18b890b | 29 | static struct kmem_cache* msi_cachep; |
1da177e4 LT |
30 | |
31 | static int pci_msi_enable = 1; | |
1da177e4 | 32 | |
1da177e4 LT |
33 | static int msi_cache_init(void) |
34 | { | |
57181784 PE |
35 | msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), |
36 | 0, SLAB_HWCACHE_ALIGN, NULL, NULL); | |
1da177e4 LT |
37 | if (!msi_cachep) |
38 | return -ENOMEM; | |
39 | ||
40 | return 0; | |
41 | } | |
42 | ||
1ce03373 | 43 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
44 | { |
45 | struct msi_desc *entry; | |
46 | ||
1ce03373 | 47 | entry = msi_desc[irq]; |
277bc33b | 48 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
49 | switch (entry->msi_attrib.type) { |
50 | case PCI_CAP_ID_MSI: | |
277bc33b | 51 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
52 | int pos; |
53 | u32 mask_bits; | |
277bc33b EB |
54 | |
55 | pos = (long)entry->mask_base; | |
56 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
57 | mask_bits &= ~(1); | |
58 | mask_bits |= flag; | |
59 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
60 | } | |
1da177e4 | 61 | break; |
1da177e4 LT |
62 | case PCI_CAP_ID_MSIX: |
63 | { | |
64 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
65 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
66 | writel(flag, entry->mask_base + offset); | |
67 | break; | |
68 | } | |
69 | default: | |
277bc33b | 70 | BUG(); |
1da177e4 LT |
71 | break; |
72 | } | |
73 | } | |
74 | ||
3b7d1921 | 75 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 76 | { |
3b7d1921 | 77 | struct msi_desc *entry = get_irq_data(irq); |
0366f8f7 EB |
78 | switch(entry->msi_attrib.type) { |
79 | case PCI_CAP_ID_MSI: | |
80 | { | |
81 | struct pci_dev *dev = entry->dev; | |
82 | int pos = entry->msi_attrib.pos; | |
83 | u16 data; | |
84 | ||
85 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
86 | &msg->address_lo); | |
87 | if (entry->msi_attrib.is_64) { | |
88 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
89 | &msg->address_hi); | |
90 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
91 | } else { | |
92 | msg->address_hi = 0; | |
93 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
94 | } | |
95 | msg->data = data; | |
96 | break; | |
97 | } | |
98 | case PCI_CAP_ID_MSIX: | |
99 | { | |
100 | void __iomem *base; | |
101 | base = entry->mask_base + | |
102 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
103 | ||
104 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
105 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
106 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
107 | break; | |
108 | } | |
109 | default: | |
110 | BUG(); | |
111 | } | |
112 | } | |
1da177e4 | 113 | |
3b7d1921 | 114 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 115 | { |
3b7d1921 | 116 | struct msi_desc *entry = get_irq_data(irq); |
1da177e4 LT |
117 | switch (entry->msi_attrib.type) { |
118 | case PCI_CAP_ID_MSI: | |
119 | { | |
0366f8f7 EB |
120 | struct pci_dev *dev = entry->dev; |
121 | int pos = entry->msi_attrib.pos; | |
122 | ||
123 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
124 | msg->address_lo); | |
125 | if (entry->msi_attrib.is_64) { | |
126 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
127 | msg->address_hi); | |
128 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
129 | msg->data); | |
130 | } else { | |
131 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
132 | msg->data); | |
133 | } | |
1da177e4 LT |
134 | break; |
135 | } | |
136 | case PCI_CAP_ID_MSIX: | |
137 | { | |
0366f8f7 EB |
138 | void __iomem *base; |
139 | base = entry->mask_base + | |
140 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
141 | ||
142 | writel(msg->address_lo, | |
143 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
144 | writel(msg->address_hi, | |
145 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
146 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
147 | break; |
148 | } | |
149 | default: | |
0366f8f7 | 150 | BUG(); |
1da177e4 LT |
151 | } |
152 | } | |
0366f8f7 | 153 | |
3b7d1921 | 154 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 155 | { |
1ce03373 | 156 | msi_set_mask_bit(irq, 1); |
1da177e4 LT |
157 | } |
158 | ||
3b7d1921 | 159 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 160 | { |
1ce03373 | 161 | msi_set_mask_bit(irq, 0); |
1da177e4 LT |
162 | } |
163 | ||
1ce03373 | 164 | static int msi_free_irq(struct pci_dev* dev, int irq); |
c54c1879 | 165 | |
1da177e4 LT |
166 | static int msi_init(void) |
167 | { | |
168 | static int status = -ENOMEM; | |
169 | ||
170 | if (!status) | |
171 | return status; | |
172 | ||
b64c05e7 GG |
173 | status = msi_cache_init(); |
174 | if (status < 0) { | |
1da177e4 LT |
175 | pci_msi_enable = 0; |
176 | printk(KERN_WARNING "PCI: MSI cache init failed\n"); | |
177 | return status; | |
178 | } | |
fd58e55f | 179 | |
1da177e4 LT |
180 | return status; |
181 | } | |
182 | ||
1da177e4 LT |
183 | static struct msi_desc* alloc_msi_entry(void) |
184 | { | |
185 | struct msi_desc *entry; | |
186 | ||
57181784 | 187 | entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); |
1da177e4 LT |
188 | if (!entry) |
189 | return NULL; | |
190 | ||
1da177e4 LT |
191 | entry->link.tail = entry->link.head = 0; /* single message */ |
192 | entry->dev = NULL; | |
193 | ||
194 | return entry; | |
195 | } | |
196 | ||
1ce03373 | 197 | static void attach_msi_entry(struct msi_desc *entry, int irq) |
1da177e4 LT |
198 | { |
199 | unsigned long flags; | |
200 | ||
201 | spin_lock_irqsave(&msi_lock, flags); | |
1ce03373 | 202 | msi_desc[irq] = entry; |
1da177e4 LT |
203 | spin_unlock_irqrestore(&msi_lock, flags); |
204 | } | |
205 | ||
3b7d1921 | 206 | static int create_msi_irq(void) |
1da177e4 | 207 | { |
1ce03373 EB |
208 | struct msi_desc *entry; |
209 | int irq; | |
210 | ||
211 | entry = alloc_msi_entry(); | |
212 | if (!entry) | |
213 | return -ENOMEM; | |
f6bc2666 | 214 | |
1ce03373 EB |
215 | irq = create_irq(); |
216 | if (irq < 0) { | |
217 | kmem_cache_free(msi_cachep, entry); | |
218 | return -EBUSY; | |
1da177e4 | 219 | } |
1ce03373 | 220 | |
1ce03373 EB |
221 | set_irq_data(irq, entry); |
222 | ||
223 | return irq; | |
224 | } | |
225 | ||
226 | static void destroy_msi_irq(unsigned int irq) | |
227 | { | |
228 | struct msi_desc *entry; | |
229 | ||
230 | entry = get_irq_data(irq); | |
231 | set_irq_chip(irq, NULL); | |
232 | set_irq_data(irq, NULL); | |
233 | destroy_irq(irq); | |
234 | kmem_cache_free(msi_cachep, entry); | |
1da177e4 LT |
235 | } |
236 | ||
237 | static void enable_msi_mode(struct pci_dev *dev, int pos, int type) | |
238 | { | |
239 | u16 control; | |
240 | ||
241 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
242 | if (type == PCI_CAP_ID_MSI) { | |
243 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
244 | msi_enable(control, 1); | |
245 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 246 | dev->msi_enabled = 1; |
1da177e4 LT |
247 | } else { |
248 | msix_enable(control); | |
249 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 250 | dev->msix_enabled = 1; |
1da177e4 | 251 | } |
1769b46a JG |
252 | |
253 | pci_intx(dev, 0); /* disable intx */ | |
1da177e4 LT |
254 | } |
255 | ||
4602b88d | 256 | void disable_msi_mode(struct pci_dev *dev, int pos, int type) |
1da177e4 LT |
257 | { |
258 | u16 control; | |
259 | ||
260 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
261 | if (type == PCI_CAP_ID_MSI) { | |
262 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
263 | msi_disable(control); | |
264 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 265 | dev->msi_enabled = 0; |
1da177e4 LT |
266 | } else { |
267 | msix_disable(control); | |
268 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 269 | dev->msix_enabled = 0; |
1da177e4 | 270 | } |
1769b46a JG |
271 | |
272 | pci_intx(dev, 1); /* enable intx */ | |
1da177e4 LT |
273 | } |
274 | ||
1ce03373 | 275 | static int msi_lookup_irq(struct pci_dev *dev, int type) |
1da177e4 | 276 | { |
1ce03373 | 277 | int irq; |
1da177e4 LT |
278 | unsigned long flags; |
279 | ||
280 | spin_lock_irqsave(&msi_lock, flags); | |
1ce03373 EB |
281 | for (irq = 0; irq < NR_IRQS; irq++) { |
282 | if (!msi_desc[irq] || msi_desc[irq]->dev != dev || | |
283 | msi_desc[irq]->msi_attrib.type != type || | |
284 | msi_desc[irq]->msi_attrib.default_irq != dev->irq) | |
1da177e4 LT |
285 | continue; |
286 | spin_unlock_irqrestore(&msi_lock, flags); | |
1ce03373 | 287 | /* This pre-assigned MSI irq for this device |
c54c1879 | 288 | already exists. Override dev->irq with this irq */ |
1ce03373 | 289 | dev->irq = irq; |
1da177e4 LT |
290 | return 0; |
291 | } | |
292 | spin_unlock_irqrestore(&msi_lock, flags); | |
293 | ||
294 | return -EACCES; | |
295 | } | |
296 | ||
41017f0c SL |
297 | #ifdef CONFIG_PM |
298 | int pci_save_msi_state(struct pci_dev *dev) | |
299 | { | |
300 | int pos, i = 0; | |
301 | u16 control; | |
302 | struct pci_cap_saved_state *save_state; | |
303 | u32 *cap; | |
304 | ||
305 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
306 | if (pos <= 0 || dev->no_msi) | |
307 | return 0; | |
308 | ||
309 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
310 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
311 | return 0; | |
312 | ||
313 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, | |
314 | GFP_KERNEL); | |
315 | if (!save_state) { | |
316 | printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); | |
317 | return -ENOMEM; | |
318 | } | |
319 | cap = &save_state->data[0]; | |
320 | ||
321 | pci_read_config_dword(dev, pos, &cap[i++]); | |
322 | control = cap[0] >> 16; | |
323 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); | |
324 | if (control & PCI_MSI_FLAGS_64BIT) { | |
325 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); | |
326 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); | |
327 | } else | |
328 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); | |
329 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
330 | pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); | |
41017f0c SL |
331 | save_state->cap_nr = PCI_CAP_ID_MSI; |
332 | pci_add_saved_cap(dev, save_state); | |
333 | return 0; | |
334 | } | |
335 | ||
336 | void pci_restore_msi_state(struct pci_dev *dev) | |
337 | { | |
338 | int i = 0, pos; | |
339 | u16 control; | |
340 | struct pci_cap_saved_state *save_state; | |
341 | u32 *cap; | |
342 | ||
343 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); | |
344 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
345 | if (!save_state || pos <= 0) | |
346 | return; | |
347 | cap = &save_state->data[0]; | |
348 | ||
349 | control = cap[i++] >> 16; | |
350 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); | |
351 | if (control & PCI_MSI_FLAGS_64BIT) { | |
352 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); | |
353 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); | |
354 | } else | |
355 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); | |
356 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
357 | pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); | |
358 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
359 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
360 | pci_remove_saved_cap(save_state); | |
361 | kfree(save_state); | |
362 | } | |
363 | ||
364 | int pci_save_msix_state(struct pci_dev *dev) | |
365 | { | |
366 | int pos; | |
fd58e55f | 367 | int temp; |
1ce03373 | 368 | int irq, head, tail = 0; |
41017f0c SL |
369 | u16 control; |
370 | struct pci_cap_saved_state *save_state; | |
371 | ||
372 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
373 | if (pos <= 0 || dev->no_msi) | |
374 | return 0; | |
375 | ||
fd58e55f | 376 | /* save the capability */ |
41017f0c SL |
377 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
378 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
379 | return 0; | |
380 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), | |
381 | GFP_KERNEL); | |
382 | if (!save_state) { | |
383 | printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); | |
384 | return -ENOMEM; | |
385 | } | |
386 | *((u16 *)&save_state->data[0]) = control; | |
387 | ||
fd58e55f MM |
388 | /* save the table */ |
389 | temp = dev->irq; | |
1ce03373 | 390 | if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
fd58e55f MM |
391 | kfree(save_state); |
392 | return -EINVAL; | |
393 | } | |
394 | ||
1ce03373 | 395 | irq = head = dev->irq; |
fd58e55f | 396 | while (head != tail) { |
fd58e55f MM |
397 | struct msi_desc *entry; |
398 | ||
1ce03373 | 399 | entry = msi_desc[irq]; |
3b7d1921 | 400 | read_msi_msg(irq, &entry->msg_save); |
fd58e55f | 401 | |
1ce03373 EB |
402 | tail = msi_desc[irq]->link.tail; |
403 | irq = tail; | |
fd58e55f MM |
404 | } |
405 | dev->irq = temp; | |
406 | ||
41017f0c SL |
407 | save_state->cap_nr = PCI_CAP_ID_MSIX; |
408 | pci_add_saved_cap(dev, save_state); | |
409 | return 0; | |
410 | } | |
411 | ||
412 | void pci_restore_msix_state(struct pci_dev *dev) | |
413 | { | |
414 | u16 save; | |
415 | int pos; | |
1ce03373 | 416 | int irq, head, tail = 0; |
41017f0c SL |
417 | struct msi_desc *entry; |
418 | int temp; | |
419 | struct pci_cap_saved_state *save_state; | |
420 | ||
421 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); | |
422 | if (!save_state) | |
423 | return; | |
424 | save = *((u16 *)&save_state->data[0]); | |
425 | pci_remove_saved_cap(save_state); | |
426 | kfree(save_state); | |
427 | ||
428 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
429 | if (pos <= 0) | |
430 | return; | |
431 | ||
432 | /* route the table */ | |
433 | temp = dev->irq; | |
1ce03373 | 434 | if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) |
41017f0c | 435 | return; |
1ce03373 | 436 | irq = head = dev->irq; |
41017f0c | 437 | while (head != tail) { |
1ce03373 | 438 | entry = msi_desc[irq]; |
3b7d1921 | 439 | write_msi_msg(irq, &entry->msg_save); |
41017f0c | 440 | |
1ce03373 EB |
441 | tail = msi_desc[irq]->link.tail; |
442 | irq = tail; | |
41017f0c SL |
443 | } |
444 | dev->irq = temp; | |
445 | ||
446 | pci_write_config_word(dev, msi_control_reg(pos), save); | |
447 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
448 | } | |
c54c1879 | 449 | #endif /* CONFIG_PM */ |
41017f0c | 450 | |
1da177e4 LT |
451 | /** |
452 | * msi_capability_init - configure device's MSI capability structure | |
453 | * @dev: pointer to the pci_dev data structure of MSI device function | |
454 | * | |
eaae4b3a | 455 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 456 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 457 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 458 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
459 | **/ |
460 | static int msi_capability_init(struct pci_dev *dev) | |
461 | { | |
fd58e55f | 462 | int status; |
1da177e4 | 463 | struct msi_desc *entry; |
1ce03373 | 464 | int pos, irq; |
1da177e4 LT |
465 | u16 control; |
466 | ||
467 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
468 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
469 | /* MSI Entry Initialization */ | |
3b7d1921 | 470 | irq = create_msi_irq(); |
1ce03373 EB |
471 | if (irq < 0) |
472 | return irq; | |
473 | ||
474 | entry = get_irq_data(irq); | |
475 | entry->link.head = irq; | |
476 | entry->link.tail = irq; | |
1da177e4 | 477 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 478 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
479 | entry->msi_attrib.entry_nr = 0; |
480 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 481 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 482 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
483 | if (is_mask_bit_support(control)) { |
484 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
485 | is_64bit_address(control)); | |
486 | } | |
3b7d1921 EB |
487 | entry->dev = dev; |
488 | if (entry->msi_attrib.maskbit) { | |
489 | unsigned int maskbits, temp; | |
490 | /* All MSIs are unmasked by default, Mask them all */ | |
491 | pci_read_config_dword(dev, | |
492 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
493 | &maskbits); | |
494 | temp = (1 << multi_msi_capable(control)); | |
495 | temp = ((temp - 1) & ~temp); | |
496 | maskbits |= temp; | |
497 | pci_write_config_dword(dev, | |
498 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
499 | maskbits); | |
500 | } | |
1da177e4 | 501 | /* Configure MSI capability structure */ |
3b7d1921 EB |
502 | status = arch_setup_msi_irq(irq, dev); |
503 | if (status < 0) { | |
1ce03373 | 504 | destroy_msi_irq(irq); |
fd58e55f MM |
505 | return status; |
506 | } | |
41017f0c | 507 | |
1ce03373 | 508 | attach_msi_entry(entry, irq); |
1da177e4 LT |
509 | /* Set MSI enabled bits */ |
510 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
511 | ||
3b7d1921 | 512 | dev->irq = irq; |
1da177e4 LT |
513 | return 0; |
514 | } | |
515 | ||
516 | /** | |
517 | * msix_capability_init - configure device's MSI-X capability | |
518 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
519 | * @entries: pointer to an array of struct msix_entry entries |
520 | * @nvec: number of @entries | |
1da177e4 | 521 | * |
eaae4b3a | 522 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
523 | * single MSI-X irq. A return of zero indicates the successful setup of |
524 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
525 | **/ |
526 | static int msix_capability_init(struct pci_dev *dev, | |
527 | struct msix_entry *entries, int nvec) | |
528 | { | |
529 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
fd58e55f | 530 | int status; |
1ce03373 | 531 | int irq, pos, i, j, nr_entries, temp = 0; |
a0454b40 GG |
532 | unsigned long phys_addr; |
533 | u32 table_offset; | |
1da177e4 LT |
534 | u16 control; |
535 | u8 bir; | |
536 | void __iomem *base; | |
537 | ||
538 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
539 | /* Request & Map MSI-X table region */ | |
540 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
541 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
542 | |
543 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 544 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
545 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
546 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
547 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
548 | if (base == NULL) | |
549 | return -ENOMEM; | |
550 | ||
551 | /* MSI-X Table Initialization */ | |
552 | for (i = 0; i < nvec; i++) { | |
3b7d1921 | 553 | irq = create_msi_irq(); |
1ce03373 | 554 | if (irq < 0) |
1da177e4 | 555 | break; |
1da177e4 | 556 | |
1ce03373 | 557 | entry = get_irq_data(irq); |
1da177e4 | 558 | j = entries[i].entry; |
1ce03373 | 559 | entries[i].vector = irq; |
1da177e4 | 560 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 561 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
562 | entry->msi_attrib.entry_nr = j; |
563 | entry->msi_attrib.maskbit = 1; | |
1ce03373 | 564 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 565 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
566 | entry->dev = dev; |
567 | entry->mask_base = base; | |
568 | if (!head) { | |
1ce03373 EB |
569 | entry->link.head = irq; |
570 | entry->link.tail = irq; | |
1da177e4 LT |
571 | head = entry; |
572 | } else { | |
573 | entry->link.head = temp; | |
574 | entry->link.tail = tail->link.tail; | |
1ce03373 EB |
575 | tail->link.tail = irq; |
576 | head->link.head = irq; | |
1da177e4 | 577 | } |
1ce03373 | 578 | temp = irq; |
1da177e4 | 579 | tail = entry; |
1da177e4 | 580 | /* Configure MSI-X capability structure */ |
3b7d1921 | 581 | status = arch_setup_msi_irq(irq, dev); |
1ce03373 EB |
582 | if (status < 0) { |
583 | destroy_msi_irq(irq); | |
fd58e55f | 584 | break; |
1ce03373 | 585 | } |
fd58e55f | 586 | |
1ce03373 | 587 | attach_msi_entry(entry, irq); |
1da177e4 LT |
588 | } |
589 | if (i != nvec) { | |
92db6d10 | 590 | int avail = i - 1; |
1da177e4 LT |
591 | i--; |
592 | for (; i >= 0; i--) { | |
1ce03373 EB |
593 | irq = (entries + i)->vector; |
594 | msi_free_irq(dev, irq); | |
1da177e4 LT |
595 | (entries + i)->vector = 0; |
596 | } | |
92db6d10 EB |
597 | /* If we had some success report the number of irqs |
598 | * we succeeded in setting up. | |
599 | */ | |
600 | if (avail <= 0) | |
601 | avail = -EBUSY; | |
602 | return avail; | |
1da177e4 LT |
603 | } |
604 | /* Set MSI-X enabled bits */ | |
605 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
24334a12 BG |
610 | /** |
611 | * pci_msi_supported - check whether MSI may be enabled on device | |
612 | * @dev: pointer to the pci_dev data structure of MSI device function | |
613 | * | |
0306ebfa BG |
614 | * Look at global flags, the device itself, and its parent busses |
615 | * to return 0 if MSI are supported for the device. | |
24334a12 BG |
616 | **/ |
617 | static | |
618 | int pci_msi_supported(struct pci_dev * dev) | |
619 | { | |
620 | struct pci_bus *bus; | |
621 | ||
0306ebfa | 622 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
623 | if (!pci_msi_enable || !dev || dev->no_msi) |
624 | return -EINVAL; | |
625 | ||
0306ebfa BG |
626 | /* Any bridge which does NOT route MSI transactions from it's |
627 | * secondary bus to it's primary bus must set NO_MSI flag on | |
628 | * the secondary pci_bus. | |
629 | * We expect only arch-specific PCI host bus controller driver | |
630 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
631 | */ | |
24334a12 BG |
632 | for (bus = dev->bus; bus; bus = bus->parent) |
633 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
634 | return -EINVAL; | |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
1da177e4 LT |
639 | /** |
640 | * pci_enable_msi - configure device's MSI capability structure | |
641 | * @dev: pointer to the pci_dev data structure of MSI device function | |
642 | * | |
643 | * Setup the MSI capability structure of device function with | |
1ce03373 | 644 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
645 | * MSI mode enabled on its hardware device function. A return of zero |
646 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 647 | * irq or non-zero for otherwise. |
1da177e4 LT |
648 | **/ |
649 | int pci_enable_msi(struct pci_dev* dev) | |
650 | { | |
24334a12 | 651 | int pos, temp, status; |
1da177e4 | 652 | |
24334a12 BG |
653 | if (pci_msi_supported(dev) < 0) |
654 | return -EINVAL; | |
6e325a62 | 655 | |
1da177e4 LT |
656 | temp = dev->irq; |
657 | ||
b64c05e7 GG |
658 | status = msi_init(); |
659 | if (status < 0) | |
1da177e4 LT |
660 | return status; |
661 | ||
b64c05e7 GG |
662 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
663 | if (!pos) | |
1da177e4 LT |
664 | return -EINVAL; |
665 | ||
1ce03373 | 666 | WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI)); |
1da177e4 | 667 | |
1ce03373 | 668 | /* Check whether driver already requested for MSI-X irqs */ |
b64c05e7 | 669 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1ce03373 | 670 | if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
1da177e4 | 671 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " |
1ce03373 | 672 | "Device already has MSI-X irq assigned\n", |
1da177e4 LT |
673 | pci_name(dev)); |
674 | dev->irq = temp; | |
675 | return -EINVAL; | |
676 | } | |
677 | status = msi_capability_init(dev); | |
1da177e4 LT |
678 | return status; |
679 | } | |
680 | ||
681 | void pci_disable_msi(struct pci_dev* dev) | |
682 | { | |
683 | struct msi_desc *entry; | |
1ce03373 | 684 | int pos, default_irq; |
1da177e4 LT |
685 | u16 control; |
686 | unsigned long flags; | |
687 | ||
309e57df MW |
688 | if (!pci_msi_enable) |
689 | return; | |
b64c05e7 GG |
690 | if (!dev) |
691 | return; | |
309e57df | 692 | |
b64c05e7 GG |
693 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
694 | if (!pos) | |
1da177e4 LT |
695 | return; |
696 | ||
697 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
698 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
699 | return; | |
700 | ||
7bd007e4 EB |
701 | disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); |
702 | ||
1da177e4 LT |
703 | spin_lock_irqsave(&msi_lock, flags); |
704 | entry = msi_desc[dev->irq]; | |
705 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { | |
706 | spin_unlock_irqrestore(&msi_lock, flags); | |
707 | return; | |
708 | } | |
1f80025e | 709 | if (irq_has_action(dev->irq)) { |
1da177e4 LT |
710 | spin_unlock_irqrestore(&msi_lock, flags); |
711 | printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " | |
1ce03373 | 712 | "free_irq() on MSI irq %d\n", |
1da177e4 | 713 | pci_name(dev), dev->irq); |
1f80025e | 714 | BUG_ON(irq_has_action(dev->irq)); |
1da177e4 | 715 | } else { |
1ce03373 | 716 | default_irq = entry->msi_attrib.default_irq; |
1da177e4 | 717 | spin_unlock_irqrestore(&msi_lock, flags); |
1ce03373 | 718 | msi_free_irq(dev, dev->irq); |
7bd007e4 | 719 | |
1ce03373 EB |
720 | /* Restore dev->irq to its default pin-assertion irq */ |
721 | dev->irq = default_irq; | |
1da177e4 LT |
722 | } |
723 | } | |
724 | ||
1ce03373 | 725 | static int msi_free_irq(struct pci_dev* dev, int irq) |
1da177e4 LT |
726 | { |
727 | struct msi_desc *entry; | |
728 | int head, entry_nr, type; | |
729 | void __iomem *base; | |
730 | unsigned long flags; | |
731 | ||
3b7d1921 | 732 | arch_teardown_msi_irq(irq); |
fd58e55f | 733 | |
1da177e4 | 734 | spin_lock_irqsave(&msi_lock, flags); |
1ce03373 | 735 | entry = msi_desc[irq]; |
1da177e4 LT |
736 | if (!entry || entry->dev != dev) { |
737 | spin_unlock_irqrestore(&msi_lock, flags); | |
738 | return -EINVAL; | |
739 | } | |
740 | type = entry->msi_attrib.type; | |
741 | entry_nr = entry->msi_attrib.entry_nr; | |
742 | head = entry->link.head; | |
743 | base = entry->mask_base; | |
744 | msi_desc[entry->link.head]->link.tail = entry->link.tail; | |
745 | msi_desc[entry->link.tail]->link.head = entry->link.head; | |
746 | entry->dev = NULL; | |
1ce03373 | 747 | msi_desc[irq] = NULL; |
1da177e4 LT |
748 | spin_unlock_irqrestore(&msi_lock, flags); |
749 | ||
1ce03373 | 750 | destroy_msi_irq(irq); |
1da177e4 LT |
751 | |
752 | if (type == PCI_CAP_ID_MSIX) { | |
1ce03373 EB |
753 | writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + |
754 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
1da177e4 | 755 | |
1ce03373 | 756 | if (head == irq) |
1da177e4 | 757 | iounmap(base); |
1da177e4 LT |
758 | } |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
1da177e4 LT |
763 | /** |
764 | * pci_enable_msix - configure device's MSI-X capability structure | |
765 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 766 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 767 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
768 | * |
769 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 770 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
771 | * MSI-X mode enabled on its hardware device function. A return of zero |
772 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 773 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 774 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 775 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
776 | * its request. |
777 | **/ | |
778 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
779 | { | |
92db6d10 | 780 | int status, pos, nr_entries; |
1da177e4 LT |
781 | int i, j, temp; |
782 | u16 control; | |
1da177e4 | 783 | |
24334a12 | 784 | if (!entries || pci_msi_supported(dev) < 0) |
1da177e4 LT |
785 | return -EINVAL; |
786 | ||
b64c05e7 GG |
787 | status = msi_init(); |
788 | if (status < 0) | |
1da177e4 LT |
789 | return status; |
790 | ||
b64c05e7 GG |
791 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
792 | if (!pos) | |
1da177e4 LT |
793 | return -EINVAL; |
794 | ||
795 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1da177e4 LT |
796 | nr_entries = multi_msix_capable(control); |
797 | if (nvec > nr_entries) | |
798 | return -EINVAL; | |
799 | ||
800 | /* Check for any invalid entries */ | |
801 | for (i = 0; i < nvec; i++) { | |
802 | if (entries[i].entry >= nr_entries) | |
803 | return -EINVAL; /* invalid entry */ | |
804 | for (j = i + 1; j < nvec; j++) { | |
805 | if (entries[i].entry == entries[j].entry) | |
806 | return -EINVAL; /* duplicate entry */ | |
807 | } | |
808 | } | |
809 | temp = dev->irq; | |
1ce03373 | 810 | WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)); |
7bd007e4 | 811 | |
1ce03373 | 812 | /* Check whether driver already requested for MSI irq */ |
1da177e4 | 813 | if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && |
1ce03373 | 814 | !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) { |
1da177e4 | 815 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 816 | "Device already has an MSI irq assigned\n", |
1da177e4 LT |
817 | pci_name(dev)); |
818 | dev->irq = temp; | |
819 | return -EINVAL; | |
820 | } | |
1da177e4 | 821 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
822 | return status; |
823 | } | |
824 | ||
825 | void pci_disable_msix(struct pci_dev* dev) | |
826 | { | |
827 | int pos, temp; | |
828 | u16 control; | |
829 | ||
309e57df MW |
830 | if (!pci_msi_enable) |
831 | return; | |
b64c05e7 GG |
832 | if (!dev) |
833 | return; | |
834 | ||
835 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
836 | if (!pos) | |
1da177e4 LT |
837 | return; |
838 | ||
839 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
840 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
841 | return; | |
842 | ||
7bd007e4 EB |
843 | disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); |
844 | ||
1da177e4 | 845 | temp = dev->irq; |
1ce03373 | 846 | if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
1f80025e | 847 | int irq, head, tail = 0, warning = 0; |
1da177e4 LT |
848 | unsigned long flags; |
849 | ||
1ce03373 | 850 | irq = head = dev->irq; |
7bd007e4 | 851 | dev->irq = temp; /* Restore pin IRQ */ |
1da177e4 | 852 | while (head != tail) { |
7bd007e4 | 853 | spin_lock_irqsave(&msi_lock, flags); |
1ce03373 | 854 | tail = msi_desc[irq]->link.tail; |
7bd007e4 | 855 | spin_unlock_irqrestore(&msi_lock, flags); |
1f80025e | 856 | if (irq_has_action(irq)) |
1da177e4 | 857 | warning = 1; |
1ce03373 EB |
858 | else if (irq != head) /* Release MSI-X irq */ |
859 | msi_free_irq(dev, irq); | |
860 | irq = tail; | |
1da177e4 | 861 | } |
1ce03373 | 862 | msi_free_irq(dev, irq); |
1da177e4 | 863 | if (warning) { |
1da177e4 | 864 | printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " |
1ce03373 | 865 | "free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
866 | pci_name(dev)); |
867 | BUG_ON(warning > 0); | |
1da177e4 LT |
868 | } |
869 | } | |
870 | } | |
871 | ||
872 | /** | |
1ce03373 | 873 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
874 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
875 | * | |
eaae4b3a | 876 | * Being called during hotplug remove, from which the device function |
1ce03373 | 877 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
878 | * allocated for this device function, are reclaimed to unused state, |
879 | * which may be used later on. | |
880 | **/ | |
881 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
882 | { | |
1f80025e | 883 | int pos, temp; |
1da177e4 LT |
884 | unsigned long flags; |
885 | ||
886 | if (!pci_msi_enable || !dev) | |
887 | return; | |
888 | ||
889 | temp = dev->irq; /* Save IOAPIC IRQ */ | |
b64c05e7 | 890 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1ce03373 | 891 | if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) { |
1f80025e | 892 | if (irq_has_action(dev->irq)) { |
1da177e4 | 893 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " |
1ce03373 | 894 | "called without free_irq() on MSI irq %d\n", |
1da177e4 | 895 | pci_name(dev), dev->irq); |
1f80025e | 896 | BUG_ON(irq_has_action(dev->irq)); |
1ce03373 EB |
897 | } else /* Release MSI irq assigned to this device */ |
898 | msi_free_irq(dev, dev->irq); | |
1da177e4 LT |
899 | dev->irq = temp; /* Restore IOAPIC IRQ */ |
900 | } | |
b64c05e7 | 901 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1ce03373 EB |
902 | if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) { |
903 | int irq, head, tail = 0, warning = 0; | |
1da177e4 LT |
904 | void __iomem *base = NULL; |
905 | ||
1ce03373 | 906 | irq = head = dev->irq; |
1da177e4 LT |
907 | while (head != tail) { |
908 | spin_lock_irqsave(&msi_lock, flags); | |
1ce03373 EB |
909 | tail = msi_desc[irq]->link.tail; |
910 | base = msi_desc[irq]->mask_base; | |
1da177e4 | 911 | spin_unlock_irqrestore(&msi_lock, flags); |
1f80025e | 912 | if (irq_has_action(irq)) |
1da177e4 | 913 | warning = 1; |
1ce03373 EB |
914 | else if (irq != head) /* Release MSI-X irq */ |
915 | msi_free_irq(dev, irq); | |
916 | irq = tail; | |
1da177e4 | 917 | } |
1ce03373 | 918 | msi_free_irq(dev, irq); |
1da177e4 | 919 | if (warning) { |
1da177e4 LT |
920 | iounmap(base); |
921 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1ce03373 | 922 | "called without free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
923 | pci_name(dev)); |
924 | BUG_ON(warning > 0); | |
925 | } | |
926 | dev->irq = temp; /* Restore IOAPIC IRQ */ | |
927 | } | |
928 | } | |
929 | ||
309e57df MW |
930 | void pci_no_msi(void) |
931 | { | |
932 | pci_msi_enable = 0; | |
933 | } | |
934 | ||
1da177e4 LT |
935 | EXPORT_SYMBOL(pci_enable_msi); |
936 | EXPORT_SYMBOL(pci_disable_msi); | |
937 | EXPORT_SYMBOL(pci_enable_msix); | |
938 | EXPORT_SYMBOL(pci_disable_msix); |