Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
1da177e4 LT |
21 | |
22 | #include "pci.h" | |
23 | #include "msi.h" | |
24 | ||
1da177e4 | 25 | static int pci_msi_enable = 1; |
1da177e4 | 26 | |
6a9e7f20 AB |
27 | /* Arch hooks */ |
28 | ||
11df1f05 ME |
29 | #ifndef arch_msi_check_device |
30 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
31 | { |
32 | return 0; | |
33 | } | |
11df1f05 | 34 | #endif |
6a9e7f20 | 35 | |
11df1f05 ME |
36 | #ifndef arch_setup_msi_irqs |
37 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
38 | { |
39 | struct msi_desc *entry; | |
40 | int ret; | |
41 | ||
1c8d7b0a MW |
42 | /* |
43 | * If an architecture wants to support multiple MSI, it needs to | |
44 | * override arch_setup_msi_irqs() | |
45 | */ | |
46 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
47 | return 1; | |
48 | ||
6a9e7f20 AB |
49 | list_for_each_entry(entry, &dev->msi_list, list) { |
50 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 51 | if (ret < 0) |
6a9e7f20 | 52 | return ret; |
b5fbf533 ME |
53 | if (ret > 0) |
54 | return -ENOSPC; | |
6a9e7f20 AB |
55 | } |
56 | ||
57 | return 0; | |
58 | } | |
11df1f05 | 59 | #endif |
6a9e7f20 | 60 | |
11df1f05 ME |
61 | #ifndef arch_teardown_msi_irqs |
62 | void arch_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
63 | { |
64 | struct msi_desc *entry; | |
65 | ||
66 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
67 | int i, nvec; |
68 | if (entry->irq == 0) | |
69 | continue; | |
70 | nvec = 1 << entry->msi_attrib.multiple; | |
71 | for (i = 0; i < nvec; i++) | |
72 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
73 | } |
74 | } | |
11df1f05 | 75 | #endif |
6a9e7f20 | 76 | |
110828c9 | 77 | static void msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 78 | { |
b1cbf4e4 EB |
79 | u16 control; |
80 | ||
110828c9 | 81 | BUG_ON(!pos); |
b1cbf4e4 | 82 | |
110828c9 MW |
83 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
84 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
85 | if (enable) | |
86 | control |= PCI_MSI_FLAGS_ENABLE; | |
87 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
5ca5c02f HS |
88 | } |
89 | ||
b1cbf4e4 EB |
90 | static void msix_set_enable(struct pci_dev *dev, int enable) |
91 | { | |
92 | int pos; | |
93 | u16 control; | |
94 | ||
95 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
96 | if (pos) { | |
97 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
98 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
99 | if (enable) | |
100 | control |= PCI_MSIX_FLAGS_ENABLE; | |
101 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
102 | } | |
103 | } | |
104 | ||
bffac3c5 MW |
105 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
106 | { | |
0b49ec37 MW |
107 | /* Don't shift by >= width of type */ |
108 | if (x >= 5) | |
109 | return 0xffffffff; | |
110 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
111 | } |
112 | ||
f2440d9a | 113 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 114 | { |
f2440d9a MW |
115 | return msi_mask((control >> 1) & 7); |
116 | } | |
988cbb15 | 117 | |
f2440d9a MW |
118 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
119 | { | |
120 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
121 | } |
122 | ||
ce6fce42 MW |
123 | /* |
124 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
125 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
126 | * reliably as devices without an INTx disable bit will then generate a | |
127 | * level IRQ which will never be cleared. | |
ce6fce42 | 128 | */ |
12abb8ba | 129 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 130 | { |
f2440d9a | 131 | u32 mask_bits = desc->masked; |
1da177e4 | 132 | |
f2440d9a | 133 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 134 | return 0; |
f2440d9a MW |
135 | |
136 | mask_bits &= ~mask; | |
137 | mask_bits |= flag; | |
138 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
139 | |
140 | return mask_bits; | |
141 | } | |
142 | ||
143 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
144 | { | |
145 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
146 | } |
147 | ||
148 | /* | |
149 | * This internal function does not flush PCI writes to the device. | |
150 | * All users must ensure that they read from the device before either | |
151 | * assuming that the device state is up to date, or returning out of this | |
152 | * file. This saves a few milliseconds when initialising devices with lots | |
153 | * of MSI-X interrupts. | |
154 | */ | |
12abb8ba | 155 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
156 | { |
157 | u32 mask_bits = desc->masked; | |
158 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 159 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
f2440d9a MW |
160 | mask_bits &= ~1; |
161 | mask_bits |= flag; | |
162 | writel(mask_bits, desc->mask_base + offset); | |
12abb8ba HS |
163 | |
164 | return mask_bits; | |
165 | } | |
166 | ||
167 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
168 | { | |
169 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 170 | } |
24d27553 | 171 | |
f2440d9a MW |
172 | static void msi_set_mask_bit(unsigned irq, u32 flag) |
173 | { | |
174 | struct msi_desc *desc = get_irq_msi(irq); | |
24d27553 | 175 | |
f2440d9a MW |
176 | if (desc->msi_attrib.is_msix) { |
177 | msix_mask_irq(desc, flag); | |
178 | readl(desc->mask_base); /* Flush write to device */ | |
179 | } else { | |
1c8d7b0a MW |
180 | unsigned offset = irq - desc->dev->irq; |
181 | msi_mask_irq(desc, 1 << offset, flag << offset); | |
1da177e4 | 182 | } |
f2440d9a MW |
183 | } |
184 | ||
185 | void mask_msi_irq(unsigned int irq) | |
186 | { | |
187 | msi_set_mask_bit(irq, 1); | |
188 | } | |
189 | ||
190 | void unmask_msi_irq(unsigned int irq) | |
191 | { | |
192 | msi_set_mask_bit(irq, 0); | |
1da177e4 LT |
193 | } |
194 | ||
3145e941 | 195 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 196 | { |
3145e941 | 197 | struct msi_desc *entry = get_irq_desc_msi(desc); |
24d27553 MW |
198 | if (entry->msi_attrib.is_msix) { |
199 | void __iomem *base = entry->mask_base + | |
200 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
201 | ||
2c21fd4b HS |
202 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); |
203 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
204 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 205 | } else { |
0366f8f7 EB |
206 | struct pci_dev *dev = entry->dev; |
207 | int pos = entry->msi_attrib.pos; | |
208 | u16 data; | |
209 | ||
210 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
211 | &msg->address_lo); | |
212 | if (entry->msi_attrib.is_64) { | |
213 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
214 | &msg->address_hi); | |
215 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
216 | } else { | |
217 | msg->address_hi = 0; | |
cbf5d9e6 | 218 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
219 | } |
220 | msg->data = data; | |
0366f8f7 EB |
221 | } |
222 | } | |
1da177e4 | 223 | |
3145e941 | 224 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 225 | { |
3145e941 YL |
226 | struct irq_desc *desc = irq_to_desc(irq); |
227 | ||
228 | read_msi_msg_desc(desc, msg); | |
229 | } | |
230 | ||
231 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
232 | { | |
233 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
24d27553 MW |
234 | if (entry->msi_attrib.is_msix) { |
235 | void __iomem *base; | |
236 | base = entry->mask_base + | |
237 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
238 | ||
2c21fd4b HS |
239 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
240 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
241 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 242 | } else { |
0366f8f7 EB |
243 | struct pci_dev *dev = entry->dev; |
244 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
245 | u16 msgctl; |
246 | ||
247 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
248 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
249 | msgctl |= entry->msi_attrib.multiple << 4; | |
250 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
251 | |
252 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
253 | msg->address_lo); | |
254 | if (entry->msi_attrib.is_64) { | |
255 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
256 | msg->address_hi); | |
257 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
258 | msg->data); | |
259 | } else { | |
260 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
261 | msg->data); | |
262 | } | |
1da177e4 | 263 | } |
392ee1e6 | 264 | entry->msg = *msg; |
1da177e4 | 265 | } |
0366f8f7 | 266 | |
3145e941 YL |
267 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
268 | { | |
269 | struct irq_desc *desc = irq_to_desc(irq); | |
270 | ||
271 | write_msi_msg_desc(desc, msg); | |
272 | } | |
273 | ||
f56e4481 HS |
274 | static void free_msi_irqs(struct pci_dev *dev) |
275 | { | |
276 | struct msi_desc *entry, *tmp; | |
277 | ||
278 | list_for_each_entry(entry, &dev->msi_list, list) { | |
279 | int i, nvec; | |
280 | if (!entry->irq) | |
281 | continue; | |
282 | nvec = 1 << entry->msi_attrib.multiple; | |
283 | for (i = 0; i < nvec; i++) | |
284 | BUG_ON(irq_has_action(entry->irq + i)); | |
285 | } | |
286 | ||
287 | arch_teardown_msi_irqs(dev); | |
288 | ||
289 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
290 | if (entry->msi_attrib.is_msix) { | |
291 | if (list_is_last(&entry->list, &dev->msi_list)) | |
292 | iounmap(entry->mask_base); | |
293 | } | |
294 | list_del(&entry->list); | |
295 | kfree(entry); | |
296 | } | |
297 | } | |
c54c1879 | 298 | |
379f5327 | 299 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 300 | { |
379f5327 MW |
301 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
302 | if (!desc) | |
1da177e4 LT |
303 | return NULL; |
304 | ||
379f5327 MW |
305 | INIT_LIST_HEAD(&desc->list); |
306 | desc->dev = dev; | |
1da177e4 | 307 | |
379f5327 | 308 | return desc; |
1da177e4 LT |
309 | } |
310 | ||
ba698ad4 DM |
311 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
312 | { | |
313 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
314 | pci_intx(dev, enable); | |
315 | } | |
316 | ||
8fed4b65 | 317 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 318 | { |
392ee1e6 | 319 | int pos; |
41017f0c | 320 | u16 control; |
392ee1e6 | 321 | struct msi_desc *entry; |
41017f0c | 322 | |
b1cbf4e4 EB |
323 | if (!dev->msi_enabled) |
324 | return; | |
325 | ||
392ee1e6 EB |
326 | entry = get_irq_msi(dev->irq); |
327 | pos = entry->msi_attrib.pos; | |
41017f0c | 328 | |
ba698ad4 | 329 | pci_intx_for_msi(dev, 0); |
110828c9 | 330 | msi_set_enable(dev, pos, 0); |
392ee1e6 | 331 | write_msi_msg(dev->irq, &entry->msg); |
392ee1e6 EB |
332 | |
333 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 334 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 335 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 336 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 337 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
338 | } |
339 | ||
340 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 341 | { |
41017f0c | 342 | int pos; |
41017f0c | 343 | struct msi_desc *entry; |
392ee1e6 | 344 | u16 control; |
41017f0c | 345 | |
ded86d8d EB |
346 | if (!dev->msix_enabled) |
347 | return; | |
f598282f | 348 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 349 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f598282f MW |
350 | pos = entry->msi_attrib.pos; |
351 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
ded86d8d | 352 | |
41017f0c | 353 | /* route the table */ |
ba698ad4 | 354 | pci_intx_for_msi(dev, 0); |
f598282f MW |
355 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
356 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 357 | |
4aa9bc95 ME |
358 | list_for_each_entry(entry, &dev->msi_list, list) { |
359 | write_msi_msg(entry->irq, &entry->msg); | |
f2440d9a | 360 | msix_mask_irq(entry, entry->masked); |
41017f0c | 361 | } |
41017f0c | 362 | |
392ee1e6 | 363 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
392ee1e6 | 364 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
41017f0c | 365 | } |
8fed4b65 ME |
366 | |
367 | void pci_restore_msi_state(struct pci_dev *dev) | |
368 | { | |
369 | __pci_restore_msi_state(dev); | |
370 | __pci_restore_msix_state(dev); | |
371 | } | |
94688cf2 | 372 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 373 | |
1da177e4 LT |
374 | /** |
375 | * msi_capability_init - configure device's MSI capability structure | |
376 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 377 | * @nvec: number of interrupts to allocate |
1da177e4 | 378 | * |
1c8d7b0a MW |
379 | * Setup the MSI capability structure of the device with the requested |
380 | * number of interrupts. A return value of zero indicates the successful | |
381 | * setup of an entry with the new MSI irq. A negative return value indicates | |
382 | * an error, and a positive return value indicates the number of interrupts | |
383 | * which could have been allocated. | |
384 | */ | |
385 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
386 | { |
387 | struct msi_desc *entry; | |
7fe3730d | 388 | int pos, ret; |
1da177e4 | 389 | u16 control; |
f2440d9a | 390 | unsigned mask; |
1da177e4 | 391 | |
500559a9 | 392 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
110828c9 MW |
393 | msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ |
394 | ||
1da177e4 LT |
395 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
396 | /* MSI Entry Initialization */ | |
379f5327 | 397 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
398 | if (!entry) |
399 | return -ENOMEM; | |
1ce03373 | 400 | |
500559a9 HS |
401 | entry->msi_attrib.is_msix = 0; |
402 | entry->msi_attrib.is_64 = is_64bit_address(control); | |
403 | entry->msi_attrib.entry_nr = 0; | |
404 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
405 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
406 | entry->msi_attrib.pos = pos; | |
f2440d9a | 407 | |
67b5db65 | 408 | entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); |
f2440d9a MW |
409 | /* All MSIs are unmasked by default, Mask them all */ |
410 | if (entry->msi_attrib.maskbit) | |
411 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
412 | mask = msi_capable_mask(control); | |
413 | msi_mask_irq(entry, mask, mask); | |
414 | ||
0dd11f9b | 415 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 416 | |
1da177e4 | 417 | /* Configure MSI capability structure */ |
1c8d7b0a | 418 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 419 | if (ret) { |
7ba1930d | 420 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 421 | free_msi_irqs(dev); |
7fe3730d | 422 | return ret; |
fd58e55f | 423 | } |
f7feaca7 | 424 | |
1da177e4 | 425 | /* Set MSI enabled bits */ |
ba698ad4 | 426 | pci_intx_for_msi(dev, 0); |
110828c9 | 427 | msi_set_enable(dev, pos, 1); |
b1cbf4e4 | 428 | dev->msi_enabled = 1; |
1da177e4 | 429 | |
7fe3730d | 430 | dev->irq = entry->irq; |
1da177e4 LT |
431 | return 0; |
432 | } | |
433 | ||
5a05a9d8 HS |
434 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos, |
435 | unsigned nr_entries) | |
436 | { | |
437 | unsigned long phys_addr; | |
438 | u32 table_offset; | |
439 | u8 bir; | |
440 | ||
441 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
442 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
443 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; | |
444 | phys_addr = pci_resource_start(dev, bir) + table_offset; | |
445 | ||
446 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
447 | } | |
448 | ||
d9d7070e HS |
449 | static int msix_setup_entries(struct pci_dev *dev, unsigned pos, |
450 | void __iomem *base, struct msix_entry *entries, | |
451 | int nvec) | |
452 | { | |
453 | struct msi_desc *entry; | |
454 | int i; | |
455 | ||
456 | for (i = 0; i < nvec; i++) { | |
457 | entry = alloc_msi_entry(dev); | |
458 | if (!entry) { | |
459 | if (!i) | |
460 | iounmap(base); | |
461 | else | |
462 | free_msi_irqs(dev); | |
463 | /* No enough memory. Don't try again */ | |
464 | return -ENOMEM; | |
465 | } | |
466 | ||
467 | entry->msi_attrib.is_msix = 1; | |
468 | entry->msi_attrib.is_64 = 1; | |
469 | entry->msi_attrib.entry_nr = entries[i].entry; | |
470 | entry->msi_attrib.default_irq = dev->irq; | |
471 | entry->msi_attrib.pos = pos; | |
472 | entry->mask_base = base; | |
473 | ||
474 | list_add_tail(&entry->list, &dev->msi_list); | |
475 | } | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
75cb3426 HS |
480 | static void msix_program_entries(struct pci_dev *dev, |
481 | struct msix_entry *entries) | |
482 | { | |
483 | struct msi_desc *entry; | |
484 | int i = 0; | |
485 | ||
486 | list_for_each_entry(entry, &dev->msi_list, list) { | |
487 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
488 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
489 | ||
490 | entries[i].vector = entry->irq; | |
491 | set_irq_msi(entry->irq, entry); | |
492 | entry->masked = readl(entry->mask_base + offset); | |
493 | msix_mask_irq(entry, 1); | |
494 | i++; | |
495 | } | |
496 | } | |
497 | ||
1da177e4 LT |
498 | /** |
499 | * msix_capability_init - configure device's MSI-X capability | |
500 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
501 | * @entries: pointer to an array of struct msix_entry entries |
502 | * @nvec: number of @entries | |
1da177e4 | 503 | * |
eaae4b3a | 504 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
505 | * single MSI-X irq. A return of zero indicates the successful setup of |
506 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
507 | **/ |
508 | static int msix_capability_init(struct pci_dev *dev, | |
509 | struct msix_entry *entries, int nvec) | |
510 | { | |
d9d7070e | 511 | int pos, ret; |
5a05a9d8 | 512 | u16 control; |
1da177e4 LT |
513 | void __iomem *base; |
514 | ||
500559a9 | 515 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
f598282f MW |
516 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
517 | ||
518 | /* Ensure MSI-X is disabled while it is set up */ | |
519 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
520 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
521 | ||
1da177e4 | 522 | /* Request & Map MSI-X table region */ |
5a05a9d8 HS |
523 | base = msix_map_region(dev, pos, multi_msix_capable(control)); |
524 | if (!base) | |
1da177e4 LT |
525 | return -ENOMEM; |
526 | ||
d9d7070e HS |
527 | ret = msix_setup_entries(dev, pos, base, entries, nvec); |
528 | if (ret) | |
529 | return ret; | |
9c831334 ME |
530 | |
531 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
532 | if (ret) |
533 | goto error; | |
9c831334 | 534 | |
f598282f MW |
535 | /* |
536 | * Some devices require MSI-X to be enabled before we can touch the | |
537 | * MSI-X registers. We need to mask all the vectors to prevent | |
538 | * interrupts coming in before they're fully set up. | |
539 | */ | |
540 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
541 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
542 | ||
75cb3426 | 543 | msix_program_entries(dev, entries); |
f598282f MW |
544 | |
545 | /* Set MSI-X enabled bits and unmask the function */ | |
ba698ad4 | 546 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 547 | dev->msix_enabled = 1; |
1da177e4 | 548 | |
f598282f MW |
549 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
550 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
8d181018 | 551 | |
1da177e4 | 552 | return 0; |
583871d4 HS |
553 | |
554 | error: | |
555 | if (ret < 0) { | |
556 | /* | |
557 | * If we had some success, report the number of irqs | |
558 | * we succeeded in setting up. | |
559 | */ | |
d9d7070e | 560 | struct msi_desc *entry; |
583871d4 HS |
561 | int avail = 0; |
562 | ||
563 | list_for_each_entry(entry, &dev->msi_list, list) { | |
564 | if (entry->irq != 0) | |
565 | avail++; | |
566 | } | |
567 | if (avail != 0) | |
568 | ret = avail; | |
569 | } | |
570 | ||
571 | free_msi_irqs(dev); | |
572 | ||
573 | return ret; | |
1da177e4 LT |
574 | } |
575 | ||
24334a12 | 576 | /** |
17bbc12a | 577 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 578 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 579 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 580 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 581 | * |
0306ebfa | 582 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
583 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
584 | * supported return 0, else return an error code. | |
24334a12 | 585 | **/ |
500559a9 | 586 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
587 | { |
588 | struct pci_bus *bus; | |
c9953a73 | 589 | int ret; |
24334a12 | 590 | |
0306ebfa | 591 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
592 | if (!pci_msi_enable || !dev || dev->no_msi) |
593 | return -EINVAL; | |
594 | ||
314e77b3 ME |
595 | /* |
596 | * You can't ask to have 0 or less MSIs configured. | |
597 | * a) it's stupid .. | |
598 | * b) the list manipulation code assumes nvec >= 1. | |
599 | */ | |
600 | if (nvec < 1) | |
601 | return -ERANGE; | |
602 | ||
500559a9 HS |
603 | /* |
604 | * Any bridge which does NOT route MSI transactions from its | |
605 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
606 | * the secondary pci_bus. |
607 | * We expect only arch-specific PCI host bus controller driver | |
608 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
609 | */ | |
24334a12 BG |
610 | for (bus = dev->bus; bus; bus = bus->parent) |
611 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
612 | return -EINVAL; | |
613 | ||
c9953a73 ME |
614 | ret = arch_msi_check_device(dev, nvec, type); |
615 | if (ret) | |
616 | return ret; | |
617 | ||
b1e2303d ME |
618 | if (!pci_find_capability(dev, type)) |
619 | return -EINVAL; | |
620 | ||
24334a12 BG |
621 | return 0; |
622 | } | |
623 | ||
1da177e4 | 624 | /** |
1c8d7b0a MW |
625 | * pci_enable_msi_block - configure device's MSI capability structure |
626 | * @dev: device to configure | |
627 | * @nvec: number of interrupts to configure | |
1da177e4 | 628 | * |
1c8d7b0a MW |
629 | * Allocate IRQs for a device with the MSI capability. |
630 | * This function returns a negative errno if an error occurs. If it | |
631 | * is unable to allocate the number of interrupts requested, it returns | |
632 | * the number of interrupts it might be able to allocate. If it successfully | |
633 | * allocates at least the number of interrupts requested, it returns 0 and | |
634 | * updates the @dev's irq member to the lowest new interrupt number; the | |
635 | * other interrupt numbers allocated to this device are consecutive. | |
636 | */ | |
637 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 638 | { |
1c8d7b0a MW |
639 | int status, pos, maxvec; |
640 | u16 msgctl; | |
641 | ||
642 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
643 | if (!pos) | |
644 | return -EINVAL; | |
645 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
646 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
647 | if (nvec > maxvec) | |
648 | return maxvec; | |
1da177e4 | 649 | |
1c8d7b0a | 650 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
651 | if (status) |
652 | return status; | |
1da177e4 | 653 | |
ded86d8d | 654 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 655 | |
1c8d7b0a | 656 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 657 | if (dev->msix_enabled) { |
80ccba11 BH |
658 | dev_info(&dev->dev, "can't enable MSI " |
659 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 660 | return -EINVAL; |
1da177e4 | 661 | } |
1c8d7b0a MW |
662 | |
663 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
664 | return status; |
665 | } | |
1c8d7b0a | 666 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 667 | |
f2440d9a | 668 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 669 | { |
f2440d9a MW |
670 | struct msi_desc *desc; |
671 | u32 mask; | |
672 | u16 ctrl; | |
110828c9 | 673 | unsigned pos; |
1da177e4 | 674 | |
128bc5fc | 675 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
676 | return; |
677 | ||
110828c9 MW |
678 | BUG_ON(list_empty(&dev->msi_list)); |
679 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
680 | pos = desc->msi_attrib.pos; | |
681 | ||
682 | msi_set_enable(dev, pos, 0); | |
ba698ad4 | 683 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 684 | dev->msi_enabled = 0; |
7bd007e4 | 685 | |
12abb8ba | 686 | /* Return the device with MSI unmasked as initial states */ |
110828c9 | 687 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 688 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
689 | /* Keep cached state to be restored */ |
690 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
691 | |
692 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 693 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 694 | } |
24d27553 | 695 | |
500559a9 | 696 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 697 | { |
d52877c7 YL |
698 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
699 | return; | |
700 | ||
701 | pci_msi_shutdown(dev); | |
f56e4481 | 702 | free_msi_irqs(dev); |
1da177e4 | 703 | } |
4cc086fa | 704 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 705 | |
a52e2e35 RW |
706 | /** |
707 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
708 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
709 | */ | |
710 | int pci_msix_table_size(struct pci_dev *dev) | |
711 | { | |
712 | int pos; | |
713 | u16 control; | |
714 | ||
715 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
716 | if (!pos) | |
717 | return 0; | |
718 | ||
719 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
720 | return multi_msix_capable(control); | |
721 | } | |
722 | ||
1da177e4 LT |
723 | /** |
724 | * pci_enable_msix - configure device's MSI-X capability structure | |
725 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 726 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 727 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
728 | * |
729 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 730 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
731 | * MSI-X mode enabled on its hardware device function. A return of zero |
732 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 733 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 734 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
735 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
736 | * re-send its request. | |
1da177e4 | 737 | **/ |
500559a9 | 738 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 739 | { |
a52e2e35 | 740 | int status, nr_entries; |
ded86d8d | 741 | int i, j; |
1da177e4 | 742 | |
c9953a73 | 743 | if (!entries) |
500559a9 | 744 | return -EINVAL; |
1da177e4 | 745 | |
c9953a73 ME |
746 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
747 | if (status) | |
748 | return status; | |
749 | ||
a52e2e35 | 750 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 751 | if (nvec > nr_entries) |
57fbf52c | 752 | return nr_entries; |
1da177e4 LT |
753 | |
754 | /* Check for any invalid entries */ | |
755 | for (i = 0; i < nvec; i++) { | |
756 | if (entries[i].entry >= nr_entries) | |
757 | return -EINVAL; /* invalid entry */ | |
758 | for (j = i + 1; j < nvec; j++) { | |
759 | if (entries[i].entry == entries[j].entry) | |
760 | return -EINVAL; /* duplicate entry */ | |
761 | } | |
762 | } | |
ded86d8d | 763 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 764 | |
1ce03373 | 765 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 766 | if (dev->msi_enabled) { |
80ccba11 BH |
767 | dev_info(&dev->dev, "can't enable MSI-X " |
768 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
769 | return -EINVAL; |
770 | } | |
1da177e4 | 771 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
772 | return status; |
773 | } | |
4cc086fa | 774 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 775 | |
500559a9 | 776 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 777 | { |
12abb8ba HS |
778 | struct msi_desc *entry; |
779 | ||
128bc5fc | 780 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
781 | return; |
782 | ||
12abb8ba HS |
783 | /* Return the device with MSI-X masked as initial states */ |
784 | list_for_each_entry(entry, &dev->msi_list, list) { | |
785 | /* Keep cached states to be restored */ | |
786 | __msix_mask_irq(entry, 1); | |
787 | } | |
788 | ||
b1cbf4e4 | 789 | msix_set_enable(dev, 0); |
ba698ad4 | 790 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 791 | dev->msix_enabled = 0; |
d52877c7 | 792 | } |
c901851f | 793 | |
500559a9 | 794 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
795 | { |
796 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
797 | return; | |
798 | ||
799 | pci_msix_shutdown(dev); | |
f56e4481 | 800 | free_msi_irqs(dev); |
1da177e4 | 801 | } |
4cc086fa | 802 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
803 | |
804 | /** | |
1ce03373 | 805 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
806 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
807 | * | |
eaae4b3a | 808 | * Being called during hotplug remove, from which the device function |
1ce03373 | 809 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
810 | * allocated for this device function, are reclaimed to unused state, |
811 | * which may be used later on. | |
812 | **/ | |
500559a9 | 813 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 814 | { |
1da177e4 | 815 | if (!pci_msi_enable || !dev) |
500559a9 | 816 | return; |
1da177e4 | 817 | |
f56e4481 HS |
818 | if (dev->msi_enabled || dev->msix_enabled) |
819 | free_msi_irqs(dev); | |
1da177e4 LT |
820 | } |
821 | ||
309e57df MW |
822 | void pci_no_msi(void) |
823 | { | |
824 | pci_msi_enable = 0; | |
825 | } | |
c9953a73 | 826 | |
07ae95f9 AP |
827 | /** |
828 | * pci_msi_enabled - is MSI enabled? | |
829 | * | |
830 | * Returns true if MSI has not been disabled by the command-line option | |
831 | * pci=nomsi. | |
832 | **/ | |
833 | int pci_msi_enabled(void) | |
d389fec6 | 834 | { |
07ae95f9 | 835 | return pci_msi_enable; |
d389fec6 | 836 | } |
07ae95f9 | 837 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 838 | |
07ae95f9 | 839 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 840 | { |
07ae95f9 | 841 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 842 | } |