Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI Message Signaled Interrupt (MSI) |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
aff17164 | 7 | * Copyright (C) 2016 Christoph Hellwig. |
1da177e4 LT |
8 | */ |
9 | ||
1ce03373 | 10 | #include <linux/err.h> |
1da177e4 LT |
11 | #include <linux/mm.h> |
12 | #include <linux/irq.h> | |
13 | #include <linux/interrupt.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
be2021ba | 22 | #include <linux/acpi_iort.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
3878eaef | 24 | #include <linux/irqdomain.h> |
b6eec9b7 | 25 | #include <linux/of_irq.h> |
1da177e4 LT |
26 | |
27 | #include "pci.h" | |
1da177e4 | 28 | |
1da177e4 | 29 | static int pci_msi_enable = 1; |
38737d82 | 30 | int pci_msi_ignore_mask; |
1da177e4 | 31 | |
527eee29 BH |
32 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
33 | ||
8e047ada | 34 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
8e047ada JL |
35 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
36 | { | |
37 | struct irq_domain *domain; | |
38 | ||
47feb418 | 39 | domain = dev_get_msi_domain(&dev->dev); |
3845d295 | 40 | if (domain && irq_domain_is_hierarchy(domain)) |
699c4cec | 41 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); |
8e047ada JL |
42 | |
43 | return arch_setup_msi_irqs(dev, nvec, type); | |
44 | } | |
45 | ||
46 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) | |
47 | { | |
48 | struct irq_domain *domain; | |
49 | ||
47feb418 | 50 | domain = dev_get_msi_domain(&dev->dev); |
3845d295 | 51 | if (domain && irq_domain_is_hierarchy(domain)) |
699c4cec | 52 | msi_domain_free_irqs(domain, &dev->dev); |
8e047ada JL |
53 | else |
54 | arch_teardown_msi_irqs(dev); | |
55 | } | |
56 | #else | |
57 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs | |
58 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs | |
59 | #endif | |
527eee29 | 60 | |
6a9e7f20 AB |
61 | /* Arch hooks */ |
62 | ||
4287d824 TP |
63 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
64 | { | |
2291ec09 | 65 | struct msi_controller *chip = dev->bus->msi; |
0cbdcfcf TR |
66 | int err; |
67 | ||
68 | if (!chip || !chip->setup_irq) | |
69 | return -EINVAL; | |
70 | ||
71 | err = chip->setup_irq(chip, dev, desc); | |
72 | if (err < 0) | |
73 | return err; | |
74 | ||
75 | irq_set_chip_data(desc->irq, chip); | |
76 | ||
77 | return 0; | |
4287d824 TP |
78 | } |
79 | ||
80 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 81 | { |
c2791b80 | 82 | struct msi_controller *chip = irq_get_chip_data(irq); |
0cbdcfcf TR |
83 | |
84 | if (!chip || !chip->teardown_irq) | |
85 | return; | |
86 | ||
87 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
88 | } |
89 | ||
4287d824 | 90 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 | 91 | { |
339e5b44 | 92 | struct msi_controller *chip = dev->bus->msi; |
6a9e7f20 AB |
93 | struct msi_desc *entry; |
94 | int ret; | |
95 | ||
339e5b44 LS |
96 | if (chip && chip->setup_irqs) |
97 | return chip->setup_irqs(chip, dev, nvec, type); | |
1c8d7b0a MW |
98 | /* |
99 | * If an architecture wants to support multiple MSI, it needs to | |
100 | * override arch_setup_msi_irqs() | |
101 | */ | |
102 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
103 | return 1; | |
104 | ||
5004e98a | 105 | for_each_pci_msi_entry(entry, dev) { |
6a9e7f20 | 106 | ret = arch_setup_msi_irq(dev, entry); |
b5fbf533 | 107 | if (ret < 0) |
6a9e7f20 | 108 | return ret; |
b5fbf533 ME |
109 | if (ret > 0) |
110 | return -ENOSPC; | |
6a9e7f20 AB |
111 | } |
112 | ||
113 | return 0; | |
114 | } | |
1525bf0d | 115 | |
4287d824 TP |
116 | /* |
117 | * We have a default implementation available as a separate non-weak | |
118 | * function, as it is used by the Xen x86 PCI code | |
119 | */ | |
1525bf0d | 120 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 121 | { |
63a7b17e | 122 | int i; |
6a9e7f20 AB |
123 | struct msi_desc *entry; |
124 | ||
5004e98a | 125 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
126 | if (entry->irq) |
127 | for (i = 0; i < entry->nvec_used; i++) | |
128 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
129 | } |
130 | ||
4287d824 TP |
131 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
132 | { | |
133 | return default_teardown_msi_irqs(dev); | |
134 | } | |
76ccc297 | 135 | |
ac8344c4 | 136 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
137 | { |
138 | struct msi_desc *entry; | |
139 | ||
140 | entry = NULL; | |
141 | if (dev->msix_enabled) { | |
5004e98a | 142 | for_each_pci_msi_entry(entry, dev) { |
76ccc297 KRW |
143 | if (irq == entry->irq) |
144 | break; | |
145 | } | |
146 | } else if (dev->msi_enabled) { | |
147 | entry = irq_get_msi_desc(irq); | |
148 | } | |
149 | ||
150 | if (entry) | |
83a18912 | 151 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 152 | } |
4287d824 | 153 | |
ac8344c4 | 154 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 155 | { |
ac8344c4 | 156 | return default_restore_msi_irqs(dev); |
4287d824 | 157 | } |
76ccc297 | 158 | |
bffac3c5 MW |
159 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
160 | { | |
0b49ec37 MW |
161 | /* Don't shift by >= width of type */ |
162 | if (x >= 5) | |
163 | return 0xffffffff; | |
164 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
165 | } |
166 | ||
ce6fce42 MW |
167 | /* |
168 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
169 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
170 | * reliably as devices without an INTx disable bit will then generate a | |
171 | * level IRQ which will never be cleared. | |
ce6fce42 | 172 | */ |
23ed8d57 | 173 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 174 | { |
f2440d9a | 175 | u32 mask_bits = desc->masked; |
1da177e4 | 176 | |
38737d82 | 177 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 178 | return 0; |
f2440d9a MW |
179 | |
180 | mask_bits &= ~mask; | |
181 | mask_bits |= flag; | |
e39758e0 JL |
182 | pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, |
183 | mask_bits); | |
12abb8ba HS |
184 | |
185 | return mask_bits; | |
186 | } | |
187 | ||
188 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
189 | { | |
23ed8d57 | 190 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
f2440d9a MW |
191 | } |
192 | ||
5eb6d660 CH |
193 | static void __iomem *pci_msix_desc_addr(struct msi_desc *desc) |
194 | { | |
195 | return desc->mask_base + | |
196 | desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
197 | } | |
198 | ||
f2440d9a MW |
199 | /* |
200 | * This internal function does not flush PCI writes to the device. | |
201 | * All users must ensure that they read from the device before either | |
202 | * assuming that the device state is up to date, or returning out of this | |
203 | * file. This saves a few milliseconds when initialising devices with lots | |
204 | * of MSI-X interrupts. | |
205 | */ | |
23ed8d57 | 206 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
207 | { |
208 | u32 mask_bits = desc->masked; | |
38737d82 YW |
209 | |
210 | if (pci_msi_ignore_mask) | |
211 | return 0; | |
212 | ||
8d805286 SY |
213 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
214 | if (flag) | |
215 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
5eb6d660 | 216 | writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL); |
12abb8ba HS |
217 | |
218 | return mask_bits; | |
219 | } | |
220 | ||
221 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
222 | { | |
23ed8d57 | 223 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
f2440d9a | 224 | } |
24d27553 | 225 | |
1c9db525 | 226 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 227 | { |
c391f262 | 228 | struct msi_desc *desc = irq_data_get_msi_desc(data); |
24d27553 | 229 | |
f2440d9a MW |
230 | if (desc->msi_attrib.is_msix) { |
231 | msix_mask_irq(desc, flag); | |
232 | readl(desc->mask_base); /* Flush write to device */ | |
233 | } else { | |
a281b788 | 234 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 235 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 236 | } |
f2440d9a MW |
237 | } |
238 | ||
23ed8d57 TG |
239 | /** |
240 | * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts | |
241 | * @data: pointer to irqdata associated to that interrupt | |
242 | */ | |
243 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 244 | { |
1c9db525 | 245 | msi_set_mask_bit(data, 1); |
f2440d9a | 246 | } |
a4289dc2 | 247 | EXPORT_SYMBOL_GPL(pci_msi_mask_irq); |
f2440d9a | 248 | |
23ed8d57 TG |
249 | /** |
250 | * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts | |
251 | * @data: pointer to irqdata associated to that interrupt | |
252 | */ | |
253 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 254 | { |
1c9db525 | 255 | msi_set_mask_bit(data, 0); |
1da177e4 | 256 | } |
a4289dc2 | 257 | EXPORT_SYMBOL_GPL(pci_msi_unmask_irq); |
1da177e4 | 258 | |
ac8344c4 D |
259 | void default_restore_msi_irqs(struct pci_dev *dev) |
260 | { | |
261 | struct msi_desc *entry; | |
262 | ||
5004e98a | 263 | for_each_pci_msi_entry(entry, dev) |
ac8344c4 | 264 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
265 | } |
266 | ||
891d4a48 | 267 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 268 | { |
e39758e0 JL |
269 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
270 | ||
271 | BUG_ON(dev->current_state != PCI_D0); | |
30da5524 BH |
272 | |
273 | if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 274 | void __iomem *base = pci_msix_desc_addr(entry); |
30da5524 BH |
275 | |
276 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
277 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
278 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
279 | } else { | |
f5322169 | 280 | int pos = dev->msi_cap; |
30da5524 BH |
281 | u16 data; |
282 | ||
9925ad0c BH |
283 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
284 | &msg->address_lo); | |
30da5524 | 285 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
286 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
287 | &msg->address_hi); | |
2f221349 | 288 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
289 | } else { |
290 | msg->address_hi = 0; | |
2f221349 | 291 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
292 | } |
293 | msg->data = data; | |
294 | } | |
295 | } | |
296 | ||
83a18912 | 297 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 298 | { |
e39758e0 JL |
299 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
300 | ||
0170591b | 301 | if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) { |
fcd097f3 BH |
302 | /* Don't touch the hardware now */ |
303 | } else if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 304 | void __iomem *base = pci_msix_desc_addr(entry); |
24d27553 | 305 | |
2c21fd4b HS |
306 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
307 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
308 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 309 | } else { |
f5322169 | 310 | int pos = dev->msi_cap; |
1c8d7b0a MW |
311 | u16 msgctl; |
312 | ||
f84ecd28 | 313 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
314 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
315 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 316 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 317 | |
9925ad0c BH |
318 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
319 | msg->address_lo); | |
0366f8f7 | 320 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
321 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
322 | msg->address_hi); | |
2f221349 BH |
323 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
324 | msg->data); | |
0366f8f7 | 325 | } else { |
2f221349 BH |
326 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
327 | msg->data); | |
0366f8f7 | 328 | } |
1da177e4 | 329 | } |
392ee1e6 | 330 | entry->msg = *msg; |
1da177e4 | 331 | } |
0366f8f7 | 332 | |
83a18912 | 333 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 334 | { |
dced35ae | 335 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 336 | |
83a18912 | 337 | __pci_write_msi_msg(entry, msg); |
3145e941 | 338 | } |
83a18912 | 339 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 340 | |
f56e4481 HS |
341 | static void free_msi_irqs(struct pci_dev *dev) |
342 | { | |
5004e98a | 343 | struct list_head *msi_list = dev_to_msi_list(&dev->dev); |
f56e4481 | 344 | struct msi_desc *entry, *tmp; |
1c51b50c GKH |
345 | struct attribute **msi_attrs; |
346 | struct device_attribute *dev_attr; | |
63a7b17e | 347 | int i, count = 0; |
f56e4481 | 348 | |
5004e98a | 349 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
350 | if (entry->irq) |
351 | for (i = 0; i < entry->nvec_used; i++) | |
352 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 | 353 | |
8e047ada | 354 | pci_msi_teardown_msi_irqs(dev); |
f56e4481 | 355 | |
5004e98a | 356 | list_for_each_entry_safe(entry, tmp, msi_list, list) { |
f56e4481 | 357 | if (entry->msi_attrib.is_msix) { |
5004e98a | 358 | if (list_is_last(&entry->list, msi_list)) |
f56e4481 HS |
359 | iounmap(entry->mask_base); |
360 | } | |
424eb391 | 361 | |
f56e4481 | 362 | list_del(&entry->list); |
81efbadd | 363 | free_msi_entry(entry); |
f56e4481 | 364 | } |
1c51b50c GKH |
365 | |
366 | if (dev->msi_irq_groups) { | |
367 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
368 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 369 | while (msi_attrs[count]) { |
1c51b50c GKH |
370 | dev_attr = container_of(msi_attrs[count], |
371 | struct device_attribute, attr); | |
372 | kfree(dev_attr->attr.name); | |
373 | kfree(dev_attr); | |
374 | ++count; | |
375 | } | |
376 | kfree(msi_attrs); | |
377 | kfree(dev->msi_irq_groups[0]); | |
378 | kfree(dev->msi_irq_groups); | |
379 | dev->msi_irq_groups = NULL; | |
380 | } | |
f56e4481 | 381 | } |
c54c1879 | 382 | |
ba698ad4 DM |
383 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
384 | { | |
385 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
386 | pci_intx(dev, enable); | |
387 | } | |
388 | ||
8fed4b65 | 389 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 390 | { |
41017f0c | 391 | u16 control; |
392ee1e6 | 392 | struct msi_desc *entry; |
41017f0c | 393 | |
b1cbf4e4 EB |
394 | if (!dev->msi_enabled) |
395 | return; | |
396 | ||
dced35ae | 397 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 398 | |
ba698ad4 | 399 | pci_intx_for_msi(dev, 0); |
61b64abd | 400 | pci_msi_set_enable(dev, 0); |
ac8344c4 | 401 | arch_restore_msi_irqs(dev); |
392ee1e6 | 402 | |
f5322169 | 403 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
404 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
405 | entry->masked); | |
abad2ec9 | 406 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 407 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 408 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
409 | } |
410 | ||
411 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 412 | { |
41017f0c | 413 | struct msi_desc *entry; |
41017f0c | 414 | |
ded86d8d EB |
415 | if (!dev->msix_enabled) |
416 | return; | |
5004e98a | 417 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
ded86d8d | 418 | |
41017f0c | 419 | /* route the table */ |
ba698ad4 | 420 | pci_intx_for_msi(dev, 0); |
61b64abd | 421 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 422 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
41017f0c | 423 | |
ac8344c4 | 424 | arch_restore_msi_irqs(dev); |
5004e98a | 425 | for_each_pci_msi_entry(entry, dev) |
f2440d9a | 426 | msix_mask_irq(entry, entry->masked); |
41017f0c | 427 | |
61b64abd | 428 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 429 | } |
8fed4b65 ME |
430 | |
431 | void pci_restore_msi_state(struct pci_dev *dev) | |
432 | { | |
433 | __pci_restore_msi_state(dev); | |
434 | __pci_restore_msix_state(dev); | |
435 | } | |
94688cf2 | 436 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 437 | |
1c51b50c | 438 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
439 | char *buf) |
440 | { | |
1c51b50c GKH |
441 | struct msi_desc *entry; |
442 | unsigned long irq; | |
443 | int retval; | |
da8d1c8b | 444 | |
1c51b50c GKH |
445 | retval = kstrtoul(attr->attr.name, 10, &irq); |
446 | if (retval) | |
447 | return retval; | |
da8d1c8b | 448 | |
e11ece5a YW |
449 | entry = irq_get_msi_desc(irq); |
450 | if (entry) | |
451 | return sprintf(buf, "%s\n", | |
452 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
453 | ||
1c51b50c | 454 | return -ENODEV; |
da8d1c8b NH |
455 | } |
456 | ||
da8d1c8b NH |
457 | static int populate_msi_sysfs(struct pci_dev *pdev) |
458 | { | |
1c51b50c GKH |
459 | struct attribute **msi_attrs; |
460 | struct attribute *msi_attr; | |
461 | struct device_attribute *msi_dev_attr; | |
462 | struct attribute_group *msi_irq_group; | |
463 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 464 | struct msi_desc *entry; |
1c51b50c GKH |
465 | int ret = -ENOMEM; |
466 | int num_msi = 0; | |
da8d1c8b | 467 | int count = 0; |
a8676066 | 468 | int i; |
da8d1c8b | 469 | |
1c51b50c | 470 | /* Determine how many msi entries we have */ |
5004e98a | 471 | for_each_pci_msi_entry(entry, pdev) |
a8676066 | 472 | num_msi += entry->nvec_used; |
1c51b50c GKH |
473 | if (!num_msi) |
474 | return 0; | |
da8d1c8b | 475 | |
1c51b50c | 476 | /* Dynamically create the MSI attributes for the PCI device */ |
6396bb22 | 477 | msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL); |
1c51b50c GKH |
478 | if (!msi_attrs) |
479 | return -ENOMEM; | |
5004e98a | 480 | for_each_pci_msi_entry(entry, pdev) { |
a8676066 RB |
481 | for (i = 0; i < entry->nvec_used; i++) { |
482 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); | |
483 | if (!msi_dev_attr) | |
484 | goto error_attrs; | |
485 | msi_attrs[count] = &msi_dev_attr->attr; | |
486 | ||
487 | sysfs_attr_init(&msi_dev_attr->attr); | |
488 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", | |
489 | entry->irq + i); | |
490 | if (!msi_dev_attr->attr.name) | |
491 | goto error_attrs; | |
492 | msi_dev_attr->attr.mode = S_IRUGO; | |
493 | msi_dev_attr->show = msi_mode_show; | |
494 | ++count; | |
495 | } | |
da8d1c8b NH |
496 | } |
497 | ||
1c51b50c GKH |
498 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
499 | if (!msi_irq_group) | |
500 | goto error_attrs; | |
501 | msi_irq_group->name = "msi_irqs"; | |
502 | msi_irq_group->attrs = msi_attrs; | |
503 | ||
6396bb22 | 504 | msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL); |
1c51b50c GKH |
505 | if (!msi_irq_groups) |
506 | goto error_irq_group; | |
507 | msi_irq_groups[0] = msi_irq_group; | |
508 | ||
509 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
510 | if (ret) | |
511 | goto error_irq_groups; | |
512 | pdev->msi_irq_groups = msi_irq_groups; | |
513 | ||
da8d1c8b NH |
514 | return 0; |
515 | ||
1c51b50c GKH |
516 | error_irq_groups: |
517 | kfree(msi_irq_groups); | |
518 | error_irq_group: | |
519 | kfree(msi_irq_group); | |
520 | error_attrs: | |
521 | count = 0; | |
522 | msi_attr = msi_attrs[count]; | |
523 | while (msi_attr) { | |
524 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
525 | kfree(msi_attr->name); | |
526 | kfree(msi_dev_attr); | |
527 | ++count; | |
528 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 529 | } |
29237756 | 530 | kfree(msi_attrs); |
da8d1c8b NH |
531 | return ret; |
532 | } | |
533 | ||
e75eafb9 | 534 | static struct msi_desc * |
c66d4bd1 | 535 | msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd) |
d873b4d4 | 536 | { |
bec04037 | 537 | struct irq_affinity_desc *masks = NULL; |
d873b4d4 | 538 | struct msi_desc *entry; |
e75eafb9 TG |
539 | u16 control; |
540 | ||
8e1101d2 | 541 | if (affd) |
61e1c590 | 542 | masks = irq_create_affinity_masks(nvec, affd); |
8e1101d2 | 543 | |
d873b4d4 | 544 | /* MSI Entry Initialization */ |
e75eafb9 | 545 | entry = alloc_msi_entry(&dev->dev, nvec, masks); |
d873b4d4 | 546 | if (!entry) |
e75eafb9 | 547 | goto out; |
d873b4d4 YW |
548 | |
549 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
550 | ||
551 | entry->msi_attrib.is_msix = 0; | |
552 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
553 | entry->msi_attrib.entry_nr = 0; | |
554 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
555 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 556 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e | 557 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
d873b4d4 YW |
558 | |
559 | if (control & PCI_MSI_FLAGS_64BIT) | |
560 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
561 | else | |
562 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
563 | ||
564 | /* Save the initial mask status */ | |
565 | if (entry->msi_attrib.maskbit) | |
566 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
567 | ||
e75eafb9 TG |
568 | out: |
569 | kfree(masks); | |
d873b4d4 YW |
570 | return entry; |
571 | } | |
572 | ||
f144d149 BH |
573 | static int msi_verify_entries(struct pci_dev *dev) |
574 | { | |
575 | struct msi_desc *entry; | |
576 | ||
5004e98a | 577 | for_each_pci_msi_entry(entry, dev) { |
f144d149 BH |
578 | if (!dev->no_64bit_msi || !entry->msg.address_hi) |
579 | continue; | |
7506dc79 | 580 | pci_err(dev, "Device has broken 64-bit MSI but arch" |
f144d149 BH |
581 | " tried to assign one above 4G\n"); |
582 | return -EIO; | |
583 | } | |
584 | return 0; | |
585 | } | |
586 | ||
1da177e4 LT |
587 | /** |
588 | * msi_capability_init - configure device's MSI capability structure | |
589 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 590 | * @nvec: number of interrupts to allocate |
dadf1733 | 591 | * @affd: description of automatic irq affinity assignments (may be %NULL) |
1da177e4 | 592 | * |
1c8d7b0a MW |
593 | * Setup the MSI capability structure of the device with the requested |
594 | * number of interrupts. A return value of zero indicates the successful | |
595 | * setup of an entry with the new MSI irq. A negative return value indicates | |
596 | * an error, and a positive return value indicates the number of interrupts | |
597 | * which could have been allocated. | |
598 | */ | |
61e1c590 | 599 | static int msi_capability_init(struct pci_dev *dev, int nvec, |
c66d4bd1 | 600 | struct irq_affinity *affd) |
1da177e4 LT |
601 | { |
602 | struct msi_desc *entry; | |
f465136d | 603 | int ret; |
f2440d9a | 604 | unsigned mask; |
1da177e4 | 605 | |
61b64abd | 606 | pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 607 | |
61e1c590 | 608 | entry = msi_setup_entry(dev, nvec, affd); |
f7feaca7 EB |
609 | if (!entry) |
610 | return -ENOMEM; | |
1ce03373 | 611 | |
f2440d9a | 612 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 613 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
614 | msi_mask_irq(entry, mask, mask); |
615 | ||
5004e98a | 616 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
9c831334 | 617 | |
1da177e4 | 618 | /* Configure MSI capability structure */ |
8e047ada | 619 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 620 | if (ret) { |
7ba1930d | 621 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 622 | free_msi_irqs(dev); |
7fe3730d | 623 | return ret; |
fd58e55f | 624 | } |
f7feaca7 | 625 | |
f144d149 BH |
626 | ret = msi_verify_entries(dev); |
627 | if (ret) { | |
628 | msi_mask_irq(entry, mask, ~mask); | |
629 | free_msi_irqs(dev); | |
630 | return ret; | |
631 | } | |
632 | ||
da8d1c8b NH |
633 | ret = populate_msi_sysfs(dev); |
634 | if (ret) { | |
635 | msi_mask_irq(entry, mask, ~mask); | |
636 | free_msi_irqs(dev); | |
637 | return ret; | |
638 | } | |
639 | ||
1da177e4 | 640 | /* Set MSI enabled bits */ |
ba698ad4 | 641 | pci_intx_for_msi(dev, 0); |
61b64abd | 642 | pci_msi_set_enable(dev, 1); |
b1cbf4e4 | 643 | dev->msi_enabled = 1; |
1da177e4 | 644 | |
5f226991 | 645 | pcibios_free_irq(dev); |
7fe3730d | 646 | dev->irq = entry->irq; |
1da177e4 LT |
647 | return 0; |
648 | } | |
649 | ||
520fe9dc | 650 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 651 | { |
4302e0fb | 652 | resource_size_t phys_addr; |
5a05a9d8 | 653 | u32 table_offset; |
6a878e50 | 654 | unsigned long flags; |
5a05a9d8 HS |
655 | u8 bir; |
656 | ||
909094c6 BH |
657 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
658 | &table_offset); | |
4d18760c | 659 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
6a878e50 YW |
660 | flags = pci_resource_flags(dev, bir); |
661 | if (!flags || (flags & IORESOURCE_UNSET)) | |
662 | return NULL; | |
663 | ||
4d18760c | 664 | table_offset &= PCI_MSIX_TABLE_OFFSET; |
5a05a9d8 HS |
665 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
666 | ||
667 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
668 | } | |
669 | ||
520fe9dc | 670 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
e75eafb9 | 671 | struct msix_entry *entries, int nvec, |
c66d4bd1 | 672 | struct irq_affinity *affd) |
d9d7070e | 673 | { |
bec04037 | 674 | struct irq_affinity_desc *curmsk, *masks = NULL; |
d9d7070e | 675 | struct msi_desc *entry; |
e75eafb9 | 676 | int ret, i; |
4ef33685 | 677 | |
8e1101d2 | 678 | if (affd) |
61e1c590 | 679 | masks = irq_create_affinity_masks(nvec, affd); |
4ef33685 | 680 | |
e75eafb9 TG |
681 | for (i = 0, curmsk = masks; i < nvec; i++) { |
682 | entry = alloc_msi_entry(&dev->dev, 1, curmsk); | |
d9d7070e HS |
683 | if (!entry) { |
684 | if (!i) | |
685 | iounmap(base); | |
686 | else | |
687 | free_msi_irqs(dev); | |
688 | /* No enough memory. Don't try again */ | |
e75eafb9 TG |
689 | ret = -ENOMEM; |
690 | goto out; | |
d9d7070e HS |
691 | } |
692 | ||
693 | entry->msi_attrib.is_msix = 1; | |
694 | entry->msi_attrib.is_64 = 1; | |
3ac020e0 CH |
695 | if (entries) |
696 | entry->msi_attrib.entry_nr = entries[i].entry; | |
697 | else | |
698 | entry->msi_attrib.entry_nr = i; | |
d9d7070e | 699 | entry->msi_attrib.default_irq = dev->irq; |
d9d7070e HS |
700 | entry->mask_base = base; |
701 | ||
5004e98a | 702 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
e75eafb9 TG |
703 | if (masks) |
704 | curmsk++; | |
d9d7070e | 705 | } |
e75eafb9 TG |
706 | ret = 0; |
707 | out: | |
708 | kfree(masks); | |
3adfb572 | 709 | return ret; |
d9d7070e HS |
710 | } |
711 | ||
75cb3426 | 712 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 713 | struct msix_entry *entries) |
75cb3426 HS |
714 | { |
715 | struct msi_desc *entry; | |
716 | int i = 0; | |
717 | ||
5004e98a | 718 | for_each_pci_msi_entry(entry, dev) { |
3ac020e0 CH |
719 | if (entries) |
720 | entries[i++].vector = entry->irq; | |
12eb21de CH |
721 | entry->masked = readl(pci_msix_desc_addr(entry) + |
722 | PCI_MSIX_ENTRY_VECTOR_CTRL); | |
75cb3426 | 723 | msix_mask_irq(entry, 1); |
75cb3426 HS |
724 | } |
725 | } | |
726 | ||
1da177e4 LT |
727 | /** |
728 | * msix_capability_init - configure device's MSI-X capability | |
729 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
730 | * @entries: pointer to an array of struct msix_entry entries |
731 | * @nvec: number of @entries | |
61e1c590 | 732 | * @affd: Optional pointer to enable automatic affinity assignement |
1da177e4 | 733 | * |
eaae4b3a | 734 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
735 | * single MSI-X irq. A return of zero indicates the successful setup of |
736 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 | 737 | **/ |
e75eafb9 | 738 | static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries, |
c66d4bd1 | 739 | int nvec, struct irq_affinity *affd) |
1da177e4 | 740 | { |
520fe9dc | 741 | int ret; |
5a05a9d8 | 742 | u16 control; |
1da177e4 LT |
743 | void __iomem *base; |
744 | ||
f598282f | 745 | /* Ensure MSI-X is disabled while it is set up */ |
61b64abd | 746 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 747 | |
66f0d0c4 | 748 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 749 | /* Request & Map MSI-X table region */ |
527eee29 | 750 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 751 | if (!base) |
1da177e4 LT |
752 | return -ENOMEM; |
753 | ||
61e1c590 | 754 | ret = msix_setup_entries(dev, base, entries, nvec, affd); |
d9d7070e HS |
755 | if (ret) |
756 | return ret; | |
9c831334 | 757 | |
8e047ada | 758 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
583871d4 | 759 | if (ret) |
2adc7907 | 760 | goto out_avail; |
9c831334 | 761 | |
f144d149 BH |
762 | /* Check if all MSI entries honor device restrictions */ |
763 | ret = msi_verify_entries(dev); | |
764 | if (ret) | |
765 | goto out_free; | |
766 | ||
f598282f MW |
767 | /* |
768 | * Some devices require MSI-X to be enabled before we can touch the | |
769 | * MSI-X registers. We need to mask all the vectors to prevent | |
770 | * interrupts coming in before they're fully set up. | |
771 | */ | |
61b64abd | 772 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 773 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); |
f598282f | 774 | |
75cb3426 | 775 | msix_program_entries(dev, entries); |
f598282f | 776 | |
da8d1c8b | 777 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
778 | if (ret) |
779 | goto out_free; | |
da8d1c8b | 780 | |
f598282f | 781 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 782 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 783 | dev->msix_enabled = 1; |
61b64abd | 784 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 785 | |
5f226991 | 786 | pcibios_free_irq(dev); |
1da177e4 | 787 | return 0; |
583871d4 | 788 | |
2adc7907 | 789 | out_avail: |
583871d4 HS |
790 | if (ret < 0) { |
791 | /* | |
792 | * If we had some success, report the number of irqs | |
793 | * we succeeded in setting up. | |
794 | */ | |
d9d7070e | 795 | struct msi_desc *entry; |
583871d4 HS |
796 | int avail = 0; |
797 | ||
5004e98a | 798 | for_each_pci_msi_entry(entry, dev) { |
583871d4 HS |
799 | if (entry->irq != 0) |
800 | avail++; | |
801 | } | |
802 | if (avail != 0) | |
803 | ret = avail; | |
804 | } | |
805 | ||
2adc7907 | 806 | out_free: |
583871d4 HS |
807 | free_msi_irqs(dev); |
808 | ||
809 | return ret; | |
1da177e4 LT |
810 | } |
811 | ||
24334a12 | 812 | /** |
a06cd74c | 813 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 814 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 815 | * @nvec: how many MSIs have been requested ? |
24334a12 | 816 | * |
f7625980 | 817 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 818 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 819 | * supported return 1, else return 0. |
24334a12 | 820 | **/ |
a06cd74c | 821 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
822 | { |
823 | struct pci_bus *bus; | |
824 | ||
0306ebfa | 825 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 826 | if (!pci_msi_enable) |
a06cd74c | 827 | return 0; |
27e20603 AG |
828 | |
829 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 830 | return 0; |
24334a12 | 831 | |
314e77b3 ME |
832 | /* |
833 | * You can't ask to have 0 or less MSIs configured. | |
834 | * a) it's stupid .. | |
835 | * b) the list manipulation code assumes nvec >= 1. | |
836 | */ | |
837 | if (nvec < 1) | |
a06cd74c | 838 | return 0; |
314e77b3 | 839 | |
500559a9 HS |
840 | /* |
841 | * Any bridge which does NOT route MSI transactions from its | |
842 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
843 | * the secondary pci_bus. |
844 | * We expect only arch-specific PCI host bus controller driver | |
845 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
846 | */ | |
24334a12 BG |
847 | for (bus = dev->bus; bus; bus = bus->parent) |
848 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 849 | return 0; |
24334a12 | 850 | |
a06cd74c | 851 | return 1; |
24334a12 BG |
852 | } |
853 | ||
d1ac1d26 AG |
854 | /** |
855 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
856 | * @dev: device to report about | |
857 | * | |
858 | * This function returns the number of MSI vectors a device requested via | |
859 | * Multiple Message Capable register. It returns a negative errno if the | |
860 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
861 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
862 | * MSI specification. | |
863 | **/ | |
864 | int pci_msi_vec_count(struct pci_dev *dev) | |
865 | { | |
866 | int ret; | |
867 | u16 msgctl; | |
868 | ||
869 | if (!dev->msi_cap) | |
870 | return -EINVAL; | |
871 | ||
872 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
873 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
874 | ||
875 | return ret; | |
876 | } | |
877 | EXPORT_SYMBOL(pci_msi_vec_count); | |
878 | ||
688769f6 | 879 | static void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 880 | { |
f2440d9a MW |
881 | struct msi_desc *desc; |
882 | u32 mask; | |
1da177e4 | 883 | |
128bc5fc | 884 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
885 | return; |
886 | ||
5004e98a | 887 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
4a7cc831 | 888 | desc = first_pci_msi_entry(dev); |
110828c9 | 889 | |
61b64abd | 890 | pci_msi_set_enable(dev, 0); |
ba698ad4 | 891 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 892 | dev->msi_enabled = 0; |
7bd007e4 | 893 | |
12abb8ba | 894 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 895 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 896 | /* Keep cached state to be restored */ |
23ed8d57 | 897 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
898 | |
899 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 900 | dev->irq = desc->msi_attrib.default_irq; |
5f226991 | 901 | pcibios_alloc_irq(dev); |
d52877c7 | 902 | } |
24d27553 | 903 | |
500559a9 | 904 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 905 | { |
d52877c7 YL |
906 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
907 | return; | |
908 | ||
909 | pci_msi_shutdown(dev); | |
f56e4481 | 910 | free_msi_irqs(dev); |
1da177e4 | 911 | } |
4cc086fa | 912 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 913 | |
a52e2e35 | 914 | /** |
ff1aa430 | 915 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 916 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
917 | * This function returns the number of device's MSI-X table entries and |
918 | * therefore the number of MSI-X vectors device is capable of sending. | |
919 | * It returns a negative errno if the device is not capable of sending MSI-X | |
920 | * interrupts. | |
921 | **/ | |
922 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 923 | { |
a52e2e35 RW |
924 | u16 control; |
925 | ||
520fe9dc | 926 | if (!dev->msix_cap) |
ff1aa430 | 927 | return -EINVAL; |
a52e2e35 | 928 | |
f84ecd28 | 929 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 930 | return msix_table_size(control); |
a52e2e35 | 931 | } |
ff1aa430 | 932 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 933 | |
e75eafb9 | 934 | static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, |
c66d4bd1 | 935 | int nvec, struct irq_affinity *affd) |
1da177e4 | 936 | { |
5ec09405 | 937 | int nr_entries; |
ded86d8d | 938 | int i, j; |
1da177e4 | 939 | |
a06cd74c AG |
940 | if (!pci_msi_supported(dev, nvec)) |
941 | return -EINVAL; | |
c9953a73 | 942 | |
ff1aa430 AG |
943 | nr_entries = pci_msix_vec_count(dev); |
944 | if (nr_entries < 0) | |
945 | return nr_entries; | |
1da177e4 | 946 | if (nvec > nr_entries) |
57fbf52c | 947 | return nr_entries; |
1da177e4 | 948 | |
3ac020e0 CH |
949 | if (entries) { |
950 | /* Check for any invalid entries */ | |
951 | for (i = 0; i < nvec; i++) { | |
952 | if (entries[i].entry >= nr_entries) | |
953 | return -EINVAL; /* invalid entry */ | |
954 | for (j = i + 1; j < nvec; j++) { | |
955 | if (entries[i].entry == entries[j].entry) | |
956 | return -EINVAL; /* duplicate entry */ | |
957 | } | |
1da177e4 LT |
958 | } |
959 | } | |
7bd007e4 | 960 | |
1ce03373 | 961 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 962 | if (dev->msi_enabled) { |
7506dc79 | 963 | pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
964 | return -EINVAL; |
965 | } | |
61e1c590 | 966 | return msix_capability_init(dev, entries, nvec, affd); |
e75eafb9 TG |
967 | } |
968 | ||
688769f6 | 969 | static void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 970 | { |
12abb8ba HS |
971 | struct msi_desc *entry; |
972 | ||
128bc5fc | 973 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
974 | return; |
975 | ||
0170591b KB |
976 | if (pci_dev_is_disconnected(dev)) { |
977 | dev->msix_enabled = 0; | |
978 | return; | |
979 | } | |
980 | ||
12abb8ba | 981 | /* Return the device with MSI-X masked as initial states */ |
5004e98a | 982 | for_each_pci_msi_entry(entry, dev) { |
12abb8ba | 983 | /* Keep cached states to be restored */ |
23ed8d57 | 984 | __pci_msix_desc_mask_irq(entry, 1); |
12abb8ba HS |
985 | } |
986 | ||
61b64abd | 987 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 988 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 989 | dev->msix_enabled = 0; |
5f226991 | 990 | pcibios_alloc_irq(dev); |
d52877c7 | 991 | } |
c901851f | 992 | |
500559a9 | 993 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
994 | { |
995 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
996 | return; | |
997 | ||
998 | pci_msix_shutdown(dev); | |
f56e4481 | 999 | free_msi_irqs(dev); |
1da177e4 | 1000 | } |
4cc086fa | 1001 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1002 | |
309e57df MW |
1003 | void pci_no_msi(void) |
1004 | { | |
1005 | pci_msi_enable = 0; | |
1006 | } | |
c9953a73 | 1007 | |
07ae95f9 AP |
1008 | /** |
1009 | * pci_msi_enabled - is MSI enabled? | |
1010 | * | |
1011 | * Returns true if MSI has not been disabled by the command-line option | |
1012 | * pci=nomsi. | |
1013 | **/ | |
1014 | int pci_msi_enabled(void) | |
d389fec6 | 1015 | { |
07ae95f9 | 1016 | return pci_msi_enable; |
d389fec6 | 1017 | } |
07ae95f9 | 1018 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1019 | |
4ef33685 | 1020 | static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, |
c66d4bd1 | 1021 | struct irq_affinity *affd) |
302a2523 | 1022 | { |
034cd97e | 1023 | int nvec; |
302a2523 AG |
1024 | int rc; |
1025 | ||
a06cd74c AG |
1026 | if (!pci_msi_supported(dev, minvec)) |
1027 | return -EINVAL; | |
034cd97e | 1028 | |
034cd97e AG |
1029 | /* Check whether driver already requested MSI-X irqs */ |
1030 | if (dev->msix_enabled) { | |
7506dc79 | 1031 | pci_info(dev, "can't enable MSI (MSI-X already enabled)\n"); |
034cd97e AG |
1032 | return -EINVAL; |
1033 | } | |
1034 | ||
302a2523 AG |
1035 | if (maxvec < minvec) |
1036 | return -ERANGE; | |
1037 | ||
4c1ef72e TZ |
1038 | if (WARN_ON_ONCE(dev->msi_enabled)) |
1039 | return -EINVAL; | |
1040 | ||
034cd97e AG |
1041 | nvec = pci_msi_vec_count(dev); |
1042 | if (nvec < 0) | |
1043 | return nvec; | |
4ef33685 | 1044 | if (nvec < minvec) |
948b7620 | 1045 | return -ENOSPC; |
4ef33685 CH |
1046 | |
1047 | if (nvec > maxvec) | |
034cd97e AG |
1048 | nvec = maxvec; |
1049 | ||
4ef33685 | 1050 | for (;;) { |
61e1c590 | 1051 | if (affd) { |
6f9a22bc | 1052 | nvec = irq_calc_affinity_vectors(minvec, nvec, affd); |
4ef33685 CH |
1053 | if (nvec < minvec) |
1054 | return -ENOSPC; | |
1055 | } | |
1056 | ||
61e1c590 | 1057 | rc = msi_capability_init(dev, nvec, affd); |
4ef33685 CH |
1058 | if (rc == 0) |
1059 | return nvec; | |
1060 | ||
4ef33685 | 1061 | if (rc < 0) |
302a2523 | 1062 | return rc; |
4ef33685 CH |
1063 | if (rc < minvec) |
1064 | return -ENOSPC; | |
1065 | ||
1066 | nvec = rc; | |
1067 | } | |
1068 | } | |
1069 | ||
4fe03955 CH |
1070 | /* deprecated, don't use */ |
1071 | int pci_enable_msi(struct pci_dev *dev) | |
4ef33685 | 1072 | { |
4fe03955 CH |
1073 | int rc = __pci_enable_msi_range(dev, 1, 1, NULL); |
1074 | if (rc < 0) | |
1075 | return rc; | |
1076 | return 0; | |
4ef33685 | 1077 | } |
4fe03955 | 1078 | EXPORT_SYMBOL(pci_enable_msi); |
4ef33685 CH |
1079 | |
1080 | static int __pci_enable_msix_range(struct pci_dev *dev, | |
61e1c590 | 1081 | struct msix_entry *entries, int minvec, |
c66d4bd1 | 1082 | int maxvec, struct irq_affinity *affd) |
4ef33685 | 1083 | { |
e75eafb9 | 1084 | int rc, nvec = maxvec; |
4ef33685 CH |
1085 | |
1086 | if (maxvec < minvec) | |
1087 | return -ERANGE; | |
1088 | ||
4c1ef72e TZ |
1089 | if (WARN_ON_ONCE(dev->msix_enabled)) |
1090 | return -EINVAL; | |
1091 | ||
4ef33685 | 1092 | for (;;) { |
61e1c590 | 1093 | if (affd) { |
6f9a22bc | 1094 | nvec = irq_calc_affinity_vectors(minvec, nvec, affd); |
4ef33685 | 1095 | if (nvec < minvec) |
302a2523 | 1096 | return -ENOSPC; |
302a2523 | 1097 | } |
302a2523 | 1098 | |
61e1c590 | 1099 | rc = __pci_enable_msix(dev, entries, nvec, affd); |
4ef33685 CH |
1100 | if (rc == 0) |
1101 | return nvec; | |
1102 | ||
4ef33685 CH |
1103 | if (rc < 0) |
1104 | return rc; | |
1105 | if (rc < minvec) | |
1106 | return -ENOSPC; | |
1107 | ||
1108 | nvec = rc; | |
1109 | } | |
302a2523 | 1110 | } |
302a2523 AG |
1111 | |
1112 | /** | |
1113 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1114 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1115 | * @entries: pointer to an array of MSI-X entries | |
1116 | * @minvec: minimum number of MSI-X irqs requested | |
1117 | * @maxvec: maximum number of MSI-X irqs requested | |
1118 | * | |
1119 | * Setup the MSI-X capability structure of device function with a maximum | |
1120 | * possible number of interrupts in the range between @minvec and @maxvec | |
1121 | * upon its software driver call to request for MSI-X mode enabled on its | |
1122 | * hardware device function. It returns a negative errno if an error occurs. | |
1123 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1124 | * indicates the successful configuration of MSI-X capability structure | |
1125 | * with new allocated MSI-X interrupts. | |
1126 | **/ | |
1127 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
4ef33685 | 1128 | int minvec, int maxvec) |
302a2523 | 1129 | { |
61e1c590 | 1130 | return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL); |
302a2523 AG |
1131 | } |
1132 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef | 1133 | |
aff17164 | 1134 | /** |
402723ad | 1135 | * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device |
aff17164 CH |
1136 | * @dev: PCI device to operate on |
1137 | * @min_vecs: minimum number of vectors required (must be >= 1) | |
1138 | * @max_vecs: maximum (desired) number of vectors | |
1139 | * @flags: flags or quirks for the allocation | |
402723ad | 1140 | * @affd: optional description of the affinity requirements |
aff17164 CH |
1141 | * |
1142 | * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI | |
1143 | * vectors if available, and fall back to a single legacy vector | |
1144 | * if neither is available. Return the number of vectors allocated, | |
1145 | * (which might be smaller than @max_vecs) if successful, or a negative | |
1146 | * error code on error. If less than @min_vecs interrupt vectors are | |
1147 | * available for @dev the function will fail with -ENOSPC. | |
1148 | * | |
1149 | * To get the Linux IRQ number used for a vector that can be passed to | |
1150 | * request_irq() use the pci_irq_vector() helper. | |
1151 | */ | |
402723ad CH |
1152 | int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
1153 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1154 | struct irq_affinity *affd) |
aff17164 | 1155 | { |
c66d4bd1 | 1156 | struct irq_affinity msi_default_affd = {0}; |
77f88abd ML |
1157 | int msix_vecs = -ENOSPC; |
1158 | int msi_vecs = -ENOSPC; | |
aff17164 | 1159 | |
402723ad CH |
1160 | if (flags & PCI_IRQ_AFFINITY) { |
1161 | if (!affd) | |
1162 | affd = &msi_default_affd; | |
1163 | } else { | |
1164 | if (WARN_ON(affd)) | |
1165 | affd = NULL; | |
1166 | } | |
61e1c590 | 1167 | |
4fe0d154 | 1168 | if (flags & PCI_IRQ_MSIX) { |
77f88abd ML |
1169 | msix_vecs = __pci_enable_msix_range(dev, NULL, min_vecs, |
1170 | max_vecs, affd); | |
1171 | if (msix_vecs > 0) | |
1172 | return msix_vecs; | |
aff17164 CH |
1173 | } |
1174 | ||
4fe0d154 | 1175 | if (flags & PCI_IRQ_MSI) { |
77f88abd ML |
1176 | msi_vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, |
1177 | affd); | |
1178 | if (msi_vecs > 0) | |
1179 | return msi_vecs; | |
aff17164 CH |
1180 | } |
1181 | ||
1182 | /* use legacy irq if allowed */ | |
862290f9 CH |
1183 | if (flags & PCI_IRQ_LEGACY) { |
1184 | if (min_vecs == 1 && dev->irq) { | |
c66d4bd1 ML |
1185 | /* |
1186 | * Invoke the affinity spreading logic to ensure that | |
1187 | * the device driver can adjust queue configuration | |
1188 | * for the single interrupt case. | |
1189 | */ | |
1190 | if (affd) | |
1191 | irq_create_affinity_masks(1, affd); | |
862290f9 CH |
1192 | pci_intx(dev, 1); |
1193 | return 1; | |
1194 | } | |
5d0bdf28 CH |
1195 | } |
1196 | ||
77f88abd ML |
1197 | if (msix_vecs == -ENOSPC) |
1198 | return -ENOSPC; | |
1199 | return msi_vecs; | |
aff17164 | 1200 | } |
402723ad | 1201 | EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); |
aff17164 CH |
1202 | |
1203 | /** | |
1204 | * pci_free_irq_vectors - free previously allocated IRQs for a device | |
1205 | * @dev: PCI device to operate on | |
1206 | * | |
1207 | * Undoes the allocations and enabling in pci_alloc_irq_vectors(). | |
1208 | */ | |
1209 | void pci_free_irq_vectors(struct pci_dev *dev) | |
1210 | { | |
1211 | pci_disable_msix(dev); | |
1212 | pci_disable_msi(dev); | |
1213 | } | |
1214 | EXPORT_SYMBOL(pci_free_irq_vectors); | |
1215 | ||
1216 | /** | |
1217 | * pci_irq_vector - return Linux IRQ number of a device vector | |
1218 | * @dev: PCI device to operate on | |
1219 | * @nr: device-relative interrupt vector index (0-based). | |
1220 | */ | |
1221 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1222 | { | |
1223 | if (dev->msix_enabled) { | |
1224 | struct msi_desc *entry; | |
1225 | int i = 0; | |
1226 | ||
1227 | for_each_pci_msi_entry(entry, dev) { | |
1228 | if (i == nr) | |
1229 | return entry->irq; | |
1230 | i++; | |
1231 | } | |
1232 | WARN_ON_ONCE(1); | |
1233 | return -EINVAL; | |
1234 | } | |
1235 | ||
1236 | if (dev->msi_enabled) { | |
1237 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1238 | ||
1239 | if (WARN_ON_ONCE(nr >= entry->nvec_used)) | |
1240 | return -EINVAL; | |
1241 | } else { | |
1242 | if (WARN_ON_ONCE(nr > 0)) | |
1243 | return -EINVAL; | |
1244 | } | |
1245 | ||
1246 | return dev->irq + nr; | |
1247 | } | |
1248 | EXPORT_SYMBOL(pci_irq_vector); | |
1249 | ||
ee8d41e5 TG |
1250 | /** |
1251 | * pci_irq_get_affinity - return the affinity of a particular msi vector | |
1252 | * @dev: PCI device to operate on | |
1253 | * @nr: device-relative interrupt vector index (0-based). | |
1254 | */ | |
1255 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr) | |
1256 | { | |
1257 | if (dev->msix_enabled) { | |
1258 | struct msi_desc *entry; | |
1259 | int i = 0; | |
1260 | ||
1261 | for_each_pci_msi_entry(entry, dev) { | |
1262 | if (i == nr) | |
bec04037 | 1263 | return &entry->affinity->mask; |
ee8d41e5 TG |
1264 | i++; |
1265 | } | |
1266 | WARN_ON_ONCE(1); | |
1267 | return NULL; | |
1268 | } else if (dev->msi_enabled) { | |
1269 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1270 | ||
d1d111e0 JB |
1271 | if (WARN_ON_ONCE(!entry || !entry->affinity || |
1272 | nr >= entry->nvec_used)) | |
ee8d41e5 TG |
1273 | return NULL; |
1274 | ||
bec04037 | 1275 | return &entry->affinity[nr].mask; |
ee8d41e5 TG |
1276 | } else { |
1277 | return cpu_possible_mask; | |
1278 | } | |
1279 | } | |
1280 | EXPORT_SYMBOL(pci_irq_get_affinity); | |
1281 | ||
27ddb689 SL |
1282 | /** |
1283 | * pci_irq_get_node - return the numa node of a particular msi vector | |
1284 | * @pdev: PCI device to operate on | |
1285 | * @vec: device-relative interrupt vector index (0-based). | |
1286 | */ | |
1287 | int pci_irq_get_node(struct pci_dev *pdev, int vec) | |
1288 | { | |
1289 | const struct cpumask *mask; | |
1290 | ||
1291 | mask = pci_irq_get_affinity(pdev, vec); | |
1292 | if (mask) | |
1293 | return local_memory_node(cpu_to_node(cpumask_first(mask))); | |
1294 | return dev_to_node(&pdev->dev); | |
1295 | } | |
1296 | EXPORT_SYMBOL(pci_irq_get_node); | |
1297 | ||
25a98bd4 JL |
1298 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc) |
1299 | { | |
1300 | return to_pci_dev(desc->dev); | |
1301 | } | |
a4289dc2 | 1302 | EXPORT_SYMBOL(msi_desc_to_pci_dev); |
25a98bd4 | 1303 | |
c179c9b9 JL |
1304 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
1305 | { | |
1306 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); | |
1307 | ||
1308 | return dev->bus->sysdata; | |
1309 | } | |
1310 | EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata); | |
1311 | ||
3878eaef JL |
1312 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
1313 | /** | |
1314 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1315 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1316 | * @msg: Pointer to the message | |
1317 | */ | |
1318 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1319 | { | |
507a883e | 1320 | struct msi_desc *desc = irq_data_get_msi_desc(irq_data); |
3878eaef JL |
1321 | |
1322 | /* | |
1323 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1324 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1325 | */ | |
1326 | if (desc->irq == irq_data->irq) | |
1327 | __pci_write_msi_msg(desc, msg); | |
1328 | } | |
1329 | ||
1330 | /** | |
1331 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
1332 | * @dev: Pointer to the PCI device | |
1333 | * @desc: Pointer to the msi descriptor | |
1334 | * | |
1335 | * The ID number is only used within the irqdomain. | |
1336 | */ | |
1337 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, | |
1338 | struct msi_desc *desc) | |
1339 | { | |
1340 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | | |
1341 | PCI_DEVID(dev->bus->number, dev->devfn) << 11 | | |
1342 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; | |
1343 | } | |
1344 | ||
1345 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1346 | { | |
1347 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1348 | } | |
1349 | ||
1350 | /** | |
1351 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev | |
1352 | * @domain: The interrupt domain to check | |
1353 | * @info: The domain info for verification | |
1354 | * @dev: The device to check | |
1355 | * | |
1356 | * Returns: | |
1357 | * 0 if the functionality is supported | |
1358 | * 1 if Multi MSI is requested, but the domain does not support it | |
1359 | * -ENOTSUPP otherwise | |
1360 | */ | |
1361 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1362 | struct msi_domain_info *info, struct device *dev) | |
1363 | { | |
1364 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1365 | ||
4fe03955 | 1366 | /* Special handling to support __pci_enable_msi_range() */ |
3878eaef JL |
1367 | if (pci_msi_desc_is_multi_msi(desc) && |
1368 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1369 | return 1; | |
1370 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1371 | return -ENOTSUPP; | |
1372 | ||
1373 | return 0; | |
1374 | } | |
1375 | ||
1376 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1377 | struct msi_desc *desc, int error) | |
1378 | { | |
4fe03955 | 1379 | /* Special handling to support __pci_enable_msi_range() */ |
3878eaef JL |
1380 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) |
1381 | return 1; | |
1382 | ||
1383 | return error; | |
1384 | } | |
1385 | ||
1386 | #ifdef GENERIC_MSI_DOMAIN_OPS | |
1387 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, | |
1388 | struct msi_desc *desc) | |
1389 | { | |
1390 | arg->desc = desc; | |
1391 | arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc), | |
1392 | desc); | |
1393 | } | |
1394 | #else | |
1395 | #define pci_msi_domain_set_desc NULL | |
1396 | #endif | |
1397 | ||
1398 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1399 | .set_desc = pci_msi_domain_set_desc, | |
1400 | .msi_check = pci_msi_domain_check_cap, | |
1401 | .handle_error = pci_msi_domain_handle_error, | |
1402 | }; | |
1403 | ||
1404 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1405 | { | |
1406 | struct msi_domain_ops *ops = info->ops; | |
1407 | ||
1408 | if (ops == NULL) { | |
1409 | info->ops = &pci_msi_domain_ops_default; | |
1410 | } else { | |
1411 | if (ops->set_desc == NULL) | |
1412 | ops->set_desc = pci_msi_domain_set_desc; | |
1413 | if (ops->msi_check == NULL) | |
1414 | ops->msi_check = pci_msi_domain_check_cap; | |
1415 | if (ops->handle_error == NULL) | |
1416 | ops->handle_error = pci_msi_domain_handle_error; | |
1417 | } | |
1418 | } | |
1419 | ||
1420 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1421 | { | |
1422 | struct irq_chip *chip = info->chip; | |
1423 | ||
1424 | BUG_ON(!chip); | |
1425 | if (!chip->irq_write_msi_msg) | |
1426 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
0701c53e MZ |
1427 | if (!chip->irq_mask) |
1428 | chip->irq_mask = pci_msi_mask_irq; | |
1429 | if (!chip->irq_unmask) | |
1430 | chip->irq_unmask = pci_msi_unmask_irq; | |
3878eaef JL |
1431 | } |
1432 | ||
1433 | /** | |
be5436c8 MZ |
1434 | * pci_msi_create_irq_domain - Create a MSI interrupt domain |
1435 | * @fwnode: Optional fwnode of the interrupt controller | |
3878eaef JL |
1436 | * @info: MSI domain info |
1437 | * @parent: Parent irq domain | |
1438 | * | |
1439 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1440 | * | |
1441 | * Returns: | |
1442 | * A domain pointer or NULL in case of failure. | |
1443 | */ | |
be5436c8 | 1444 | struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, |
3878eaef JL |
1445 | struct msi_domain_info *info, |
1446 | struct irq_domain *parent) | |
1447 | { | |
0380839d MZ |
1448 | struct irq_domain *domain; |
1449 | ||
6988e0e0 MZ |
1450 | if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE)) |
1451 | info->flags &= ~MSI_FLAG_LEVEL_CAPABLE; | |
1452 | ||
3878eaef JL |
1453 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
1454 | pci_msi_domain_update_dom_ops(info); | |
1455 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1456 | pci_msi_domain_update_chip_ops(info); | |
1457 | ||
f3b0946d | 1458 | info->flags |= MSI_FLAG_ACTIVATE_EARLY; |
25e960ef TG |
1459 | if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE)) |
1460 | info->flags |= MSI_FLAG_MUST_REACTIVATE; | |
f3b0946d | 1461 | |
923aa4c3 HK |
1462 | /* PCI-MSI is oneshot-safe */ |
1463 | info->chip->flags |= IRQCHIP_ONESHOT_SAFE; | |
1464 | ||
be5436c8 | 1465 | domain = msi_create_irq_domain(fwnode, info, parent); |
0380839d MZ |
1466 | if (!domain) |
1467 | return NULL; | |
1468 | ||
96f0d93a | 1469 | irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI); |
0380839d | 1470 | return domain; |
3878eaef | 1471 | } |
a4289dc2 | 1472 | EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain); |
3878eaef | 1473 | |
235b2c77 RM |
1474 | /* |
1475 | * Users of the generic MSI infrastructure expect a device to have a single ID, | |
1476 | * so with DMA aliases we have to pick the least-worst compromise. Devices with | |
1477 | * DMA phantom functions tend to still emit MSIs from the real function number, | |
1478 | * so we ignore those and only consider topological aliases where either the | |
1479 | * alias device or RID appears on a different bus number. We also make the | |
1480 | * reasonable assumption that bridges are walked in an upstream direction (so | |
1481 | * the last one seen wins), and the much braver assumption that the most likely | |
1482 | * case is that of PCI->PCIe so we should always use the alias RID. This echoes | |
1483 | * the logic from intel_irq_remapping's set_msi_sid(), which presumably works | |
1484 | * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions | |
1485 | * for taking ownership all we can really do is close our eyes and hope... | |
1486 | */ | |
b6eec9b7 DD |
1487 | static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data) |
1488 | { | |
1489 | u32 *pa = data; | |
235b2c77 RM |
1490 | u8 bus = PCI_BUS_NUM(*pa); |
1491 | ||
1492 | if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus) | |
1493 | *pa = alias; | |
b6eec9b7 | 1494 | |
b6eec9b7 DD |
1495 | return 0; |
1496 | } | |
235b2c77 | 1497 | |
b6eec9b7 DD |
1498 | /** |
1499 | * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID) | |
1500 | * @domain: The interrupt domain | |
1501 | * @pdev: The PCI device. | |
1502 | * | |
1503 | * The RID for a device is formed from the alias, with a firmware | |
1504 | * supplied mapping applied | |
1505 | * | |
1506 | * Returns: The RID. | |
1507 | */ | |
1508 | u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev) | |
1509 | { | |
1510 | struct device_node *of_node; | |
235b2c77 | 1511 | u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn); |
b6eec9b7 DD |
1512 | |
1513 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
1514 | ||
1515 | of_node = irq_domain_get_of_node(domain); | |
be2021ba TN |
1516 | rid = of_node ? of_msi_map_rid(&pdev->dev, of_node, rid) : |
1517 | iort_msi_map_rid(&pdev->dev, rid); | |
b6eec9b7 DD |
1518 | |
1519 | return rid; | |
1520 | } | |
54fa97ee MZ |
1521 | |
1522 | /** | |
1523 | * pci_msi_get_device_domain - Get the MSI domain for a given PCI device | |
1524 | * @pdev: The PCI device | |
1525 | * | |
1526 | * Use the firmware data to find a device-specific MSI domain | |
235b2c77 | 1527 | * (i.e. not one that is set as a default). |
54fa97ee | 1528 | * |
235b2c77 | 1529 | * Returns: The corresponding MSI domain or NULL if none has been found. |
54fa97ee MZ |
1530 | */ |
1531 | struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) | |
1532 | { | |
be2021ba | 1533 | struct irq_domain *dom; |
235b2c77 | 1534 | u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn); |
54fa97ee MZ |
1535 | |
1536 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
be2021ba TN |
1537 | dom = of_msi_map_get_device_domain(&pdev->dev, rid); |
1538 | if (!dom) | |
1539 | dom = iort_get_device_domain(&pdev->dev, rid); | |
1540 | return dom; | |
54fa97ee | 1541 | } |
3878eaef | 1542 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |