Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI Message Signaled Interrupt (MSI) |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
aff17164 | 7 | * Copyright (C) 2016 Christoph Hellwig. |
1da177e4 LT |
8 | */ |
9 | ||
1ce03373 | 10 | #include <linux/err.h> |
1da177e4 LT |
11 | #include <linux/mm.h> |
12 | #include <linux/irq.h> | |
13 | #include <linux/interrupt.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
be2021ba | 22 | #include <linux/acpi_iort.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
3878eaef | 24 | #include <linux/irqdomain.h> |
b6eec9b7 | 25 | #include <linux/of_irq.h> |
1da177e4 LT |
26 | |
27 | #include "pci.h" | |
1da177e4 | 28 | |
cbc40d5c BH |
29 | #ifdef CONFIG_PCI_MSI |
30 | ||
1da177e4 | 31 | static int pci_msi_enable = 1; |
38737d82 | 32 | int pci_msi_ignore_mask; |
1da177e4 | 33 | |
527eee29 BH |
34 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
35 | ||
8e047ada | 36 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
8e047ada JL |
37 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
38 | { | |
39 | struct irq_domain *domain; | |
40 | ||
47feb418 | 41 | domain = dev_get_msi_domain(&dev->dev); |
3845d295 | 42 | if (domain && irq_domain_is_hierarchy(domain)) |
699c4cec | 43 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); |
8e047ada JL |
44 | |
45 | return arch_setup_msi_irqs(dev, nvec, type); | |
46 | } | |
47 | ||
48 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) | |
49 | { | |
50 | struct irq_domain *domain; | |
51 | ||
47feb418 | 52 | domain = dev_get_msi_domain(&dev->dev); |
3845d295 | 53 | if (domain && irq_domain_is_hierarchy(domain)) |
699c4cec | 54 | msi_domain_free_irqs(domain, &dev->dev); |
8e047ada JL |
55 | else |
56 | arch_teardown_msi_irqs(dev); | |
57 | } | |
58 | #else | |
59 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs | |
60 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs | |
61 | #endif | |
527eee29 | 62 | |
077ee78e | 63 | #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS |
6a9e7f20 | 64 | /* Arch hooks */ |
4287d824 TP |
65 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
66 | { | |
3a05d08f | 67 | return -EINVAL; |
4287d824 TP |
68 | } |
69 | ||
70 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 71 | { |
6a9e7f20 AB |
72 | } |
73 | ||
4287d824 | 74 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
75 | { |
76 | struct msi_desc *entry; | |
77 | int ret; | |
78 | ||
1c8d7b0a MW |
79 | /* |
80 | * If an architecture wants to support multiple MSI, it needs to | |
81 | * override arch_setup_msi_irqs() | |
82 | */ | |
83 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
84 | return 1; | |
85 | ||
5004e98a | 86 | for_each_pci_msi_entry(entry, dev) { |
6a9e7f20 | 87 | ret = arch_setup_msi_irq(dev, entry); |
b5fbf533 | 88 | if (ret < 0) |
6a9e7f20 | 89 | return ret; |
b5fbf533 ME |
90 | if (ret > 0) |
91 | return -ENOSPC; | |
6a9e7f20 AB |
92 | } |
93 | ||
94 | return 0; | |
95 | } | |
1525bf0d | 96 | |
f8bcf249 | 97 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 98 | { |
63a7b17e | 99 | int i; |
6a9e7f20 AB |
100 | struct msi_desc *entry; |
101 | ||
5004e98a | 102 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
103 | if (entry->irq) |
104 | for (i = 0; i < entry->nvec_used; i++) | |
105 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 | 106 | } |
077ee78e | 107 | #endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */ |
76ccc297 | 108 | |
ac8344c4 | 109 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
110 | { |
111 | struct msi_desc *entry; | |
112 | ||
113 | entry = NULL; | |
114 | if (dev->msix_enabled) { | |
5004e98a | 115 | for_each_pci_msi_entry(entry, dev) { |
76ccc297 KRW |
116 | if (irq == entry->irq) |
117 | break; | |
118 | } | |
119 | } else if (dev->msi_enabled) { | |
120 | entry = irq_get_msi_desc(irq); | |
121 | } | |
122 | ||
123 | if (entry) | |
83a18912 | 124 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 125 | } |
4287d824 | 126 | |
ac8344c4 | 127 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 128 | { |
ac8344c4 | 129 | return default_restore_msi_irqs(dev); |
4287d824 | 130 | } |
76ccc297 | 131 | |
ce6fce42 MW |
132 | /* |
133 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
134 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
135 | * reliably as devices without an INTx disable bit will then generate a | |
136 | * level IRQ which will never be cleared. | |
ce6fce42 | 137 | */ |
7327cefe TG |
138 | static inline __attribute_const__ u32 msi_multi_mask(struct msi_desc *desc) |
139 | { | |
140 | /* Don't shift by >= width of type */ | |
141 | if (desc->msi_attrib.multi_cap >= 5) | |
142 | return 0xffffffff; | |
143 | return (1 << (1 << desc->msi_attrib.multi_cap)) - 1; | |
144 | } | |
145 | ||
fcacdfbe | 146 | static noinline void pci_msi_update_mask(struct msi_desc *desc, u32 clear, u32 set) |
1da177e4 | 147 | { |
77e89afc TG |
148 | raw_spinlock_t *lock = &desc->dev->msi_lock; |
149 | unsigned long flags; | |
1da177e4 | 150 | |
77e89afc | 151 | raw_spin_lock_irqsave(lock, flags); |
fcacdfbe TG |
152 | desc->msi_mask &= ~clear; |
153 | desc->msi_mask |= set; | |
e39758e0 | 154 | pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, |
fcacdfbe | 155 | desc->msi_mask); |
77e89afc | 156 | raw_spin_unlock_irqrestore(lock, flags); |
12abb8ba HS |
157 | } |
158 | ||
fcacdfbe | 159 | static inline void pci_msi_mask(struct msi_desc *desc, u32 mask) |
12abb8ba | 160 | { |
fcacdfbe | 161 | pci_msi_update_mask(desc, 0, mask); |
f2440d9a MW |
162 | } |
163 | ||
fcacdfbe | 164 | static inline void pci_msi_unmask(struct msi_desc *desc, u32 mask) |
5eb6d660 | 165 | { |
fcacdfbe TG |
166 | pci_msi_update_mask(desc, mask, 0); |
167 | } | |
d7cc609f | 168 | |
446a98b1 TG |
169 | static inline void __iomem *pci_msix_desc_addr(struct msi_desc *desc) |
170 | { | |
171 | return desc->mask_base + desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
5eb6d660 CH |
172 | } |
173 | ||
f2440d9a | 174 | /* |
fcacdfbe TG |
175 | * This internal function does not flush PCI writes to the device. All |
176 | * users must ensure that they read from the device before either assuming | |
177 | * that the device state is up to date, or returning out of this file. | |
178 | * It does not affect the msi_desc::msix_ctrl cache either. Use with care! | |
f2440d9a | 179 | */ |
fcacdfbe | 180 | static void pci_msix_write_vector_ctrl(struct msi_desc *desc, u32 ctrl) |
f2440d9a | 181 | { |
fcacdfbe | 182 | void __iomem *desc_addr = pci_msix_desc_addr(desc); |
38737d82 | 183 | |
fcacdfbe TG |
184 | writel(ctrl, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL); |
185 | } | |
d7cc609f | 186 | |
fcacdfbe TG |
187 | static inline void pci_msix_mask(struct msi_desc *desc) |
188 | { | |
189 | desc->msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
190 | pci_msix_write_vector_ctrl(desc, desc->msix_ctrl); | |
191 | /* Flush write to device */ | |
192 | readl(desc->mask_base); | |
193 | } | |
12abb8ba | 194 | |
fcacdfbe TG |
195 | static inline void pci_msix_unmask(struct msi_desc *desc) |
196 | { | |
197 | desc->msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
198 | pci_msix_write_vector_ctrl(desc, desc->msix_ctrl); | |
12abb8ba HS |
199 | } |
200 | ||
fcacdfbe | 201 | static void __pci_msi_mask_desc(struct msi_desc *desc, u32 mask) |
12abb8ba | 202 | { |
fcacdfbe TG |
203 | if (pci_msi_ignore_mask || desc->msi_attrib.is_virtual) |
204 | return; | |
205 | ||
206 | if (desc->msi_attrib.is_msix) | |
207 | pci_msix_mask(desc); | |
208 | else if (desc->msi_attrib.maskbit) | |
209 | pci_msi_mask(desc, mask); | |
f2440d9a | 210 | } |
24d27553 | 211 | |
fcacdfbe | 212 | static void __pci_msi_unmask_desc(struct msi_desc *desc, u32 mask) |
f2440d9a | 213 | { |
fcacdfbe TG |
214 | if (pci_msi_ignore_mask || desc->msi_attrib.is_virtual) |
215 | return; | |
24d27553 | 216 | |
fcacdfbe TG |
217 | if (desc->msi_attrib.is_msix) |
218 | pci_msix_unmask(desc); | |
219 | else if (desc->msi_attrib.maskbit) | |
220 | pci_msi_unmask(desc, mask); | |
f2440d9a MW |
221 | } |
222 | ||
23ed8d57 | 223 | /** |
f6b6aefe | 224 | * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts |
23ed8d57 TG |
225 | * @data: pointer to irqdata associated to that interrupt |
226 | */ | |
227 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 228 | { |
446a98b1 TG |
229 | struct msi_desc *desc = irq_data_get_msi_desc(data); |
230 | ||
231 | __pci_msi_mask_desc(desc, BIT(data->irq - desc->irq)); | |
f2440d9a | 232 | } |
a4289dc2 | 233 | EXPORT_SYMBOL_GPL(pci_msi_mask_irq); |
f2440d9a | 234 | |
23ed8d57 | 235 | /** |
f6b6aefe | 236 | * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts |
23ed8d57 TG |
237 | * @data: pointer to irqdata associated to that interrupt |
238 | */ | |
239 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 240 | { |
446a98b1 TG |
241 | struct msi_desc *desc = irq_data_get_msi_desc(data); |
242 | ||
243 | __pci_msi_unmask_desc(desc, BIT(data->irq - desc->irq)); | |
1da177e4 | 244 | } |
a4289dc2 | 245 | EXPORT_SYMBOL_GPL(pci_msi_unmask_irq); |
1da177e4 | 246 | |
ac8344c4 D |
247 | void default_restore_msi_irqs(struct pci_dev *dev) |
248 | { | |
249 | struct msi_desc *entry; | |
250 | ||
5004e98a | 251 | for_each_pci_msi_entry(entry, dev) |
ac8344c4 | 252 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
253 | } |
254 | ||
891d4a48 | 255 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 256 | { |
e39758e0 JL |
257 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
258 | ||
259 | BUG_ON(dev->current_state != PCI_D0); | |
30da5524 BH |
260 | |
261 | if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 262 | void __iomem *base = pci_msix_desc_addr(entry); |
30da5524 | 263 | |
b296abab | 264 | if (WARN_ON_ONCE(entry->msi_attrib.is_virtual)) |
d7cc609f | 265 | return; |
d7cc609f | 266 | |
30da5524 BH |
267 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); |
268 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
269 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
270 | } else { | |
f5322169 | 271 | int pos = dev->msi_cap; |
30da5524 BH |
272 | u16 data; |
273 | ||
9925ad0c BH |
274 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
275 | &msg->address_lo); | |
30da5524 | 276 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
277 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
278 | &msg->address_hi); | |
2f221349 | 279 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
280 | } else { |
281 | msg->address_hi = 0; | |
2f221349 | 282 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
283 | } |
284 | msg->data = data; | |
285 | } | |
286 | } | |
287 | ||
83a18912 | 288 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 289 | { |
e39758e0 JL |
290 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
291 | ||
0170591b | 292 | if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) { |
fcd097f3 BH |
293 | /* Don't touch the hardware now */ |
294 | } else if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 295 | void __iomem *base = pci_msix_desc_addr(entry); |
446a98b1 TG |
296 | u32 ctrl = entry->msix_ctrl; |
297 | bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT); | |
24d27553 | 298 | |
b296abab | 299 | if (entry->msi_attrib.is_virtual) |
d7cc609f LG |
300 | goto skip; |
301 | ||
da181dc9 TG |
302 | /* |
303 | * The specification mandates that the entry is masked | |
304 | * when the message is modified: | |
305 | * | |
306 | * "If software changes the Address or Data value of an | |
307 | * entry while the entry is unmasked, the result is | |
308 | * undefined." | |
309 | */ | |
310 | if (unmasked) | |
446a98b1 | 311 | pci_msix_write_vector_ctrl(entry, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT); |
da181dc9 | 312 | |
2c21fd4b HS |
313 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
314 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
315 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
da181dc9 TG |
316 | |
317 | if (unmasked) | |
446a98b1 | 318 | pci_msix_write_vector_ctrl(entry, ctrl); |
b9255a7c TG |
319 | |
320 | /* Ensure that the writes are visible in the device */ | |
321 | readl(base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 322 | } else { |
f5322169 | 323 | int pos = dev->msi_cap; |
1c8d7b0a MW |
324 | u16 msgctl; |
325 | ||
f84ecd28 | 326 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
327 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
328 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 329 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 330 | |
9925ad0c BH |
331 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
332 | msg->address_lo); | |
0366f8f7 | 333 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
334 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
335 | msg->address_hi); | |
2f221349 BH |
336 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
337 | msg->data); | |
0366f8f7 | 338 | } else { |
2f221349 BH |
339 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
340 | msg->data); | |
0366f8f7 | 341 | } |
b9255a7c TG |
342 | /* Ensure that the writes are visible in the device */ |
343 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
1da177e4 | 344 | } |
d7cc609f LG |
345 | |
346 | skip: | |
392ee1e6 | 347 | entry->msg = *msg; |
d7cc609f LG |
348 | |
349 | if (entry->write_msi_msg) | |
350 | entry->write_msi_msg(entry, entry->write_msi_msg_data); | |
351 | ||
1da177e4 | 352 | } |
0366f8f7 | 353 | |
83a18912 | 354 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 355 | { |
dced35ae | 356 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 357 | |
83a18912 | 358 | __pci_write_msi_msg(entry, msg); |
3145e941 | 359 | } |
83a18912 | 360 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 361 | |
f56e4481 HS |
362 | static void free_msi_irqs(struct pci_dev *dev) |
363 | { | |
5004e98a | 364 | struct list_head *msi_list = dev_to_msi_list(&dev->dev); |
f56e4481 | 365 | struct msi_desc *entry, *tmp; |
2f170814 | 366 | int i; |
f56e4481 | 367 | |
5004e98a | 368 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
369 | if (entry->irq) |
370 | for (i = 0; i < entry->nvec_used; i++) | |
371 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 | 372 | |
8e047ada | 373 | pci_msi_teardown_msi_irqs(dev); |
f56e4481 | 374 | |
5004e98a | 375 | list_for_each_entry_safe(entry, tmp, msi_list, list) { |
f56e4481 | 376 | if (entry->msi_attrib.is_msix) { |
5004e98a | 377 | if (list_is_last(&entry->list, msi_list)) |
f56e4481 HS |
378 | iounmap(entry->mask_base); |
379 | } | |
424eb391 | 380 | |
f56e4481 | 381 | list_del(&entry->list); |
81efbadd | 382 | free_msi_entry(entry); |
f56e4481 | 383 | } |
1c51b50c GKH |
384 | |
385 | if (dev->msi_irq_groups) { | |
2f170814 | 386 | msi_destroy_sysfs(&dev->dev, dev->msi_irq_groups); |
1c51b50c GKH |
387 | dev->msi_irq_groups = NULL; |
388 | } | |
f56e4481 | 389 | } |
c54c1879 | 390 | |
ba698ad4 DM |
391 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
392 | { | |
393 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
394 | pci_intx(dev, enable); | |
395 | } | |
396 | ||
830dfe88 BH |
397 | static void pci_msi_set_enable(struct pci_dev *dev, int enable) |
398 | { | |
399 | u16 control; | |
400 | ||
401 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
402 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
403 | if (enable) | |
404 | control |= PCI_MSI_FLAGS_ENABLE; | |
405 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
406 | } | |
407 | ||
8fed4b65 | 408 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 409 | { |
41017f0c | 410 | u16 control; |
392ee1e6 | 411 | struct msi_desc *entry; |
41017f0c | 412 | |
b1cbf4e4 EB |
413 | if (!dev->msi_enabled) |
414 | return; | |
415 | ||
dced35ae | 416 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 417 | |
ba698ad4 | 418 | pci_intx_for_msi(dev, 0); |
61b64abd | 419 | pci_msi_set_enable(dev, 0); |
ac8344c4 | 420 | arch_restore_msi_irqs(dev); |
392ee1e6 | 421 | |
f5322169 | 422 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
446a98b1 | 423 | pci_msi_update_mask(entry, 0, 0); |
abad2ec9 | 424 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 425 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 426 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
427 | } |
428 | ||
830dfe88 BH |
429 | static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) |
430 | { | |
431 | u16 ctrl; | |
432 | ||
433 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
434 | ctrl &= ~clear; | |
435 | ctrl |= set; | |
436 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
437 | } | |
438 | ||
8fed4b65 | 439 | static void __pci_restore_msix_state(struct pci_dev *dev) |
41017f0c | 440 | { |
41017f0c | 441 | struct msi_desc *entry; |
41017f0c | 442 | |
ded86d8d EB |
443 | if (!dev->msix_enabled) |
444 | return; | |
5004e98a | 445 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
ded86d8d | 446 | |
41017f0c | 447 | /* route the table */ |
ba698ad4 | 448 | pci_intx_for_msi(dev, 0); |
61b64abd | 449 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 450 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
41017f0c | 451 | |
ac8344c4 | 452 | arch_restore_msi_irqs(dev); |
5004e98a | 453 | for_each_pci_msi_entry(entry, dev) |
446a98b1 | 454 | pci_msix_write_vector_ctrl(entry, entry->msix_ctrl); |
41017f0c | 455 | |
61b64abd | 456 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 457 | } |
8fed4b65 ME |
458 | |
459 | void pci_restore_msi_state(struct pci_dev *dev) | |
460 | { | |
461 | __pci_restore_msi_state(dev); | |
462 | __pci_restore_msix_state(dev); | |
463 | } | |
94688cf2 | 464 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 465 | |
e75eafb9 | 466 | static struct msi_desc * |
c66d4bd1 | 467 | msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd) |
d873b4d4 | 468 | { |
bec04037 | 469 | struct irq_affinity_desc *masks = NULL; |
d873b4d4 | 470 | struct msi_desc *entry; |
e75eafb9 TG |
471 | u16 control; |
472 | ||
8e1101d2 | 473 | if (affd) |
61e1c590 | 474 | masks = irq_create_affinity_masks(nvec, affd); |
8e1101d2 | 475 | |
d873b4d4 | 476 | /* MSI Entry Initialization */ |
e75eafb9 | 477 | entry = alloc_msi_entry(&dev->dev, nvec, masks); |
d873b4d4 | 478 | if (!entry) |
e75eafb9 | 479 | goto out; |
d873b4d4 YW |
480 | |
481 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
482 | ||
483 | entry->msi_attrib.is_msix = 0; | |
484 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
d7cc609f | 485 | entry->msi_attrib.is_virtual = 0; |
d873b4d4 YW |
486 | entry->msi_attrib.entry_nr = 0; |
487 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
488 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 489 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e | 490 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
d873b4d4 YW |
491 | |
492 | if (control & PCI_MSI_FLAGS_64BIT) | |
493 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
494 | else | |
495 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
496 | ||
497 | /* Save the initial mask status */ | |
498 | if (entry->msi_attrib.maskbit) | |
67961e77 | 499 | pci_read_config_dword(dev, entry->mask_pos, &entry->msi_mask); |
d873b4d4 | 500 | |
e75eafb9 TG |
501 | out: |
502 | kfree(masks); | |
d873b4d4 YW |
503 | return entry; |
504 | } | |
505 | ||
f144d149 BH |
506 | static int msi_verify_entries(struct pci_dev *dev) |
507 | { | |
508 | struct msi_desc *entry; | |
509 | ||
a6e8b946 TG |
510 | if (!dev->no_64bit_msi) |
511 | return 0; | |
512 | ||
5004e98a | 513 | for_each_pci_msi_entry(entry, dev) { |
a6e8b946 | 514 | if (entry->msg.address_hi) { |
2053230a VS |
515 | pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", |
516 | entry->msg.address_hi, entry->msg.address_lo); | |
517 | return -EIO; | |
518 | } | |
f144d149 BH |
519 | } |
520 | return 0; | |
521 | } | |
522 | ||
1da177e4 LT |
523 | /** |
524 | * msi_capability_init - configure device's MSI capability structure | |
525 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 526 | * @nvec: number of interrupts to allocate |
f6b6aefe | 527 | * @affd: description of automatic IRQ affinity assignments (may be %NULL) |
1da177e4 | 528 | * |
1c8d7b0a MW |
529 | * Setup the MSI capability structure of the device with the requested |
530 | * number of interrupts. A return value of zero indicates the successful | |
f6b6aefe | 531 | * setup of an entry with the new MSI IRQ. A negative return value indicates |
1c8d7b0a MW |
532 | * an error, and a positive return value indicates the number of interrupts |
533 | * which could have been allocated. | |
534 | */ | |
61e1c590 | 535 | static int msi_capability_init(struct pci_dev *dev, int nvec, |
c66d4bd1 | 536 | struct irq_affinity *affd) |
1da177e4 | 537 | { |
2b94b6b7 | 538 | const struct attribute_group **groups; |
1da177e4 | 539 | struct msi_desc *entry; |
f465136d | 540 | int ret; |
1da177e4 | 541 | |
61b64abd | 542 | pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 543 | |
61e1c590 | 544 | entry = msi_setup_entry(dev, nvec, affd); |
f7feaca7 EB |
545 | if (!entry) |
546 | return -ENOMEM; | |
1ce03373 | 547 | |
f6b6aefe | 548 | /* All MSIs are unmasked by default; mask them all */ |
446a98b1 | 549 | pci_msi_mask(entry, msi_multi_mask(entry)); |
f2440d9a | 550 | |
5004e98a | 551 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
9c831334 | 552 | |
1da177e4 | 553 | /* Configure MSI capability structure */ |
8e047ada | 554 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
8eb5ce3f TG |
555 | if (ret) |
556 | goto err; | |
f7feaca7 | 557 | |
f144d149 | 558 | ret = msi_verify_entries(dev); |
8eb5ce3f TG |
559 | if (ret) |
560 | goto err; | |
f144d149 | 561 | |
2b94b6b7 WH |
562 | groups = msi_populate_sysfs(&dev->dev); |
563 | if (IS_ERR(groups)) { | |
564 | ret = PTR_ERR(groups); | |
8eb5ce3f | 565 | goto err; |
da8d1c8b NH |
566 | } |
567 | ||
2b94b6b7 WH |
568 | dev->msi_irq_groups = groups; |
569 | ||
f6b6aefe | 570 | /* Set MSI enabled bits */ |
ba698ad4 | 571 | pci_intx_for_msi(dev, 0); |
61b64abd | 572 | pci_msi_set_enable(dev, 1); |
b1cbf4e4 | 573 | dev->msi_enabled = 1; |
1da177e4 | 574 | |
5f226991 | 575 | pcibios_free_irq(dev); |
7fe3730d | 576 | dev->irq = entry->irq; |
1da177e4 | 577 | return 0; |
8eb5ce3f TG |
578 | |
579 | err: | |
446a98b1 | 580 | pci_msi_unmask(entry, msi_multi_mask(entry)); |
8eb5ce3f TG |
581 | free_msi_irqs(dev); |
582 | return ret; | |
1da177e4 LT |
583 | } |
584 | ||
520fe9dc | 585 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 586 | { |
4302e0fb | 587 | resource_size_t phys_addr; |
5a05a9d8 | 588 | u32 table_offset; |
6a878e50 | 589 | unsigned long flags; |
5a05a9d8 HS |
590 | u8 bir; |
591 | ||
909094c6 BH |
592 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
593 | &table_offset); | |
4d18760c | 594 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
6a878e50 YW |
595 | flags = pci_resource_flags(dev, bir); |
596 | if (!flags || (flags & IORESOURCE_UNSET)) | |
597 | return NULL; | |
598 | ||
4d18760c | 599 | table_offset &= PCI_MSIX_TABLE_OFFSET; |
5a05a9d8 HS |
600 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
601 | ||
4bdc0d67 | 602 | return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
5a05a9d8 HS |
603 | } |
604 | ||
520fe9dc | 605 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
e75eafb9 | 606 | struct msix_entry *entries, int nvec, |
c66d4bd1 | 607 | struct irq_affinity *affd) |
d9d7070e | 608 | { |
bec04037 | 609 | struct irq_affinity_desc *curmsk, *masks = NULL; |
d9d7070e | 610 | struct msi_desc *entry; |
7d5ec3d3 | 611 | void __iomem *addr; |
e75eafb9 | 612 | int ret, i; |
d7cc609f | 613 | int vec_count = pci_msix_vec_count(dev); |
4ef33685 | 614 | |
8e1101d2 | 615 | if (affd) |
61e1c590 | 616 | masks = irq_create_affinity_masks(nvec, affd); |
4ef33685 | 617 | |
e75eafb9 TG |
618 | for (i = 0, curmsk = masks; i < nvec; i++) { |
619 | entry = alloc_msi_entry(&dev->dev, 1, curmsk); | |
d9d7070e HS |
620 | if (!entry) { |
621 | if (!i) | |
622 | iounmap(base); | |
623 | else | |
624 | free_msi_irqs(dev); | |
625 | /* No enough memory. Don't try again */ | |
e75eafb9 TG |
626 | ret = -ENOMEM; |
627 | goto out; | |
d9d7070e HS |
628 | } |
629 | ||
630 | entry->msi_attrib.is_msix = 1; | |
631 | entry->msi_attrib.is_64 = 1; | |
7d5ec3d3 | 632 | |
3ac020e0 CH |
633 | if (entries) |
634 | entry->msi_attrib.entry_nr = entries[i].entry; | |
635 | else | |
636 | entry->msi_attrib.entry_nr = i; | |
d7cc609f LG |
637 | |
638 | entry->msi_attrib.is_virtual = | |
639 | entry->msi_attrib.entry_nr >= vec_count; | |
640 | ||
d9d7070e | 641 | entry->msi_attrib.default_irq = dev->irq; |
d9d7070e HS |
642 | entry->mask_base = base; |
643 | ||
b296abab TG |
644 | if (!entry->msi_attrib.is_virtual) { |
645 | addr = pci_msix_desc_addr(entry); | |
67961e77 | 646 | entry->msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL); |
b296abab | 647 | } |
7d5ec3d3 | 648 | |
5004e98a | 649 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
e75eafb9 TG |
650 | if (masks) |
651 | curmsk++; | |
d9d7070e | 652 | } |
e75eafb9 TG |
653 | ret = 0; |
654 | out: | |
655 | kfree(masks); | |
3adfb572 | 656 | return ret; |
d9d7070e HS |
657 | } |
658 | ||
7d5ec3d3 | 659 | static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries) |
75cb3426 HS |
660 | { |
661 | struct msi_desc *entry; | |
75cb3426 | 662 | |
5004e98a | 663 | for_each_pci_msi_entry(entry, dev) { |
7d5ec3d3 TG |
664 | if (entries) { |
665 | entries->vector = entry->irq; | |
666 | entries++; | |
667 | } | |
668 | } | |
669 | } | |
d7cc609f | 670 | |
7d5ec3d3 TG |
671 | static void msix_mask_all(void __iomem *base, int tsize) |
672 | { | |
673 | u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
674 | int i; | |
d7cc609f | 675 | |
1a519dc7 MMG |
676 | if (pci_msi_ignore_mask) |
677 | return; | |
678 | ||
7d5ec3d3 TG |
679 | for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE) |
680 | writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL); | |
75cb3426 HS |
681 | } |
682 | ||
1da177e4 LT |
683 | /** |
684 | * msix_capability_init - configure device's MSI-X capability | |
685 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
686 | * @entries: pointer to an array of struct msix_entry entries |
687 | * @nvec: number of @entries | |
f6b6aefe | 688 | * @affd: Optional pointer to enable automatic affinity assignment |
1da177e4 | 689 | * |
eaae4b3a | 690 | * Setup the MSI-X capability structure of device function with a |
f6b6aefe BH |
691 | * single MSI-X IRQ. A return of zero indicates the successful setup of |
692 | * requested MSI-X entries with allocated IRQs or non-zero for otherwise. | |
1da177e4 | 693 | **/ |
e75eafb9 | 694 | static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries, |
c66d4bd1 | 695 | int nvec, struct irq_affinity *affd) |
1da177e4 | 696 | { |
2b94b6b7 | 697 | const struct attribute_group **groups; |
1da177e4 | 698 | void __iomem *base; |
7d5ec3d3 TG |
699 | int ret, tsize; |
700 | u16 control; | |
1da177e4 | 701 | |
43855395 TG |
702 | /* |
703 | * Some devices require MSI-X to be enabled before the MSI-X | |
704 | * registers can be accessed. Mask all the vectors to prevent | |
705 | * interrupts coming in before they're fully set up. | |
706 | */ | |
707 | pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL | | |
708 | PCI_MSIX_FLAGS_ENABLE); | |
f598282f | 709 | |
66f0d0c4 | 710 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 711 | /* Request & Map MSI-X table region */ |
7d5ec3d3 TG |
712 | tsize = msix_table_size(control); |
713 | base = msix_map_region(dev, tsize); | |
43855395 TG |
714 | if (!base) { |
715 | ret = -ENOMEM; | |
716 | goto out_disable; | |
717 | } | |
1da177e4 | 718 | |
7d5ec3d3 TG |
719 | /* Ensure that all table entries are masked. */ |
720 | msix_mask_all(base, tsize); | |
721 | ||
61e1c590 | 722 | ret = msix_setup_entries(dev, base, entries, nvec, affd); |
d9d7070e | 723 | if (ret) |
43855395 | 724 | goto out_disable; |
9c831334 | 725 | |
8e047ada | 726 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
583871d4 | 727 | if (ret) |
2adc7907 | 728 | goto out_avail; |
9c831334 | 729 | |
f144d149 BH |
730 | /* Check if all MSI entries honor device restrictions */ |
731 | ret = msi_verify_entries(dev); | |
732 | if (ret) | |
733 | goto out_free; | |
734 | ||
7d5ec3d3 | 735 | msix_update_entries(dev, entries); |
f598282f | 736 | |
2b94b6b7 WH |
737 | groups = msi_populate_sysfs(&dev->dev); |
738 | if (IS_ERR(groups)) { | |
739 | ret = PTR_ERR(groups); | |
2adc7907 | 740 | goto out_free; |
2f170814 | 741 | } |
da8d1c8b | 742 | |
2b94b6b7 WH |
743 | dev->msi_irq_groups = groups; |
744 | ||
f598282f | 745 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 746 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 747 | dev->msix_enabled = 1; |
61b64abd | 748 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 749 | |
5f226991 | 750 | pcibios_free_irq(dev); |
1da177e4 | 751 | return 0; |
583871d4 | 752 | |
2adc7907 | 753 | out_avail: |
583871d4 HS |
754 | if (ret < 0) { |
755 | /* | |
f6b6aefe | 756 | * If we had some success, report the number of IRQs |
583871d4 HS |
757 | * we succeeded in setting up. |
758 | */ | |
d9d7070e | 759 | struct msi_desc *entry; |
583871d4 HS |
760 | int avail = 0; |
761 | ||
5004e98a | 762 | for_each_pci_msi_entry(entry, dev) { |
583871d4 HS |
763 | if (entry->irq != 0) |
764 | avail++; | |
765 | } | |
766 | if (avail != 0) | |
767 | ret = avail; | |
768 | } | |
769 | ||
2adc7907 | 770 | out_free: |
583871d4 HS |
771 | free_msi_irqs(dev); |
772 | ||
43855395 TG |
773 | out_disable: |
774 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); | |
775 | ||
583871d4 | 776 | return ret; |
1da177e4 LT |
777 | } |
778 | ||
24334a12 | 779 | /** |
a06cd74c | 780 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 781 | * @dev: pointer to the pci_dev data structure of MSI device function |
f6b6aefe | 782 | * @nvec: how many MSIs have been requested? |
24334a12 | 783 | * |
f7625980 | 784 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 785 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 786 | * supported return 1, else return 0. |
24334a12 | 787 | **/ |
a06cd74c | 788 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
789 | { |
790 | struct pci_bus *bus; | |
791 | ||
0306ebfa | 792 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 793 | if (!pci_msi_enable) |
a06cd74c | 794 | return 0; |
27e20603 | 795 | |
901c4ddb | 796 | if (!dev || dev->no_msi) |
a06cd74c | 797 | return 0; |
24334a12 | 798 | |
314e77b3 ME |
799 | /* |
800 | * You can't ask to have 0 or less MSIs configured. | |
801 | * a) it's stupid .. | |
802 | * b) the list manipulation code assumes nvec >= 1. | |
803 | */ | |
804 | if (nvec < 1) | |
a06cd74c | 805 | return 0; |
314e77b3 | 806 | |
500559a9 HS |
807 | /* |
808 | * Any bridge which does NOT route MSI transactions from its | |
809 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa | 810 | * the secondary pci_bus. |
61af6929 MZ |
811 | * |
812 | * The NO_MSI flag can either be set directly by: | |
813 | * - arch-specific PCI host bus controller drivers (deprecated) | |
814 | * - quirks for specific PCI bridges | |
815 | * | |
816 | * or indirectly by platform-specific PCI host bridge drivers by | |
817 | * advertising the 'msi_domain' property, which results in | |
818 | * the NO_MSI flag when no MSI domain is found for this bridge | |
819 | * at probe time. | |
0306ebfa | 820 | */ |
24334a12 BG |
821 | for (bus = dev->bus; bus; bus = bus->parent) |
822 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 823 | return 0; |
24334a12 | 824 | |
a06cd74c | 825 | return 1; |
24334a12 BG |
826 | } |
827 | ||
d1ac1d26 AG |
828 | /** |
829 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
830 | * @dev: device to report about | |
831 | * | |
832 | * This function returns the number of MSI vectors a device requested via | |
833 | * Multiple Message Capable register. It returns a negative errno if the | |
834 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
835 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
836 | * MSI specification. | |
837 | **/ | |
838 | int pci_msi_vec_count(struct pci_dev *dev) | |
839 | { | |
840 | int ret; | |
841 | u16 msgctl; | |
842 | ||
843 | if (!dev->msi_cap) | |
844 | return -EINVAL; | |
845 | ||
846 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
847 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
848 | ||
849 | return ret; | |
850 | } | |
851 | EXPORT_SYMBOL(pci_msi_vec_count); | |
852 | ||
688769f6 | 853 | static void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 854 | { |
f2440d9a | 855 | struct msi_desc *desc; |
1da177e4 | 856 | |
128bc5fc | 857 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
858 | return; |
859 | ||
5004e98a | 860 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
4a7cc831 | 861 | desc = first_pci_msi_entry(dev); |
110828c9 | 862 | |
61b64abd | 863 | pci_msi_set_enable(dev, 0); |
ba698ad4 | 864 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 865 | dev->msi_enabled = 0; |
7bd007e4 | 866 | |
12abb8ba | 867 | /* Return the device with MSI unmasked as initial states */ |
446a98b1 | 868 | pci_msi_unmask(desc, msi_multi_mask(desc)); |
e387b9ee | 869 | |
f6b6aefe | 870 | /* Restore dev->irq to its default pin-assertion IRQ */ |
f2440d9a | 871 | dev->irq = desc->msi_attrib.default_irq; |
5f226991 | 872 | pcibios_alloc_irq(dev); |
d52877c7 | 873 | } |
24d27553 | 874 | |
500559a9 | 875 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 876 | { |
d52877c7 YL |
877 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
878 | return; | |
879 | ||
880 | pci_msi_shutdown(dev); | |
f56e4481 | 881 | free_msi_irqs(dev); |
1da177e4 | 882 | } |
4cc086fa | 883 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 884 | |
a52e2e35 | 885 | /** |
ff1aa430 | 886 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 887 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
888 | * This function returns the number of device's MSI-X table entries and |
889 | * therefore the number of MSI-X vectors device is capable of sending. | |
890 | * It returns a negative errno if the device is not capable of sending MSI-X | |
891 | * interrupts. | |
892 | **/ | |
893 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 894 | { |
a52e2e35 RW |
895 | u16 control; |
896 | ||
520fe9dc | 897 | if (!dev->msix_cap) |
ff1aa430 | 898 | return -EINVAL; |
a52e2e35 | 899 | |
f84ecd28 | 900 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 901 | return msix_table_size(control); |
a52e2e35 | 902 | } |
ff1aa430 | 903 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 904 | |
e75eafb9 | 905 | static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, |
d7cc609f | 906 | int nvec, struct irq_affinity *affd, int flags) |
1da177e4 | 907 | { |
5ec09405 | 908 | int nr_entries; |
ded86d8d | 909 | int i, j; |
1da177e4 | 910 | |
901c4ddb | 911 | if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0) |
a06cd74c | 912 | return -EINVAL; |
c9953a73 | 913 | |
ff1aa430 AG |
914 | nr_entries = pci_msix_vec_count(dev); |
915 | if (nr_entries < 0) | |
916 | return nr_entries; | |
d7cc609f | 917 | if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL)) |
57fbf52c | 918 | return nr_entries; |
1da177e4 | 919 | |
3ac020e0 CH |
920 | if (entries) { |
921 | /* Check for any invalid entries */ | |
922 | for (i = 0; i < nvec; i++) { | |
923 | if (entries[i].entry >= nr_entries) | |
924 | return -EINVAL; /* invalid entry */ | |
925 | for (j = i + 1; j < nvec; j++) { | |
926 | if (entries[i].entry == entries[j].entry) | |
927 | return -EINVAL; /* duplicate entry */ | |
928 | } | |
1da177e4 LT |
929 | } |
930 | } | |
7bd007e4 | 931 | |
f6b6aefe | 932 | /* Check whether driver already requested for MSI IRQ */ |
500559a9 | 933 | if (dev->msi_enabled) { |
7506dc79 | 934 | pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
935 | return -EINVAL; |
936 | } | |
61e1c590 | 937 | return msix_capability_init(dev, entries, nvec, affd); |
e75eafb9 TG |
938 | } |
939 | ||
688769f6 | 940 | static void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 941 | { |
12abb8ba HS |
942 | struct msi_desc *entry; |
943 | ||
128bc5fc | 944 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
945 | return; |
946 | ||
0170591b KB |
947 | if (pci_dev_is_disconnected(dev)) { |
948 | dev->msix_enabled = 0; | |
949 | return; | |
950 | } | |
951 | ||
12abb8ba | 952 | /* Return the device with MSI-X masked as initial states */ |
689e6b53 | 953 | for_each_pci_msi_entry(entry, dev) |
446a98b1 | 954 | pci_msix_mask(entry); |
12abb8ba | 955 | |
61b64abd | 956 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 957 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 958 | dev->msix_enabled = 0; |
5f226991 | 959 | pcibios_alloc_irq(dev); |
d52877c7 | 960 | } |
c901851f | 961 | |
500559a9 | 962 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
963 | { |
964 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
965 | return; | |
966 | ||
967 | pci_msix_shutdown(dev); | |
f56e4481 | 968 | free_msi_irqs(dev); |
1da177e4 | 969 | } |
4cc086fa | 970 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 971 | |
309e57df MW |
972 | void pci_no_msi(void) |
973 | { | |
974 | pci_msi_enable = 0; | |
975 | } | |
c9953a73 | 976 | |
07ae95f9 AP |
977 | /** |
978 | * pci_msi_enabled - is MSI enabled? | |
979 | * | |
980 | * Returns true if MSI has not been disabled by the command-line option | |
981 | * pci=nomsi. | |
982 | **/ | |
983 | int pci_msi_enabled(void) | |
d389fec6 | 984 | { |
07ae95f9 | 985 | return pci_msi_enable; |
d389fec6 | 986 | } |
07ae95f9 | 987 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 988 | |
4ef33685 | 989 | static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, |
c66d4bd1 | 990 | struct irq_affinity *affd) |
302a2523 | 991 | { |
034cd97e | 992 | int nvec; |
302a2523 AG |
993 | int rc; |
994 | ||
901c4ddb | 995 | if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0) |
a06cd74c | 996 | return -EINVAL; |
034cd97e | 997 | |
f6b6aefe | 998 | /* Check whether driver already requested MSI-X IRQs */ |
034cd97e | 999 | if (dev->msix_enabled) { |
7506dc79 | 1000 | pci_info(dev, "can't enable MSI (MSI-X already enabled)\n"); |
034cd97e AG |
1001 | return -EINVAL; |
1002 | } | |
1003 | ||
302a2523 AG |
1004 | if (maxvec < minvec) |
1005 | return -ERANGE; | |
1006 | ||
4c1ef72e TZ |
1007 | if (WARN_ON_ONCE(dev->msi_enabled)) |
1008 | return -EINVAL; | |
1009 | ||
034cd97e AG |
1010 | nvec = pci_msi_vec_count(dev); |
1011 | if (nvec < 0) | |
1012 | return nvec; | |
4ef33685 | 1013 | if (nvec < minvec) |
948b7620 | 1014 | return -ENOSPC; |
4ef33685 CH |
1015 | |
1016 | if (nvec > maxvec) | |
034cd97e AG |
1017 | nvec = maxvec; |
1018 | ||
4ef33685 | 1019 | for (;;) { |
61e1c590 | 1020 | if (affd) { |
6f9a22bc | 1021 | nvec = irq_calc_affinity_vectors(minvec, nvec, affd); |
4ef33685 CH |
1022 | if (nvec < minvec) |
1023 | return -ENOSPC; | |
1024 | } | |
1025 | ||
61e1c590 | 1026 | rc = msi_capability_init(dev, nvec, affd); |
4ef33685 CH |
1027 | if (rc == 0) |
1028 | return nvec; | |
1029 | ||
4ef33685 | 1030 | if (rc < 0) |
302a2523 | 1031 | return rc; |
4ef33685 CH |
1032 | if (rc < minvec) |
1033 | return -ENOSPC; | |
1034 | ||
1035 | nvec = rc; | |
1036 | } | |
1037 | } | |
1038 | ||
4fe03955 CH |
1039 | /* deprecated, don't use */ |
1040 | int pci_enable_msi(struct pci_dev *dev) | |
4ef33685 | 1041 | { |
4fe03955 CH |
1042 | int rc = __pci_enable_msi_range(dev, 1, 1, NULL); |
1043 | if (rc < 0) | |
1044 | return rc; | |
1045 | return 0; | |
4ef33685 | 1046 | } |
4fe03955 | 1047 | EXPORT_SYMBOL(pci_enable_msi); |
4ef33685 CH |
1048 | |
1049 | static int __pci_enable_msix_range(struct pci_dev *dev, | |
61e1c590 | 1050 | struct msix_entry *entries, int minvec, |
d7cc609f LG |
1051 | int maxvec, struct irq_affinity *affd, |
1052 | int flags) | |
4ef33685 | 1053 | { |
e75eafb9 | 1054 | int rc, nvec = maxvec; |
4ef33685 CH |
1055 | |
1056 | if (maxvec < minvec) | |
1057 | return -ERANGE; | |
1058 | ||
4c1ef72e TZ |
1059 | if (WARN_ON_ONCE(dev->msix_enabled)) |
1060 | return -EINVAL; | |
1061 | ||
4ef33685 | 1062 | for (;;) { |
61e1c590 | 1063 | if (affd) { |
6f9a22bc | 1064 | nvec = irq_calc_affinity_vectors(minvec, nvec, affd); |
4ef33685 | 1065 | if (nvec < minvec) |
302a2523 | 1066 | return -ENOSPC; |
302a2523 | 1067 | } |
302a2523 | 1068 | |
d7cc609f | 1069 | rc = __pci_enable_msix(dev, entries, nvec, affd, flags); |
4ef33685 CH |
1070 | if (rc == 0) |
1071 | return nvec; | |
1072 | ||
4ef33685 CH |
1073 | if (rc < 0) |
1074 | return rc; | |
1075 | if (rc < minvec) | |
1076 | return -ENOSPC; | |
1077 | ||
1078 | nvec = rc; | |
1079 | } | |
302a2523 | 1080 | } |
302a2523 AG |
1081 | |
1082 | /** | |
1083 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1084 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1085 | * @entries: pointer to an array of MSI-X entries | |
f6b6aefe BH |
1086 | * @minvec: minimum number of MSI-X IRQs requested |
1087 | * @maxvec: maximum number of MSI-X IRQs requested | |
302a2523 AG |
1088 | * |
1089 | * Setup the MSI-X capability structure of device function with a maximum | |
1090 | * possible number of interrupts in the range between @minvec and @maxvec | |
1091 | * upon its software driver call to request for MSI-X mode enabled on its | |
1092 | * hardware device function. It returns a negative errno if an error occurs. | |
1093 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1094 | * indicates the successful configuration of MSI-X capability structure | |
1095 | * with new allocated MSI-X interrupts. | |
1096 | **/ | |
1097 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
4ef33685 | 1098 | int minvec, int maxvec) |
302a2523 | 1099 | { |
d7cc609f | 1100 | return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0); |
302a2523 AG |
1101 | } |
1102 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef | 1103 | |
aff17164 | 1104 | /** |
402723ad | 1105 | * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device |
aff17164 CH |
1106 | * @dev: PCI device to operate on |
1107 | * @min_vecs: minimum number of vectors required (must be >= 1) | |
1108 | * @max_vecs: maximum (desired) number of vectors | |
1109 | * @flags: flags or quirks for the allocation | |
402723ad | 1110 | * @affd: optional description of the affinity requirements |
aff17164 CH |
1111 | * |
1112 | * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI | |
1113 | * vectors if available, and fall back to a single legacy vector | |
1114 | * if neither is available. Return the number of vectors allocated, | |
1115 | * (which might be smaller than @max_vecs) if successful, or a negative | |
1116 | * error code on error. If less than @min_vecs interrupt vectors are | |
1117 | * available for @dev the function will fail with -ENOSPC. | |
1118 | * | |
1119 | * To get the Linux IRQ number used for a vector that can be passed to | |
1120 | * request_irq() use the pci_irq_vector() helper. | |
1121 | */ | |
402723ad CH |
1122 | int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
1123 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1124 | struct irq_affinity *affd) |
aff17164 | 1125 | { |
c66d4bd1 | 1126 | struct irq_affinity msi_default_affd = {0}; |
30ff3e8c | 1127 | int nvecs = -ENOSPC; |
aff17164 | 1128 | |
402723ad CH |
1129 | if (flags & PCI_IRQ_AFFINITY) { |
1130 | if (!affd) | |
1131 | affd = &msi_default_affd; | |
1132 | } else { | |
1133 | if (WARN_ON(affd)) | |
1134 | affd = NULL; | |
1135 | } | |
61e1c590 | 1136 | |
4fe0d154 | 1137 | if (flags & PCI_IRQ_MSIX) { |
30ff3e8c PS |
1138 | nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs, |
1139 | affd, flags); | |
1140 | if (nvecs > 0) | |
1141 | return nvecs; | |
aff17164 CH |
1142 | } |
1143 | ||
4fe0d154 | 1144 | if (flags & PCI_IRQ_MSI) { |
30ff3e8c PS |
1145 | nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd); |
1146 | if (nvecs > 0) | |
1147 | return nvecs; | |
aff17164 CH |
1148 | } |
1149 | ||
f6b6aefe | 1150 | /* use legacy IRQ if allowed */ |
862290f9 CH |
1151 | if (flags & PCI_IRQ_LEGACY) { |
1152 | if (min_vecs == 1 && dev->irq) { | |
c66d4bd1 ML |
1153 | /* |
1154 | * Invoke the affinity spreading logic to ensure that | |
1155 | * the device driver can adjust queue configuration | |
1156 | * for the single interrupt case. | |
1157 | */ | |
1158 | if (affd) | |
1159 | irq_create_affinity_masks(1, affd); | |
862290f9 CH |
1160 | pci_intx(dev, 1); |
1161 | return 1; | |
1162 | } | |
5d0bdf28 CH |
1163 | } |
1164 | ||
30ff3e8c | 1165 | return nvecs; |
aff17164 | 1166 | } |
402723ad | 1167 | EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); |
aff17164 CH |
1168 | |
1169 | /** | |
1170 | * pci_free_irq_vectors - free previously allocated IRQs for a device | |
1171 | * @dev: PCI device to operate on | |
1172 | * | |
1173 | * Undoes the allocations and enabling in pci_alloc_irq_vectors(). | |
1174 | */ | |
1175 | void pci_free_irq_vectors(struct pci_dev *dev) | |
1176 | { | |
1177 | pci_disable_msix(dev); | |
1178 | pci_disable_msi(dev); | |
1179 | } | |
1180 | EXPORT_SYMBOL(pci_free_irq_vectors); | |
1181 | ||
1182 | /** | |
1183 | * pci_irq_vector - return Linux IRQ number of a device vector | |
1184 | * @dev: PCI device to operate on | |
1185 | * @nr: device-relative interrupt vector index (0-based). | |
1186 | */ | |
1187 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1188 | { | |
1189 | if (dev->msix_enabled) { | |
1190 | struct msi_desc *entry; | |
1191 | int i = 0; | |
1192 | ||
1193 | for_each_pci_msi_entry(entry, dev) { | |
1194 | if (i == nr) | |
1195 | return entry->irq; | |
1196 | i++; | |
1197 | } | |
1198 | WARN_ON_ONCE(1); | |
1199 | return -EINVAL; | |
1200 | } | |
1201 | ||
1202 | if (dev->msi_enabled) { | |
1203 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1204 | ||
1205 | if (WARN_ON_ONCE(nr >= entry->nvec_used)) | |
1206 | return -EINVAL; | |
1207 | } else { | |
1208 | if (WARN_ON_ONCE(nr > 0)) | |
1209 | return -EINVAL; | |
1210 | } | |
1211 | ||
1212 | return dev->irq + nr; | |
1213 | } | |
1214 | EXPORT_SYMBOL(pci_irq_vector); | |
1215 | ||
ee8d41e5 | 1216 | /** |
f6b6aefe | 1217 | * pci_irq_get_affinity - return the affinity of a particular MSI vector |
ee8d41e5 TG |
1218 | * @dev: PCI device to operate on |
1219 | * @nr: device-relative interrupt vector index (0-based). | |
1220 | */ | |
1221 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr) | |
1222 | { | |
1223 | if (dev->msix_enabled) { | |
1224 | struct msi_desc *entry; | |
1225 | int i = 0; | |
1226 | ||
1227 | for_each_pci_msi_entry(entry, dev) { | |
1228 | if (i == nr) | |
bec04037 | 1229 | return &entry->affinity->mask; |
ee8d41e5 TG |
1230 | i++; |
1231 | } | |
1232 | WARN_ON_ONCE(1); | |
1233 | return NULL; | |
1234 | } else if (dev->msi_enabled) { | |
1235 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1236 | ||
d1d111e0 JB |
1237 | if (WARN_ON_ONCE(!entry || !entry->affinity || |
1238 | nr >= entry->nvec_used)) | |
ee8d41e5 TG |
1239 | return NULL; |
1240 | ||
bec04037 | 1241 | return &entry->affinity[nr].mask; |
ee8d41e5 TG |
1242 | } else { |
1243 | return cpu_possible_mask; | |
1244 | } | |
1245 | } | |
1246 | EXPORT_SYMBOL(pci_irq_get_affinity); | |
1247 | ||
25a98bd4 JL |
1248 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc) |
1249 | { | |
1250 | return to_pci_dev(desc->dev); | |
1251 | } | |
a4289dc2 | 1252 | EXPORT_SYMBOL(msi_desc_to_pci_dev); |
25a98bd4 | 1253 | |
c179c9b9 JL |
1254 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
1255 | { | |
1256 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); | |
1257 | ||
1258 | return dev->bus->sysdata; | |
1259 | } | |
1260 | EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata); | |
1261 | ||
3878eaef JL |
1262 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
1263 | /** | |
1264 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1265 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1266 | * @msg: Pointer to the message | |
1267 | */ | |
1268 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1269 | { | |
507a883e | 1270 | struct msi_desc *desc = irq_data_get_msi_desc(irq_data); |
3878eaef JL |
1271 | |
1272 | /* | |
1273 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1274 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1275 | */ | |
1276 | if (desc->irq == irq_data->irq) | |
1277 | __pci_write_msi_msg(desc, msg); | |
1278 | } | |
1279 | ||
1280 | /** | |
1281 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
f6b6aefe | 1282 | * @desc: Pointer to the MSI descriptor |
3878eaef JL |
1283 | * |
1284 | * The ID number is only used within the irqdomain. | |
1285 | */ | |
9006c133 | 1286 | static irq_hw_number_t pci_msi_domain_calc_hwirq(struct msi_desc *desc) |
3878eaef | 1287 | { |
dfb9eb7c TG |
1288 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); |
1289 | ||
3878eaef | 1290 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | |
4e544bac | 1291 | pci_dev_id(dev) << 11 | |
3878eaef JL |
1292 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; |
1293 | } | |
1294 | ||
1295 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1296 | { | |
1297 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1298 | } | |
1299 | ||
1300 | /** | |
f6b6aefe BH |
1301 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities |
1302 | * for @dev | |
3878eaef JL |
1303 | * @domain: The interrupt domain to check |
1304 | * @info: The domain info for verification | |
1305 | * @dev: The device to check | |
1306 | * | |
1307 | * Returns: | |
1308 | * 0 if the functionality is supported | |
1309 | * 1 if Multi MSI is requested, but the domain does not support it | |
1310 | * -ENOTSUPP otherwise | |
1311 | */ | |
1312 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1313 | struct msi_domain_info *info, struct device *dev) | |
1314 | { | |
1315 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1316 | ||
4fe03955 | 1317 | /* Special handling to support __pci_enable_msi_range() */ |
3878eaef JL |
1318 | if (pci_msi_desc_is_multi_msi(desc) && |
1319 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1320 | return 1; | |
1321 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1322 | return -ENOTSUPP; | |
1323 | ||
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1328 | struct msi_desc *desc, int error) | |
1329 | { | |
4fe03955 | 1330 | /* Special handling to support __pci_enable_msi_range() */ |
3878eaef JL |
1331 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) |
1332 | return 1; | |
1333 | ||
1334 | return error; | |
1335 | } | |
1336 | ||
3878eaef JL |
1337 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, |
1338 | struct msi_desc *desc) | |
1339 | { | |
1340 | arg->desc = desc; | |
dfb9eb7c | 1341 | arg->hwirq = pci_msi_domain_calc_hwirq(desc); |
3878eaef | 1342 | } |
3878eaef JL |
1343 | |
1344 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1345 | .set_desc = pci_msi_domain_set_desc, | |
1346 | .msi_check = pci_msi_domain_check_cap, | |
1347 | .handle_error = pci_msi_domain_handle_error, | |
1348 | }; | |
1349 | ||
1350 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1351 | { | |
1352 | struct msi_domain_ops *ops = info->ops; | |
1353 | ||
1354 | if (ops == NULL) { | |
1355 | info->ops = &pci_msi_domain_ops_default; | |
1356 | } else { | |
1357 | if (ops->set_desc == NULL) | |
1358 | ops->set_desc = pci_msi_domain_set_desc; | |
1359 | if (ops->msi_check == NULL) | |
1360 | ops->msi_check = pci_msi_domain_check_cap; | |
1361 | if (ops->handle_error == NULL) | |
1362 | ops->handle_error = pci_msi_domain_handle_error; | |
1363 | } | |
1364 | } | |
1365 | ||
1366 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1367 | { | |
1368 | struct irq_chip *chip = info->chip; | |
1369 | ||
1370 | BUG_ON(!chip); | |
1371 | if (!chip->irq_write_msi_msg) | |
1372 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
0701c53e MZ |
1373 | if (!chip->irq_mask) |
1374 | chip->irq_mask = pci_msi_mask_irq; | |
1375 | if (!chip->irq_unmask) | |
1376 | chip->irq_unmask = pci_msi_unmask_irq; | |
3878eaef JL |
1377 | } |
1378 | ||
1379 | /** | |
be5436c8 MZ |
1380 | * pci_msi_create_irq_domain - Create a MSI interrupt domain |
1381 | * @fwnode: Optional fwnode of the interrupt controller | |
3878eaef JL |
1382 | * @info: MSI domain info |
1383 | * @parent: Parent irq domain | |
1384 | * | |
1385 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1386 | * | |
1387 | * Returns: | |
1388 | * A domain pointer or NULL in case of failure. | |
1389 | */ | |
be5436c8 | 1390 | struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, |
3878eaef JL |
1391 | struct msi_domain_info *info, |
1392 | struct irq_domain *parent) | |
1393 | { | |
0380839d MZ |
1394 | struct irq_domain *domain; |
1395 | ||
6988e0e0 MZ |
1396 | if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE)) |
1397 | info->flags &= ~MSI_FLAG_LEVEL_CAPABLE; | |
1398 | ||
3878eaef JL |
1399 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
1400 | pci_msi_domain_update_dom_ops(info); | |
1401 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1402 | pci_msi_domain_update_chip_ops(info); | |
1403 | ||
f3b0946d | 1404 | info->flags |= MSI_FLAG_ACTIVATE_EARLY; |
25e960ef TG |
1405 | if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE)) |
1406 | info->flags |= MSI_FLAG_MUST_REACTIVATE; | |
f3b0946d | 1407 | |
923aa4c3 HK |
1408 | /* PCI-MSI is oneshot-safe */ |
1409 | info->chip->flags |= IRQCHIP_ONESHOT_SAFE; | |
1410 | ||
be5436c8 | 1411 | domain = msi_create_irq_domain(fwnode, info, parent); |
0380839d MZ |
1412 | if (!domain) |
1413 | return NULL; | |
1414 | ||
96f0d93a | 1415 | irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI); |
0380839d | 1416 | return domain; |
3878eaef | 1417 | } |
a4289dc2 | 1418 | EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain); |
3878eaef | 1419 | |
235b2c77 RM |
1420 | /* |
1421 | * Users of the generic MSI infrastructure expect a device to have a single ID, | |
1422 | * so with DMA aliases we have to pick the least-worst compromise. Devices with | |
1423 | * DMA phantom functions tend to still emit MSIs from the real function number, | |
1424 | * so we ignore those and only consider topological aliases where either the | |
1425 | * alias device or RID appears on a different bus number. We also make the | |
1426 | * reasonable assumption that bridges are walked in an upstream direction (so | |
1427 | * the last one seen wins), and the much braver assumption that the most likely | |
1428 | * case is that of PCI->PCIe so we should always use the alias RID. This echoes | |
1429 | * the logic from intel_irq_remapping's set_msi_sid(), which presumably works | |
1430 | * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions | |
1431 | * for taking ownership all we can really do is close our eyes and hope... | |
1432 | */ | |
b6eec9b7 DD |
1433 | static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data) |
1434 | { | |
1435 | u32 *pa = data; | |
235b2c77 RM |
1436 | u8 bus = PCI_BUS_NUM(*pa); |
1437 | ||
1438 | if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus) | |
1439 | *pa = alias; | |
b6eec9b7 | 1440 | |
b6eec9b7 DD |
1441 | return 0; |
1442 | } | |
235b2c77 | 1443 | |
b6eec9b7 DD |
1444 | /** |
1445 | * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID) | |
1446 | * @domain: The interrupt domain | |
1447 | * @pdev: The PCI device. | |
1448 | * | |
1449 | * The RID for a device is formed from the alias, with a firmware | |
1450 | * supplied mapping applied | |
1451 | * | |
1452 | * Returns: The RID. | |
1453 | */ | |
1454 | u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev) | |
1455 | { | |
1456 | struct device_node *of_node; | |
4e544bac | 1457 | u32 rid = pci_dev_id(pdev); |
b6eec9b7 DD |
1458 | |
1459 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
1460 | ||
1461 | of_node = irq_domain_get_of_node(domain); | |
2bcdd8f2 | 1462 | rid = of_node ? of_msi_map_id(&pdev->dev, of_node, rid) : |
39c3cf56 | 1463 | iort_msi_map_id(&pdev->dev, rid); |
b6eec9b7 DD |
1464 | |
1465 | return rid; | |
1466 | } | |
54fa97ee MZ |
1467 | |
1468 | /** | |
1469 | * pci_msi_get_device_domain - Get the MSI domain for a given PCI device | |
1470 | * @pdev: The PCI device | |
1471 | * | |
1472 | * Use the firmware data to find a device-specific MSI domain | |
235b2c77 | 1473 | * (i.e. not one that is set as a default). |
54fa97ee | 1474 | * |
235b2c77 | 1475 | * Returns: The corresponding MSI domain or NULL if none has been found. |
54fa97ee MZ |
1476 | */ |
1477 | struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) | |
1478 | { | |
be2021ba | 1479 | struct irq_domain *dom; |
4e544bac | 1480 | u32 rid = pci_dev_id(pdev); |
54fa97ee MZ |
1481 | |
1482 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
6f881aba | 1483 | dom = of_msi_map_get_device_domain(&pdev->dev, rid, DOMAIN_BUS_PCI_MSI); |
be2021ba | 1484 | if (!dom) |
d1718a1b LP |
1485 | dom = iort_get_device_domain(&pdev->dev, rid, |
1486 | DOMAIN_BUS_PCI_MSI); | |
be2021ba | 1487 | return dom; |
54fa97ee | 1488 | } |
2fd60266 TG |
1489 | |
1490 | /** | |
1491 | * pci_dev_has_special_msi_domain - Check whether the device is handled by | |
1492 | * a non-standard PCI-MSI domain | |
1493 | * @pdev: The PCI device to check. | |
1494 | * | |
1495 | * Returns: True if the device irqdomain or the bus irqdomain is | |
1496 | * non-standard PCI/MSI. | |
1497 | */ | |
1498 | bool pci_dev_has_special_msi_domain(struct pci_dev *pdev) | |
1499 | { | |
1500 | struct irq_domain *dom = dev_get_msi_domain(&pdev->dev); | |
1501 | ||
1502 | if (!dom) | |
1503 | dom = dev_get_msi_domain(&pdev->bus->dev); | |
1504 | ||
1505 | if (!dom) | |
1506 | return true; | |
1507 | ||
1508 | return dom->bus_token != DOMAIN_BUS_PCI_MSI; | |
1509 | } | |
1510 | ||
3878eaef | 1511 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |
cbc40d5c BH |
1512 | #endif /* CONFIG_PCI_MSI */ |
1513 | ||
1514 | void pci_msi_init(struct pci_dev *dev) | |
1515 | { | |
1516 | u16 ctrl; | |
1517 | ||
1518 | /* | |
1519 | * Disable the MSI hardware to avoid screaming interrupts | |
1520 | * during boot. This is the power on reset default so | |
1521 | * usually this should be a noop. | |
1522 | */ | |
1523 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1524 | if (!dev->msi_cap) | |
1525 | return; | |
1526 | ||
1527 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); | |
1528 | if (ctrl & PCI_MSI_FLAGS_ENABLE) | |
1529 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, | |
1530 | ctrl & ~PCI_MSI_FLAGS_ENABLE); | |
2053230a VS |
1531 | |
1532 | if (!(ctrl & PCI_MSI_FLAGS_64BIT)) | |
1533 | dev->no_64bit_msi = 1; | |
cbc40d5c BH |
1534 | } |
1535 | ||
1536 | void pci_msix_init(struct pci_dev *dev) | |
1537 | { | |
1538 | u16 ctrl; | |
1539 | ||
1540 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1541 | if (!dev->msix_cap) | |
1542 | return; | |
1543 | ||
1544 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
1545 | if (ctrl & PCI_MSIX_FLAGS_ENABLE) | |
1546 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, | |
1547 | ctrl & ~PCI_MSIX_FLAGS_ENABLE); | |
1548 | } |