Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
30 | int __attribute__ ((weak)) | |
31 | arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
32 | { | |
33 | return 0; | |
34 | } | |
35 | ||
36 | int __attribute__ ((weak)) | |
37 | arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *entry) | |
38 | { | |
39 | return 0; | |
40 | } | |
41 | ||
42 | int __attribute__ ((weak)) | |
43 | arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
44 | { | |
45 | struct msi_desc *entry; | |
46 | int ret; | |
47 | ||
48 | list_for_each_entry(entry, &dev->msi_list, list) { | |
49 | ret = arch_setup_msi_irq(dev, entry); | |
50 | if (ret) | |
51 | return ret; | |
52 | } | |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
57 | void __attribute__ ((weak)) arch_teardown_msi_irq(unsigned int irq) | |
58 | { | |
59 | return; | |
60 | } | |
61 | ||
62 | void __attribute__ ((weak)) | |
63 | arch_teardown_msi_irqs(struct pci_dev *dev) | |
64 | { | |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
68 | if (entry->irq != 0) | |
69 | arch_teardown_msi_irq(entry->irq); | |
70 | } | |
71 | } | |
72 | ||
5ca5c02f | 73 | static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 74 | { |
b1cbf4e4 EB |
75 | u16 control; |
76 | ||
b1cbf4e4 EB |
77 | if (pos) { |
78 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
79 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
80 | if (enable) | |
81 | control |= PCI_MSI_FLAGS_ENABLE; | |
82 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
83 | } | |
84 | } | |
85 | ||
5ca5c02f HS |
86 | static void msi_set_enable(struct pci_dev *dev, int enable) |
87 | { | |
88 | __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); | |
89 | } | |
90 | ||
b1cbf4e4 EB |
91 | static void msix_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | int pos; | |
94 | u16 control; | |
95 | ||
96 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
97 | if (pos) { | |
98 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
99 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
100 | if (enable) | |
101 | control |= PCI_MSIX_FLAGS_ENABLE; | |
102 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
103 | } | |
104 | } | |
105 | ||
bffac3c5 MW |
106 | /* |
107 | * Essentially, this is ((1 << (1 << x)) - 1), but without the | |
108 | * undefinedness of a << 32. | |
109 | */ | |
110 | static inline __attribute_const__ u32 msi_mask(unsigned x) | |
111 | { | |
112 | static const u32 mask[] = { 1, 2, 4, 0xf, 0xff, 0xffff, 0xffffffff }; | |
113 | return mask[x]; | |
114 | } | |
115 | ||
3145e941 | 116 | static void msix_flush_writes(struct irq_desc *desc) |
988cbb15 MW |
117 | { |
118 | struct msi_desc *entry; | |
119 | ||
3145e941 | 120 | entry = get_irq_desc_msi(desc); |
988cbb15 MW |
121 | BUG_ON(!entry || !entry->dev); |
122 | switch (entry->msi_attrib.type) { | |
123 | case PCI_CAP_ID_MSI: | |
124 | /* nothing to do */ | |
125 | break; | |
126 | case PCI_CAP_ID_MSIX: | |
127 | { | |
128 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
129 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
130 | readl(entry->mask_base + offset); | |
131 | break; | |
132 | } | |
133 | default: | |
134 | BUG(); | |
135 | break; | |
136 | } | |
137 | } | |
138 | ||
ce6fce42 MW |
139 | /* |
140 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
141 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
142 | * reliably as devices without an INTx disable bit will then generate a | |
143 | * level IRQ which will never be cleared. | |
144 | * | |
145 | * Returns 1 if it succeeded in masking the interrupt and 0 if the device | |
146 | * doesn't support MSI masking. | |
147 | */ | |
3145e941 | 148 | static int msi_set_mask_bits(struct irq_desc *desc, u32 mask, u32 flag) |
1da177e4 LT |
149 | { |
150 | struct msi_desc *entry; | |
151 | ||
3145e941 | 152 | entry = get_irq_desc_msi(desc); |
277bc33b | 153 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
154 | switch (entry->msi_attrib.type) { |
155 | case PCI_CAP_ID_MSI: | |
277bc33b | 156 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
157 | int pos; |
158 | u32 mask_bits; | |
277bc33b EB |
159 | |
160 | pos = (long)entry->mask_base; | |
161 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
8e149e09 YL |
162 | mask_bits &= ~(mask); |
163 | mask_bits |= flag & mask; | |
277bc33b | 164 | pci_write_config_dword(entry->dev, pos, mask_bits); |
58e0543e | 165 | } else { |
ce6fce42 | 166 | return 0; |
277bc33b | 167 | } |
1da177e4 | 168 | break; |
1da177e4 LT |
169 | case PCI_CAP_ID_MSIX: |
170 | { | |
171 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
172 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
173 | writel(flag, entry->mask_base + offset); | |
348e3fd1 | 174 | readl(entry->mask_base + offset); |
1da177e4 LT |
175 | break; |
176 | } | |
177 | default: | |
277bc33b | 178 | BUG(); |
1da177e4 LT |
179 | break; |
180 | } | |
392ee1e6 | 181 | entry->msi_attrib.masked = !!flag; |
ce6fce42 | 182 | return 1; |
1da177e4 LT |
183 | } |
184 | ||
3145e941 | 185 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 186 | { |
3145e941 | 187 | struct msi_desc *entry = get_irq_desc_msi(desc); |
0366f8f7 EB |
188 | switch(entry->msi_attrib.type) { |
189 | case PCI_CAP_ID_MSI: | |
190 | { | |
191 | struct pci_dev *dev = entry->dev; | |
192 | int pos = entry->msi_attrib.pos; | |
193 | u16 data; | |
194 | ||
195 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
196 | &msg->address_lo); | |
197 | if (entry->msi_attrib.is_64) { | |
198 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
199 | &msg->address_hi); | |
200 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
201 | } else { | |
202 | msg->address_hi = 0; | |
cbf5d9e6 | 203 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
204 | } |
205 | msg->data = data; | |
206 | break; | |
207 | } | |
208 | case PCI_CAP_ID_MSIX: | |
209 | { | |
210 | void __iomem *base; | |
211 | base = entry->mask_base + | |
212 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
213 | ||
214 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
215 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
216 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
217 | break; | |
218 | } | |
219 | default: | |
220 | BUG(); | |
221 | } | |
222 | } | |
1da177e4 | 223 | |
3145e941 | 224 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 225 | { |
3145e941 YL |
226 | struct irq_desc *desc = irq_to_desc(irq); |
227 | ||
228 | read_msi_msg_desc(desc, msg); | |
229 | } | |
230 | ||
231 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
232 | { | |
233 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
1da177e4 LT |
234 | switch (entry->msi_attrib.type) { |
235 | case PCI_CAP_ID_MSI: | |
236 | { | |
0366f8f7 EB |
237 | struct pci_dev *dev = entry->dev; |
238 | int pos = entry->msi_attrib.pos; | |
239 | ||
240 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
241 | msg->address_lo); | |
242 | if (entry->msi_attrib.is_64) { | |
243 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
244 | msg->address_hi); | |
245 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
246 | msg->data); | |
247 | } else { | |
248 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
249 | msg->data); | |
250 | } | |
1da177e4 LT |
251 | break; |
252 | } | |
253 | case PCI_CAP_ID_MSIX: | |
254 | { | |
0366f8f7 EB |
255 | void __iomem *base; |
256 | base = entry->mask_base + | |
257 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
258 | ||
259 | writel(msg->address_lo, | |
260 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
261 | writel(msg->address_hi, | |
262 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
263 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
264 | break; |
265 | } | |
266 | default: | |
0366f8f7 | 267 | BUG(); |
1da177e4 | 268 | } |
392ee1e6 | 269 | entry->msg = *msg; |
1da177e4 | 270 | } |
0366f8f7 | 271 | |
3145e941 YL |
272 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
273 | { | |
274 | struct irq_desc *desc = irq_to_desc(irq); | |
275 | ||
276 | write_msi_msg_desc(desc, msg); | |
277 | } | |
278 | ||
3b7d1921 | 279 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 280 | { |
3145e941 YL |
281 | struct irq_desc *desc = irq_to_desc(irq); |
282 | ||
283 | msi_set_mask_bits(desc, 1, 1); | |
284 | msix_flush_writes(desc); | |
1da177e4 LT |
285 | } |
286 | ||
3b7d1921 | 287 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 288 | { |
3145e941 YL |
289 | struct irq_desc *desc = irq_to_desc(irq); |
290 | ||
291 | msi_set_mask_bits(desc, 1, 0); | |
292 | msix_flush_writes(desc); | |
1da177e4 LT |
293 | } |
294 | ||
032de8e2 | 295 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 296 | |
1da177e4 LT |
297 | static struct msi_desc* alloc_msi_entry(void) |
298 | { | |
299 | struct msi_desc *entry; | |
300 | ||
3e916c05 | 301 | entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL); |
1da177e4 LT |
302 | if (!entry) |
303 | return NULL; | |
304 | ||
4aa9bc95 ME |
305 | INIT_LIST_HEAD(&entry->list); |
306 | entry->irq = 0; | |
1da177e4 LT |
307 | entry->dev = NULL; |
308 | ||
309 | return entry; | |
310 | } | |
311 | ||
ba698ad4 DM |
312 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
313 | { | |
314 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
315 | pci_intx(dev, enable); | |
316 | } | |
317 | ||
8fed4b65 | 318 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 319 | { |
392ee1e6 | 320 | int pos; |
41017f0c | 321 | u16 control; |
392ee1e6 | 322 | struct msi_desc *entry; |
41017f0c | 323 | |
b1cbf4e4 EB |
324 | if (!dev->msi_enabled) |
325 | return; | |
326 | ||
392ee1e6 EB |
327 | entry = get_irq_msi(dev->irq); |
328 | pos = entry->msi_attrib.pos; | |
41017f0c | 329 | |
ba698ad4 | 330 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 331 | msi_set_enable(dev, 0); |
392ee1e6 | 332 | write_msi_msg(dev->irq, &entry->msg); |
3145e941 YL |
333 | if (entry->msi_attrib.maskbit) { |
334 | struct irq_desc *desc = irq_to_desc(dev->irq); | |
335 | msi_set_mask_bits(desc, entry->msi_attrib.maskbits_mask, | |
8e149e09 | 336 | entry->msi_attrib.masked); |
3145e941 | 337 | } |
392ee1e6 EB |
338 | |
339 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
abad2ec9 JB |
340 | control &= ~PCI_MSI_FLAGS_QSIZE; |
341 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 342 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
343 | } |
344 | ||
345 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 346 | { |
41017f0c | 347 | int pos; |
41017f0c | 348 | struct msi_desc *entry; |
392ee1e6 | 349 | u16 control; |
41017f0c | 350 | |
ded86d8d EB |
351 | if (!dev->msix_enabled) |
352 | return; | |
353 | ||
41017f0c | 354 | /* route the table */ |
ba698ad4 | 355 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 356 | msix_set_enable(dev, 0); |
41017f0c | 357 | |
4aa9bc95 | 358 | list_for_each_entry(entry, &dev->msi_list, list) { |
3145e941 | 359 | struct irq_desc *desc = irq_to_desc(entry->irq); |
4aa9bc95 | 360 | write_msi_msg(entry->irq, &entry->msg); |
3145e941 | 361 | msi_set_mask_bits(desc, 1, entry->msi_attrib.masked); |
41017f0c | 362 | } |
41017f0c | 363 | |
314e77b3 ME |
364 | BUG_ON(list_empty(&dev->msi_list)); |
365 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
4aa9bc95 | 366 | pos = entry->msi_attrib.pos; |
392ee1e6 EB |
367 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
368 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
369 | control |= PCI_MSIX_FLAGS_ENABLE; | |
370 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 371 | } |
8fed4b65 ME |
372 | |
373 | void pci_restore_msi_state(struct pci_dev *dev) | |
374 | { | |
375 | __pci_restore_msi_state(dev); | |
376 | __pci_restore_msix_state(dev); | |
377 | } | |
94688cf2 | 378 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 379 | |
1da177e4 LT |
380 | /** |
381 | * msi_capability_init - configure device's MSI capability structure | |
382 | * @dev: pointer to the pci_dev data structure of MSI device function | |
383 | * | |
eaae4b3a | 384 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 385 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 386 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 387 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
388 | **/ |
389 | static int msi_capability_init(struct pci_dev *dev) | |
390 | { | |
391 | struct msi_desc *entry; | |
7fe3730d | 392 | int pos, ret; |
1da177e4 LT |
393 | u16 control; |
394 | ||
b1cbf4e4 EB |
395 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
396 | ||
1da177e4 LT |
397 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
398 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
399 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
400 | entry = alloc_msi_entry(); |
401 | if (!entry) | |
402 | return -ENOMEM; | |
1ce03373 | 403 | |
1da177e4 | 404 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 405 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
406 | entry->msi_attrib.entry_nr = 0; |
407 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 408 | entry->msi_attrib.masked = 1; |
1ce03373 | 409 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 410 | entry->msi_attrib.pos = pos; |
3b7d1921 EB |
411 | entry->dev = dev; |
412 | if (entry->msi_attrib.maskbit) { | |
0db29af1 HS |
413 | unsigned int base, maskbits, temp; |
414 | ||
415 | base = msi_mask_bits_reg(pos, entry->msi_attrib.is_64); | |
416 | entry->mask_base = (void __iomem *)(long)base; | |
417 | ||
3b7d1921 | 418 | /* All MSIs are unmasked by default, Mask them all */ |
0db29af1 | 419 | pci_read_config_dword(dev, base, &maskbits); |
bffac3c5 | 420 | temp = msi_mask((control & PCI_MSI_FLAGS_QMASK) >> 1); |
3b7d1921 | 421 | maskbits |= temp; |
0db29af1 | 422 | pci_write_config_dword(dev, base, maskbits); |
8e149e09 | 423 | entry->msi_attrib.maskbits_mask = temp; |
3b7d1921 | 424 | } |
0dd11f9b | 425 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 426 | |
1da177e4 | 427 | /* Configure MSI capability structure */ |
9c831334 | 428 | ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI); |
7fe3730d | 429 | if (ret) { |
032de8e2 | 430 | msi_free_irqs(dev); |
7fe3730d | 431 | return ret; |
fd58e55f | 432 | } |
f7feaca7 | 433 | |
1da177e4 | 434 | /* Set MSI enabled bits */ |
ba698ad4 | 435 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
436 | msi_set_enable(dev, 1); |
437 | dev->msi_enabled = 1; | |
1da177e4 | 438 | |
7fe3730d | 439 | dev->irq = entry->irq; |
1da177e4 LT |
440 | return 0; |
441 | } | |
442 | ||
443 | /** | |
444 | * msix_capability_init - configure device's MSI-X capability | |
445 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
446 | * @entries: pointer to an array of struct msix_entry entries |
447 | * @nvec: number of @entries | |
1da177e4 | 448 | * |
eaae4b3a | 449 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
450 | * single MSI-X irq. A return of zero indicates the successful setup of |
451 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
452 | **/ |
453 | static int msix_capability_init(struct pci_dev *dev, | |
454 | struct msix_entry *entries, int nvec) | |
455 | { | |
4aa9bc95 | 456 | struct msi_desc *entry; |
9c831334 | 457 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
458 | unsigned long phys_addr; |
459 | u32 table_offset; | |
1da177e4 LT |
460 | u16 control; |
461 | u8 bir; | |
462 | void __iomem *base; | |
463 | ||
b1cbf4e4 EB |
464 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
465 | ||
1da177e4 LT |
466 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
467 | /* Request & Map MSI-X table region */ | |
468 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
469 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
470 | |
471 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 472 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
473 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
474 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
475 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
476 | if (base == NULL) | |
477 | return -ENOMEM; | |
478 | ||
479 | /* MSI-X Table Initialization */ | |
480 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
481 | entry = alloc_msi_entry(); |
482 | if (!entry) | |
1da177e4 | 483 | break; |
1da177e4 LT |
484 | |
485 | j = entries[i].entry; | |
1da177e4 | 486 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 487 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
488 | entry->msi_attrib.entry_nr = j; |
489 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 490 | entry->msi_attrib.masked = 1; |
1ce03373 | 491 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 492 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
493 | entry->dev = dev; |
494 | entry->mask_base = base; | |
f7feaca7 | 495 | |
0dd11f9b | 496 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 497 | } |
9c831334 ME |
498 | |
499 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
500 | if (ret) { | |
501 | int avail = 0; | |
502 | list_for_each_entry(entry, &dev->msi_list, list) { | |
503 | if (entry->irq != 0) { | |
504 | avail++; | |
9c831334 | 505 | } |
1da177e4 | 506 | } |
9c831334 | 507 | |
032de8e2 ME |
508 | msi_free_irqs(dev); |
509 | ||
92db6d10 EB |
510 | /* If we had some success report the number of irqs |
511 | * we succeeded in setting up. | |
512 | */ | |
9c831334 ME |
513 | if (avail == 0) |
514 | avail = ret; | |
92db6d10 | 515 | return avail; |
1da177e4 | 516 | } |
9c831334 ME |
517 | |
518 | i = 0; | |
519 | list_for_each_entry(entry, &dev->msi_list, list) { | |
520 | entries[i].vector = entry->irq; | |
521 | set_irq_msi(entry->irq, entry); | |
522 | i++; | |
523 | } | |
1da177e4 | 524 | /* Set MSI-X enabled bits */ |
ba698ad4 | 525 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
526 | msix_set_enable(dev, 1); |
527 | dev->msix_enabled = 1; | |
1da177e4 LT |
528 | |
529 | return 0; | |
530 | } | |
531 | ||
24334a12 | 532 | /** |
17bbc12a | 533 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 534 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 535 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 536 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 537 | * |
0306ebfa | 538 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
539 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
540 | * supported return 0, else return an error code. | |
24334a12 | 541 | **/ |
c9953a73 | 542 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
543 | { |
544 | struct pci_bus *bus; | |
c9953a73 | 545 | int ret; |
24334a12 | 546 | |
0306ebfa | 547 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
548 | if (!pci_msi_enable || !dev || dev->no_msi) |
549 | return -EINVAL; | |
550 | ||
314e77b3 ME |
551 | /* |
552 | * You can't ask to have 0 or less MSIs configured. | |
553 | * a) it's stupid .. | |
554 | * b) the list manipulation code assumes nvec >= 1. | |
555 | */ | |
556 | if (nvec < 1) | |
557 | return -ERANGE; | |
558 | ||
0306ebfa BG |
559 | /* Any bridge which does NOT route MSI transactions from it's |
560 | * secondary bus to it's primary bus must set NO_MSI flag on | |
561 | * the secondary pci_bus. | |
562 | * We expect only arch-specific PCI host bus controller driver | |
563 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
564 | */ | |
24334a12 BG |
565 | for (bus = dev->bus; bus; bus = bus->parent) |
566 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
567 | return -EINVAL; | |
568 | ||
c9953a73 ME |
569 | ret = arch_msi_check_device(dev, nvec, type); |
570 | if (ret) | |
571 | return ret; | |
572 | ||
b1e2303d ME |
573 | if (!pci_find_capability(dev, type)) |
574 | return -EINVAL; | |
575 | ||
24334a12 BG |
576 | return 0; |
577 | } | |
578 | ||
1da177e4 LT |
579 | /** |
580 | * pci_enable_msi - configure device's MSI capability structure | |
581 | * @dev: pointer to the pci_dev data structure of MSI device function | |
582 | * | |
583 | * Setup the MSI capability structure of device function with | |
1ce03373 | 584 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
585 | * MSI mode enabled on its hardware device function. A return of zero |
586 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 587 | * irq or non-zero for otherwise. |
1da177e4 LT |
588 | **/ |
589 | int pci_enable_msi(struct pci_dev* dev) | |
590 | { | |
b1e2303d | 591 | int status; |
1da177e4 | 592 | |
c9953a73 ME |
593 | status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI); |
594 | if (status) | |
595 | return status; | |
1da177e4 | 596 | |
ded86d8d | 597 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 598 | |
1ce03373 | 599 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 | 600 | if (dev->msix_enabled) { |
80ccba11 BH |
601 | dev_info(&dev->dev, "can't enable MSI " |
602 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 603 | return -EINVAL; |
1da177e4 LT |
604 | } |
605 | status = msi_capability_init(dev); | |
1da177e4 LT |
606 | return status; |
607 | } | |
4cc086fa | 608 | EXPORT_SYMBOL(pci_enable_msi); |
1da177e4 | 609 | |
d52877c7 | 610 | void pci_msi_shutdown(struct pci_dev* dev) |
1da177e4 LT |
611 | { |
612 | struct msi_desc *entry; | |
1da177e4 | 613 | |
128bc5fc | 614 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
615 | return; |
616 | ||
b1cbf4e4 | 617 | msi_set_enable(dev, 0); |
ba698ad4 | 618 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 619 | dev->msi_enabled = 0; |
7bd007e4 | 620 | |
314e77b3 ME |
621 | BUG_ON(list_empty(&dev->msi_list)); |
622 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
8e149e09 YL |
623 | /* Return the the pci reset with msi irqs unmasked */ |
624 | if (entry->msi_attrib.maskbit) { | |
625 | u32 mask = entry->msi_attrib.maskbits_mask; | |
3145e941 YL |
626 | struct irq_desc *desc = irq_to_desc(dev->irq); |
627 | msi_set_mask_bits(desc, mask, ~mask); | |
8e149e09 | 628 | } |
d52877c7 | 629 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) |
1da177e4 | 630 | return; |
e387b9ee ME |
631 | |
632 | /* Restore dev->irq to its default pin-assertion irq */ | |
d52877c7 YL |
633 | dev->irq = entry->msi_attrib.default_irq; |
634 | } | |
635 | void pci_disable_msi(struct pci_dev* dev) | |
636 | { | |
637 | struct msi_desc *entry; | |
638 | ||
639 | if (!pci_msi_enable || !dev || !dev->msi_enabled) | |
640 | return; | |
641 | ||
642 | pci_msi_shutdown(dev); | |
643 | ||
644 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
645 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) | |
646 | return; | |
647 | ||
648 | msi_free_irqs(dev); | |
1da177e4 | 649 | } |
4cc086fa | 650 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 651 | |
032de8e2 | 652 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 653 | { |
032de8e2 | 654 | struct msi_desc *entry, *tmp; |
7ede9c1f | 655 | |
b3b7cc7b DM |
656 | list_for_each_entry(entry, &dev->msi_list, list) { |
657 | if (entry->irq) | |
658 | BUG_ON(irq_has_action(entry->irq)); | |
659 | } | |
1da177e4 | 660 | |
032de8e2 | 661 | arch_teardown_msi_irqs(dev); |
1da177e4 | 662 | |
032de8e2 ME |
663 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
664 | if (entry->msi_attrib.type == PCI_CAP_ID_MSIX) { | |
032de8e2 ME |
665 | writel(1, entry->mask_base + entry->msi_attrib.entry_nr |
666 | * PCI_MSIX_ENTRY_SIZE | |
667 | + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
78b7611c EB |
668 | |
669 | if (list_is_last(&entry->list, &dev->msi_list)) | |
670 | iounmap(entry->mask_base); | |
032de8e2 ME |
671 | } |
672 | list_del(&entry->list); | |
673 | kfree(entry); | |
1da177e4 LT |
674 | } |
675 | ||
676 | return 0; | |
677 | } | |
678 | ||
1da177e4 LT |
679 | /** |
680 | * pci_enable_msix - configure device's MSI-X capability structure | |
681 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 682 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 683 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
684 | * |
685 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 686 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
687 | * MSI-X mode enabled on its hardware device function. A return of zero |
688 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 689 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 690 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 691 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
692 | * its request. |
693 | **/ | |
694 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
695 | { | |
92db6d10 | 696 | int status, pos, nr_entries; |
ded86d8d | 697 | int i, j; |
1da177e4 | 698 | u16 control; |
1da177e4 | 699 | |
c9953a73 | 700 | if (!entries) |
1da177e4 LT |
701 | return -EINVAL; |
702 | ||
c9953a73 ME |
703 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
704 | if (status) | |
705 | return status; | |
706 | ||
b64c05e7 | 707 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1da177e4 | 708 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
1da177e4 LT |
709 | nr_entries = multi_msix_capable(control); |
710 | if (nvec > nr_entries) | |
711 | return -EINVAL; | |
712 | ||
713 | /* Check for any invalid entries */ | |
714 | for (i = 0; i < nvec; i++) { | |
715 | if (entries[i].entry >= nr_entries) | |
716 | return -EINVAL; /* invalid entry */ | |
717 | for (j = i + 1; j < nvec; j++) { | |
718 | if (entries[i].entry == entries[j].entry) | |
719 | return -EINVAL; /* duplicate entry */ | |
720 | } | |
721 | } | |
ded86d8d | 722 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 723 | |
1ce03373 | 724 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 725 | if (dev->msi_enabled) { |
80ccba11 BH |
726 | dev_info(&dev->dev, "can't enable MSI-X " |
727 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
728 | return -EINVAL; |
729 | } | |
1da177e4 | 730 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
731 | return status; |
732 | } | |
4cc086fa | 733 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 734 | |
fc4afc7b | 735 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 736 | { |
032de8e2 | 737 | msi_free_irqs(dev); |
fc4afc7b ME |
738 | } |
739 | ||
d52877c7 | 740 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 741 | { |
128bc5fc | 742 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
743 | return; |
744 | ||
b1cbf4e4 | 745 | msix_set_enable(dev, 0); |
ba698ad4 | 746 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 747 | dev->msix_enabled = 0; |
d52877c7 YL |
748 | } |
749 | void pci_disable_msix(struct pci_dev* dev) | |
750 | { | |
751 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
752 | return; | |
753 | ||
754 | pci_msix_shutdown(dev); | |
7bd007e4 | 755 | |
fc4afc7b | 756 | msix_free_all_irqs(dev); |
1da177e4 | 757 | } |
4cc086fa | 758 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
759 | |
760 | /** | |
1ce03373 | 761 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
762 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
763 | * | |
eaae4b3a | 764 | * Being called during hotplug remove, from which the device function |
1ce03373 | 765 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
766 | * allocated for this device function, are reclaimed to unused state, |
767 | * which may be used later on. | |
768 | **/ | |
769 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
770 | { | |
1da177e4 LT |
771 | if (!pci_msi_enable || !dev) |
772 | return; | |
773 | ||
032de8e2 ME |
774 | if (dev->msi_enabled) |
775 | msi_free_irqs(dev); | |
1da177e4 | 776 | |
fc4afc7b ME |
777 | if (dev->msix_enabled) |
778 | msix_free_all_irqs(dev); | |
1da177e4 LT |
779 | } |
780 | ||
309e57df MW |
781 | void pci_no_msi(void) |
782 | { | |
783 | pci_msi_enable = 0; | |
784 | } | |
c9953a73 | 785 | |
07ae95f9 AP |
786 | /** |
787 | * pci_msi_enabled - is MSI enabled? | |
788 | * | |
789 | * Returns true if MSI has not been disabled by the command-line option | |
790 | * pci=nomsi. | |
791 | **/ | |
792 | int pci_msi_enabled(void) | |
d389fec6 | 793 | { |
07ae95f9 | 794 | return pci_msi_enable; |
d389fec6 | 795 | } |
07ae95f9 | 796 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 797 | |
07ae95f9 | 798 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 799 | { |
07ae95f9 | 800 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 801 | } |