Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI Message Signaled Interrupt (MSI) |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
aff17164 | 7 | * Copyright (C) 2016 Christoph Hellwig. |
1da177e4 LT |
8 | */ |
9 | ||
1ce03373 | 10 | #include <linux/err.h> |
1da177e4 LT |
11 | #include <linux/mm.h> |
12 | #include <linux/irq.h> | |
13 | #include <linux/interrupt.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
be2021ba | 22 | #include <linux/acpi_iort.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
3878eaef | 24 | #include <linux/irqdomain.h> |
b6eec9b7 | 25 | #include <linux/of_irq.h> |
1da177e4 LT |
26 | |
27 | #include "pci.h" | |
1da177e4 | 28 | |
cbc40d5c BH |
29 | #ifdef CONFIG_PCI_MSI |
30 | ||
1da177e4 | 31 | static int pci_msi_enable = 1; |
38737d82 | 32 | int pci_msi_ignore_mask; |
1da177e4 | 33 | |
527eee29 BH |
34 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
35 | ||
8e047ada | 36 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
8e047ada JL |
37 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
38 | { | |
39 | struct irq_domain *domain; | |
40 | ||
47feb418 | 41 | domain = dev_get_msi_domain(&dev->dev); |
3845d295 | 42 | if (domain && irq_domain_is_hierarchy(domain)) |
699c4cec | 43 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); |
8e047ada JL |
44 | |
45 | return arch_setup_msi_irqs(dev, nvec, type); | |
46 | } | |
47 | ||
48 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) | |
49 | { | |
50 | struct irq_domain *domain; | |
51 | ||
47feb418 | 52 | domain = dev_get_msi_domain(&dev->dev); |
3845d295 | 53 | if (domain && irq_domain_is_hierarchy(domain)) |
699c4cec | 54 | msi_domain_free_irqs(domain, &dev->dev); |
8e047ada JL |
55 | else |
56 | arch_teardown_msi_irqs(dev); | |
57 | } | |
58 | #else | |
59 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs | |
60 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs | |
61 | #endif | |
527eee29 | 62 | |
077ee78e | 63 | #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS |
6a9e7f20 | 64 | /* Arch hooks */ |
4287d824 TP |
65 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
66 | { | |
2291ec09 | 67 | struct msi_controller *chip = dev->bus->msi; |
0cbdcfcf TR |
68 | int err; |
69 | ||
70 | if (!chip || !chip->setup_irq) | |
71 | return -EINVAL; | |
72 | ||
73 | err = chip->setup_irq(chip, dev, desc); | |
74 | if (err < 0) | |
75 | return err; | |
76 | ||
77 | irq_set_chip_data(desc->irq, chip); | |
78 | ||
79 | return 0; | |
4287d824 TP |
80 | } |
81 | ||
82 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 83 | { |
c2791b80 | 84 | struct msi_controller *chip = irq_get_chip_data(irq); |
0cbdcfcf TR |
85 | |
86 | if (!chip || !chip->teardown_irq) | |
87 | return; | |
88 | ||
89 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
90 | } |
91 | ||
4287d824 | 92 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 | 93 | { |
339e5b44 | 94 | struct msi_controller *chip = dev->bus->msi; |
6a9e7f20 AB |
95 | struct msi_desc *entry; |
96 | int ret; | |
97 | ||
339e5b44 LS |
98 | if (chip && chip->setup_irqs) |
99 | return chip->setup_irqs(chip, dev, nvec, type); | |
1c8d7b0a MW |
100 | /* |
101 | * If an architecture wants to support multiple MSI, it needs to | |
102 | * override arch_setup_msi_irqs() | |
103 | */ | |
104 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
105 | return 1; | |
106 | ||
5004e98a | 107 | for_each_pci_msi_entry(entry, dev) { |
6a9e7f20 | 108 | ret = arch_setup_msi_irq(dev, entry); |
b5fbf533 | 109 | if (ret < 0) |
6a9e7f20 | 110 | return ret; |
b5fbf533 ME |
111 | if (ret > 0) |
112 | return -ENOSPC; | |
6a9e7f20 AB |
113 | } |
114 | ||
115 | return 0; | |
116 | } | |
1525bf0d | 117 | |
4287d824 TP |
118 | /* |
119 | * We have a default implementation available as a separate non-weak | |
120 | * function, as it is used by the Xen x86 PCI code | |
121 | */ | |
1525bf0d | 122 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 123 | { |
63a7b17e | 124 | int i; |
6a9e7f20 AB |
125 | struct msi_desc *entry; |
126 | ||
5004e98a | 127 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
128 | if (entry->irq) |
129 | for (i = 0; i < entry->nvec_used; i++) | |
130 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
131 | } |
132 | ||
4287d824 TP |
133 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
134 | { | |
135 | return default_teardown_msi_irqs(dev); | |
136 | } | |
077ee78e | 137 | #endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */ |
76ccc297 | 138 | |
ac8344c4 | 139 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
140 | { |
141 | struct msi_desc *entry; | |
142 | ||
143 | entry = NULL; | |
144 | if (dev->msix_enabled) { | |
5004e98a | 145 | for_each_pci_msi_entry(entry, dev) { |
76ccc297 KRW |
146 | if (irq == entry->irq) |
147 | break; | |
148 | } | |
149 | } else if (dev->msi_enabled) { | |
150 | entry = irq_get_msi_desc(irq); | |
151 | } | |
152 | ||
153 | if (entry) | |
83a18912 | 154 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 155 | } |
4287d824 | 156 | |
ac8344c4 | 157 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 158 | { |
ac8344c4 | 159 | return default_restore_msi_irqs(dev); |
4287d824 | 160 | } |
76ccc297 | 161 | |
bffac3c5 MW |
162 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
163 | { | |
0b49ec37 MW |
164 | /* Don't shift by >= width of type */ |
165 | if (x >= 5) | |
166 | return 0xffffffff; | |
167 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
168 | } |
169 | ||
ce6fce42 MW |
170 | /* |
171 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
172 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
173 | * reliably as devices without an INTx disable bit will then generate a | |
174 | * level IRQ which will never be cleared. | |
ce6fce42 | 175 | */ |
23ed8d57 | 176 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 177 | { |
f2440d9a | 178 | u32 mask_bits = desc->masked; |
1da177e4 | 179 | |
38737d82 | 180 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 181 | return 0; |
f2440d9a MW |
182 | |
183 | mask_bits &= ~mask; | |
184 | mask_bits |= flag; | |
e39758e0 JL |
185 | pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, |
186 | mask_bits); | |
12abb8ba HS |
187 | |
188 | return mask_bits; | |
189 | } | |
190 | ||
191 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
192 | { | |
23ed8d57 | 193 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
f2440d9a MW |
194 | } |
195 | ||
5eb6d660 CH |
196 | static void __iomem *pci_msix_desc_addr(struct msi_desc *desc) |
197 | { | |
d7cc609f LG |
198 | if (desc->msi_attrib.is_virtual) |
199 | return NULL; | |
200 | ||
5eb6d660 CH |
201 | return desc->mask_base + |
202 | desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
203 | } | |
204 | ||
f2440d9a MW |
205 | /* |
206 | * This internal function does not flush PCI writes to the device. | |
207 | * All users must ensure that they read from the device before either | |
208 | * assuming that the device state is up to date, or returning out of this | |
209 | * file. This saves a few milliseconds when initialising devices with lots | |
210 | * of MSI-X interrupts. | |
211 | */ | |
23ed8d57 | 212 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
213 | { |
214 | u32 mask_bits = desc->masked; | |
d7cc609f | 215 | void __iomem *desc_addr; |
38737d82 YW |
216 | |
217 | if (pci_msi_ignore_mask) | |
218 | return 0; | |
e045fa29 | 219 | |
d7cc609f LG |
220 | desc_addr = pci_msix_desc_addr(desc); |
221 | if (!desc_addr) | |
222 | return 0; | |
38737d82 | 223 | |
8d805286 | 224 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
e045fa29 | 225 | if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT) |
8d805286 | 226 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; |
d7cc609f LG |
227 | |
228 | writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL); | |
12abb8ba HS |
229 | |
230 | return mask_bits; | |
231 | } | |
232 | ||
233 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
234 | { | |
23ed8d57 | 235 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
f2440d9a | 236 | } |
24d27553 | 237 | |
1c9db525 | 238 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 239 | { |
c391f262 | 240 | struct msi_desc *desc = irq_data_get_msi_desc(data); |
24d27553 | 241 | |
f2440d9a MW |
242 | if (desc->msi_attrib.is_msix) { |
243 | msix_mask_irq(desc, flag); | |
244 | readl(desc->mask_base); /* Flush write to device */ | |
245 | } else { | |
a281b788 | 246 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 247 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 248 | } |
f2440d9a MW |
249 | } |
250 | ||
23ed8d57 | 251 | /** |
f6b6aefe | 252 | * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts |
23ed8d57 TG |
253 | * @data: pointer to irqdata associated to that interrupt |
254 | */ | |
255 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 256 | { |
1c9db525 | 257 | msi_set_mask_bit(data, 1); |
f2440d9a | 258 | } |
a4289dc2 | 259 | EXPORT_SYMBOL_GPL(pci_msi_mask_irq); |
f2440d9a | 260 | |
23ed8d57 | 261 | /** |
f6b6aefe | 262 | * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts |
23ed8d57 TG |
263 | * @data: pointer to irqdata associated to that interrupt |
264 | */ | |
265 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 266 | { |
1c9db525 | 267 | msi_set_mask_bit(data, 0); |
1da177e4 | 268 | } |
a4289dc2 | 269 | EXPORT_SYMBOL_GPL(pci_msi_unmask_irq); |
1da177e4 | 270 | |
ac8344c4 D |
271 | void default_restore_msi_irqs(struct pci_dev *dev) |
272 | { | |
273 | struct msi_desc *entry; | |
274 | ||
5004e98a | 275 | for_each_pci_msi_entry(entry, dev) |
ac8344c4 | 276 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
277 | } |
278 | ||
891d4a48 | 279 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 280 | { |
e39758e0 JL |
281 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
282 | ||
283 | BUG_ON(dev->current_state != PCI_D0); | |
30da5524 BH |
284 | |
285 | if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 286 | void __iomem *base = pci_msix_desc_addr(entry); |
30da5524 | 287 | |
d7cc609f LG |
288 | if (!base) { |
289 | WARN_ON(1); | |
290 | return; | |
291 | } | |
292 | ||
30da5524 BH |
293 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); |
294 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
295 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
296 | } else { | |
f5322169 | 297 | int pos = dev->msi_cap; |
30da5524 BH |
298 | u16 data; |
299 | ||
9925ad0c BH |
300 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
301 | &msg->address_lo); | |
30da5524 | 302 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
303 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
304 | &msg->address_hi); | |
2f221349 | 305 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
306 | } else { |
307 | msg->address_hi = 0; | |
2f221349 | 308 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
309 | } |
310 | msg->data = data; | |
311 | } | |
312 | } | |
313 | ||
83a18912 | 314 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 315 | { |
e39758e0 JL |
316 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
317 | ||
0170591b | 318 | if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) { |
fcd097f3 BH |
319 | /* Don't touch the hardware now */ |
320 | } else if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 321 | void __iomem *base = pci_msix_desc_addr(entry); |
24d27553 | 322 | |
d7cc609f LG |
323 | if (!base) |
324 | goto skip; | |
325 | ||
2c21fd4b HS |
326 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
327 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
328 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 329 | } else { |
f5322169 | 330 | int pos = dev->msi_cap; |
1c8d7b0a MW |
331 | u16 msgctl; |
332 | ||
f84ecd28 | 333 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
334 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
335 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 336 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 337 | |
9925ad0c BH |
338 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
339 | msg->address_lo); | |
0366f8f7 | 340 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
341 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
342 | msg->address_hi); | |
2f221349 BH |
343 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
344 | msg->data); | |
0366f8f7 | 345 | } else { |
2f221349 BH |
346 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
347 | msg->data); | |
0366f8f7 | 348 | } |
1da177e4 | 349 | } |
d7cc609f LG |
350 | |
351 | skip: | |
392ee1e6 | 352 | entry->msg = *msg; |
d7cc609f LG |
353 | |
354 | if (entry->write_msi_msg) | |
355 | entry->write_msi_msg(entry, entry->write_msi_msg_data); | |
356 | ||
1da177e4 | 357 | } |
0366f8f7 | 358 | |
83a18912 | 359 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 360 | { |
dced35ae | 361 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 362 | |
83a18912 | 363 | __pci_write_msi_msg(entry, msg); |
3145e941 | 364 | } |
83a18912 | 365 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 366 | |
f56e4481 HS |
367 | static void free_msi_irqs(struct pci_dev *dev) |
368 | { | |
5004e98a | 369 | struct list_head *msi_list = dev_to_msi_list(&dev->dev); |
f56e4481 | 370 | struct msi_desc *entry, *tmp; |
1c51b50c GKH |
371 | struct attribute **msi_attrs; |
372 | struct device_attribute *dev_attr; | |
63a7b17e | 373 | int i, count = 0; |
f56e4481 | 374 | |
5004e98a | 375 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
376 | if (entry->irq) |
377 | for (i = 0; i < entry->nvec_used; i++) | |
378 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 | 379 | |
8e047ada | 380 | pci_msi_teardown_msi_irqs(dev); |
f56e4481 | 381 | |
5004e98a | 382 | list_for_each_entry_safe(entry, tmp, msi_list, list) { |
f56e4481 | 383 | if (entry->msi_attrib.is_msix) { |
5004e98a | 384 | if (list_is_last(&entry->list, msi_list)) |
f56e4481 HS |
385 | iounmap(entry->mask_base); |
386 | } | |
424eb391 | 387 | |
f56e4481 | 388 | list_del(&entry->list); |
81efbadd | 389 | free_msi_entry(entry); |
f56e4481 | 390 | } |
1c51b50c GKH |
391 | |
392 | if (dev->msi_irq_groups) { | |
393 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
394 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 395 | while (msi_attrs[count]) { |
1c51b50c GKH |
396 | dev_attr = container_of(msi_attrs[count], |
397 | struct device_attribute, attr); | |
398 | kfree(dev_attr->attr.name); | |
399 | kfree(dev_attr); | |
400 | ++count; | |
401 | } | |
402 | kfree(msi_attrs); | |
403 | kfree(dev->msi_irq_groups[0]); | |
404 | kfree(dev->msi_irq_groups); | |
405 | dev->msi_irq_groups = NULL; | |
406 | } | |
f56e4481 | 407 | } |
c54c1879 | 408 | |
ba698ad4 DM |
409 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
410 | { | |
411 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
412 | pci_intx(dev, enable); | |
413 | } | |
414 | ||
830dfe88 BH |
415 | static void pci_msi_set_enable(struct pci_dev *dev, int enable) |
416 | { | |
417 | u16 control; | |
418 | ||
419 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
420 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
421 | if (enable) | |
422 | control |= PCI_MSI_FLAGS_ENABLE; | |
423 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
424 | } | |
425 | ||
8fed4b65 | 426 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 427 | { |
41017f0c | 428 | u16 control; |
392ee1e6 | 429 | struct msi_desc *entry; |
41017f0c | 430 | |
b1cbf4e4 EB |
431 | if (!dev->msi_enabled) |
432 | return; | |
433 | ||
dced35ae | 434 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 435 | |
ba698ad4 | 436 | pci_intx_for_msi(dev, 0); |
61b64abd | 437 | pci_msi_set_enable(dev, 0); |
ac8344c4 | 438 | arch_restore_msi_irqs(dev); |
392ee1e6 | 439 | |
f5322169 | 440 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
441 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
442 | entry->masked); | |
abad2ec9 | 443 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 444 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 445 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
446 | } |
447 | ||
830dfe88 BH |
448 | static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) |
449 | { | |
450 | u16 ctrl; | |
451 | ||
452 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
453 | ctrl &= ~clear; | |
454 | ctrl |= set; | |
455 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
456 | } | |
457 | ||
8fed4b65 | 458 | static void __pci_restore_msix_state(struct pci_dev *dev) |
41017f0c | 459 | { |
41017f0c | 460 | struct msi_desc *entry; |
41017f0c | 461 | |
ded86d8d EB |
462 | if (!dev->msix_enabled) |
463 | return; | |
5004e98a | 464 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
ded86d8d | 465 | |
41017f0c | 466 | /* route the table */ |
ba698ad4 | 467 | pci_intx_for_msi(dev, 0); |
61b64abd | 468 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 469 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
41017f0c | 470 | |
ac8344c4 | 471 | arch_restore_msi_irqs(dev); |
5004e98a | 472 | for_each_pci_msi_entry(entry, dev) |
f2440d9a | 473 | msix_mask_irq(entry, entry->masked); |
41017f0c | 474 | |
61b64abd | 475 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 476 | } |
8fed4b65 ME |
477 | |
478 | void pci_restore_msi_state(struct pci_dev *dev) | |
479 | { | |
480 | __pci_restore_msi_state(dev); | |
481 | __pci_restore_msix_state(dev); | |
482 | } | |
94688cf2 | 483 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 484 | |
1c51b50c | 485 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
486 | char *buf) |
487 | { | |
1c51b50c GKH |
488 | struct msi_desc *entry; |
489 | unsigned long irq; | |
490 | int retval; | |
da8d1c8b | 491 | |
1c51b50c GKH |
492 | retval = kstrtoul(attr->attr.name, 10, &irq); |
493 | if (retval) | |
494 | return retval; | |
da8d1c8b | 495 | |
e11ece5a YW |
496 | entry = irq_get_msi_desc(irq); |
497 | if (entry) | |
498 | return sprintf(buf, "%s\n", | |
499 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
500 | ||
1c51b50c | 501 | return -ENODEV; |
da8d1c8b NH |
502 | } |
503 | ||
da8d1c8b NH |
504 | static int populate_msi_sysfs(struct pci_dev *pdev) |
505 | { | |
1c51b50c GKH |
506 | struct attribute **msi_attrs; |
507 | struct attribute *msi_attr; | |
508 | struct device_attribute *msi_dev_attr; | |
509 | struct attribute_group *msi_irq_group; | |
510 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 511 | struct msi_desc *entry; |
1c51b50c GKH |
512 | int ret = -ENOMEM; |
513 | int num_msi = 0; | |
da8d1c8b | 514 | int count = 0; |
a8676066 | 515 | int i; |
da8d1c8b | 516 | |
1c51b50c | 517 | /* Determine how many msi entries we have */ |
5004e98a | 518 | for_each_pci_msi_entry(entry, pdev) |
a8676066 | 519 | num_msi += entry->nvec_used; |
1c51b50c GKH |
520 | if (!num_msi) |
521 | return 0; | |
da8d1c8b | 522 | |
1c51b50c | 523 | /* Dynamically create the MSI attributes for the PCI device */ |
6396bb22 | 524 | msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL); |
1c51b50c GKH |
525 | if (!msi_attrs) |
526 | return -ENOMEM; | |
5004e98a | 527 | for_each_pci_msi_entry(entry, pdev) { |
a8676066 RB |
528 | for (i = 0; i < entry->nvec_used; i++) { |
529 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); | |
530 | if (!msi_dev_attr) | |
531 | goto error_attrs; | |
532 | msi_attrs[count] = &msi_dev_attr->attr; | |
533 | ||
534 | sysfs_attr_init(&msi_dev_attr->attr); | |
535 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", | |
536 | entry->irq + i); | |
537 | if (!msi_dev_attr->attr.name) | |
538 | goto error_attrs; | |
539 | msi_dev_attr->attr.mode = S_IRUGO; | |
540 | msi_dev_attr->show = msi_mode_show; | |
541 | ++count; | |
542 | } | |
da8d1c8b NH |
543 | } |
544 | ||
1c51b50c GKH |
545 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
546 | if (!msi_irq_group) | |
547 | goto error_attrs; | |
548 | msi_irq_group->name = "msi_irqs"; | |
549 | msi_irq_group->attrs = msi_attrs; | |
550 | ||
6396bb22 | 551 | msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL); |
1c51b50c GKH |
552 | if (!msi_irq_groups) |
553 | goto error_irq_group; | |
554 | msi_irq_groups[0] = msi_irq_group; | |
555 | ||
556 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
557 | if (ret) | |
558 | goto error_irq_groups; | |
559 | pdev->msi_irq_groups = msi_irq_groups; | |
560 | ||
da8d1c8b NH |
561 | return 0; |
562 | ||
1c51b50c GKH |
563 | error_irq_groups: |
564 | kfree(msi_irq_groups); | |
565 | error_irq_group: | |
566 | kfree(msi_irq_group); | |
567 | error_attrs: | |
568 | count = 0; | |
569 | msi_attr = msi_attrs[count]; | |
570 | while (msi_attr) { | |
571 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
572 | kfree(msi_attr->name); | |
573 | kfree(msi_dev_attr); | |
574 | ++count; | |
575 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 576 | } |
29237756 | 577 | kfree(msi_attrs); |
da8d1c8b NH |
578 | return ret; |
579 | } | |
580 | ||
e75eafb9 | 581 | static struct msi_desc * |
c66d4bd1 | 582 | msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd) |
d873b4d4 | 583 | { |
bec04037 | 584 | struct irq_affinity_desc *masks = NULL; |
d873b4d4 | 585 | struct msi_desc *entry; |
e75eafb9 TG |
586 | u16 control; |
587 | ||
8e1101d2 | 588 | if (affd) |
61e1c590 | 589 | masks = irq_create_affinity_masks(nvec, affd); |
8e1101d2 | 590 | |
d873b4d4 | 591 | /* MSI Entry Initialization */ |
e75eafb9 | 592 | entry = alloc_msi_entry(&dev->dev, nvec, masks); |
d873b4d4 | 593 | if (!entry) |
e75eafb9 | 594 | goto out; |
d873b4d4 YW |
595 | |
596 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
597 | ||
598 | entry->msi_attrib.is_msix = 0; | |
599 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
d7cc609f | 600 | entry->msi_attrib.is_virtual = 0; |
d873b4d4 YW |
601 | entry->msi_attrib.entry_nr = 0; |
602 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
603 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 604 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e | 605 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
d873b4d4 YW |
606 | |
607 | if (control & PCI_MSI_FLAGS_64BIT) | |
608 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
609 | else | |
610 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
611 | ||
612 | /* Save the initial mask status */ | |
613 | if (entry->msi_attrib.maskbit) | |
614 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
615 | ||
e75eafb9 TG |
616 | out: |
617 | kfree(masks); | |
d873b4d4 YW |
618 | return entry; |
619 | } | |
620 | ||
f144d149 BH |
621 | static int msi_verify_entries(struct pci_dev *dev) |
622 | { | |
623 | struct msi_desc *entry; | |
624 | ||
5004e98a | 625 | for_each_pci_msi_entry(entry, dev) { |
2053230a VS |
626 | if (entry->msg.address_hi && dev->no_64bit_msi) { |
627 | pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", | |
628 | entry->msg.address_hi, entry->msg.address_lo); | |
629 | return -EIO; | |
630 | } | |
f144d149 BH |
631 | } |
632 | return 0; | |
633 | } | |
634 | ||
1da177e4 LT |
635 | /** |
636 | * msi_capability_init - configure device's MSI capability structure | |
637 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 638 | * @nvec: number of interrupts to allocate |
f6b6aefe | 639 | * @affd: description of automatic IRQ affinity assignments (may be %NULL) |
1da177e4 | 640 | * |
1c8d7b0a MW |
641 | * Setup the MSI capability structure of the device with the requested |
642 | * number of interrupts. A return value of zero indicates the successful | |
f6b6aefe | 643 | * setup of an entry with the new MSI IRQ. A negative return value indicates |
1c8d7b0a MW |
644 | * an error, and a positive return value indicates the number of interrupts |
645 | * which could have been allocated. | |
646 | */ | |
61e1c590 | 647 | static int msi_capability_init(struct pci_dev *dev, int nvec, |
c66d4bd1 | 648 | struct irq_affinity *affd) |
1da177e4 LT |
649 | { |
650 | struct msi_desc *entry; | |
f465136d | 651 | int ret; |
f2440d9a | 652 | unsigned mask; |
1da177e4 | 653 | |
61b64abd | 654 | pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 655 | |
61e1c590 | 656 | entry = msi_setup_entry(dev, nvec, affd); |
f7feaca7 EB |
657 | if (!entry) |
658 | return -ENOMEM; | |
1ce03373 | 659 | |
f6b6aefe | 660 | /* All MSIs are unmasked by default; mask them all */ |
31ea5d4d | 661 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
662 | msi_mask_irq(entry, mask, mask); |
663 | ||
5004e98a | 664 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
9c831334 | 665 | |
1da177e4 | 666 | /* Configure MSI capability structure */ |
8e047ada | 667 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 668 | if (ret) { |
7ba1930d | 669 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 670 | free_msi_irqs(dev); |
7fe3730d | 671 | return ret; |
fd58e55f | 672 | } |
f7feaca7 | 673 | |
f144d149 BH |
674 | ret = msi_verify_entries(dev); |
675 | if (ret) { | |
676 | msi_mask_irq(entry, mask, ~mask); | |
677 | free_msi_irqs(dev); | |
678 | return ret; | |
679 | } | |
680 | ||
da8d1c8b NH |
681 | ret = populate_msi_sysfs(dev); |
682 | if (ret) { | |
683 | msi_mask_irq(entry, mask, ~mask); | |
684 | free_msi_irqs(dev); | |
685 | return ret; | |
686 | } | |
687 | ||
f6b6aefe | 688 | /* Set MSI enabled bits */ |
ba698ad4 | 689 | pci_intx_for_msi(dev, 0); |
61b64abd | 690 | pci_msi_set_enable(dev, 1); |
b1cbf4e4 | 691 | dev->msi_enabled = 1; |
1da177e4 | 692 | |
5f226991 | 693 | pcibios_free_irq(dev); |
7fe3730d | 694 | dev->irq = entry->irq; |
1da177e4 LT |
695 | return 0; |
696 | } | |
697 | ||
520fe9dc | 698 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 699 | { |
4302e0fb | 700 | resource_size_t phys_addr; |
5a05a9d8 | 701 | u32 table_offset; |
6a878e50 | 702 | unsigned long flags; |
5a05a9d8 HS |
703 | u8 bir; |
704 | ||
909094c6 BH |
705 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
706 | &table_offset); | |
4d18760c | 707 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
6a878e50 YW |
708 | flags = pci_resource_flags(dev, bir); |
709 | if (!flags || (flags & IORESOURCE_UNSET)) | |
710 | return NULL; | |
711 | ||
4d18760c | 712 | table_offset &= PCI_MSIX_TABLE_OFFSET; |
5a05a9d8 HS |
713 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
714 | ||
4bdc0d67 | 715 | return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
5a05a9d8 HS |
716 | } |
717 | ||
520fe9dc | 718 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
e75eafb9 | 719 | struct msix_entry *entries, int nvec, |
c66d4bd1 | 720 | struct irq_affinity *affd) |
d9d7070e | 721 | { |
bec04037 | 722 | struct irq_affinity_desc *curmsk, *masks = NULL; |
d9d7070e | 723 | struct msi_desc *entry; |
e75eafb9 | 724 | int ret, i; |
d7cc609f | 725 | int vec_count = pci_msix_vec_count(dev); |
4ef33685 | 726 | |
8e1101d2 | 727 | if (affd) |
61e1c590 | 728 | masks = irq_create_affinity_masks(nvec, affd); |
4ef33685 | 729 | |
e75eafb9 TG |
730 | for (i = 0, curmsk = masks; i < nvec; i++) { |
731 | entry = alloc_msi_entry(&dev->dev, 1, curmsk); | |
d9d7070e HS |
732 | if (!entry) { |
733 | if (!i) | |
734 | iounmap(base); | |
735 | else | |
736 | free_msi_irqs(dev); | |
737 | /* No enough memory. Don't try again */ | |
e75eafb9 TG |
738 | ret = -ENOMEM; |
739 | goto out; | |
d9d7070e HS |
740 | } |
741 | ||
742 | entry->msi_attrib.is_msix = 1; | |
743 | entry->msi_attrib.is_64 = 1; | |
3ac020e0 CH |
744 | if (entries) |
745 | entry->msi_attrib.entry_nr = entries[i].entry; | |
746 | else | |
747 | entry->msi_attrib.entry_nr = i; | |
d7cc609f LG |
748 | |
749 | entry->msi_attrib.is_virtual = | |
750 | entry->msi_attrib.entry_nr >= vec_count; | |
751 | ||
d9d7070e | 752 | entry->msi_attrib.default_irq = dev->irq; |
d9d7070e HS |
753 | entry->mask_base = base; |
754 | ||
5004e98a | 755 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
e75eafb9 TG |
756 | if (masks) |
757 | curmsk++; | |
d9d7070e | 758 | } |
e75eafb9 TG |
759 | ret = 0; |
760 | out: | |
761 | kfree(masks); | |
3adfb572 | 762 | return ret; |
d9d7070e HS |
763 | } |
764 | ||
75cb3426 | 765 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 766 | struct msix_entry *entries) |
75cb3426 HS |
767 | { |
768 | struct msi_desc *entry; | |
769 | int i = 0; | |
d7cc609f | 770 | void __iomem *desc_addr; |
75cb3426 | 771 | |
5004e98a | 772 | for_each_pci_msi_entry(entry, dev) { |
3ac020e0 CH |
773 | if (entries) |
774 | entries[i++].vector = entry->irq; | |
d7cc609f LG |
775 | |
776 | desc_addr = pci_msix_desc_addr(entry); | |
777 | if (desc_addr) | |
778 | entry->masked = readl(desc_addr + | |
779 | PCI_MSIX_ENTRY_VECTOR_CTRL); | |
780 | else | |
781 | entry->masked = 0; | |
782 | ||
75cb3426 | 783 | msix_mask_irq(entry, 1); |
75cb3426 HS |
784 | } |
785 | } | |
786 | ||
1da177e4 LT |
787 | /** |
788 | * msix_capability_init - configure device's MSI-X capability | |
789 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
790 | * @entries: pointer to an array of struct msix_entry entries |
791 | * @nvec: number of @entries | |
f6b6aefe | 792 | * @affd: Optional pointer to enable automatic affinity assignment |
1da177e4 | 793 | * |
eaae4b3a | 794 | * Setup the MSI-X capability structure of device function with a |
f6b6aefe BH |
795 | * single MSI-X IRQ. A return of zero indicates the successful setup of |
796 | * requested MSI-X entries with allocated IRQs or non-zero for otherwise. | |
1da177e4 | 797 | **/ |
e75eafb9 | 798 | static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries, |
c66d4bd1 | 799 | int nvec, struct irq_affinity *affd) |
1da177e4 | 800 | { |
520fe9dc | 801 | int ret; |
5a05a9d8 | 802 | u16 control; |
1da177e4 LT |
803 | void __iomem *base; |
804 | ||
f598282f | 805 | /* Ensure MSI-X is disabled while it is set up */ |
61b64abd | 806 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 807 | |
66f0d0c4 | 808 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 809 | /* Request & Map MSI-X table region */ |
527eee29 | 810 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 811 | if (!base) |
1da177e4 LT |
812 | return -ENOMEM; |
813 | ||
61e1c590 | 814 | ret = msix_setup_entries(dev, base, entries, nvec, affd); |
d9d7070e HS |
815 | if (ret) |
816 | return ret; | |
9c831334 | 817 | |
8e047ada | 818 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
583871d4 | 819 | if (ret) |
2adc7907 | 820 | goto out_avail; |
9c831334 | 821 | |
f144d149 BH |
822 | /* Check if all MSI entries honor device restrictions */ |
823 | ret = msi_verify_entries(dev); | |
824 | if (ret) | |
825 | goto out_free; | |
826 | ||
f598282f MW |
827 | /* |
828 | * Some devices require MSI-X to be enabled before we can touch the | |
829 | * MSI-X registers. We need to mask all the vectors to prevent | |
830 | * interrupts coming in before they're fully set up. | |
831 | */ | |
61b64abd | 832 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 833 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); |
f598282f | 834 | |
75cb3426 | 835 | msix_program_entries(dev, entries); |
f598282f | 836 | |
da8d1c8b | 837 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
838 | if (ret) |
839 | goto out_free; | |
da8d1c8b | 840 | |
f598282f | 841 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 842 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 843 | dev->msix_enabled = 1; |
61b64abd | 844 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 845 | |
5f226991 | 846 | pcibios_free_irq(dev); |
1da177e4 | 847 | return 0; |
583871d4 | 848 | |
2adc7907 | 849 | out_avail: |
583871d4 HS |
850 | if (ret < 0) { |
851 | /* | |
f6b6aefe | 852 | * If we had some success, report the number of IRQs |
583871d4 HS |
853 | * we succeeded in setting up. |
854 | */ | |
d9d7070e | 855 | struct msi_desc *entry; |
583871d4 HS |
856 | int avail = 0; |
857 | ||
5004e98a | 858 | for_each_pci_msi_entry(entry, dev) { |
583871d4 HS |
859 | if (entry->irq != 0) |
860 | avail++; | |
861 | } | |
862 | if (avail != 0) | |
863 | ret = avail; | |
864 | } | |
865 | ||
2adc7907 | 866 | out_free: |
583871d4 HS |
867 | free_msi_irqs(dev); |
868 | ||
869 | return ret; | |
1da177e4 LT |
870 | } |
871 | ||
24334a12 | 872 | /** |
a06cd74c | 873 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 874 | * @dev: pointer to the pci_dev data structure of MSI device function |
f6b6aefe | 875 | * @nvec: how many MSIs have been requested? |
24334a12 | 876 | * |
f7625980 | 877 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 878 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 879 | * supported return 1, else return 0. |
24334a12 | 880 | **/ |
a06cd74c | 881 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
882 | { |
883 | struct pci_bus *bus; | |
884 | ||
0306ebfa | 885 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 886 | if (!pci_msi_enable) |
a06cd74c | 887 | return 0; |
27e20603 | 888 | |
901c4ddb | 889 | if (!dev || dev->no_msi) |
a06cd74c | 890 | return 0; |
24334a12 | 891 | |
314e77b3 ME |
892 | /* |
893 | * You can't ask to have 0 or less MSIs configured. | |
894 | * a) it's stupid .. | |
895 | * b) the list manipulation code assumes nvec >= 1. | |
896 | */ | |
897 | if (nvec < 1) | |
a06cd74c | 898 | return 0; |
314e77b3 | 899 | |
500559a9 HS |
900 | /* |
901 | * Any bridge which does NOT route MSI transactions from its | |
902 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
903 | * the secondary pci_bus. |
904 | * We expect only arch-specific PCI host bus controller driver | |
905 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
906 | */ | |
24334a12 BG |
907 | for (bus = dev->bus; bus; bus = bus->parent) |
908 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 909 | return 0; |
24334a12 | 910 | |
a06cd74c | 911 | return 1; |
24334a12 BG |
912 | } |
913 | ||
d1ac1d26 AG |
914 | /** |
915 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
916 | * @dev: device to report about | |
917 | * | |
918 | * This function returns the number of MSI vectors a device requested via | |
919 | * Multiple Message Capable register. It returns a negative errno if the | |
920 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
921 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
922 | * MSI specification. | |
923 | **/ | |
924 | int pci_msi_vec_count(struct pci_dev *dev) | |
925 | { | |
926 | int ret; | |
927 | u16 msgctl; | |
928 | ||
929 | if (!dev->msi_cap) | |
930 | return -EINVAL; | |
931 | ||
932 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
933 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
934 | ||
935 | return ret; | |
936 | } | |
937 | EXPORT_SYMBOL(pci_msi_vec_count); | |
938 | ||
688769f6 | 939 | static void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 940 | { |
f2440d9a MW |
941 | struct msi_desc *desc; |
942 | u32 mask; | |
1da177e4 | 943 | |
128bc5fc | 944 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
945 | return; |
946 | ||
5004e98a | 947 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
4a7cc831 | 948 | desc = first_pci_msi_entry(dev); |
110828c9 | 949 | |
61b64abd | 950 | pci_msi_set_enable(dev, 0); |
ba698ad4 | 951 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 952 | dev->msi_enabled = 0; |
7bd007e4 | 953 | |
12abb8ba | 954 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 955 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 956 | /* Keep cached state to be restored */ |
23ed8d57 | 957 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
e387b9ee | 958 | |
f6b6aefe | 959 | /* Restore dev->irq to its default pin-assertion IRQ */ |
f2440d9a | 960 | dev->irq = desc->msi_attrib.default_irq; |
5f226991 | 961 | pcibios_alloc_irq(dev); |
d52877c7 | 962 | } |
24d27553 | 963 | |
500559a9 | 964 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 965 | { |
d52877c7 YL |
966 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
967 | return; | |
968 | ||
969 | pci_msi_shutdown(dev); | |
f56e4481 | 970 | free_msi_irqs(dev); |
1da177e4 | 971 | } |
4cc086fa | 972 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 973 | |
a52e2e35 | 974 | /** |
ff1aa430 | 975 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 976 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
977 | * This function returns the number of device's MSI-X table entries and |
978 | * therefore the number of MSI-X vectors device is capable of sending. | |
979 | * It returns a negative errno if the device is not capable of sending MSI-X | |
980 | * interrupts. | |
981 | **/ | |
982 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 983 | { |
a52e2e35 RW |
984 | u16 control; |
985 | ||
520fe9dc | 986 | if (!dev->msix_cap) |
ff1aa430 | 987 | return -EINVAL; |
a52e2e35 | 988 | |
f84ecd28 | 989 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 990 | return msix_table_size(control); |
a52e2e35 | 991 | } |
ff1aa430 | 992 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 993 | |
e75eafb9 | 994 | static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, |
d7cc609f | 995 | int nvec, struct irq_affinity *affd, int flags) |
1da177e4 | 996 | { |
5ec09405 | 997 | int nr_entries; |
ded86d8d | 998 | int i, j; |
1da177e4 | 999 | |
901c4ddb | 1000 | if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0) |
a06cd74c | 1001 | return -EINVAL; |
c9953a73 | 1002 | |
ff1aa430 AG |
1003 | nr_entries = pci_msix_vec_count(dev); |
1004 | if (nr_entries < 0) | |
1005 | return nr_entries; | |
d7cc609f | 1006 | if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL)) |
57fbf52c | 1007 | return nr_entries; |
1da177e4 | 1008 | |
3ac020e0 CH |
1009 | if (entries) { |
1010 | /* Check for any invalid entries */ | |
1011 | for (i = 0; i < nvec; i++) { | |
1012 | if (entries[i].entry >= nr_entries) | |
1013 | return -EINVAL; /* invalid entry */ | |
1014 | for (j = i + 1; j < nvec; j++) { | |
1015 | if (entries[i].entry == entries[j].entry) | |
1016 | return -EINVAL; /* duplicate entry */ | |
1017 | } | |
1da177e4 LT |
1018 | } |
1019 | } | |
7bd007e4 | 1020 | |
f6b6aefe | 1021 | /* Check whether driver already requested for MSI IRQ */ |
500559a9 | 1022 | if (dev->msi_enabled) { |
7506dc79 | 1023 | pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
1024 | return -EINVAL; |
1025 | } | |
61e1c590 | 1026 | return msix_capability_init(dev, entries, nvec, affd); |
e75eafb9 TG |
1027 | } |
1028 | ||
688769f6 | 1029 | static void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 1030 | { |
12abb8ba HS |
1031 | struct msi_desc *entry; |
1032 | ||
128bc5fc | 1033 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
1034 | return; |
1035 | ||
0170591b KB |
1036 | if (pci_dev_is_disconnected(dev)) { |
1037 | dev->msix_enabled = 0; | |
1038 | return; | |
1039 | } | |
1040 | ||
12abb8ba | 1041 | /* Return the device with MSI-X masked as initial states */ |
5004e98a | 1042 | for_each_pci_msi_entry(entry, dev) { |
12abb8ba | 1043 | /* Keep cached states to be restored */ |
23ed8d57 | 1044 | __pci_msix_desc_mask_irq(entry, 1); |
12abb8ba HS |
1045 | } |
1046 | ||
61b64abd | 1047 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 1048 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1049 | dev->msix_enabled = 0; |
5f226991 | 1050 | pcibios_alloc_irq(dev); |
d52877c7 | 1051 | } |
c901851f | 1052 | |
500559a9 | 1053 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1054 | { |
1055 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1056 | return; | |
1057 | ||
1058 | pci_msix_shutdown(dev); | |
f56e4481 | 1059 | free_msi_irqs(dev); |
1da177e4 | 1060 | } |
4cc086fa | 1061 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1062 | |
309e57df MW |
1063 | void pci_no_msi(void) |
1064 | { | |
1065 | pci_msi_enable = 0; | |
1066 | } | |
c9953a73 | 1067 | |
07ae95f9 AP |
1068 | /** |
1069 | * pci_msi_enabled - is MSI enabled? | |
1070 | * | |
1071 | * Returns true if MSI has not been disabled by the command-line option | |
1072 | * pci=nomsi. | |
1073 | **/ | |
1074 | int pci_msi_enabled(void) | |
d389fec6 | 1075 | { |
07ae95f9 | 1076 | return pci_msi_enable; |
d389fec6 | 1077 | } |
07ae95f9 | 1078 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1079 | |
4ef33685 | 1080 | static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, |
c66d4bd1 | 1081 | struct irq_affinity *affd) |
302a2523 | 1082 | { |
034cd97e | 1083 | int nvec; |
302a2523 AG |
1084 | int rc; |
1085 | ||
901c4ddb | 1086 | if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0) |
a06cd74c | 1087 | return -EINVAL; |
034cd97e | 1088 | |
f6b6aefe | 1089 | /* Check whether driver already requested MSI-X IRQs */ |
034cd97e | 1090 | if (dev->msix_enabled) { |
7506dc79 | 1091 | pci_info(dev, "can't enable MSI (MSI-X already enabled)\n"); |
034cd97e AG |
1092 | return -EINVAL; |
1093 | } | |
1094 | ||
302a2523 AG |
1095 | if (maxvec < minvec) |
1096 | return -ERANGE; | |
1097 | ||
4c1ef72e TZ |
1098 | if (WARN_ON_ONCE(dev->msi_enabled)) |
1099 | return -EINVAL; | |
1100 | ||
034cd97e AG |
1101 | nvec = pci_msi_vec_count(dev); |
1102 | if (nvec < 0) | |
1103 | return nvec; | |
4ef33685 | 1104 | if (nvec < minvec) |
948b7620 | 1105 | return -ENOSPC; |
4ef33685 CH |
1106 | |
1107 | if (nvec > maxvec) | |
034cd97e AG |
1108 | nvec = maxvec; |
1109 | ||
4ef33685 | 1110 | for (;;) { |
61e1c590 | 1111 | if (affd) { |
6f9a22bc | 1112 | nvec = irq_calc_affinity_vectors(minvec, nvec, affd); |
4ef33685 CH |
1113 | if (nvec < minvec) |
1114 | return -ENOSPC; | |
1115 | } | |
1116 | ||
61e1c590 | 1117 | rc = msi_capability_init(dev, nvec, affd); |
4ef33685 CH |
1118 | if (rc == 0) |
1119 | return nvec; | |
1120 | ||
4ef33685 | 1121 | if (rc < 0) |
302a2523 | 1122 | return rc; |
4ef33685 CH |
1123 | if (rc < minvec) |
1124 | return -ENOSPC; | |
1125 | ||
1126 | nvec = rc; | |
1127 | } | |
1128 | } | |
1129 | ||
4fe03955 CH |
1130 | /* deprecated, don't use */ |
1131 | int pci_enable_msi(struct pci_dev *dev) | |
4ef33685 | 1132 | { |
4fe03955 CH |
1133 | int rc = __pci_enable_msi_range(dev, 1, 1, NULL); |
1134 | if (rc < 0) | |
1135 | return rc; | |
1136 | return 0; | |
4ef33685 | 1137 | } |
4fe03955 | 1138 | EXPORT_SYMBOL(pci_enable_msi); |
4ef33685 CH |
1139 | |
1140 | static int __pci_enable_msix_range(struct pci_dev *dev, | |
61e1c590 | 1141 | struct msix_entry *entries, int minvec, |
d7cc609f LG |
1142 | int maxvec, struct irq_affinity *affd, |
1143 | int flags) | |
4ef33685 | 1144 | { |
e75eafb9 | 1145 | int rc, nvec = maxvec; |
4ef33685 CH |
1146 | |
1147 | if (maxvec < minvec) | |
1148 | return -ERANGE; | |
1149 | ||
4c1ef72e TZ |
1150 | if (WARN_ON_ONCE(dev->msix_enabled)) |
1151 | return -EINVAL; | |
1152 | ||
4ef33685 | 1153 | for (;;) { |
61e1c590 | 1154 | if (affd) { |
6f9a22bc | 1155 | nvec = irq_calc_affinity_vectors(minvec, nvec, affd); |
4ef33685 | 1156 | if (nvec < minvec) |
302a2523 | 1157 | return -ENOSPC; |
302a2523 | 1158 | } |
302a2523 | 1159 | |
d7cc609f | 1160 | rc = __pci_enable_msix(dev, entries, nvec, affd, flags); |
4ef33685 CH |
1161 | if (rc == 0) |
1162 | return nvec; | |
1163 | ||
4ef33685 CH |
1164 | if (rc < 0) |
1165 | return rc; | |
1166 | if (rc < minvec) | |
1167 | return -ENOSPC; | |
1168 | ||
1169 | nvec = rc; | |
1170 | } | |
302a2523 | 1171 | } |
302a2523 AG |
1172 | |
1173 | /** | |
1174 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1175 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1176 | * @entries: pointer to an array of MSI-X entries | |
f6b6aefe BH |
1177 | * @minvec: minimum number of MSI-X IRQs requested |
1178 | * @maxvec: maximum number of MSI-X IRQs requested | |
302a2523 AG |
1179 | * |
1180 | * Setup the MSI-X capability structure of device function with a maximum | |
1181 | * possible number of interrupts in the range between @minvec and @maxvec | |
1182 | * upon its software driver call to request for MSI-X mode enabled on its | |
1183 | * hardware device function. It returns a negative errno if an error occurs. | |
1184 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1185 | * indicates the successful configuration of MSI-X capability structure | |
1186 | * with new allocated MSI-X interrupts. | |
1187 | **/ | |
1188 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
4ef33685 | 1189 | int minvec, int maxvec) |
302a2523 | 1190 | { |
d7cc609f | 1191 | return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0); |
302a2523 AG |
1192 | } |
1193 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef | 1194 | |
aff17164 | 1195 | /** |
402723ad | 1196 | * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device |
aff17164 CH |
1197 | * @dev: PCI device to operate on |
1198 | * @min_vecs: minimum number of vectors required (must be >= 1) | |
1199 | * @max_vecs: maximum (desired) number of vectors | |
1200 | * @flags: flags or quirks for the allocation | |
402723ad | 1201 | * @affd: optional description of the affinity requirements |
aff17164 CH |
1202 | * |
1203 | * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI | |
1204 | * vectors if available, and fall back to a single legacy vector | |
1205 | * if neither is available. Return the number of vectors allocated, | |
1206 | * (which might be smaller than @max_vecs) if successful, or a negative | |
1207 | * error code on error. If less than @min_vecs interrupt vectors are | |
1208 | * available for @dev the function will fail with -ENOSPC. | |
1209 | * | |
1210 | * To get the Linux IRQ number used for a vector that can be passed to | |
1211 | * request_irq() use the pci_irq_vector() helper. | |
1212 | */ | |
402723ad CH |
1213 | int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
1214 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1215 | struct irq_affinity *affd) |
aff17164 | 1216 | { |
c66d4bd1 | 1217 | struct irq_affinity msi_default_affd = {0}; |
30ff3e8c | 1218 | int nvecs = -ENOSPC; |
aff17164 | 1219 | |
402723ad CH |
1220 | if (flags & PCI_IRQ_AFFINITY) { |
1221 | if (!affd) | |
1222 | affd = &msi_default_affd; | |
1223 | } else { | |
1224 | if (WARN_ON(affd)) | |
1225 | affd = NULL; | |
1226 | } | |
61e1c590 | 1227 | |
4fe0d154 | 1228 | if (flags & PCI_IRQ_MSIX) { |
30ff3e8c PS |
1229 | nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs, |
1230 | affd, flags); | |
1231 | if (nvecs > 0) | |
1232 | return nvecs; | |
aff17164 CH |
1233 | } |
1234 | ||
4fe0d154 | 1235 | if (flags & PCI_IRQ_MSI) { |
30ff3e8c PS |
1236 | nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd); |
1237 | if (nvecs > 0) | |
1238 | return nvecs; | |
aff17164 CH |
1239 | } |
1240 | ||
f6b6aefe | 1241 | /* use legacy IRQ if allowed */ |
862290f9 CH |
1242 | if (flags & PCI_IRQ_LEGACY) { |
1243 | if (min_vecs == 1 && dev->irq) { | |
c66d4bd1 ML |
1244 | /* |
1245 | * Invoke the affinity spreading logic to ensure that | |
1246 | * the device driver can adjust queue configuration | |
1247 | * for the single interrupt case. | |
1248 | */ | |
1249 | if (affd) | |
1250 | irq_create_affinity_masks(1, affd); | |
862290f9 CH |
1251 | pci_intx(dev, 1); |
1252 | return 1; | |
1253 | } | |
5d0bdf28 CH |
1254 | } |
1255 | ||
30ff3e8c | 1256 | return nvecs; |
aff17164 | 1257 | } |
402723ad | 1258 | EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); |
aff17164 CH |
1259 | |
1260 | /** | |
1261 | * pci_free_irq_vectors - free previously allocated IRQs for a device | |
1262 | * @dev: PCI device to operate on | |
1263 | * | |
1264 | * Undoes the allocations and enabling in pci_alloc_irq_vectors(). | |
1265 | */ | |
1266 | void pci_free_irq_vectors(struct pci_dev *dev) | |
1267 | { | |
1268 | pci_disable_msix(dev); | |
1269 | pci_disable_msi(dev); | |
1270 | } | |
1271 | EXPORT_SYMBOL(pci_free_irq_vectors); | |
1272 | ||
1273 | /** | |
1274 | * pci_irq_vector - return Linux IRQ number of a device vector | |
1275 | * @dev: PCI device to operate on | |
1276 | * @nr: device-relative interrupt vector index (0-based). | |
1277 | */ | |
1278 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1279 | { | |
1280 | if (dev->msix_enabled) { | |
1281 | struct msi_desc *entry; | |
1282 | int i = 0; | |
1283 | ||
1284 | for_each_pci_msi_entry(entry, dev) { | |
1285 | if (i == nr) | |
1286 | return entry->irq; | |
1287 | i++; | |
1288 | } | |
1289 | WARN_ON_ONCE(1); | |
1290 | return -EINVAL; | |
1291 | } | |
1292 | ||
1293 | if (dev->msi_enabled) { | |
1294 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1295 | ||
1296 | if (WARN_ON_ONCE(nr >= entry->nvec_used)) | |
1297 | return -EINVAL; | |
1298 | } else { | |
1299 | if (WARN_ON_ONCE(nr > 0)) | |
1300 | return -EINVAL; | |
1301 | } | |
1302 | ||
1303 | return dev->irq + nr; | |
1304 | } | |
1305 | EXPORT_SYMBOL(pci_irq_vector); | |
1306 | ||
ee8d41e5 | 1307 | /** |
f6b6aefe | 1308 | * pci_irq_get_affinity - return the affinity of a particular MSI vector |
ee8d41e5 TG |
1309 | * @dev: PCI device to operate on |
1310 | * @nr: device-relative interrupt vector index (0-based). | |
1311 | */ | |
1312 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr) | |
1313 | { | |
1314 | if (dev->msix_enabled) { | |
1315 | struct msi_desc *entry; | |
1316 | int i = 0; | |
1317 | ||
1318 | for_each_pci_msi_entry(entry, dev) { | |
1319 | if (i == nr) | |
bec04037 | 1320 | return &entry->affinity->mask; |
ee8d41e5 TG |
1321 | i++; |
1322 | } | |
1323 | WARN_ON_ONCE(1); | |
1324 | return NULL; | |
1325 | } else if (dev->msi_enabled) { | |
1326 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1327 | ||
d1d111e0 JB |
1328 | if (WARN_ON_ONCE(!entry || !entry->affinity || |
1329 | nr >= entry->nvec_used)) | |
ee8d41e5 TG |
1330 | return NULL; |
1331 | ||
bec04037 | 1332 | return &entry->affinity[nr].mask; |
ee8d41e5 TG |
1333 | } else { |
1334 | return cpu_possible_mask; | |
1335 | } | |
1336 | } | |
1337 | EXPORT_SYMBOL(pci_irq_get_affinity); | |
1338 | ||
25a98bd4 JL |
1339 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc) |
1340 | { | |
1341 | return to_pci_dev(desc->dev); | |
1342 | } | |
a4289dc2 | 1343 | EXPORT_SYMBOL(msi_desc_to_pci_dev); |
25a98bd4 | 1344 | |
c179c9b9 JL |
1345 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
1346 | { | |
1347 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); | |
1348 | ||
1349 | return dev->bus->sysdata; | |
1350 | } | |
1351 | EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata); | |
1352 | ||
3878eaef JL |
1353 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
1354 | /** | |
1355 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1356 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1357 | * @msg: Pointer to the message | |
1358 | */ | |
1359 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1360 | { | |
507a883e | 1361 | struct msi_desc *desc = irq_data_get_msi_desc(irq_data); |
3878eaef JL |
1362 | |
1363 | /* | |
1364 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1365 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1366 | */ | |
1367 | if (desc->irq == irq_data->irq) | |
1368 | __pci_write_msi_msg(desc, msg); | |
1369 | } | |
1370 | ||
1371 | /** | |
1372 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
f6b6aefe | 1373 | * @desc: Pointer to the MSI descriptor |
3878eaef JL |
1374 | * |
1375 | * The ID number is only used within the irqdomain. | |
1376 | */ | |
9006c133 | 1377 | static irq_hw_number_t pci_msi_domain_calc_hwirq(struct msi_desc *desc) |
3878eaef | 1378 | { |
dfb9eb7c TG |
1379 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); |
1380 | ||
3878eaef | 1381 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | |
4e544bac | 1382 | pci_dev_id(dev) << 11 | |
3878eaef JL |
1383 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; |
1384 | } | |
1385 | ||
1386 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1387 | { | |
1388 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1389 | } | |
1390 | ||
1391 | /** | |
f6b6aefe BH |
1392 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities |
1393 | * for @dev | |
3878eaef JL |
1394 | * @domain: The interrupt domain to check |
1395 | * @info: The domain info for verification | |
1396 | * @dev: The device to check | |
1397 | * | |
1398 | * Returns: | |
1399 | * 0 if the functionality is supported | |
1400 | * 1 if Multi MSI is requested, but the domain does not support it | |
1401 | * -ENOTSUPP otherwise | |
1402 | */ | |
1403 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1404 | struct msi_domain_info *info, struct device *dev) | |
1405 | { | |
1406 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1407 | ||
4fe03955 | 1408 | /* Special handling to support __pci_enable_msi_range() */ |
3878eaef JL |
1409 | if (pci_msi_desc_is_multi_msi(desc) && |
1410 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1411 | return 1; | |
1412 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1413 | return -ENOTSUPP; | |
1414 | ||
1415 | return 0; | |
1416 | } | |
1417 | ||
1418 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1419 | struct msi_desc *desc, int error) | |
1420 | { | |
4fe03955 | 1421 | /* Special handling to support __pci_enable_msi_range() */ |
3878eaef JL |
1422 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) |
1423 | return 1; | |
1424 | ||
1425 | return error; | |
1426 | } | |
1427 | ||
3878eaef JL |
1428 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, |
1429 | struct msi_desc *desc) | |
1430 | { | |
1431 | arg->desc = desc; | |
dfb9eb7c | 1432 | arg->hwirq = pci_msi_domain_calc_hwirq(desc); |
3878eaef | 1433 | } |
3878eaef JL |
1434 | |
1435 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1436 | .set_desc = pci_msi_domain_set_desc, | |
1437 | .msi_check = pci_msi_domain_check_cap, | |
1438 | .handle_error = pci_msi_domain_handle_error, | |
1439 | }; | |
1440 | ||
1441 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1442 | { | |
1443 | struct msi_domain_ops *ops = info->ops; | |
1444 | ||
1445 | if (ops == NULL) { | |
1446 | info->ops = &pci_msi_domain_ops_default; | |
1447 | } else { | |
1448 | if (ops->set_desc == NULL) | |
1449 | ops->set_desc = pci_msi_domain_set_desc; | |
1450 | if (ops->msi_check == NULL) | |
1451 | ops->msi_check = pci_msi_domain_check_cap; | |
1452 | if (ops->handle_error == NULL) | |
1453 | ops->handle_error = pci_msi_domain_handle_error; | |
1454 | } | |
1455 | } | |
1456 | ||
1457 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1458 | { | |
1459 | struct irq_chip *chip = info->chip; | |
1460 | ||
1461 | BUG_ON(!chip); | |
1462 | if (!chip->irq_write_msi_msg) | |
1463 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
0701c53e MZ |
1464 | if (!chip->irq_mask) |
1465 | chip->irq_mask = pci_msi_mask_irq; | |
1466 | if (!chip->irq_unmask) | |
1467 | chip->irq_unmask = pci_msi_unmask_irq; | |
3878eaef JL |
1468 | } |
1469 | ||
1470 | /** | |
be5436c8 MZ |
1471 | * pci_msi_create_irq_domain - Create a MSI interrupt domain |
1472 | * @fwnode: Optional fwnode of the interrupt controller | |
3878eaef JL |
1473 | * @info: MSI domain info |
1474 | * @parent: Parent irq domain | |
1475 | * | |
1476 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1477 | * | |
1478 | * Returns: | |
1479 | * A domain pointer or NULL in case of failure. | |
1480 | */ | |
be5436c8 | 1481 | struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, |
3878eaef JL |
1482 | struct msi_domain_info *info, |
1483 | struct irq_domain *parent) | |
1484 | { | |
0380839d MZ |
1485 | struct irq_domain *domain; |
1486 | ||
6988e0e0 MZ |
1487 | if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE)) |
1488 | info->flags &= ~MSI_FLAG_LEVEL_CAPABLE; | |
1489 | ||
3878eaef JL |
1490 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
1491 | pci_msi_domain_update_dom_ops(info); | |
1492 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1493 | pci_msi_domain_update_chip_ops(info); | |
1494 | ||
f3b0946d | 1495 | info->flags |= MSI_FLAG_ACTIVATE_EARLY; |
25e960ef TG |
1496 | if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE)) |
1497 | info->flags |= MSI_FLAG_MUST_REACTIVATE; | |
f3b0946d | 1498 | |
923aa4c3 HK |
1499 | /* PCI-MSI is oneshot-safe */ |
1500 | info->chip->flags |= IRQCHIP_ONESHOT_SAFE; | |
1501 | ||
be5436c8 | 1502 | domain = msi_create_irq_domain(fwnode, info, parent); |
0380839d MZ |
1503 | if (!domain) |
1504 | return NULL; | |
1505 | ||
96f0d93a | 1506 | irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI); |
0380839d | 1507 | return domain; |
3878eaef | 1508 | } |
a4289dc2 | 1509 | EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain); |
3878eaef | 1510 | |
235b2c77 RM |
1511 | /* |
1512 | * Users of the generic MSI infrastructure expect a device to have a single ID, | |
1513 | * so with DMA aliases we have to pick the least-worst compromise. Devices with | |
1514 | * DMA phantom functions tend to still emit MSIs from the real function number, | |
1515 | * so we ignore those and only consider topological aliases where either the | |
1516 | * alias device or RID appears on a different bus number. We also make the | |
1517 | * reasonable assumption that bridges are walked in an upstream direction (so | |
1518 | * the last one seen wins), and the much braver assumption that the most likely | |
1519 | * case is that of PCI->PCIe so we should always use the alias RID. This echoes | |
1520 | * the logic from intel_irq_remapping's set_msi_sid(), which presumably works | |
1521 | * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions | |
1522 | * for taking ownership all we can really do is close our eyes and hope... | |
1523 | */ | |
b6eec9b7 DD |
1524 | static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data) |
1525 | { | |
1526 | u32 *pa = data; | |
235b2c77 RM |
1527 | u8 bus = PCI_BUS_NUM(*pa); |
1528 | ||
1529 | if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus) | |
1530 | *pa = alias; | |
b6eec9b7 | 1531 | |
b6eec9b7 DD |
1532 | return 0; |
1533 | } | |
235b2c77 | 1534 | |
b6eec9b7 DD |
1535 | /** |
1536 | * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID) | |
1537 | * @domain: The interrupt domain | |
1538 | * @pdev: The PCI device. | |
1539 | * | |
1540 | * The RID for a device is formed from the alias, with a firmware | |
1541 | * supplied mapping applied | |
1542 | * | |
1543 | * Returns: The RID. | |
1544 | */ | |
1545 | u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev) | |
1546 | { | |
1547 | struct device_node *of_node; | |
4e544bac | 1548 | u32 rid = pci_dev_id(pdev); |
b6eec9b7 DD |
1549 | |
1550 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
1551 | ||
1552 | of_node = irq_domain_get_of_node(domain); | |
2bcdd8f2 | 1553 | rid = of_node ? of_msi_map_id(&pdev->dev, of_node, rid) : |
39c3cf56 | 1554 | iort_msi_map_id(&pdev->dev, rid); |
b6eec9b7 DD |
1555 | |
1556 | return rid; | |
1557 | } | |
54fa97ee MZ |
1558 | |
1559 | /** | |
1560 | * pci_msi_get_device_domain - Get the MSI domain for a given PCI device | |
1561 | * @pdev: The PCI device | |
1562 | * | |
1563 | * Use the firmware data to find a device-specific MSI domain | |
235b2c77 | 1564 | * (i.e. not one that is set as a default). |
54fa97ee | 1565 | * |
235b2c77 | 1566 | * Returns: The corresponding MSI domain or NULL if none has been found. |
54fa97ee MZ |
1567 | */ |
1568 | struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) | |
1569 | { | |
be2021ba | 1570 | struct irq_domain *dom; |
4e544bac | 1571 | u32 rid = pci_dev_id(pdev); |
54fa97ee MZ |
1572 | |
1573 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
6f881aba | 1574 | dom = of_msi_map_get_device_domain(&pdev->dev, rid, DOMAIN_BUS_PCI_MSI); |
be2021ba | 1575 | if (!dom) |
d1718a1b LP |
1576 | dom = iort_get_device_domain(&pdev->dev, rid, |
1577 | DOMAIN_BUS_PCI_MSI); | |
be2021ba | 1578 | return dom; |
54fa97ee | 1579 | } |
2fd60266 TG |
1580 | |
1581 | /** | |
1582 | * pci_dev_has_special_msi_domain - Check whether the device is handled by | |
1583 | * a non-standard PCI-MSI domain | |
1584 | * @pdev: The PCI device to check. | |
1585 | * | |
1586 | * Returns: True if the device irqdomain or the bus irqdomain is | |
1587 | * non-standard PCI/MSI. | |
1588 | */ | |
1589 | bool pci_dev_has_special_msi_domain(struct pci_dev *pdev) | |
1590 | { | |
1591 | struct irq_domain *dom = dev_get_msi_domain(&pdev->dev); | |
1592 | ||
1593 | if (!dom) | |
1594 | dom = dev_get_msi_domain(&pdev->bus->dev); | |
1595 | ||
1596 | if (!dom) | |
1597 | return true; | |
1598 | ||
1599 | return dom->bus_token != DOMAIN_BUS_PCI_MSI; | |
1600 | } | |
1601 | ||
3878eaef | 1602 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |
cbc40d5c BH |
1603 | #endif /* CONFIG_PCI_MSI */ |
1604 | ||
1605 | void pci_msi_init(struct pci_dev *dev) | |
1606 | { | |
1607 | u16 ctrl; | |
1608 | ||
1609 | /* | |
1610 | * Disable the MSI hardware to avoid screaming interrupts | |
1611 | * during boot. This is the power on reset default so | |
1612 | * usually this should be a noop. | |
1613 | */ | |
1614 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1615 | if (!dev->msi_cap) | |
1616 | return; | |
1617 | ||
1618 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); | |
1619 | if (ctrl & PCI_MSI_FLAGS_ENABLE) | |
1620 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, | |
1621 | ctrl & ~PCI_MSI_FLAGS_ENABLE); | |
2053230a VS |
1622 | |
1623 | if (!(ctrl & PCI_MSI_FLAGS_64BIT)) | |
1624 | dev->no_64bit_msi = 1; | |
cbc40d5c BH |
1625 | } |
1626 | ||
1627 | void pci_msix_init(struct pci_dev *dev) | |
1628 | { | |
1629 | u16 ctrl; | |
1630 | ||
1631 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1632 | if (!dev->msix_cap) | |
1633 | return; | |
1634 | ||
1635 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
1636 | if (ctrl & PCI_MSIX_FLAGS_ENABLE) | |
1637 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, | |
1638 | ctrl & ~PCI_MSIX_FLAGS_ENABLE); | |
1639 | } |