Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
363c75db | 13 | #include <linux/export.h> |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
1da177e4 | 24 | |
1da177e4 | 25 | static int pci_msi_enable = 1; |
1da177e4 | 26 | |
527eee29 BH |
27 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
28 | ||
29 | ||
6a9e7f20 AB |
30 | /* Arch hooks */ |
31 | ||
4287d824 TP |
32 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
33 | { | |
0cbdcfcf TR |
34 | struct msi_chip *chip = dev->bus->msi; |
35 | int err; | |
36 | ||
37 | if (!chip || !chip->setup_irq) | |
38 | return -EINVAL; | |
39 | ||
40 | err = chip->setup_irq(chip, dev, desc); | |
41 | if (err < 0) | |
42 | return err; | |
43 | ||
44 | irq_set_chip_data(desc->irq, chip); | |
45 | ||
46 | return 0; | |
4287d824 TP |
47 | } |
48 | ||
49 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 50 | { |
0cbdcfcf TR |
51 | struct msi_chip *chip = irq_get_chip_data(irq); |
52 | ||
53 | if (!chip || !chip->teardown_irq) | |
54 | return; | |
55 | ||
56 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
57 | } |
58 | ||
4287d824 | 59 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
60 | { |
61 | struct msi_desc *entry; | |
62 | int ret; | |
63 | ||
1c8d7b0a MW |
64 | /* |
65 | * If an architecture wants to support multiple MSI, it needs to | |
66 | * override arch_setup_msi_irqs() | |
67 | */ | |
68 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
69 | return 1; | |
70 | ||
6a9e7f20 AB |
71 | list_for_each_entry(entry, &dev->msi_list, list) { |
72 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 73 | if (ret < 0) |
6a9e7f20 | 74 | return ret; |
b5fbf533 ME |
75 | if (ret > 0) |
76 | return -ENOSPC; | |
6a9e7f20 AB |
77 | } |
78 | ||
79 | return 0; | |
80 | } | |
1525bf0d | 81 | |
4287d824 TP |
82 | /* |
83 | * We have a default implementation available as a separate non-weak | |
84 | * function, as it is used by the Xen x86 PCI code | |
85 | */ | |
1525bf0d | 86 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
87 | { |
88 | struct msi_desc *entry; | |
89 | ||
90 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
91 | int i, nvec; |
92 | if (entry->irq == 0) | |
93 | continue; | |
65f6ae66 AG |
94 | if (entry->nvec_used) |
95 | nvec = entry->nvec_used; | |
96 | else | |
97 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
98 | for (i = 0; i < nvec; i++) |
99 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
100 | } |
101 | } | |
102 | ||
4287d824 TP |
103 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
104 | { | |
105 | return default_teardown_msi_irqs(dev); | |
106 | } | |
76ccc297 | 107 | |
ac8344c4 | 108 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
109 | { |
110 | struct msi_desc *entry; | |
111 | ||
112 | entry = NULL; | |
113 | if (dev->msix_enabled) { | |
114 | list_for_each_entry(entry, &dev->msi_list, list) { | |
115 | if (irq == entry->irq) | |
116 | break; | |
117 | } | |
118 | } else if (dev->msi_enabled) { | |
119 | entry = irq_get_msi_desc(irq); | |
120 | } | |
121 | ||
122 | if (entry) | |
56b72b40 | 123 | __write_msi_msg(entry, &entry->msg); |
76ccc297 | 124 | } |
4287d824 | 125 | |
ac8344c4 | 126 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 127 | { |
ac8344c4 | 128 | return default_restore_msi_irqs(dev); |
4287d824 | 129 | } |
76ccc297 | 130 | |
e375b561 | 131 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 132 | { |
b1cbf4e4 EB |
133 | u16 control; |
134 | ||
e375b561 | 135 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
136 | control &= ~PCI_MSI_FLAGS_ENABLE; |
137 | if (enable) | |
138 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 139 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
140 | } |
141 | ||
66f0d0c4 | 142 | static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) |
b1cbf4e4 | 143 | { |
66f0d0c4 | 144 | u16 ctrl; |
b1cbf4e4 | 145 | |
66f0d0c4 YW |
146 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); |
147 | ctrl &= ~clear; | |
148 | ctrl |= set; | |
149 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
b1cbf4e4 EB |
150 | } |
151 | ||
bffac3c5 MW |
152 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
153 | { | |
0b49ec37 MW |
154 | /* Don't shift by >= width of type */ |
155 | if (x >= 5) | |
156 | return 0xffffffff; | |
157 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
158 | } |
159 | ||
ce6fce42 MW |
160 | /* |
161 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
162 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
163 | * reliably as devices without an INTx disable bit will then generate a | |
164 | * level IRQ which will never be cleared. | |
ce6fce42 | 165 | */ |
0e4ccb15 | 166 | u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 167 | { |
f2440d9a | 168 | u32 mask_bits = desc->masked; |
1da177e4 | 169 | |
f2440d9a | 170 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 171 | return 0; |
f2440d9a MW |
172 | |
173 | mask_bits &= ~mask; | |
174 | mask_bits |= flag; | |
175 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
176 | |
177 | return mask_bits; | |
178 | } | |
179 | ||
0e4ccb15 KRW |
180 | __weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
181 | { | |
182 | return default_msi_mask_irq(desc, mask, flag); | |
183 | } | |
184 | ||
12abb8ba HS |
185 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
186 | { | |
0e4ccb15 | 187 | desc->masked = arch_msi_mask_irq(desc, mask, flag); |
f2440d9a MW |
188 | } |
189 | ||
190 | /* | |
191 | * This internal function does not flush PCI writes to the device. | |
192 | * All users must ensure that they read from the device before either | |
193 | * assuming that the device state is up to date, or returning out of this | |
194 | * file. This saves a few milliseconds when initialising devices with lots | |
195 | * of MSI-X interrupts. | |
196 | */ | |
0e4ccb15 | 197 | u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
198 | { |
199 | u32 mask_bits = desc->masked; | |
200 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 201 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
202 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
203 | if (flag) | |
204 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 205 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
206 | |
207 | return mask_bits; | |
208 | } | |
209 | ||
0e4ccb15 KRW |
210 | __weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag) |
211 | { | |
212 | return default_msix_mask_irq(desc, flag); | |
213 | } | |
214 | ||
12abb8ba HS |
215 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) |
216 | { | |
0e4ccb15 | 217 | desc->masked = arch_msix_mask_irq(desc, flag); |
f2440d9a | 218 | } |
24d27553 | 219 | |
1c9db525 | 220 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 221 | { |
1c9db525 | 222 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 223 | |
f2440d9a MW |
224 | if (desc->msi_attrib.is_msix) { |
225 | msix_mask_irq(desc, flag); | |
226 | readl(desc->mask_base); /* Flush write to device */ | |
227 | } else { | |
a281b788 | 228 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 229 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 230 | } |
f2440d9a MW |
231 | } |
232 | ||
1c9db525 | 233 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 234 | { |
1c9db525 | 235 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
236 | } |
237 | ||
1c9db525 | 238 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 239 | { |
1c9db525 | 240 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
241 | } |
242 | ||
ac8344c4 D |
243 | void default_restore_msi_irqs(struct pci_dev *dev) |
244 | { | |
245 | struct msi_desc *entry; | |
246 | ||
247 | list_for_each_entry(entry, &dev->msi_list, list) { | |
248 | default_restore_msi_irq(dev, entry->irq); | |
249 | } | |
250 | } | |
251 | ||
39431acb | 252 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 253 | { |
30da5524 BH |
254 | BUG_ON(entry->dev->current_state != PCI_D0); |
255 | ||
256 | if (entry->msi_attrib.is_msix) { | |
257 | void __iomem *base = entry->mask_base + | |
258 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
259 | ||
260 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
261 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
262 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
263 | } else { | |
264 | struct pci_dev *dev = entry->dev; | |
f5322169 | 265 | int pos = dev->msi_cap; |
30da5524 BH |
266 | u16 data; |
267 | ||
9925ad0c BH |
268 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
269 | &msg->address_lo); | |
30da5524 | 270 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
271 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
272 | &msg->address_hi); | |
2f221349 | 273 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
274 | } else { |
275 | msg->address_hi = 0; | |
2f221349 | 276 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
277 | } |
278 | msg->data = data; | |
279 | } | |
280 | } | |
281 | ||
282 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
283 | { | |
dced35ae | 284 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 285 | |
39431acb | 286 | __read_msi_msg(entry, msg); |
30da5524 BH |
287 | } |
288 | ||
39431acb | 289 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 290 | { |
30da5524 | 291 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
292 | * valid messages are not all-zeroes. */ |
293 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
294 | entry->msg.data)); | |
0366f8f7 | 295 | |
fcd097f3 | 296 | *msg = entry->msg; |
0366f8f7 | 297 | } |
1da177e4 | 298 | |
30da5524 | 299 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 300 | { |
dced35ae | 301 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 302 | |
39431acb | 303 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
304 | } |
305 | ||
39431acb | 306 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 307 | { |
fcd097f3 BH |
308 | if (entry->dev->current_state != PCI_D0) { |
309 | /* Don't touch the hardware now */ | |
310 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
311 | void __iomem *base; |
312 | base = entry->mask_base + | |
313 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
314 | ||
2c21fd4b HS |
315 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
316 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
317 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 318 | } else { |
0366f8f7 | 319 | struct pci_dev *dev = entry->dev; |
f5322169 | 320 | int pos = dev->msi_cap; |
1c8d7b0a MW |
321 | u16 msgctl; |
322 | ||
f84ecd28 | 323 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
324 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
325 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 326 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 327 | |
9925ad0c BH |
328 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
329 | msg->address_lo); | |
0366f8f7 | 330 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
331 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
332 | msg->address_hi); | |
2f221349 BH |
333 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
334 | msg->data); | |
0366f8f7 | 335 | } else { |
2f221349 BH |
336 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
337 | msg->data); | |
0366f8f7 | 338 | } |
1da177e4 | 339 | } |
392ee1e6 | 340 | entry->msg = *msg; |
1da177e4 | 341 | } |
0366f8f7 | 342 | |
3145e941 YL |
343 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
344 | { | |
dced35ae | 345 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 346 | |
39431acb | 347 | __write_msi_msg(entry, msg); |
3145e941 YL |
348 | } |
349 | ||
f56e4481 HS |
350 | static void free_msi_irqs(struct pci_dev *dev) |
351 | { | |
352 | struct msi_desc *entry, *tmp; | |
1c51b50c GKH |
353 | struct attribute **msi_attrs; |
354 | struct device_attribute *dev_attr; | |
355 | int count = 0; | |
f56e4481 HS |
356 | |
357 | list_for_each_entry(entry, &dev->msi_list, list) { | |
358 | int i, nvec; | |
359 | if (!entry->irq) | |
360 | continue; | |
65f6ae66 AG |
361 | if (entry->nvec_used) |
362 | nvec = entry->nvec_used; | |
363 | else | |
364 | nvec = 1 << entry->msi_attrib.multiple; | |
f56e4481 HS |
365 | for (i = 0; i < nvec; i++) |
366 | BUG_ON(irq_has_action(entry->irq + i)); | |
367 | } | |
368 | ||
369 | arch_teardown_msi_irqs(dev); | |
370 | ||
371 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
372 | if (entry->msi_attrib.is_msix) { | |
373 | if (list_is_last(&entry->list, &dev->msi_list)) | |
374 | iounmap(entry->mask_base); | |
375 | } | |
424eb391 | 376 | |
f56e4481 HS |
377 | list_del(&entry->list); |
378 | kfree(entry); | |
379 | } | |
1c51b50c GKH |
380 | |
381 | if (dev->msi_irq_groups) { | |
382 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
383 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 384 | while (msi_attrs[count]) { |
1c51b50c GKH |
385 | dev_attr = container_of(msi_attrs[count], |
386 | struct device_attribute, attr); | |
387 | kfree(dev_attr->attr.name); | |
388 | kfree(dev_attr); | |
389 | ++count; | |
390 | } | |
391 | kfree(msi_attrs); | |
392 | kfree(dev->msi_irq_groups[0]); | |
393 | kfree(dev->msi_irq_groups); | |
394 | dev->msi_irq_groups = NULL; | |
395 | } | |
f56e4481 | 396 | } |
c54c1879 | 397 | |
379f5327 | 398 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 399 | { |
379f5327 MW |
400 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
401 | if (!desc) | |
1da177e4 LT |
402 | return NULL; |
403 | ||
379f5327 MW |
404 | INIT_LIST_HEAD(&desc->list); |
405 | desc->dev = dev; | |
1da177e4 | 406 | |
379f5327 | 407 | return desc; |
1da177e4 LT |
408 | } |
409 | ||
ba698ad4 DM |
410 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
411 | { | |
412 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
413 | pci_intx(dev, enable); | |
414 | } | |
415 | ||
8fed4b65 | 416 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 417 | { |
41017f0c | 418 | u16 control; |
392ee1e6 | 419 | struct msi_desc *entry; |
41017f0c | 420 | |
b1cbf4e4 EB |
421 | if (!dev->msi_enabled) |
422 | return; | |
423 | ||
dced35ae | 424 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 425 | |
ba698ad4 | 426 | pci_intx_for_msi(dev, 0); |
e375b561 | 427 | msi_set_enable(dev, 0); |
ac8344c4 | 428 | arch_restore_msi_irqs(dev); |
392ee1e6 | 429 | |
f5322169 | 430 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
431 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
432 | entry->masked); | |
abad2ec9 | 433 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 434 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 435 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
436 | } |
437 | ||
438 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 439 | { |
41017f0c | 440 | struct msi_desc *entry; |
41017f0c | 441 | |
ded86d8d EB |
442 | if (!dev->msix_enabled) |
443 | return; | |
f598282f | 444 | BUG_ON(list_empty(&dev->msi_list)); |
ded86d8d | 445 | |
41017f0c | 446 | /* route the table */ |
ba698ad4 | 447 | pci_intx_for_msi(dev, 0); |
66f0d0c4 YW |
448 | msix_clear_and_set_ctrl(dev, 0, |
449 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); | |
41017f0c | 450 | |
ac8344c4 | 451 | arch_restore_msi_irqs(dev); |
4aa9bc95 | 452 | list_for_each_entry(entry, &dev->msi_list, list) { |
f2440d9a | 453 | msix_mask_irq(entry, entry->masked); |
41017f0c | 454 | } |
41017f0c | 455 | |
66f0d0c4 | 456 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 457 | } |
8fed4b65 ME |
458 | |
459 | void pci_restore_msi_state(struct pci_dev *dev) | |
460 | { | |
461 | __pci_restore_msi_state(dev); | |
462 | __pci_restore_msix_state(dev); | |
463 | } | |
94688cf2 | 464 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 465 | |
1c51b50c | 466 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
467 | char *buf) |
468 | { | |
1c51b50c GKH |
469 | struct msi_desc *entry; |
470 | unsigned long irq; | |
471 | int retval; | |
da8d1c8b | 472 | |
1c51b50c GKH |
473 | retval = kstrtoul(attr->attr.name, 10, &irq); |
474 | if (retval) | |
475 | return retval; | |
da8d1c8b | 476 | |
e11ece5a YW |
477 | entry = irq_get_msi_desc(irq); |
478 | if (entry) | |
479 | return sprintf(buf, "%s\n", | |
480 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
481 | ||
1c51b50c | 482 | return -ENODEV; |
da8d1c8b NH |
483 | } |
484 | ||
da8d1c8b NH |
485 | static int populate_msi_sysfs(struct pci_dev *pdev) |
486 | { | |
1c51b50c GKH |
487 | struct attribute **msi_attrs; |
488 | struct attribute *msi_attr; | |
489 | struct device_attribute *msi_dev_attr; | |
490 | struct attribute_group *msi_irq_group; | |
491 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 492 | struct msi_desc *entry; |
1c51b50c GKH |
493 | int ret = -ENOMEM; |
494 | int num_msi = 0; | |
da8d1c8b NH |
495 | int count = 0; |
496 | ||
1c51b50c GKH |
497 | /* Determine how many msi entries we have */ |
498 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
499 | ++num_msi; | |
500 | } | |
501 | if (!num_msi) | |
502 | return 0; | |
da8d1c8b | 503 | |
1c51b50c GKH |
504 | /* Dynamically create the MSI attributes for the PCI device */ |
505 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
506 | if (!msi_attrs) | |
507 | return -ENOMEM; | |
da8d1c8b | 508 | list_for_each_entry(entry, &pdev->msi_list, list) { |
1c51b50c | 509 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
1406276c | 510 | if (!msi_dev_attr) |
1c51b50c | 511 | goto error_attrs; |
1406276c | 512 | msi_attrs[count] = &msi_dev_attr->attr; |
86bb4f69 | 513 | |
1c51b50c | 514 | sysfs_attr_init(&msi_dev_attr->attr); |
1406276c JB |
515 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", |
516 | entry->irq); | |
517 | if (!msi_dev_attr->attr.name) | |
518 | goto error_attrs; | |
1c51b50c GKH |
519 | msi_dev_attr->attr.mode = S_IRUGO; |
520 | msi_dev_attr->show = msi_mode_show; | |
1c51b50c | 521 | ++count; |
da8d1c8b NH |
522 | } |
523 | ||
1c51b50c GKH |
524 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
525 | if (!msi_irq_group) | |
526 | goto error_attrs; | |
527 | msi_irq_group->name = "msi_irqs"; | |
528 | msi_irq_group->attrs = msi_attrs; | |
529 | ||
530 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
531 | if (!msi_irq_groups) | |
532 | goto error_irq_group; | |
533 | msi_irq_groups[0] = msi_irq_group; | |
534 | ||
535 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
536 | if (ret) | |
537 | goto error_irq_groups; | |
538 | pdev->msi_irq_groups = msi_irq_groups; | |
539 | ||
da8d1c8b NH |
540 | return 0; |
541 | ||
1c51b50c GKH |
542 | error_irq_groups: |
543 | kfree(msi_irq_groups); | |
544 | error_irq_group: | |
545 | kfree(msi_irq_group); | |
546 | error_attrs: | |
547 | count = 0; | |
548 | msi_attr = msi_attrs[count]; | |
549 | while (msi_attr) { | |
550 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
551 | kfree(msi_attr->name); | |
552 | kfree(msi_dev_attr); | |
553 | ++count; | |
554 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 555 | } |
29237756 | 556 | kfree(msi_attrs); |
da8d1c8b NH |
557 | return ret; |
558 | } | |
559 | ||
d873b4d4 YW |
560 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev) |
561 | { | |
562 | u16 control; | |
563 | struct msi_desc *entry; | |
564 | ||
565 | /* MSI Entry Initialization */ | |
566 | entry = alloc_msi_entry(dev); | |
567 | if (!entry) | |
568 | return NULL; | |
569 | ||
570 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
571 | ||
572 | entry->msi_attrib.is_msix = 0; | |
573 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
574 | entry->msi_attrib.entry_nr = 0; | |
575 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
576 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 YW |
577 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
578 | ||
579 | if (control & PCI_MSI_FLAGS_64BIT) | |
580 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
581 | else | |
582 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
583 | ||
584 | /* Save the initial mask status */ | |
585 | if (entry->msi_attrib.maskbit) | |
586 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
587 | ||
588 | return entry; | |
589 | } | |
590 | ||
1da177e4 LT |
591 | /** |
592 | * msi_capability_init - configure device's MSI capability structure | |
593 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 594 | * @nvec: number of interrupts to allocate |
1da177e4 | 595 | * |
1c8d7b0a MW |
596 | * Setup the MSI capability structure of the device with the requested |
597 | * number of interrupts. A return value of zero indicates the successful | |
598 | * setup of an entry with the new MSI irq. A negative return value indicates | |
599 | * an error, and a positive return value indicates the number of interrupts | |
600 | * which could have been allocated. | |
601 | */ | |
602 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
603 | { |
604 | struct msi_desc *entry; | |
f465136d | 605 | int ret; |
f2440d9a | 606 | unsigned mask; |
1da177e4 | 607 | |
e375b561 | 608 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 609 | |
d873b4d4 | 610 | entry = msi_setup_entry(dev); |
f7feaca7 EB |
611 | if (!entry) |
612 | return -ENOMEM; | |
1ce03373 | 613 | |
f2440d9a | 614 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 615 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
616 | msi_mask_irq(entry, mask, mask); |
617 | ||
0dd11f9b | 618 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 619 | |
1da177e4 | 620 | /* Configure MSI capability structure */ |
1c8d7b0a | 621 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 622 | if (ret) { |
7ba1930d | 623 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 624 | free_msi_irqs(dev); |
7fe3730d | 625 | return ret; |
fd58e55f | 626 | } |
f7feaca7 | 627 | |
da8d1c8b NH |
628 | ret = populate_msi_sysfs(dev); |
629 | if (ret) { | |
630 | msi_mask_irq(entry, mask, ~mask); | |
631 | free_msi_irqs(dev); | |
632 | return ret; | |
633 | } | |
634 | ||
1da177e4 | 635 | /* Set MSI enabled bits */ |
ba698ad4 | 636 | pci_intx_for_msi(dev, 0); |
e375b561 | 637 | msi_set_enable(dev, 1); |
b1cbf4e4 | 638 | dev->msi_enabled = 1; |
1da177e4 | 639 | |
7fe3730d | 640 | dev->irq = entry->irq; |
1da177e4 LT |
641 | return 0; |
642 | } | |
643 | ||
520fe9dc | 644 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 645 | { |
4302e0fb | 646 | resource_size_t phys_addr; |
5a05a9d8 HS |
647 | u32 table_offset; |
648 | u8 bir; | |
649 | ||
909094c6 BH |
650 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
651 | &table_offset); | |
4d18760c BH |
652 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
653 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
654 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
655 | ||
656 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
657 | } | |
658 | ||
520fe9dc GS |
659 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
660 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
661 | { |
662 | struct msi_desc *entry; | |
663 | int i; | |
664 | ||
665 | for (i = 0; i < nvec; i++) { | |
666 | entry = alloc_msi_entry(dev); | |
667 | if (!entry) { | |
668 | if (!i) | |
669 | iounmap(base); | |
670 | else | |
671 | free_msi_irqs(dev); | |
672 | /* No enough memory. Don't try again */ | |
673 | return -ENOMEM; | |
674 | } | |
675 | ||
676 | entry->msi_attrib.is_msix = 1; | |
677 | entry->msi_attrib.is_64 = 1; | |
678 | entry->msi_attrib.entry_nr = entries[i].entry; | |
679 | entry->msi_attrib.default_irq = dev->irq; | |
d9d7070e HS |
680 | entry->mask_base = base; |
681 | ||
682 | list_add_tail(&entry->list, &dev->msi_list); | |
683 | } | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
75cb3426 | 688 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 689 | struct msix_entry *entries) |
75cb3426 HS |
690 | { |
691 | struct msi_desc *entry; | |
692 | int i = 0; | |
693 | ||
694 | list_for_each_entry(entry, &dev->msi_list, list) { | |
695 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
696 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
697 | ||
698 | entries[i].vector = entry->irq; | |
dced35ae | 699 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
700 | entry->masked = readl(entry->mask_base + offset); |
701 | msix_mask_irq(entry, 1); | |
702 | i++; | |
703 | } | |
704 | } | |
705 | ||
1da177e4 LT |
706 | /** |
707 | * msix_capability_init - configure device's MSI-X capability | |
708 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
709 | * @entries: pointer to an array of struct msix_entry entries |
710 | * @nvec: number of @entries | |
1da177e4 | 711 | * |
eaae4b3a | 712 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
713 | * single MSI-X irq. A return of zero indicates the successful setup of |
714 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
715 | **/ |
716 | static int msix_capability_init(struct pci_dev *dev, | |
717 | struct msix_entry *entries, int nvec) | |
718 | { | |
520fe9dc | 719 | int ret; |
5a05a9d8 | 720 | u16 control; |
1da177e4 LT |
721 | void __iomem *base; |
722 | ||
f598282f | 723 | /* Ensure MSI-X is disabled while it is set up */ |
66f0d0c4 | 724 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 725 | |
66f0d0c4 | 726 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 727 | /* Request & Map MSI-X table region */ |
527eee29 | 728 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 729 | if (!base) |
1da177e4 LT |
730 | return -ENOMEM; |
731 | ||
520fe9dc | 732 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
733 | if (ret) |
734 | return ret; | |
9c831334 ME |
735 | |
736 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 | 737 | if (ret) |
2adc7907 | 738 | goto out_avail; |
9c831334 | 739 | |
f598282f MW |
740 | /* |
741 | * Some devices require MSI-X to be enabled before we can touch the | |
742 | * MSI-X registers. We need to mask all the vectors to prevent | |
743 | * interrupts coming in before they're fully set up. | |
744 | */ | |
66f0d0c4 YW |
745 | msix_clear_and_set_ctrl(dev, 0, |
746 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); | |
f598282f | 747 | |
75cb3426 | 748 | msix_program_entries(dev, entries); |
f598282f | 749 | |
da8d1c8b | 750 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
751 | if (ret) |
752 | goto out_free; | |
da8d1c8b | 753 | |
f598282f | 754 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 755 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 756 | dev->msix_enabled = 1; |
1da177e4 | 757 | |
66f0d0c4 | 758 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 759 | |
1da177e4 | 760 | return 0; |
583871d4 | 761 | |
2adc7907 | 762 | out_avail: |
583871d4 HS |
763 | if (ret < 0) { |
764 | /* | |
765 | * If we had some success, report the number of irqs | |
766 | * we succeeded in setting up. | |
767 | */ | |
d9d7070e | 768 | struct msi_desc *entry; |
583871d4 HS |
769 | int avail = 0; |
770 | ||
771 | list_for_each_entry(entry, &dev->msi_list, list) { | |
772 | if (entry->irq != 0) | |
773 | avail++; | |
774 | } | |
775 | if (avail != 0) | |
776 | ret = avail; | |
777 | } | |
778 | ||
2adc7907 | 779 | out_free: |
583871d4 HS |
780 | free_msi_irqs(dev); |
781 | ||
782 | return ret; | |
1da177e4 LT |
783 | } |
784 | ||
24334a12 | 785 | /** |
a06cd74c | 786 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 787 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 788 | * @nvec: how many MSIs have been requested ? |
24334a12 | 789 | * |
f7625980 | 790 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 791 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 792 | * supported return 1, else return 0. |
24334a12 | 793 | **/ |
a06cd74c | 794 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
795 | { |
796 | struct pci_bus *bus; | |
797 | ||
0306ebfa | 798 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 799 | if (!pci_msi_enable) |
a06cd74c | 800 | return 0; |
27e20603 AG |
801 | |
802 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 803 | return 0; |
24334a12 | 804 | |
314e77b3 ME |
805 | /* |
806 | * You can't ask to have 0 or less MSIs configured. | |
807 | * a) it's stupid .. | |
808 | * b) the list manipulation code assumes nvec >= 1. | |
809 | */ | |
810 | if (nvec < 1) | |
a06cd74c | 811 | return 0; |
314e77b3 | 812 | |
500559a9 HS |
813 | /* |
814 | * Any bridge which does NOT route MSI transactions from its | |
815 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
816 | * the secondary pci_bus. |
817 | * We expect only arch-specific PCI host bus controller driver | |
818 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
819 | */ | |
24334a12 BG |
820 | for (bus = dev->bus; bus; bus = bus->parent) |
821 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 822 | return 0; |
24334a12 | 823 | |
a06cd74c | 824 | return 1; |
24334a12 BG |
825 | } |
826 | ||
d1ac1d26 AG |
827 | /** |
828 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
829 | * @dev: device to report about | |
830 | * | |
831 | * This function returns the number of MSI vectors a device requested via | |
832 | * Multiple Message Capable register. It returns a negative errno if the | |
833 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
834 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
835 | * MSI specification. | |
836 | **/ | |
837 | int pci_msi_vec_count(struct pci_dev *dev) | |
838 | { | |
839 | int ret; | |
840 | u16 msgctl; | |
841 | ||
842 | if (!dev->msi_cap) | |
843 | return -EINVAL; | |
844 | ||
845 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
846 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
847 | ||
848 | return ret; | |
849 | } | |
850 | EXPORT_SYMBOL(pci_msi_vec_count); | |
851 | ||
f2440d9a | 852 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 853 | { |
f2440d9a MW |
854 | struct msi_desc *desc; |
855 | u32 mask; | |
1da177e4 | 856 | |
128bc5fc | 857 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
858 | return; |
859 | ||
110828c9 MW |
860 | BUG_ON(list_empty(&dev->msi_list)); |
861 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 862 | |
e375b561 | 863 | msi_set_enable(dev, 0); |
ba698ad4 | 864 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 865 | dev->msi_enabled = 0; |
7bd007e4 | 866 | |
12abb8ba | 867 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 868 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 869 | /* Keep cached state to be restored */ |
0e4ccb15 | 870 | arch_msi_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
871 | |
872 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 873 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 874 | } |
24d27553 | 875 | |
500559a9 | 876 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 877 | { |
d52877c7 YL |
878 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
879 | return; | |
880 | ||
881 | pci_msi_shutdown(dev); | |
f56e4481 | 882 | free_msi_irqs(dev); |
1da177e4 | 883 | } |
4cc086fa | 884 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 885 | |
a52e2e35 | 886 | /** |
ff1aa430 | 887 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 888 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
889 | * This function returns the number of device's MSI-X table entries and |
890 | * therefore the number of MSI-X vectors device is capable of sending. | |
891 | * It returns a negative errno if the device is not capable of sending MSI-X | |
892 | * interrupts. | |
893 | **/ | |
894 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 895 | { |
a52e2e35 RW |
896 | u16 control; |
897 | ||
520fe9dc | 898 | if (!dev->msix_cap) |
ff1aa430 | 899 | return -EINVAL; |
a52e2e35 | 900 | |
f84ecd28 | 901 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 902 | return msix_table_size(control); |
a52e2e35 | 903 | } |
ff1aa430 | 904 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 905 | |
1da177e4 LT |
906 | /** |
907 | * pci_enable_msix - configure device's MSI-X capability structure | |
908 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 909 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 910 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
911 | * |
912 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 913 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
914 | * MSI-X mode enabled on its hardware device function. A return of zero |
915 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 916 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 917 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
918 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
919 | * re-send its request. | |
1da177e4 | 920 | **/ |
500559a9 | 921 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 922 | { |
5ec09405 | 923 | int nr_entries; |
ded86d8d | 924 | int i, j; |
1da177e4 | 925 | |
a06cd74c AG |
926 | if (!pci_msi_supported(dev, nvec)) |
927 | return -EINVAL; | |
c9953a73 | 928 | |
27e20603 AG |
929 | if (!entries) |
930 | return -EINVAL; | |
931 | ||
ff1aa430 AG |
932 | nr_entries = pci_msix_vec_count(dev); |
933 | if (nr_entries < 0) | |
934 | return nr_entries; | |
1da177e4 | 935 | if (nvec > nr_entries) |
57fbf52c | 936 | return nr_entries; |
1da177e4 LT |
937 | |
938 | /* Check for any invalid entries */ | |
939 | for (i = 0; i < nvec; i++) { | |
940 | if (entries[i].entry >= nr_entries) | |
941 | return -EINVAL; /* invalid entry */ | |
942 | for (j = i + 1; j < nvec; j++) { | |
943 | if (entries[i].entry == entries[j].entry) | |
944 | return -EINVAL; /* duplicate entry */ | |
945 | } | |
946 | } | |
ded86d8d | 947 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 948 | |
1ce03373 | 949 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 950 | if (dev->msi_enabled) { |
227f0647 | 951 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
952 | return -EINVAL; |
953 | } | |
5ec09405 | 954 | return msix_capability_init(dev, entries, nvec); |
1da177e4 | 955 | } |
4cc086fa | 956 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 957 | |
500559a9 | 958 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 959 | { |
12abb8ba HS |
960 | struct msi_desc *entry; |
961 | ||
128bc5fc | 962 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
963 | return; |
964 | ||
12abb8ba HS |
965 | /* Return the device with MSI-X masked as initial states */ |
966 | list_for_each_entry(entry, &dev->msi_list, list) { | |
967 | /* Keep cached states to be restored */ | |
0e4ccb15 | 968 | arch_msix_mask_irq(entry, 1); |
12abb8ba HS |
969 | } |
970 | ||
66f0d0c4 | 971 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 972 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 973 | dev->msix_enabled = 0; |
d52877c7 | 974 | } |
c901851f | 975 | |
500559a9 | 976 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
977 | { |
978 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
979 | return; | |
980 | ||
981 | pci_msix_shutdown(dev); | |
f56e4481 | 982 | free_msi_irqs(dev); |
1da177e4 | 983 | } |
4cc086fa | 984 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 985 | |
309e57df MW |
986 | void pci_no_msi(void) |
987 | { | |
988 | pci_msi_enable = 0; | |
989 | } | |
c9953a73 | 990 | |
07ae95f9 AP |
991 | /** |
992 | * pci_msi_enabled - is MSI enabled? | |
993 | * | |
994 | * Returns true if MSI has not been disabled by the command-line option | |
995 | * pci=nomsi. | |
996 | **/ | |
997 | int pci_msi_enabled(void) | |
d389fec6 | 998 | { |
07ae95f9 | 999 | return pci_msi_enable; |
d389fec6 | 1000 | } |
07ae95f9 | 1001 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1002 | |
07ae95f9 | 1003 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1004 | { |
07ae95f9 | 1005 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1006 | |
1007 | /* Disable the msi hardware to avoid screaming interrupts | |
1008 | * during boot. This is the power on reset default so | |
1009 | * usually this should be a noop. | |
1010 | */ | |
e375b561 GS |
1011 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1012 | if (dev->msi_cap) | |
1013 | msi_set_enable(dev, 0); | |
1014 | ||
1015 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1016 | if (dev->msix_cap) | |
66f0d0c4 | 1017 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
d389fec6 | 1018 | } |
302a2523 AG |
1019 | |
1020 | /** | |
1021 | * pci_enable_msi_range - configure device's MSI capability structure | |
1022 | * @dev: device to configure | |
1023 | * @minvec: minimal number of interrupts to configure | |
1024 | * @maxvec: maximum number of interrupts to configure | |
1025 | * | |
1026 | * This function tries to allocate a maximum possible number of interrupts in a | |
1027 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1028 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1029 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1030 | * the other interrupt numbers allocated to this device are consecutive. | |
1031 | **/ | |
1032 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1033 | { | |
034cd97e | 1034 | int nvec; |
302a2523 AG |
1035 | int rc; |
1036 | ||
a06cd74c AG |
1037 | if (!pci_msi_supported(dev, minvec)) |
1038 | return -EINVAL; | |
034cd97e AG |
1039 | |
1040 | WARN_ON(!!dev->msi_enabled); | |
1041 | ||
1042 | /* Check whether driver already requested MSI-X irqs */ | |
1043 | if (dev->msix_enabled) { | |
1044 | dev_info(&dev->dev, | |
1045 | "can't enable MSI (MSI-X already enabled)\n"); | |
1046 | return -EINVAL; | |
1047 | } | |
1048 | ||
302a2523 AG |
1049 | if (maxvec < minvec) |
1050 | return -ERANGE; | |
1051 | ||
034cd97e AG |
1052 | nvec = pci_msi_vec_count(dev); |
1053 | if (nvec < 0) | |
1054 | return nvec; | |
1055 | else if (nvec < minvec) | |
1056 | return -EINVAL; | |
1057 | else if (nvec > maxvec) | |
1058 | nvec = maxvec; | |
1059 | ||
302a2523 | 1060 | do { |
034cd97e | 1061 | rc = msi_capability_init(dev, nvec); |
302a2523 AG |
1062 | if (rc < 0) { |
1063 | return rc; | |
1064 | } else if (rc > 0) { | |
1065 | if (rc < minvec) | |
1066 | return -ENOSPC; | |
1067 | nvec = rc; | |
1068 | } | |
1069 | } while (rc); | |
1070 | ||
1071 | return nvec; | |
1072 | } | |
1073 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1074 | ||
1075 | /** | |
1076 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1077 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1078 | * @entries: pointer to an array of MSI-X entries | |
1079 | * @minvec: minimum number of MSI-X irqs requested | |
1080 | * @maxvec: maximum number of MSI-X irqs requested | |
1081 | * | |
1082 | * Setup the MSI-X capability structure of device function with a maximum | |
1083 | * possible number of interrupts in the range between @minvec and @maxvec | |
1084 | * upon its software driver call to request for MSI-X mode enabled on its | |
1085 | * hardware device function. It returns a negative errno if an error occurs. | |
1086 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1087 | * indicates the successful configuration of MSI-X capability structure | |
1088 | * with new allocated MSI-X interrupts. | |
1089 | **/ | |
1090 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1091 | int minvec, int maxvec) | |
1092 | { | |
1093 | int nvec = maxvec; | |
1094 | int rc; | |
1095 | ||
1096 | if (maxvec < minvec) | |
1097 | return -ERANGE; | |
1098 | ||
1099 | do { | |
1100 | rc = pci_enable_msix(dev, entries, nvec); | |
1101 | if (rc < 0) { | |
1102 | return rc; | |
1103 | } else if (rc > 0) { | |
1104 | if (rc < minvec) | |
1105 | return -ENOSPC; | |
1106 | nvec = rc; | |
1107 | } | |
1108 | } while (rc); | |
1109 | ||
1110 | return nvec; | |
1111 | } | |
1112 | EXPORT_SYMBOL(pci_enable_msix_range); |