Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
30 | int __attribute__ ((weak)) | |
31 | arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
32 | { | |
33 | return 0; | |
34 | } | |
35 | ||
36 | int __attribute__ ((weak)) | |
37 | arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *entry) | |
38 | { | |
39 | return 0; | |
40 | } | |
41 | ||
42 | int __attribute__ ((weak)) | |
43 | arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
44 | { | |
45 | struct msi_desc *entry; | |
46 | int ret; | |
47 | ||
48 | list_for_each_entry(entry, &dev->msi_list, list) { | |
49 | ret = arch_setup_msi_irq(dev, entry); | |
50 | if (ret) | |
51 | return ret; | |
52 | } | |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
57 | void __attribute__ ((weak)) arch_teardown_msi_irq(unsigned int irq) | |
58 | { | |
59 | return; | |
60 | } | |
61 | ||
62 | void __attribute__ ((weak)) | |
63 | arch_teardown_msi_irqs(struct pci_dev *dev) | |
64 | { | |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
68 | if (entry->irq != 0) | |
69 | arch_teardown_msi_irq(entry->irq); | |
70 | } | |
71 | } | |
72 | ||
5ca5c02f | 73 | static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 74 | { |
b1cbf4e4 EB |
75 | u16 control; |
76 | ||
b1cbf4e4 EB |
77 | if (pos) { |
78 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
79 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
80 | if (enable) | |
81 | control |= PCI_MSI_FLAGS_ENABLE; | |
82 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
83 | } | |
84 | } | |
85 | ||
5ca5c02f HS |
86 | static void msi_set_enable(struct pci_dev *dev, int enable) |
87 | { | |
88 | __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); | |
89 | } | |
90 | ||
b1cbf4e4 EB |
91 | static void msix_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | int pos; | |
94 | u16 control; | |
95 | ||
96 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
97 | if (pos) { | |
98 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
99 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
100 | if (enable) | |
101 | control |= PCI_MSIX_FLAGS_ENABLE; | |
102 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
103 | } | |
104 | } | |
105 | ||
988cbb15 MW |
106 | static void msix_flush_writes(unsigned int irq) |
107 | { | |
108 | struct msi_desc *entry; | |
109 | ||
110 | entry = get_irq_msi(irq); | |
111 | BUG_ON(!entry || !entry->dev); | |
112 | switch (entry->msi_attrib.type) { | |
113 | case PCI_CAP_ID_MSI: | |
114 | /* nothing to do */ | |
115 | break; | |
116 | case PCI_CAP_ID_MSIX: | |
117 | { | |
118 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
119 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
120 | readl(entry->mask_base + offset); | |
121 | break; | |
122 | } | |
123 | default: | |
124 | BUG(); | |
125 | break; | |
126 | } | |
127 | } | |
128 | ||
ce6fce42 MW |
129 | /* |
130 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
131 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
132 | * reliably as devices without an INTx disable bit will then generate a | |
133 | * level IRQ which will never be cleared. | |
134 | * | |
135 | * Returns 1 if it succeeded in masking the interrupt and 0 if the device | |
136 | * doesn't support MSI masking. | |
137 | */ | |
138 | static int msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag) | |
1da177e4 LT |
139 | { |
140 | struct msi_desc *entry; | |
141 | ||
5b912c10 | 142 | entry = get_irq_msi(irq); |
277bc33b | 143 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
144 | switch (entry->msi_attrib.type) { |
145 | case PCI_CAP_ID_MSI: | |
277bc33b | 146 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
147 | int pos; |
148 | u32 mask_bits; | |
277bc33b EB |
149 | |
150 | pos = (long)entry->mask_base; | |
151 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
8e149e09 YL |
152 | mask_bits &= ~(mask); |
153 | mask_bits |= flag & mask; | |
277bc33b | 154 | pci_write_config_dword(entry->dev, pos, mask_bits); |
58e0543e | 155 | } else { |
ce6fce42 | 156 | return 0; |
277bc33b | 157 | } |
1da177e4 | 158 | break; |
1da177e4 LT |
159 | case PCI_CAP_ID_MSIX: |
160 | { | |
161 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
162 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
163 | writel(flag, entry->mask_base + offset); | |
348e3fd1 | 164 | readl(entry->mask_base + offset); |
1da177e4 LT |
165 | break; |
166 | } | |
167 | default: | |
277bc33b | 168 | BUG(); |
1da177e4 LT |
169 | break; |
170 | } | |
392ee1e6 | 171 | entry->msi_attrib.masked = !!flag; |
ce6fce42 | 172 | return 1; |
1da177e4 LT |
173 | } |
174 | ||
3b7d1921 | 175 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 176 | { |
5b912c10 | 177 | struct msi_desc *entry = get_irq_msi(irq); |
0366f8f7 EB |
178 | switch(entry->msi_attrib.type) { |
179 | case PCI_CAP_ID_MSI: | |
180 | { | |
181 | struct pci_dev *dev = entry->dev; | |
182 | int pos = entry->msi_attrib.pos; | |
183 | u16 data; | |
184 | ||
185 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
186 | &msg->address_lo); | |
187 | if (entry->msi_attrib.is_64) { | |
188 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
189 | &msg->address_hi); | |
190 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
191 | } else { | |
192 | msg->address_hi = 0; | |
cbf5d9e6 | 193 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
194 | } |
195 | msg->data = data; | |
196 | break; | |
197 | } | |
198 | case PCI_CAP_ID_MSIX: | |
199 | { | |
200 | void __iomem *base; | |
201 | base = entry->mask_base + | |
202 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
203 | ||
204 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
205 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
206 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
207 | break; | |
208 | } | |
209 | default: | |
210 | BUG(); | |
211 | } | |
212 | } | |
1da177e4 | 213 | |
3b7d1921 | 214 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 215 | { |
5b912c10 | 216 | struct msi_desc *entry = get_irq_msi(irq); |
1da177e4 LT |
217 | switch (entry->msi_attrib.type) { |
218 | case PCI_CAP_ID_MSI: | |
219 | { | |
0366f8f7 EB |
220 | struct pci_dev *dev = entry->dev; |
221 | int pos = entry->msi_attrib.pos; | |
222 | ||
223 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
224 | msg->address_lo); | |
225 | if (entry->msi_attrib.is_64) { | |
226 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
227 | msg->address_hi); | |
228 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
229 | msg->data); | |
230 | } else { | |
231 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
232 | msg->data); | |
233 | } | |
1da177e4 LT |
234 | break; |
235 | } | |
236 | case PCI_CAP_ID_MSIX: | |
237 | { | |
0366f8f7 EB |
238 | void __iomem *base; |
239 | base = entry->mask_base + | |
240 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
241 | ||
242 | writel(msg->address_lo, | |
243 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
244 | writel(msg->address_hi, | |
245 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
246 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
247 | break; |
248 | } | |
249 | default: | |
0366f8f7 | 250 | BUG(); |
1da177e4 | 251 | } |
392ee1e6 | 252 | entry->msg = *msg; |
1da177e4 | 253 | } |
0366f8f7 | 254 | |
3b7d1921 | 255 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 256 | { |
8e149e09 | 257 | msi_set_mask_bits(irq, 1, 1); |
988cbb15 | 258 | msix_flush_writes(irq); |
1da177e4 LT |
259 | } |
260 | ||
3b7d1921 | 261 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 262 | { |
8e149e09 | 263 | msi_set_mask_bits(irq, 1, 0); |
988cbb15 | 264 | msix_flush_writes(irq); |
1da177e4 LT |
265 | } |
266 | ||
032de8e2 | 267 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 268 | |
1da177e4 | 269 | |
1da177e4 LT |
270 | static struct msi_desc* alloc_msi_entry(void) |
271 | { | |
272 | struct msi_desc *entry; | |
273 | ||
3e916c05 | 274 | entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL); |
1da177e4 LT |
275 | if (!entry) |
276 | return NULL; | |
277 | ||
4aa9bc95 ME |
278 | INIT_LIST_HEAD(&entry->list); |
279 | entry->irq = 0; | |
1da177e4 LT |
280 | entry->dev = NULL; |
281 | ||
282 | return entry; | |
283 | } | |
284 | ||
ba698ad4 DM |
285 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
286 | { | |
287 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
288 | pci_intx(dev, enable); | |
289 | } | |
290 | ||
8fed4b65 | 291 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 292 | { |
392ee1e6 | 293 | int pos; |
41017f0c | 294 | u16 control; |
392ee1e6 | 295 | struct msi_desc *entry; |
41017f0c | 296 | |
b1cbf4e4 EB |
297 | if (!dev->msi_enabled) |
298 | return; | |
299 | ||
392ee1e6 EB |
300 | entry = get_irq_msi(dev->irq); |
301 | pos = entry->msi_attrib.pos; | |
41017f0c | 302 | |
ba698ad4 | 303 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 304 | msi_set_enable(dev, 0); |
392ee1e6 EB |
305 | write_msi_msg(dev->irq, &entry->msg); |
306 | if (entry->msi_attrib.maskbit) | |
8e149e09 YL |
307 | msi_set_mask_bits(dev->irq, entry->msi_attrib.maskbits_mask, |
308 | entry->msi_attrib.masked); | |
392ee1e6 EB |
309 | |
310 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
311 | control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE); | |
312 | if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked) | |
313 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 314 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
315 | } |
316 | ||
317 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 318 | { |
41017f0c | 319 | int pos; |
41017f0c | 320 | struct msi_desc *entry; |
392ee1e6 | 321 | u16 control; |
41017f0c | 322 | |
ded86d8d EB |
323 | if (!dev->msix_enabled) |
324 | return; | |
325 | ||
41017f0c | 326 | /* route the table */ |
ba698ad4 | 327 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 328 | msix_set_enable(dev, 0); |
41017f0c | 329 | |
4aa9bc95 ME |
330 | list_for_each_entry(entry, &dev->msi_list, list) { |
331 | write_msi_msg(entry->irq, &entry->msg); | |
8e149e09 | 332 | msi_set_mask_bits(entry->irq, 1, entry->msi_attrib.masked); |
41017f0c | 333 | } |
41017f0c | 334 | |
314e77b3 ME |
335 | BUG_ON(list_empty(&dev->msi_list)); |
336 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
4aa9bc95 | 337 | pos = entry->msi_attrib.pos; |
392ee1e6 EB |
338 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
339 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
340 | control |= PCI_MSIX_FLAGS_ENABLE; | |
341 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 342 | } |
8fed4b65 ME |
343 | |
344 | void pci_restore_msi_state(struct pci_dev *dev) | |
345 | { | |
346 | __pci_restore_msi_state(dev); | |
347 | __pci_restore_msix_state(dev); | |
348 | } | |
94688cf2 | 349 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 350 | |
1da177e4 LT |
351 | /** |
352 | * msi_capability_init - configure device's MSI capability structure | |
353 | * @dev: pointer to the pci_dev data structure of MSI device function | |
354 | * | |
eaae4b3a | 355 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 356 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 357 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 358 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
359 | **/ |
360 | static int msi_capability_init(struct pci_dev *dev) | |
361 | { | |
362 | struct msi_desc *entry; | |
7fe3730d | 363 | int pos, ret; |
1da177e4 LT |
364 | u16 control; |
365 | ||
b1cbf4e4 EB |
366 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
367 | ||
1da177e4 LT |
368 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
369 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
370 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
371 | entry = alloc_msi_entry(); |
372 | if (!entry) | |
373 | return -ENOMEM; | |
1ce03373 | 374 | |
1da177e4 | 375 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 376 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
377 | entry->msi_attrib.entry_nr = 0; |
378 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 379 | entry->msi_attrib.masked = 1; |
1ce03373 | 380 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 381 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
382 | if (is_mask_bit_support(control)) { |
383 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
384 | is_64bit_address(control)); | |
385 | } | |
3b7d1921 EB |
386 | entry->dev = dev; |
387 | if (entry->msi_attrib.maskbit) { | |
388 | unsigned int maskbits, temp; | |
389 | /* All MSIs are unmasked by default, Mask them all */ | |
390 | pci_read_config_dword(dev, | |
391 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
392 | &maskbits); | |
393 | temp = (1 << multi_msi_capable(control)); | |
394 | temp = ((temp - 1) & ~temp); | |
395 | maskbits |= temp; | |
396 | pci_write_config_dword(dev, | |
397 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
398 | maskbits); | |
8e149e09 | 399 | entry->msi_attrib.maskbits_mask = temp; |
3b7d1921 | 400 | } |
0dd11f9b | 401 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 402 | |
1da177e4 | 403 | /* Configure MSI capability structure */ |
9c831334 | 404 | ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI); |
7fe3730d | 405 | if (ret) { |
032de8e2 | 406 | msi_free_irqs(dev); |
7fe3730d | 407 | return ret; |
fd58e55f | 408 | } |
f7feaca7 | 409 | |
1da177e4 | 410 | /* Set MSI enabled bits */ |
ba698ad4 | 411 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
412 | msi_set_enable(dev, 1); |
413 | dev->msi_enabled = 1; | |
1da177e4 | 414 | |
7fe3730d | 415 | dev->irq = entry->irq; |
1da177e4 LT |
416 | return 0; |
417 | } | |
418 | ||
419 | /** | |
420 | * msix_capability_init - configure device's MSI-X capability | |
421 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
422 | * @entries: pointer to an array of struct msix_entry entries |
423 | * @nvec: number of @entries | |
1da177e4 | 424 | * |
eaae4b3a | 425 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
426 | * single MSI-X irq. A return of zero indicates the successful setup of |
427 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
428 | **/ |
429 | static int msix_capability_init(struct pci_dev *dev, | |
430 | struct msix_entry *entries, int nvec) | |
431 | { | |
4aa9bc95 | 432 | struct msi_desc *entry; |
9c831334 | 433 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
434 | unsigned long phys_addr; |
435 | u32 table_offset; | |
1da177e4 LT |
436 | u16 control; |
437 | u8 bir; | |
438 | void __iomem *base; | |
439 | ||
b1cbf4e4 EB |
440 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
441 | ||
1da177e4 LT |
442 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
443 | /* Request & Map MSI-X table region */ | |
444 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
445 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
446 | |
447 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 448 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
449 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
450 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
451 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
452 | if (base == NULL) | |
453 | return -ENOMEM; | |
454 | ||
455 | /* MSI-X Table Initialization */ | |
456 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
457 | entry = alloc_msi_entry(); |
458 | if (!entry) | |
1da177e4 | 459 | break; |
1da177e4 LT |
460 | |
461 | j = entries[i].entry; | |
1da177e4 | 462 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 463 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
464 | entry->msi_attrib.entry_nr = j; |
465 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 466 | entry->msi_attrib.masked = 1; |
1ce03373 | 467 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 468 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
469 | entry->dev = dev; |
470 | entry->mask_base = base; | |
f7feaca7 | 471 | |
0dd11f9b | 472 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 473 | } |
9c831334 ME |
474 | |
475 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
476 | if (ret) { | |
477 | int avail = 0; | |
478 | list_for_each_entry(entry, &dev->msi_list, list) { | |
479 | if (entry->irq != 0) { | |
480 | avail++; | |
9c831334 | 481 | } |
1da177e4 | 482 | } |
9c831334 | 483 | |
032de8e2 ME |
484 | msi_free_irqs(dev); |
485 | ||
92db6d10 EB |
486 | /* If we had some success report the number of irqs |
487 | * we succeeded in setting up. | |
488 | */ | |
9c831334 ME |
489 | if (avail == 0) |
490 | avail = ret; | |
92db6d10 | 491 | return avail; |
1da177e4 | 492 | } |
9c831334 ME |
493 | |
494 | i = 0; | |
495 | list_for_each_entry(entry, &dev->msi_list, list) { | |
496 | entries[i].vector = entry->irq; | |
497 | set_irq_msi(entry->irq, entry); | |
498 | i++; | |
499 | } | |
1da177e4 | 500 | /* Set MSI-X enabled bits */ |
ba698ad4 | 501 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
502 | msix_set_enable(dev, 1); |
503 | dev->msix_enabled = 1; | |
1da177e4 LT |
504 | |
505 | return 0; | |
506 | } | |
507 | ||
24334a12 | 508 | /** |
17bbc12a | 509 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 510 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 511 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 512 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 513 | * |
0306ebfa | 514 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
515 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
516 | * supported return 0, else return an error code. | |
24334a12 | 517 | **/ |
c9953a73 | 518 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
519 | { |
520 | struct pci_bus *bus; | |
c9953a73 | 521 | int ret; |
24334a12 | 522 | |
0306ebfa | 523 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
524 | if (!pci_msi_enable || !dev || dev->no_msi) |
525 | return -EINVAL; | |
526 | ||
314e77b3 ME |
527 | /* |
528 | * You can't ask to have 0 or less MSIs configured. | |
529 | * a) it's stupid .. | |
530 | * b) the list manipulation code assumes nvec >= 1. | |
531 | */ | |
532 | if (nvec < 1) | |
533 | return -ERANGE; | |
534 | ||
0306ebfa BG |
535 | /* Any bridge which does NOT route MSI transactions from it's |
536 | * secondary bus to it's primary bus must set NO_MSI flag on | |
537 | * the secondary pci_bus. | |
538 | * We expect only arch-specific PCI host bus controller driver | |
539 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
540 | */ | |
24334a12 BG |
541 | for (bus = dev->bus; bus; bus = bus->parent) |
542 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
543 | return -EINVAL; | |
544 | ||
c9953a73 ME |
545 | ret = arch_msi_check_device(dev, nvec, type); |
546 | if (ret) | |
547 | return ret; | |
548 | ||
b1e2303d ME |
549 | if (!pci_find_capability(dev, type)) |
550 | return -EINVAL; | |
551 | ||
24334a12 BG |
552 | return 0; |
553 | } | |
554 | ||
1da177e4 LT |
555 | /** |
556 | * pci_enable_msi - configure device's MSI capability structure | |
557 | * @dev: pointer to the pci_dev data structure of MSI device function | |
558 | * | |
559 | * Setup the MSI capability structure of device function with | |
1ce03373 | 560 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
561 | * MSI mode enabled on its hardware device function. A return of zero |
562 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 563 | * irq or non-zero for otherwise. |
1da177e4 LT |
564 | **/ |
565 | int pci_enable_msi(struct pci_dev* dev) | |
566 | { | |
b1e2303d | 567 | int status; |
1da177e4 | 568 | |
c9953a73 ME |
569 | status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI); |
570 | if (status) | |
571 | return status; | |
1da177e4 | 572 | |
ded86d8d | 573 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 574 | |
1ce03373 | 575 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 | 576 | if (dev->msix_enabled) { |
80ccba11 BH |
577 | dev_info(&dev->dev, "can't enable MSI " |
578 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 579 | return -EINVAL; |
1da177e4 LT |
580 | } |
581 | status = msi_capability_init(dev); | |
1da177e4 LT |
582 | return status; |
583 | } | |
4cc086fa | 584 | EXPORT_SYMBOL(pci_enable_msi); |
1da177e4 | 585 | |
d52877c7 | 586 | void pci_msi_shutdown(struct pci_dev* dev) |
1da177e4 LT |
587 | { |
588 | struct msi_desc *entry; | |
1da177e4 | 589 | |
128bc5fc | 590 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
591 | return; |
592 | ||
b1cbf4e4 | 593 | msi_set_enable(dev, 0); |
ba698ad4 | 594 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 595 | dev->msi_enabled = 0; |
7bd007e4 | 596 | |
314e77b3 ME |
597 | BUG_ON(list_empty(&dev->msi_list)); |
598 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
8e149e09 YL |
599 | /* Return the the pci reset with msi irqs unmasked */ |
600 | if (entry->msi_attrib.maskbit) { | |
601 | u32 mask = entry->msi_attrib.maskbits_mask; | |
602 | msi_set_mask_bits(dev->irq, mask, ~mask); | |
603 | } | |
d52877c7 | 604 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) |
1da177e4 | 605 | return; |
e387b9ee ME |
606 | |
607 | /* Restore dev->irq to its default pin-assertion irq */ | |
d52877c7 YL |
608 | dev->irq = entry->msi_attrib.default_irq; |
609 | } | |
610 | void pci_disable_msi(struct pci_dev* dev) | |
611 | { | |
612 | struct msi_desc *entry; | |
613 | ||
614 | if (!pci_msi_enable || !dev || !dev->msi_enabled) | |
615 | return; | |
616 | ||
617 | pci_msi_shutdown(dev); | |
618 | ||
619 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
620 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) | |
621 | return; | |
622 | ||
623 | msi_free_irqs(dev); | |
1da177e4 | 624 | } |
4cc086fa | 625 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 626 | |
032de8e2 | 627 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 628 | { |
032de8e2 | 629 | struct msi_desc *entry, *tmp; |
7ede9c1f | 630 | |
b3b7cc7b DM |
631 | list_for_each_entry(entry, &dev->msi_list, list) { |
632 | if (entry->irq) | |
633 | BUG_ON(irq_has_action(entry->irq)); | |
634 | } | |
1da177e4 | 635 | |
032de8e2 | 636 | arch_teardown_msi_irqs(dev); |
1da177e4 | 637 | |
032de8e2 ME |
638 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
639 | if (entry->msi_attrib.type == PCI_CAP_ID_MSIX) { | |
032de8e2 ME |
640 | writel(1, entry->mask_base + entry->msi_attrib.entry_nr |
641 | * PCI_MSIX_ENTRY_SIZE | |
642 | + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
78b7611c EB |
643 | |
644 | if (list_is_last(&entry->list, &dev->msi_list)) | |
645 | iounmap(entry->mask_base); | |
032de8e2 ME |
646 | } |
647 | list_del(&entry->list); | |
648 | kfree(entry); | |
1da177e4 LT |
649 | } |
650 | ||
651 | return 0; | |
652 | } | |
653 | ||
1da177e4 LT |
654 | /** |
655 | * pci_enable_msix - configure device's MSI-X capability structure | |
656 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 657 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 658 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
659 | * |
660 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 661 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
662 | * MSI-X mode enabled on its hardware device function. A return of zero |
663 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 664 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 665 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 666 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
667 | * its request. |
668 | **/ | |
669 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
670 | { | |
92db6d10 | 671 | int status, pos, nr_entries; |
ded86d8d | 672 | int i, j; |
1da177e4 | 673 | u16 control; |
1da177e4 | 674 | |
c9953a73 | 675 | if (!entries) |
1da177e4 LT |
676 | return -EINVAL; |
677 | ||
c9953a73 ME |
678 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
679 | if (status) | |
680 | return status; | |
681 | ||
b64c05e7 | 682 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1da177e4 | 683 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
1da177e4 LT |
684 | nr_entries = multi_msix_capable(control); |
685 | if (nvec > nr_entries) | |
686 | return -EINVAL; | |
687 | ||
688 | /* Check for any invalid entries */ | |
689 | for (i = 0; i < nvec; i++) { | |
690 | if (entries[i].entry >= nr_entries) | |
691 | return -EINVAL; /* invalid entry */ | |
692 | for (j = i + 1; j < nvec; j++) { | |
693 | if (entries[i].entry == entries[j].entry) | |
694 | return -EINVAL; /* duplicate entry */ | |
695 | } | |
696 | } | |
ded86d8d | 697 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 698 | |
1ce03373 | 699 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 700 | if (dev->msi_enabled) { |
80ccba11 BH |
701 | dev_info(&dev->dev, "can't enable MSI-X " |
702 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
703 | return -EINVAL; |
704 | } | |
1da177e4 | 705 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
706 | return status; |
707 | } | |
4cc086fa | 708 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 709 | |
fc4afc7b | 710 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 711 | { |
032de8e2 | 712 | msi_free_irqs(dev); |
fc4afc7b ME |
713 | } |
714 | ||
d52877c7 | 715 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 716 | { |
128bc5fc | 717 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
718 | return; |
719 | ||
b1cbf4e4 | 720 | msix_set_enable(dev, 0); |
ba698ad4 | 721 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 722 | dev->msix_enabled = 0; |
d52877c7 YL |
723 | } |
724 | void pci_disable_msix(struct pci_dev* dev) | |
725 | { | |
726 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
727 | return; | |
728 | ||
729 | pci_msix_shutdown(dev); | |
7bd007e4 | 730 | |
fc4afc7b | 731 | msix_free_all_irqs(dev); |
1da177e4 | 732 | } |
4cc086fa | 733 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
734 | |
735 | /** | |
1ce03373 | 736 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
737 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
738 | * | |
eaae4b3a | 739 | * Being called during hotplug remove, from which the device function |
1ce03373 | 740 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
741 | * allocated for this device function, are reclaimed to unused state, |
742 | * which may be used later on. | |
743 | **/ | |
744 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
745 | { | |
1da177e4 LT |
746 | if (!pci_msi_enable || !dev) |
747 | return; | |
748 | ||
032de8e2 ME |
749 | if (dev->msi_enabled) |
750 | msi_free_irqs(dev); | |
1da177e4 | 751 | |
fc4afc7b ME |
752 | if (dev->msix_enabled) |
753 | msix_free_all_irqs(dev); | |
1da177e4 LT |
754 | } |
755 | ||
309e57df MW |
756 | void pci_no_msi(void) |
757 | { | |
758 | pci_msi_enable = 0; | |
759 | } | |
c9953a73 | 760 | |
4aa9bc95 ME |
761 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
762 | { | |
763 | INIT_LIST_HEAD(&dev->msi_list); | |
764 | } |