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ba395927 KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
17 | * Copyright (C) Ashok Raj <ashok.raj@intel.com> | |
18 | * Copyright (C) Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
19 | */ | |
20 | ||
21 | #ifndef _INTEL_IOMMU_H_ | |
22 | #define _INTEL_IOMMU_H_ | |
23 | ||
24 | #include <linux/types.h> | |
25 | #include <linux/msi.h> | |
f661197e | 26 | #include <linux/sysdev.h> |
ba395927 KA |
27 | #include "iova.h" |
28 | #include <linux/io.h> | |
29 | ||
f661197e DM |
30 | /* |
31 | * We need a fixed PAGE_SIZE of 4K irrespective of | |
32 | * arch PAGE_SIZE for IOMMU page tables. | |
33 | */ | |
34 | #define PAGE_SHIFT_4K (12) | |
35 | #define PAGE_SIZE_4K (1UL << PAGE_SHIFT_4K) | |
36 | #define PAGE_MASK_4K (((u64)-1) << PAGE_SHIFT_4K) | |
37 | #define PAGE_ALIGN_4K(addr) (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K) | |
38 | ||
39 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT_4K) | |
40 | #define DMA_32BIT_PFN IOVA_PFN(DMA_32BIT_MASK) | |
41 | #define DMA_64BIT_PFN IOVA_PFN(DMA_64BIT_MASK) | |
42 | ||
ba395927 KA |
43 | /* |
44 | * Intel IOMMU register specification per version 1.0 public spec. | |
45 | */ | |
46 | ||
47 | #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ | |
48 | #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ | |
49 | #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ | |
50 | #define DMAR_GCMD_REG 0x18 /* Global command register */ | |
51 | #define DMAR_GSTS_REG 0x1c /* Global status register */ | |
52 | #define DMAR_RTADDR_REG 0x20 /* Root entry table */ | |
53 | #define DMAR_CCMD_REG 0x28 /* Context command reg */ | |
54 | #define DMAR_FSTS_REG 0x34 /* Fault Status register */ | |
55 | #define DMAR_FECTL_REG 0x38 /* Fault control register */ | |
56 | #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ | |
57 | #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ | |
58 | #define DMAR_FEUADDR_REG 0x44 /* Upper address register */ | |
59 | #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ | |
60 | #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ | |
61 | #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ | |
62 | #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ | |
63 | #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ | |
64 | #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ | |
65 | ||
66 | #define OFFSET_STRIDE (9) | |
67 | /* | |
68 | #define dmar_readl(dmar, reg) readl(dmar + reg) | |
69 | #define dmar_readq(dmar, reg) ({ \ | |
70 | u32 lo, hi; \ | |
71 | lo = readl(dmar + reg); \ | |
72 | hi = readl(dmar + reg + 4); \ | |
73 | (((u64) hi) << 32) + lo; }) | |
74 | */ | |
4fe05bbc | 75 | static inline u64 dmar_readq(void __iomem *addr) |
ba395927 KA |
76 | { |
77 | u32 lo, hi; | |
78 | lo = readl(addr); | |
79 | hi = readl(addr + 4); | |
80 | return (((u64) hi) << 32) + lo; | |
81 | } | |
82 | ||
83 | static inline void dmar_writeq(void __iomem *addr, u64 val) | |
84 | { | |
85 | writel((u32)val, addr); | |
86 | writel((u32)(val >> 32), addr + 4); | |
87 | } | |
88 | ||
89 | #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) | |
90 | #define DMAR_VER_MINOR(v) ((v) & 0x0f) | |
91 | ||
92 | /* | |
93 | * Decoding Capability Register | |
94 | */ | |
95 | #define cap_read_drain(c) (((c) >> 55) & 1) | |
96 | #define cap_write_drain(c) (((c) >> 54) & 1) | |
97 | #define cap_max_amask_val(c) (((c) >> 48) & 0x3f) | |
98 | #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1) | |
99 | #define cap_pgsel_inv(c) (((c) >> 39) & 1) | |
100 | ||
101 | #define cap_super_page_val(c) (((c) >> 34) & 0xf) | |
102 | #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \ | |
103 | * OFFSET_STRIDE) + 21) | |
104 | ||
105 | #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16) | |
106 | #define cap_max_fault_reg_offset(c) \ | |
107 | (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16) | |
108 | ||
109 | #define cap_zlr(c) (((c) >> 22) & 1) | |
110 | #define cap_isoch(c) (((c) >> 23) & 1) | |
111 | #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1) | |
112 | #define cap_sagaw(c) (((c) >> 8) & 0x1f) | |
113 | #define cap_caching_mode(c) (((c) >> 7) & 1) | |
114 | #define cap_phmr(c) (((c) >> 6) & 1) | |
115 | #define cap_plmr(c) (((c) >> 5) & 1) | |
116 | #define cap_rwbf(c) (((c) >> 4) & 1) | |
117 | #define cap_afl(c) (((c) >> 3) & 1) | |
118 | #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7))) | |
119 | /* | |
120 | * Extended Capability Register | |
121 | */ | |
122 | ||
123 | #define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1) | |
124 | #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) | |
125 | #define ecap_max_iotlb_offset(e) \ | |
126 | (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16) | |
127 | #define ecap_coherent(e) ((e) & 0x1) | |
128 | ||
129 | ||
130 | /* IOTLB_REG */ | |
131 | #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) | |
132 | #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) | |
133 | #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) | |
134 | #define DMA_TLB_IIRG(type) ((type >> 60) & 7) | |
135 | #define DMA_TLB_IAIG(val) (((val) >> 57) & 7) | |
136 | #define DMA_TLB_READ_DRAIN (((u64)1) << 49) | |
137 | #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) | |
138 | #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) | |
139 | #define DMA_TLB_IVT (((u64)1) << 63) | |
140 | #define DMA_TLB_IH_NONLEAF (((u64)1) << 6) | |
141 | #define DMA_TLB_MAX_SIZE (0x3f) | |
142 | ||
f8bab735 | 143 | /* PMEN_REG */ |
144 | #define DMA_PMEN_EPM (((u32)1)<<31) | |
145 | #define DMA_PMEN_PRS (((u32)1)<<0) | |
146 | ||
ba395927 KA |
147 | /* GCMD_REG */ |
148 | #define DMA_GCMD_TE (((u32)1) << 31) | |
149 | #define DMA_GCMD_SRTP (((u32)1) << 30) | |
150 | #define DMA_GCMD_SFL (((u32)1) << 29) | |
151 | #define DMA_GCMD_EAFL (((u32)1) << 28) | |
152 | #define DMA_GCMD_WBF (((u32)1) << 27) | |
153 | ||
154 | /* GSTS_REG */ | |
155 | #define DMA_GSTS_TES (((u32)1) << 31) | |
156 | #define DMA_GSTS_RTPS (((u32)1) << 30) | |
157 | #define DMA_GSTS_FLS (((u32)1) << 29) | |
158 | #define DMA_GSTS_AFLS (((u32)1) << 28) | |
159 | #define DMA_GSTS_WBFS (((u32)1) << 27) | |
160 | ||
161 | /* CCMD_REG */ | |
162 | #define DMA_CCMD_ICC (((u64)1) << 63) | |
163 | #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) | |
164 | #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61) | |
165 | #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61) | |
166 | #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32) | |
167 | #define DMA_CCMD_MASK_NOBIT 0 | |
168 | #define DMA_CCMD_MASK_1BIT 1 | |
169 | #define DMA_CCMD_MASK_2BIT 2 | |
170 | #define DMA_CCMD_MASK_3BIT 3 | |
171 | #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16) | |
172 | #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff)) | |
173 | ||
174 | /* FECTL_REG */ | |
175 | #define DMA_FECTL_IM (((u32)1) << 31) | |
176 | ||
177 | /* FSTS_REG */ | |
178 | #define DMA_FSTS_PPF ((u32)2) | |
179 | #define DMA_FSTS_PFO ((u32)1) | |
180 | #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) | |
181 | ||
182 | /* FRCD_REG, 32 bits access */ | |
183 | #define DMA_FRCD_F (((u32)1) << 31) | |
184 | #define dma_frcd_type(d) ((d >> 30) & 1) | |
185 | #define dma_frcd_fault_reason(c) (c & 0xff) | |
186 | #define dma_frcd_source_id(c) (c & 0xffff) | |
187 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */ | |
188 | ||
189 | /* | |
190 | * 0: Present | |
191 | * 1-11: Reserved | |
192 | * 12-63: Context Ptr (12 - (haw-1)) | |
193 | * 64-127: Reserved | |
194 | */ | |
195 | struct root_entry { | |
196 | u64 val; | |
197 | u64 rsvd1; | |
198 | }; | |
199 | #define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry)) | |
200 | static inline bool root_present(struct root_entry *root) | |
201 | { | |
202 | return (root->val & 1); | |
203 | } | |
204 | static inline void set_root_present(struct root_entry *root) | |
205 | { | |
206 | root->val |= 1; | |
207 | } | |
208 | static inline void set_root_value(struct root_entry *root, unsigned long value) | |
209 | { | |
210 | root->val |= value & PAGE_MASK_4K; | |
211 | } | |
212 | ||
213 | struct context_entry; | |
214 | static inline struct context_entry * | |
215 | get_context_addr_from_root(struct root_entry *root) | |
216 | { | |
217 | return (struct context_entry *) | |
218 | (root_present(root)?phys_to_virt( | |
219 | root->val & PAGE_MASK_4K): | |
220 | NULL); | |
221 | } | |
222 | ||
223 | /* | |
224 | * low 64 bits: | |
225 | * 0: present | |
226 | * 1: fault processing disable | |
227 | * 2-3: translation type | |
228 | * 12-63: address space root | |
229 | * high 64 bits: | |
230 | * 0-2: address width | |
231 | * 3-6: aval | |
232 | * 8-23: domain id | |
233 | */ | |
234 | struct context_entry { | |
235 | u64 lo; | |
236 | u64 hi; | |
237 | }; | |
238 | #define context_present(c) ((c).lo & 1) | |
239 | #define context_fault_disable(c) (((c).lo >> 1) & 1) | |
240 | #define context_translation_type(c) (((c).lo >> 2) & 3) | |
241 | #define context_address_root(c) ((c).lo & PAGE_MASK_4K) | |
242 | #define context_address_width(c) ((c).hi & 7) | |
243 | #define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1)) | |
244 | ||
245 | #define context_set_present(c) do {(c).lo |= 1;} while (0) | |
246 | #define context_set_fault_enable(c) \ | |
247 | do {(c).lo &= (((u64)-1) << 2) | 1;} while (0) | |
248 | #define context_set_translation_type(c, val) \ | |
249 | do { \ | |
250 | (c).lo &= (((u64)-1) << 4) | 3; \ | |
251 | (c).lo |= ((val) & 3) << 2; \ | |
252 | } while (0) | |
253 | #define CONTEXT_TT_MULTI_LEVEL 0 | |
254 | #define context_set_address_root(c, val) \ | |
255 | do {(c).lo |= (val) & PAGE_MASK_4K;} while (0) | |
256 | #define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0) | |
257 | #define context_set_domain_id(c, val) \ | |
258 | do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0) | |
259 | #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0) | |
260 | ||
261 | /* | |
262 | * 0: readable | |
263 | * 1: writable | |
264 | * 2-6: reserved | |
265 | * 7: super page | |
266 | * 8-11: available | |
267 | * 12-63: Host physcial address | |
268 | */ | |
269 | struct dma_pte { | |
270 | u64 val; | |
271 | }; | |
272 | #define dma_clear_pte(p) do {(p).val = 0;} while (0) | |
273 | ||
274 | #define DMA_PTE_READ (1) | |
275 | #define DMA_PTE_WRITE (2) | |
276 | ||
277 | #define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0) | |
278 | #define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0) | |
279 | #define dma_set_pte_prot(p, prot) \ | |
280 | do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0) | |
281 | #define dma_pte_addr(p) ((p).val & PAGE_MASK_4K) | |
282 | #define dma_set_pte_addr(p, addr) do {\ | |
283 | (p).val |= ((addr) & PAGE_MASK_4K); } while (0) | |
284 | #define dma_pte_present(p) (((p).val & 3) != 0) | |
285 | ||
286 | struct intel_iommu; | |
287 | ||
288 | struct dmar_domain { | |
289 | int id; /* domain id */ | |
290 | struct intel_iommu *iommu; /* back pointer to owning iommu */ | |
291 | ||
292 | struct list_head devices; /* all devices' list */ | |
293 | struct iova_domain iovad; /* iova's that belong to this domain */ | |
294 | ||
295 | struct dma_pte *pgd; /* virtual address */ | |
296 | spinlock_t mapping_lock; /* page table lock */ | |
297 | int gaw; /* max guest address width */ | |
298 | ||
299 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
300 | int agaw; | |
301 | ||
302 | #define DOMAIN_FLAG_MULTIPLE_DEVICES 1 | |
303 | int flags; | |
304 | }; | |
305 | ||
306 | /* PCI domain-device relationship */ | |
307 | struct device_domain_info { | |
308 | struct list_head link; /* link to domain siblings */ | |
309 | struct list_head global; /* link to global list */ | |
310 | u8 bus; /* PCI bus numer */ | |
311 | u8 devfn; /* PCI devfn number */ | |
312 | struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ | |
313 | struct dmar_domain *domain; /* pointer to domain */ | |
314 | }; | |
315 | ||
316 | extern int init_dmars(void); | |
317 | ||
318 | struct intel_iommu { | |
319 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ | |
320 | u64 cap; | |
321 | u64 ecap; | |
322 | unsigned long *domain_ids; /* bitmap of domains */ | |
323 | struct dmar_domain **domains; /* ptr to domains */ | |
324 | int seg; | |
325 | u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ | |
326 | spinlock_t lock; /* protect context, domain ids */ | |
327 | spinlock_t register_lock; /* protect register handling */ | |
328 | struct root_entry *root_entry; /* virtual address */ | |
329 | ||
330 | unsigned int irq; | |
331 | unsigned char name[7]; /* Device Name */ | |
332 | struct msi_msg saved_msg; | |
333 | struct sys_device sysdev; | |
334 | }; | |
335 | ||
e820482c KA |
336 | #ifndef CONFIG_DMAR_GFX_WA |
337 | static inline void iommu_prepare_gfx_mapping(void) | |
338 | { | |
339 | return; | |
340 | } | |
341 | #endif /* !CONFIG_DMAR_GFX_WA */ | |
342 | ||
ba395927 | 343 | #endif |